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2
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4
5
6#include <linux/bitfield.h>
7#include <linux/clk.h>
8#include <linux/dmaengine.h>
9#include <linux/dma-mapping.h>
10#include <linux/errno.h>
11#include <linux/io.h>
12#include <linux/iopoll.h>
13#include <linux/interrupt.h>
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/pinctrl/consumer.h>
19#include <linux/pm_runtime.h>
20#include <linux/platform_device.h>
21#include <linux/reset.h>
22#include <linux/sizes.h>
23#include <linux/spi/spi-mem.h>
24
25#define QSPI_CR 0x00
26#define CR_EN BIT(0)
27#define CR_ABORT BIT(1)
28#define CR_DMAEN BIT(2)
29#define CR_TCEN BIT(3)
30#define CR_SSHIFT BIT(4)
31#define CR_DFM BIT(6)
32#define CR_FSEL BIT(7)
33#define CR_FTHRES_SHIFT 8
34#define CR_TEIE BIT(16)
35#define CR_TCIE BIT(17)
36#define CR_FTIE BIT(18)
37#define CR_SMIE BIT(19)
38#define CR_TOIE BIT(20)
39#define CR_PRESC_MASK GENMASK(31, 24)
40
41#define QSPI_DCR 0x04
42#define DCR_FSIZE_MASK GENMASK(20, 16)
43
44#define QSPI_SR 0x08
45#define SR_TEF BIT(0)
46#define SR_TCF BIT(1)
47#define SR_FTF BIT(2)
48#define SR_SMF BIT(3)
49#define SR_TOF BIT(4)
50#define SR_BUSY BIT(5)
51#define SR_FLEVEL_MASK GENMASK(13, 8)
52
53#define QSPI_FCR 0x0c
54#define FCR_CTEF BIT(0)
55#define FCR_CTCF BIT(1)
56
57#define QSPI_DLR 0x10
58
59#define QSPI_CCR 0x14
60#define CCR_INST_MASK GENMASK(7, 0)
61#define CCR_IMODE_MASK GENMASK(9, 8)
62#define CCR_ADMODE_MASK GENMASK(11, 10)
63#define CCR_ADSIZE_MASK GENMASK(13, 12)
64#define CCR_DCYC_MASK GENMASK(22, 18)
65#define CCR_DMODE_MASK GENMASK(25, 24)
66#define CCR_FMODE_MASK GENMASK(27, 26)
67#define CCR_FMODE_INDW (0U << 26)
68#define CCR_FMODE_INDR (1U << 26)
69#define CCR_FMODE_APM (2U << 26)
70#define CCR_FMODE_MM (3U << 26)
71#define CCR_BUSWIDTH_0 0x0
72#define CCR_BUSWIDTH_1 0x1
73#define CCR_BUSWIDTH_2 0x2
74#define CCR_BUSWIDTH_4 0x3
75
76#define QSPI_AR 0x18
77#define QSPI_ABR 0x1c
78#define QSPI_DR 0x20
79#define QSPI_PSMKR 0x24
80#define QSPI_PSMAR 0x28
81#define QSPI_PIR 0x2c
82#define QSPI_LPTR 0x30
83
84#define STM32_QSPI_MAX_MMAP_SZ SZ_256M
85#define STM32_QSPI_MAX_NORCHIP 2
86
87#define STM32_FIFO_TIMEOUT_US 30000
88#define STM32_BUSY_TIMEOUT_US 100000
89#define STM32_ABT_TIMEOUT_US 100000
90#define STM32_COMP_TIMEOUT_MS 1000
91#define STM32_AUTOSUSPEND_DELAY -1
92
93struct stm32_qspi_flash {
94 struct stm32_qspi *qspi;
95 u32 cs;
96 u32 presc;
97};
98
99struct stm32_qspi {
100 struct device *dev;
101 struct spi_controller *ctrl;
102 phys_addr_t phys_base;
103 void __iomem *io_base;
104 void __iomem *mm_base;
105 resource_size_t mm_size;
106 struct clk *clk;
107 u32 clk_rate;
108 struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
109 struct completion data_completion;
110 u32 fmode;
111
112 struct dma_chan *dma_chtx;
113 struct dma_chan *dma_chrx;
114 struct completion dma_completion;
115
116 u32 cr_reg;
117 u32 dcr_reg;
118
119
120
121
122
123 struct mutex lock;
124};
125
126static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
127{
128 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
129 u32 cr, sr;
130
131 sr = readl_relaxed(qspi->io_base + QSPI_SR);
132
133 if (sr & (SR_TEF | SR_TCF)) {
134
135 cr = readl_relaxed(qspi->io_base + QSPI_CR);
136 cr &= ~CR_TCIE & ~CR_TEIE;
137 writel_relaxed(cr, qspi->io_base + QSPI_CR);
138 complete(&qspi->data_completion);
139 }
140
141 return IRQ_HANDLED;
142}
143
144static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
145{
146 *val = readb_relaxed(addr);
147}
148
149static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
150{
151 writeb_relaxed(*val, addr);
152}
153
154static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
155 const struct spi_mem_op *op)
156{
157 void (*tx_fifo)(u8 *val, void __iomem *addr);
158 u32 len = op->data.nbytes, sr;
159 u8 *buf;
160 int ret;
161
162 if (op->data.dir == SPI_MEM_DATA_IN) {
163 tx_fifo = stm32_qspi_read_fifo;
164 buf = op->data.buf.in;
165
166 } else {
167 tx_fifo = stm32_qspi_write_fifo;
168 buf = (u8 *)op->data.buf.out;
169 }
170
171 while (len--) {
172 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR,
173 sr, (sr & SR_FTF), 1,
174 STM32_FIFO_TIMEOUT_US);
175 if (ret) {
176 dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n",
177 len, sr);
178 return ret;
179 }
180 tx_fifo(buf++, qspi->io_base + QSPI_DR);
181 }
182
183 return 0;
184}
185
186static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
187 const struct spi_mem_op *op)
188{
189 memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val,
190 op->data.nbytes);
191 return 0;
192}
193
194static void stm32_qspi_dma_callback(void *arg)
195{
196 struct completion *dma_completion = arg;
197
198 complete(dma_completion);
199}
200
201static int stm32_qspi_tx_dma(struct stm32_qspi *qspi,
202 const struct spi_mem_op *op)
203{
204 struct dma_async_tx_descriptor *desc;
205 enum dma_transfer_direction dma_dir;
206 struct dma_chan *dma_ch;
207 struct sg_table sgt;
208 dma_cookie_t cookie;
209 u32 cr, t_out;
210 int err;
211
212 if (op->data.dir == SPI_MEM_DATA_IN) {
213 dma_dir = DMA_DEV_TO_MEM;
214 dma_ch = qspi->dma_chrx;
215 } else {
216 dma_dir = DMA_MEM_TO_DEV;
217 dma_ch = qspi->dma_chtx;
218 }
219
220
221
222
223
224 err = spi_controller_dma_map_mem_op_data(qspi->ctrl, op, &sgt);
225 if (err)
226 return err;
227
228 desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents,
229 dma_dir, DMA_PREP_INTERRUPT);
230 if (!desc) {
231 err = -ENOMEM;
232 goto out_unmap;
233 }
234
235 cr = readl_relaxed(qspi->io_base + QSPI_CR);
236
237 reinit_completion(&qspi->dma_completion);
238 desc->callback = stm32_qspi_dma_callback;
239 desc->callback_param = &qspi->dma_completion;
240 cookie = dmaengine_submit(desc);
241 err = dma_submit_error(cookie);
242 if (err)
243 goto out;
244
245 dma_async_issue_pending(dma_ch);
246
247 writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR);
248
249 t_out = sgt.nents * STM32_COMP_TIMEOUT_MS;
250 if (!wait_for_completion_timeout(&qspi->dma_completion,
251 msecs_to_jiffies(t_out)))
252 err = -ETIMEDOUT;
253
254 if (err)
255 dmaengine_terminate_all(dma_ch);
256
257out:
258 writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR);
259out_unmap:
260 spi_controller_dma_unmap_mem_op_data(qspi->ctrl, op, &sgt);
261
262 return err;
263}
264
265static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op)
266{
267 if (!op->data.nbytes)
268 return 0;
269
270 if (qspi->fmode == CCR_FMODE_MM)
271 return stm32_qspi_tx_mm(qspi, op);
272 else if ((op->data.dir == SPI_MEM_DATA_IN && qspi->dma_chrx) ||
273 (op->data.dir == SPI_MEM_DATA_OUT && qspi->dma_chtx))
274 if (!stm32_qspi_tx_dma(qspi, op))
275 return 0;
276
277 return stm32_qspi_tx_poll(qspi, op);
278}
279
280static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
281{
282 u32 sr;
283
284 return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr,
285 !(sr & SR_BUSY), 1,
286 STM32_BUSY_TIMEOUT_US);
287}
288
289static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi,
290 const struct spi_mem_op *op)
291{
292 u32 cr, sr;
293 int err = 0;
294
295 if (!op->data.nbytes)
296 return stm32_qspi_wait_nobusy(qspi);
297
298 if (readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF)
299 goto out;
300
301 reinit_completion(&qspi->data_completion);
302 cr = readl_relaxed(qspi->io_base + QSPI_CR);
303 writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR);
304
305 if (!wait_for_completion_timeout(&qspi->data_completion,
306 msecs_to_jiffies(STM32_COMP_TIMEOUT_MS))) {
307 err = -ETIMEDOUT;
308 } else {
309 sr = readl_relaxed(qspi->io_base + QSPI_SR);
310 if (sr & SR_TEF)
311 err = -EIO;
312 }
313
314out:
315
316 writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);
317
318 return err;
319}
320
321static int stm32_qspi_get_mode(struct stm32_qspi *qspi, u8 buswidth)
322{
323 if (buswidth == 4)
324 return CCR_BUSWIDTH_4;
325
326 return buswidth;
327}
328
329static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
330{
331 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
332 struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
333 u32 ccr, cr, addr_max;
334 int timeout, err = 0;
335
336 dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
337 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
338 op->dummy.buswidth, op->data.buswidth,
339 op->addr.val, op->data.nbytes);
340
341 err = stm32_qspi_wait_nobusy(qspi);
342 if (err)
343 goto abort;
344
345 addr_max = op->addr.val + op->data.nbytes + 1;
346
347 if (op->data.dir == SPI_MEM_DATA_IN) {
348 if (addr_max < qspi->mm_size &&
349 op->addr.buswidth)
350 qspi->fmode = CCR_FMODE_MM;
351 else
352 qspi->fmode = CCR_FMODE_INDR;
353 } else {
354 qspi->fmode = CCR_FMODE_INDW;
355 }
356
357 cr = readl_relaxed(qspi->io_base + QSPI_CR);
358 cr &= ~CR_PRESC_MASK & ~CR_FSEL;
359 cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
360 cr |= FIELD_PREP(CR_FSEL, flash->cs);
361 writel_relaxed(cr, qspi->io_base + QSPI_CR);
362
363 if (op->data.nbytes)
364 writel_relaxed(op->data.nbytes - 1,
365 qspi->io_base + QSPI_DLR);
366 else
367 qspi->fmode = CCR_FMODE_INDW;
368
369 ccr = qspi->fmode;
370 ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode);
371 ccr |= FIELD_PREP(CCR_IMODE_MASK,
372 stm32_qspi_get_mode(qspi, op->cmd.buswidth));
373
374 if (op->addr.nbytes) {
375 ccr |= FIELD_PREP(CCR_ADMODE_MASK,
376 stm32_qspi_get_mode(qspi, op->addr.buswidth));
377 ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1);
378 }
379
380 if (op->dummy.buswidth && op->dummy.nbytes)
381 ccr |= FIELD_PREP(CCR_DCYC_MASK,
382 op->dummy.nbytes * 8 / op->dummy.buswidth);
383
384 if (op->data.nbytes) {
385 ccr |= FIELD_PREP(CCR_DMODE_MASK,
386 stm32_qspi_get_mode(qspi, op->data.buswidth));
387 }
388
389 writel_relaxed(ccr, qspi->io_base + QSPI_CCR);
390
391 if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
392 writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
393
394 err = stm32_qspi_tx(qspi, op);
395
396
397
398
399
400
401
402
403 if (err || qspi->fmode == CCR_FMODE_MM)
404 goto abort;
405
406
407 err = stm32_qspi_wait_cmd(qspi, op);
408 if (err)
409 goto abort;
410
411 return 0;
412
413abort:
414 cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT;
415 writel_relaxed(cr, qspi->io_base + QSPI_CR);
416
417
418 timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR,
419 cr, !(cr & CR_ABORT), 1,
420 STM32_ABT_TIMEOUT_US);
421
422 writel_relaxed(FCR_CTCF, qspi->io_base + QSPI_FCR);
423
424 if (err || timeout)
425 dev_err(qspi->dev, "%s err:%d abort timeout:%d\n",
426 __func__, err, timeout);
427
428 return err;
429}
430
431static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
432{
433 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
434 int ret;
435
436 ret = pm_runtime_get_sync(qspi->dev);
437 if (ret < 0)
438 return ret;
439
440 mutex_lock(&qspi->lock);
441 ret = stm32_qspi_send(mem, op);
442 mutex_unlock(&qspi->lock);
443
444 pm_runtime_mark_last_busy(qspi->dev);
445 pm_runtime_put_autosuspend(qspi->dev);
446
447 return ret;
448}
449
450static int stm32_qspi_setup(struct spi_device *spi)
451{
452 struct spi_controller *ctrl = spi->master;
453 struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
454 struct stm32_qspi_flash *flash;
455 u32 presc;
456 int ret;
457
458 if (ctrl->busy)
459 return -EBUSY;
460
461 if (!spi->max_speed_hz)
462 return -EINVAL;
463
464 ret = pm_runtime_get_sync(qspi->dev);
465 if (ret < 0)
466 return ret;
467
468 presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
469
470 flash = &qspi->flash[spi->chip_select];
471 flash->qspi = qspi;
472 flash->cs = spi->chip_select;
473 flash->presc = presc;
474
475 mutex_lock(&qspi->lock);
476 qspi->cr_reg = 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN;
477 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
478
479
480 qspi->dcr_reg = DCR_FSIZE_MASK;
481 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
482 mutex_unlock(&qspi->lock);
483
484 pm_runtime_mark_last_busy(qspi->dev);
485 pm_runtime_put_autosuspend(qspi->dev);
486
487 return 0;
488}
489
490static int stm32_qspi_dma_setup(struct stm32_qspi *qspi)
491{
492 struct dma_slave_config dma_cfg;
493 struct device *dev = qspi->dev;
494 int ret = 0;
495
496 memset(&dma_cfg, 0, sizeof(dma_cfg));
497
498 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
499 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
500 dma_cfg.src_addr = qspi->phys_base + QSPI_DR;
501 dma_cfg.dst_addr = qspi->phys_base + QSPI_DR;
502 dma_cfg.src_maxburst = 4;
503 dma_cfg.dst_maxburst = 4;
504
505 qspi->dma_chrx = dma_request_chan(dev, "rx");
506 if (IS_ERR(qspi->dma_chrx)) {
507 ret = PTR_ERR(qspi->dma_chrx);
508 qspi->dma_chrx = NULL;
509 if (ret == -EPROBE_DEFER)
510 goto out;
511 } else {
512 if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) {
513 dev_err(dev, "dma rx config failed\n");
514 dma_release_channel(qspi->dma_chrx);
515 qspi->dma_chrx = NULL;
516 }
517 }
518
519 qspi->dma_chtx = dma_request_chan(dev, "tx");
520 if (IS_ERR(qspi->dma_chtx)) {
521 ret = PTR_ERR(qspi->dma_chtx);
522 qspi->dma_chtx = NULL;
523 } else {
524 if (dmaengine_slave_config(qspi->dma_chtx, &dma_cfg)) {
525 dev_err(dev, "dma tx config failed\n");
526 dma_release_channel(qspi->dma_chtx);
527 qspi->dma_chtx = NULL;
528 }
529 }
530
531out:
532 init_completion(&qspi->dma_completion);
533
534 if (ret != -EPROBE_DEFER)
535 ret = 0;
536
537 return ret;
538}
539
540static void stm32_qspi_dma_free(struct stm32_qspi *qspi)
541{
542 if (qspi->dma_chtx)
543 dma_release_channel(qspi->dma_chtx);
544 if (qspi->dma_chrx)
545 dma_release_channel(qspi->dma_chrx);
546}
547
548
549
550
551
552static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
553 .exec_op = stm32_qspi_exec_op,
554};
555
556static int stm32_qspi_probe(struct platform_device *pdev)
557{
558 struct device *dev = &pdev->dev;
559 struct spi_controller *ctrl;
560 struct reset_control *rstc;
561 struct stm32_qspi *qspi;
562 struct resource *res;
563 int ret, irq;
564
565 ctrl = spi_alloc_master(dev, sizeof(*qspi));
566 if (!ctrl)
567 return -ENOMEM;
568
569 qspi = spi_controller_get_devdata(ctrl);
570 qspi->ctrl = ctrl;
571
572 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
573 qspi->io_base = devm_ioremap_resource(dev, res);
574 if (IS_ERR(qspi->io_base)) {
575 ret = PTR_ERR(qspi->io_base);
576 goto err_master_put;
577 }
578
579 qspi->phys_base = res->start;
580
581 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
582 qspi->mm_base = devm_ioremap_resource(dev, res);
583 if (IS_ERR(qspi->mm_base)) {
584 ret = PTR_ERR(qspi->mm_base);
585 goto err_master_put;
586 }
587
588 qspi->mm_size = resource_size(res);
589 if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) {
590 ret = -EINVAL;
591 goto err_master_put;
592 }
593
594 irq = platform_get_irq(pdev, 0);
595 if (irq < 0) {
596 ret = irq;
597 goto err_master_put;
598 }
599
600 ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
601 dev_name(dev), qspi);
602 if (ret) {
603 dev_err(dev, "failed to request irq\n");
604 goto err_master_put;
605 }
606
607 init_completion(&qspi->data_completion);
608
609 qspi->clk = devm_clk_get(dev, NULL);
610 if (IS_ERR(qspi->clk)) {
611 ret = PTR_ERR(qspi->clk);
612 goto err_master_put;
613 }
614
615 qspi->clk_rate = clk_get_rate(qspi->clk);
616 if (!qspi->clk_rate) {
617 ret = -EINVAL;
618 goto err_master_put;
619 }
620
621 ret = clk_prepare_enable(qspi->clk);
622 if (ret) {
623 dev_err(dev, "can not enable the clock\n");
624 goto err_master_put;
625 }
626
627 rstc = devm_reset_control_get_exclusive(dev, NULL);
628 if (IS_ERR(rstc)) {
629 ret = PTR_ERR(rstc);
630 if (ret == -EPROBE_DEFER)
631 goto err_clk_disable;
632 } else {
633 reset_control_assert(rstc);
634 udelay(2);
635 reset_control_deassert(rstc);
636 }
637
638 qspi->dev = dev;
639 platform_set_drvdata(pdev, qspi);
640 ret = stm32_qspi_dma_setup(qspi);
641 if (ret)
642 goto err_dma_free;
643
644 mutex_init(&qspi->lock);
645
646 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD
647 | SPI_TX_DUAL | SPI_TX_QUAD;
648 ctrl->setup = stm32_qspi_setup;
649 ctrl->bus_num = -1;
650 ctrl->mem_ops = &stm32_qspi_mem_ops;
651 ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP;
652 ctrl->dev.of_node = dev->of_node;
653
654 pm_runtime_set_autosuspend_delay(dev, STM32_AUTOSUSPEND_DELAY);
655 pm_runtime_use_autosuspend(dev);
656 pm_runtime_set_active(dev);
657 pm_runtime_enable(dev);
658 pm_runtime_get_noresume(dev);
659
660 ret = devm_spi_register_master(dev, ctrl);
661 if (ret)
662 goto err_pm_runtime_free;
663
664 pm_runtime_mark_last_busy(dev);
665 pm_runtime_put_autosuspend(dev);
666
667 return 0;
668
669err_pm_runtime_free:
670 pm_runtime_get_sync(qspi->dev);
671
672 writel_relaxed(0, qspi->io_base + QSPI_CR);
673 mutex_destroy(&qspi->lock);
674 pm_runtime_put_noidle(qspi->dev);
675 pm_runtime_disable(qspi->dev);
676 pm_runtime_set_suspended(qspi->dev);
677 pm_runtime_dont_use_autosuspend(qspi->dev);
678err_dma_free:
679 stm32_qspi_dma_free(qspi);
680err_clk_disable:
681 clk_disable_unprepare(qspi->clk);
682err_master_put:
683 spi_master_put(qspi->ctrl);
684
685 return ret;
686}
687
688static int stm32_qspi_remove(struct platform_device *pdev)
689{
690 struct stm32_qspi *qspi = platform_get_drvdata(pdev);
691
692 pm_runtime_get_sync(qspi->dev);
693
694 writel_relaxed(0, qspi->io_base + QSPI_CR);
695 stm32_qspi_dma_free(qspi);
696 mutex_destroy(&qspi->lock);
697 pm_runtime_put_noidle(qspi->dev);
698 pm_runtime_disable(qspi->dev);
699 pm_runtime_set_suspended(qspi->dev);
700 pm_runtime_dont_use_autosuspend(qspi->dev);
701 clk_disable_unprepare(qspi->clk);
702
703 return 0;
704}
705
706static int __maybe_unused stm32_qspi_runtime_suspend(struct device *dev)
707{
708 struct stm32_qspi *qspi = dev_get_drvdata(dev);
709
710 clk_disable_unprepare(qspi->clk);
711
712 return 0;
713}
714
715static int __maybe_unused stm32_qspi_runtime_resume(struct device *dev)
716{
717 struct stm32_qspi *qspi = dev_get_drvdata(dev);
718
719 return clk_prepare_enable(qspi->clk);
720}
721
722static int __maybe_unused stm32_qspi_suspend(struct device *dev)
723{
724 pinctrl_pm_select_sleep_state(dev);
725
726 return 0;
727}
728
729static int __maybe_unused stm32_qspi_resume(struct device *dev)
730{
731 struct stm32_qspi *qspi = dev_get_drvdata(dev);
732
733 pinctrl_pm_select_default_state(dev);
734 clk_prepare_enable(qspi->clk);
735
736 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
737 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
738
739 pm_runtime_mark_last_busy(qspi->dev);
740 pm_runtime_put_autosuspend(qspi->dev);
741
742 return 0;
743}
744
745static const struct dev_pm_ops stm32_qspi_pm_ops = {
746 SET_RUNTIME_PM_OPS(stm32_qspi_runtime_suspend,
747 stm32_qspi_runtime_resume, NULL)
748 SET_SYSTEM_SLEEP_PM_OPS(stm32_qspi_suspend, stm32_qspi_resume)
749};
750
751static const struct of_device_id stm32_qspi_match[] = {
752 {.compatible = "st,stm32f469-qspi"},
753 {}
754};
755MODULE_DEVICE_TABLE(of, stm32_qspi_match);
756
757static struct platform_driver stm32_qspi_driver = {
758 .probe = stm32_qspi_probe,
759 .remove = stm32_qspi_remove,
760 .driver = {
761 .name = "stm32-qspi",
762 .of_match_table = stm32_qspi_match,
763 .pm = &stm32_qspi_pm_ops,
764 },
765};
766module_platform_driver(stm32_qspi_driver);
767
768MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
769MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
770MODULE_LICENSE("GPL v2");
771
