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8#include <linux/debugfs.h>
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/dmaengine.h>
12#include <linux/interrupt.h>
13#include <linux/iopoll.h>
14#include <linux/module.h>
15#include <linux/of_platform.h>
16#include <linux/pinctrl/consumer.h>
17#include <linux/pm_runtime.h>
18#include <linux/reset.h>
19#include <linux/spi/spi.h>
20
21#define DRIVER_NAME "spi_stm32"
22
23
24#define STM32F4_SPI_CR1 0x00
25#define STM32F4_SPI_CR2 0x04
26#define STM32F4_SPI_SR 0x08
27#define STM32F4_SPI_DR 0x0C
28#define STM32F4_SPI_I2SCFGR 0x1C
29
30
31#define STM32F4_SPI_CR1_CPHA BIT(0)
32#define STM32F4_SPI_CR1_CPOL BIT(1)
33#define STM32F4_SPI_CR1_MSTR BIT(2)
34#define STM32F4_SPI_CR1_BR_SHIFT 3
35#define STM32F4_SPI_CR1_BR GENMASK(5, 3)
36#define STM32F4_SPI_CR1_SPE BIT(6)
37#define STM32F4_SPI_CR1_LSBFRST BIT(7)
38#define STM32F4_SPI_CR1_SSI BIT(8)
39#define STM32F4_SPI_CR1_SSM BIT(9)
40#define STM32F4_SPI_CR1_RXONLY BIT(10)
41#define STM32F4_SPI_CR1_DFF BIT(11)
42#define STM32F4_SPI_CR1_CRCNEXT BIT(12)
43#define STM32F4_SPI_CR1_CRCEN BIT(13)
44#define STM32F4_SPI_CR1_BIDIOE BIT(14)
45#define STM32F4_SPI_CR1_BIDIMODE BIT(15)
46#define STM32F4_SPI_CR1_BR_MIN 0
47#define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)
48
49
50#define STM32F4_SPI_CR2_RXDMAEN BIT(0)
51#define STM32F4_SPI_CR2_TXDMAEN BIT(1)
52#define STM32F4_SPI_CR2_SSOE BIT(2)
53#define STM32F4_SPI_CR2_FRF BIT(4)
54#define STM32F4_SPI_CR2_ERRIE BIT(5)
55#define STM32F4_SPI_CR2_RXNEIE BIT(6)
56#define STM32F4_SPI_CR2_TXEIE BIT(7)
57
58
59#define STM32F4_SPI_SR_RXNE BIT(0)
60#define STM32F4_SPI_SR_TXE BIT(1)
61#define STM32F4_SPI_SR_CHSIDE BIT(2)
62#define STM32F4_SPI_SR_UDR BIT(3)
63#define STM32F4_SPI_SR_CRCERR BIT(4)
64#define STM32F4_SPI_SR_MODF BIT(5)
65#define STM32F4_SPI_SR_OVR BIT(6)
66#define STM32F4_SPI_SR_BSY BIT(7)
67#define STM32F4_SPI_SR_FRE BIT(8)
68
69
70#define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11)
71
72
73#define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN)
74#define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX)
75
76
77#define STM32H7_SPI_CR1 0x00
78#define STM32H7_SPI_CR2 0x04
79#define STM32H7_SPI_CFG1 0x08
80#define STM32H7_SPI_CFG2 0x0C
81#define STM32H7_SPI_IER 0x10
82#define STM32H7_SPI_SR 0x14
83#define STM32H7_SPI_IFCR 0x18
84#define STM32H7_SPI_TXDR 0x20
85#define STM32H7_SPI_RXDR 0x30
86#define STM32H7_SPI_I2SCFGR 0x50
87
88
89#define STM32H7_SPI_CR1_SPE BIT(0)
90#define STM32H7_SPI_CR1_MASRX BIT(8)
91#define STM32H7_SPI_CR1_CSTART BIT(9)
92#define STM32H7_SPI_CR1_CSUSP BIT(10)
93#define STM32H7_SPI_CR1_HDDIR BIT(11)
94#define STM32H7_SPI_CR1_SSI BIT(12)
95
96
97#define STM32H7_SPI_CR2_TSIZE_SHIFT 0
98#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
99
100
101#define STM32H7_SPI_CFG1_DSIZE_SHIFT 0
102#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
103#define STM32H7_SPI_CFG1_FTHLV_SHIFT 5
104#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
105#define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
106#define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
107#define STM32H7_SPI_CFG1_MBR_SHIFT 28
108#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
109#define STM32H7_SPI_CFG1_MBR_MIN 0
110#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
111
112
113#define STM32H7_SPI_CFG2_MIDI_SHIFT 4
114#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
115#define STM32H7_SPI_CFG2_COMM_SHIFT 17
116#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
117#define STM32H7_SPI_CFG2_SP_SHIFT 19
118#define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
119#define STM32H7_SPI_CFG2_MASTER BIT(22)
120#define STM32H7_SPI_CFG2_LSBFRST BIT(23)
121#define STM32H7_SPI_CFG2_CPHA BIT(24)
122#define STM32H7_SPI_CFG2_CPOL BIT(25)
123#define STM32H7_SPI_CFG2_SSM BIT(26)
124#define STM32H7_SPI_CFG2_AFCNTR BIT(31)
125
126
127#define STM32H7_SPI_IER_RXPIE BIT(0)
128#define STM32H7_SPI_IER_TXPIE BIT(1)
129#define STM32H7_SPI_IER_DXPIE BIT(2)
130#define STM32H7_SPI_IER_EOTIE BIT(3)
131#define STM32H7_SPI_IER_TXTFIE BIT(4)
132#define STM32H7_SPI_IER_OVRIE BIT(6)
133#define STM32H7_SPI_IER_MODFIE BIT(9)
134#define STM32H7_SPI_IER_ALL GENMASK(10, 0)
135
136
137#define STM32H7_SPI_SR_RXP BIT(0)
138#define STM32H7_SPI_SR_TXP BIT(1)
139#define STM32H7_SPI_SR_EOT BIT(3)
140#define STM32H7_SPI_SR_OVR BIT(6)
141#define STM32H7_SPI_SR_MODF BIT(9)
142#define STM32H7_SPI_SR_SUSP BIT(11)
143#define STM32H7_SPI_SR_RXPLVL_SHIFT 13
144#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
145#define STM32H7_SPI_SR_RXWNE BIT(15)
146
147
148#define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)
149
150
151#define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
152
153
154#define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
155#define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
156
157
158#define STM32H7_SPI_FULL_DUPLEX 0
159#define STM32H7_SPI_SIMPLEX_TX 1
160#define STM32H7_SPI_SIMPLEX_RX 2
161#define STM32H7_SPI_HALF_DUPLEX 3
162
163
164#define SPI_FULL_DUPLEX 0
165#define SPI_SIMPLEX_TX 1
166#define SPI_SIMPLEX_RX 2
167#define SPI_3WIRE_TX 3
168#define SPI_3WIRE_RX 4
169
170#define SPI_1HZ_NS 1000000000
171
172
173
174
175
176#define SPI_DMA_MIN_BYTES 16
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183
184struct stm32_spi_reg {
185 int reg;
186 int mask;
187 int shift;
188};
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201
202struct stm32_spi_regspec {
203 const struct stm32_spi_reg en;
204 const struct stm32_spi_reg dma_rx_en;
205 const struct stm32_spi_reg dma_tx_en;
206 const struct stm32_spi_reg cpol;
207 const struct stm32_spi_reg cpha;
208 const struct stm32_spi_reg lsb_first;
209 const struct stm32_spi_reg br;
210 const struct stm32_spi_reg rx;
211 const struct stm32_spi_reg tx;
212};
213
214struct stm32_spi;
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242struct stm32_spi_cfg {
243 const struct stm32_spi_regspec *regs;
244 int (*get_fifo_size)(struct stm32_spi *spi);
245 int (*get_bpw_mask)(struct stm32_spi *spi);
246 void (*disable)(struct stm32_spi *spi);
247 int (*config)(struct stm32_spi *spi);
248 void (*set_bpw)(struct stm32_spi *spi);
249 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
250 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
251 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
252 void (*transfer_one_dma_start)(struct stm32_spi *spi);
253 void (*dma_rx_cb)(void *data);
254 void (*dma_tx_cb)(void *data);
255 int (*transfer_one_irq)(struct stm32_spi *spi);
256 irqreturn_t (*irq_handler_event)(int irq, void *dev_id);
257 irqreturn_t (*irq_handler_thread)(int irq, void *dev_id);
258 unsigned int baud_rate_div_min;
259 unsigned int baud_rate_div_max;
260 bool has_fifo;
261};
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290struct stm32_spi {
291 struct device *dev;
292 struct spi_master *master;
293 const struct stm32_spi_cfg *cfg;
294 void __iomem *base;
295 struct clk *clk;
296 u32 clk_rate;
297 struct reset_control *rst;
298 spinlock_t lock;
299 int irq;
300 unsigned int fifo_size;
301
302 unsigned int cur_midi;
303 unsigned int cur_speed;
304 unsigned int cur_bpw;
305 unsigned int cur_fthlv;
306 unsigned int cur_comm;
307 unsigned int cur_xferlen;
308 bool cur_usedma;
309
310 const void *tx_buf;
311 void *rx_buf;
312 int tx_len;
313 int rx_len;
314 struct dma_chan *dma_tx;
315 struct dma_chan *dma_rx;
316 dma_addr_t phys_addr;
317};
318
319static const struct stm32_spi_regspec stm32f4_spi_regspec = {
320 .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE },
321
322 .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN },
323 .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN },
324
325 .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL },
326 .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
327 .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST },
328 .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT },
329
330 .rx = { STM32F4_SPI_DR },
331 .tx = { STM32F4_SPI_DR },
332};
333
334static const struct stm32_spi_regspec stm32h7_spi_regspec = {
335
336
337
338 .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
339
340 .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
341 .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
342
343 .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
344 .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
345 .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
346 .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
347 STM32H7_SPI_CFG1_MBR_SHIFT },
348
349 .rx = { STM32H7_SPI_RXDR },
350 .tx = { STM32H7_SPI_TXDR },
351};
352
353static inline void stm32_spi_set_bits(struct stm32_spi *spi,
354 u32 offset, u32 bits)
355{
356 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
357 spi->base + offset);
358}
359
360static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
361 u32 offset, u32 bits)
362{
363 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
364 spi->base + offset);
365}
366
367
368
369
370
371static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
372{
373 unsigned long flags;
374 u32 count = 0;
375
376 spin_lock_irqsave(&spi->lock, flags);
377
378 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
379
380 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
381 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
382
383 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
384
385 spin_unlock_irqrestore(&spi->lock, flags);
386
387 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
388
389 return count;
390}
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395
396static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
397{
398 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
399 return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
400}
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406static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
407{
408 unsigned long flags;
409 u32 cfg1, max_bpw;
410
411 spin_lock_irqsave(&spi->lock, flags);
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417 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
418
419 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
420 max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
421 STM32H7_SPI_CFG1_DSIZE_SHIFT;
422 max_bpw += 1;
423
424 spin_unlock_irqrestore(&spi->lock, flags);
425
426 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
427
428 return SPI_BPW_RANGE_MASK(4, max_bpw);
429}
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439
440static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
441 u32 min_div, u32 max_div)
442{
443 u32 div, mbrdiv;
444
445
446 div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
447
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453
454
455 if ((div < min_div) || (div > max_div))
456 return -EINVAL;
457
458
459 if (div & (div - 1))
460 mbrdiv = fls(div);
461 else
462 mbrdiv = fls(div) - 1;
463
464 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
465
466 return mbrdiv - 1;
467}
468
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473
474static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
475{
476 u32 fthlv, half_fifo, packet;
477
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479 half_fifo = (spi->fifo_size / 2);
480
481
482 if (half_fifo > xfer_len)
483 packet = xfer_len;
484 else
485 packet = half_fifo;
486
487 if (spi->cur_bpw <= 8)
488 fthlv = packet;
489 else if (spi->cur_bpw <= 16)
490 fthlv = packet / 2;
491 else
492 fthlv = packet / 4;
493
494
495 if (spi->cur_bpw > 8)
496 fthlv -= (fthlv % 2);
497 else
498 fthlv -= (fthlv % 4);
499
500 if (!fthlv)
501 fthlv = 1;
502
503 return fthlv;
504}
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512
513static void stm32f4_spi_write_tx(struct stm32_spi *spi)
514{
515 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
516 STM32F4_SPI_SR_TXE)) {
517 u32 offs = spi->cur_xferlen - spi->tx_len;
518
519 if (spi->cur_bpw == 16) {
520 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
521
522 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
523 spi->tx_len -= sizeof(u16);
524 } else {
525 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
526
527 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
528 spi->tx_len -= sizeof(u8);
529 }
530 }
531
532 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
533}
534
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541
542static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
543{
544 while ((spi->tx_len > 0) &&
545 (readl_relaxed(spi->base + STM32H7_SPI_SR) &
546 STM32H7_SPI_SR_TXP)) {
547 u32 offs = spi->cur_xferlen - spi->tx_len;
548
549 if (spi->tx_len >= sizeof(u32)) {
550 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
551
552 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
553 spi->tx_len -= sizeof(u32);
554 } else if (spi->tx_len >= sizeof(u16)) {
555 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
556
557 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
558 spi->tx_len -= sizeof(u16);
559 } else {
560 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
561
562 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
563 spi->tx_len -= sizeof(u8);
564 }
565 }
566
567 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
568}
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576
577static void stm32f4_spi_read_rx(struct stm32_spi *spi)
578{
579 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
580 STM32F4_SPI_SR_RXNE)) {
581 u32 offs = spi->cur_xferlen - spi->rx_len;
582
583 if (spi->cur_bpw == 16) {
584 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
585
586 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
587 spi->rx_len -= sizeof(u16);
588 } else {
589 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
590
591 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
592 spi->rx_len -= sizeof(u8);
593 }
594 }
595
596 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
597}
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606
607static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
608{
609 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
610 u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
611 STM32H7_SPI_SR_RXPLVL_SHIFT;
612
613 while ((spi->rx_len > 0) &&
614 ((sr & STM32H7_SPI_SR_RXP) ||
615 (flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
616 u32 offs = spi->cur_xferlen - spi->rx_len;
617
618 if ((spi->rx_len >= sizeof(u32)) ||
619 (flush && (sr & STM32H7_SPI_SR_RXWNE))) {
620 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
621
622 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
623 spi->rx_len -= sizeof(u32);
624 } else if ((spi->rx_len >= sizeof(u16)) ||
625 (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
626 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
627
628 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
629 spi->rx_len -= sizeof(u16);
630 } else {
631 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
632
633 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
634 spi->rx_len -= sizeof(u8);
635 }
636
637 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
638 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
639 STM32H7_SPI_SR_RXPLVL_SHIFT;
640 }
641
642 dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
643 flush ? "(flush)" : "", spi->rx_len);
644}
645
646
647
648
649
650static void stm32_spi_enable(struct stm32_spi *spi)
651{
652 dev_dbg(spi->dev, "enable controller\n");
653
654 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
655 spi->cfg->regs->en.mask);
656}
657
658
659
660
661
662static void stm32f4_spi_disable(struct stm32_spi *spi)
663{
664 unsigned long flags;
665 u32 sr;
666
667 dev_dbg(spi->dev, "disable controller\n");
668
669 spin_lock_irqsave(&spi->lock, flags);
670
671 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
672 STM32F4_SPI_CR1_SPE)) {
673 spin_unlock_irqrestore(&spi->lock, flags);
674 return;
675 }
676
677
678 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |
679 STM32F4_SPI_CR2_RXNEIE |
680 STM32F4_SPI_CR2_ERRIE);
681
682
683 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
684 sr, !(sr & STM32F4_SPI_SR_BSY),
685 10, 100000) < 0) {
686 dev_warn(spi->dev, "disabling condition timeout\n");
687 }
688
689 if (spi->cur_usedma && spi->dma_tx)
690 dmaengine_terminate_all(spi->dma_tx);
691 if (spi->cur_usedma && spi->dma_rx)
692 dmaengine_terminate_all(spi->dma_rx);
693
694 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
695
696 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
697 STM32F4_SPI_CR2_RXDMAEN);
698
699
700 readl_relaxed(spi->base + STM32F4_SPI_DR);
701 readl_relaxed(spi->base + STM32F4_SPI_SR);
702
703 spin_unlock_irqrestore(&spi->lock, flags);
704}
705
706
707
708
709
710
711
712
713
714
715
716
717
718static void stm32h7_spi_disable(struct stm32_spi *spi)
719{
720 unsigned long flags;
721 u32 cr1, sr;
722
723 dev_dbg(spi->dev, "disable controller\n");
724
725 spin_lock_irqsave(&spi->lock, flags);
726
727 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
728
729 if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
730 spin_unlock_irqrestore(&spi->lock, flags);
731 return;
732 }
733
734
735 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
736 sr, !(sr & STM32H7_SPI_SR_EOT),
737 10, 100000) < 0) {
738 if (cr1 & STM32H7_SPI_CR1_CSTART) {
739 writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP,
740 spi->base + STM32H7_SPI_CR1);
741 if (readl_relaxed_poll_timeout_atomic(
742 spi->base + STM32H7_SPI_SR,
743 sr, !(sr & STM32H7_SPI_SR_SUSP),
744 10, 100000) < 0)
745 dev_warn(spi->dev,
746 "Suspend request timeout\n");
747 }
748 }
749
750 if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
751 stm32h7_spi_read_rxfifo(spi, true);
752
753 if (spi->cur_usedma && spi->dma_tx)
754 dmaengine_terminate_all(spi->dma_tx);
755 if (spi->cur_usedma && spi->dma_rx)
756 dmaengine_terminate_all(spi->dma_rx);
757
758 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
759
760 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
761 STM32H7_SPI_CFG1_RXDMAEN);
762
763
764 writel_relaxed(0, spi->base + STM32H7_SPI_IER);
765 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
766
767 spin_unlock_irqrestore(&spi->lock, flags);
768}
769
770
771
772
773
774
775
776
777
778
779static bool stm32_spi_can_dma(struct spi_master *master,
780 struct spi_device *spi_dev,
781 struct spi_transfer *transfer)
782{
783 unsigned int dma_size;
784 struct stm32_spi *spi = spi_master_get_devdata(master);
785
786 if (spi->cfg->has_fifo)
787 dma_size = spi->fifo_size;
788 else
789 dma_size = SPI_DMA_MIN_BYTES;
790
791 dev_dbg(spi->dev, "%s: %s\n", __func__,
792 (transfer->len > dma_size) ? "true" : "false");
793
794 return (transfer->len > dma_size);
795}
796
797
798
799
800
801
802static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
803{
804 struct spi_master *master = dev_id;
805 struct stm32_spi *spi = spi_master_get_devdata(master);
806 u32 sr, mask = 0;
807 bool end = false;
808
809 spin_lock(&spi->lock);
810
811 sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
812
813
814
815
816 sr &= ~STM32F4_SPI_SR_BSY;
817
818 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
819 spi->cur_comm == SPI_3WIRE_TX)) {
820
821 sr &= ~STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE;
822 mask |= STM32F4_SPI_SR_TXE;
823 }
824
825 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
826 spi->cur_comm == SPI_SIMPLEX_RX ||
827 spi->cur_comm == SPI_3WIRE_RX)) {
828
829 sr &= ~STM32F4_SPI_SR_TXE;
830 mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR;
831 }
832
833 if (!(sr & mask)) {
834 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
835 spin_unlock(&spi->lock);
836 return IRQ_NONE;
837 }
838
839 if (sr & STM32F4_SPI_SR_OVR) {
840 dev_warn(spi->dev, "Overrun: received value discarded\n");
841
842
843 readl_relaxed(spi->base + STM32F4_SPI_DR);
844 readl_relaxed(spi->base + STM32F4_SPI_SR);
845
846
847
848
849
850
851 end = true;
852 goto end_irq;
853 }
854
855 if (sr & STM32F4_SPI_SR_TXE) {
856 if (spi->tx_buf)
857 stm32f4_spi_write_tx(spi);
858 if (spi->tx_len == 0)
859 end = true;
860 }
861
862 if (sr & STM32F4_SPI_SR_RXNE) {
863 stm32f4_spi_read_rx(spi);
864 if (spi->rx_len == 0)
865 end = true;
866 else if (spi->tx_buf)
867 stm32f4_spi_write_tx(spi);
868 }
869
870end_irq:
871 if (end) {
872
873 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
874 STM32F4_SPI_CR2_TXEIE |
875 STM32F4_SPI_CR2_RXNEIE |
876 STM32F4_SPI_CR2_ERRIE);
877 spin_unlock(&spi->lock);
878 return IRQ_WAKE_THREAD;
879 }
880
881 spin_unlock(&spi->lock);
882 return IRQ_HANDLED;
883}
884
885
886
887
888
889
890static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
891{
892 struct spi_master *master = dev_id;
893 struct stm32_spi *spi = spi_master_get_devdata(master);
894
895 spi_finalize_current_transfer(master);
896 stm32f4_spi_disable(spi);
897
898 return IRQ_HANDLED;
899}
900
901
902
903
904
905
906static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
907{
908 struct spi_master *master = dev_id;
909 struct stm32_spi *spi = spi_master_get_devdata(master);
910 u32 sr, ier, mask;
911 unsigned long flags;
912 bool end = false;
913
914 spin_lock_irqsave(&spi->lock, flags);
915
916 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
917 ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
918
919 mask = ier;
920
921 mask |= STM32H7_SPI_SR_SUSP;
922
923
924
925
926
927 if (spi->rx_buf && !spi->cur_usedma)
928 mask |= STM32H7_SPI_SR_RXP;
929
930 if (!(sr & mask)) {
931 dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
932 sr, ier);
933 spin_unlock_irqrestore(&spi->lock, flags);
934 return IRQ_NONE;
935 }
936
937 if (sr & STM32H7_SPI_SR_SUSP) {
938 static DEFINE_RATELIMIT_STATE(rs,
939 DEFAULT_RATELIMIT_INTERVAL * 10,
940 1);
941 if (__ratelimit(&rs))
942 dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
943 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
944 stm32h7_spi_read_rxfifo(spi, false);
945
946
947
948
949 if (spi->cur_usedma)
950 end = true;
951 }
952
953 if (sr & STM32H7_SPI_SR_MODF) {
954 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
955 end = true;
956 }
957
958 if (sr & STM32H7_SPI_SR_OVR) {
959 dev_warn(spi->dev, "Overrun: received value discarded\n");
960 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
961 stm32h7_spi_read_rxfifo(spi, false);
962
963
964
965
966 if (spi->cur_usedma)
967 end = true;
968 }
969
970 if (sr & STM32H7_SPI_SR_EOT) {
971 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
972 stm32h7_spi_read_rxfifo(spi, true);
973 end = true;
974 }
975
976 if (sr & STM32H7_SPI_SR_TXP)
977 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
978 stm32h7_spi_write_txfifo(spi);
979
980 if (sr & STM32H7_SPI_SR_RXP)
981 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
982 stm32h7_spi_read_rxfifo(spi, false);
983
984 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
985
986 spin_unlock_irqrestore(&spi->lock, flags);
987
988 if (end) {
989 stm32h7_spi_disable(spi);
990 spi_finalize_current_transfer(master);
991 }
992
993 return IRQ_HANDLED;
994}
995
996
997
998
999
1000
1001static int stm32_spi_prepare_msg(struct spi_master *master,
1002 struct spi_message *msg)
1003{
1004 struct stm32_spi *spi = spi_master_get_devdata(master);
1005 struct spi_device *spi_dev = msg->spi;
1006 struct device_node *np = spi_dev->dev.of_node;
1007 unsigned long flags;
1008 u32 clrb = 0, setb = 0;
1009
1010
1011 spi->cur_midi = 0;
1012 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
1013 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
1014
1015 if (spi_dev->mode & SPI_CPOL)
1016 setb |= spi->cfg->regs->cpol.mask;
1017 else
1018 clrb |= spi->cfg->regs->cpol.mask;
1019
1020 if (spi_dev->mode & SPI_CPHA)
1021 setb |= spi->cfg->regs->cpha.mask;
1022 else
1023 clrb |= spi->cfg->regs->cpha.mask;
1024
1025 if (spi_dev->mode & SPI_LSB_FIRST)
1026 setb |= spi->cfg->regs->lsb_first.mask;
1027 else
1028 clrb |= spi->cfg->regs->lsb_first.mask;
1029
1030 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
1031 spi_dev->mode & SPI_CPOL,
1032 spi_dev->mode & SPI_CPHA,
1033 spi_dev->mode & SPI_LSB_FIRST,
1034 spi_dev->mode & SPI_CS_HIGH);
1035
1036 spin_lock_irqsave(&spi->lock, flags);
1037
1038
1039 if (clrb || setb)
1040 writel_relaxed(
1041 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
1042 ~clrb) | setb,
1043 spi->base + spi->cfg->regs->cpol.reg);
1044
1045 spin_unlock_irqrestore(&spi->lock, flags);
1046
1047 return 0;
1048}
1049
1050
1051
1052
1053
1054
1055
1056static void stm32f4_spi_dma_tx_cb(void *data)
1057{
1058 struct stm32_spi *spi = data;
1059
1060 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1061 spi_finalize_current_transfer(spi->master);
1062 stm32f4_spi_disable(spi);
1063 }
1064}
1065
1066
1067
1068
1069
1070
1071
1072static void stm32f4_spi_dma_rx_cb(void *data)
1073{
1074 struct stm32_spi *spi = data;
1075
1076 spi_finalize_current_transfer(spi->master);
1077 stm32f4_spi_disable(spi);
1078}
1079
1080
1081
1082
1083
1084
1085
1086
1087static void stm32h7_spi_dma_cb(void *data)
1088{
1089 struct stm32_spi *spi = data;
1090 unsigned long flags;
1091 u32 sr;
1092
1093 spin_lock_irqsave(&spi->lock, flags);
1094
1095 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
1096
1097 spin_unlock_irqrestore(&spi->lock, flags);
1098
1099 if (!(sr & STM32H7_SPI_SR_EOT))
1100 dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
1101
1102
1103}
1104
1105
1106
1107
1108
1109
1110
1111
1112static void stm32_spi_dma_config(struct stm32_spi *spi,
1113 struct dma_slave_config *dma_conf,
1114 enum dma_transfer_direction dir)
1115{
1116 enum dma_slave_buswidth buswidth;
1117 u32 maxburst;
1118
1119 if (spi->cur_bpw <= 8)
1120 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1121 else if (spi->cur_bpw <= 16)
1122 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1123 else
1124 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1125
1126 if (spi->cfg->has_fifo) {
1127
1128 if (spi->cur_fthlv == 2)
1129 maxburst = 1;
1130 else
1131 maxburst = spi->cur_fthlv;
1132 } else {
1133 maxburst = 1;
1134 }
1135
1136 memset(dma_conf, 0, sizeof(struct dma_slave_config));
1137 dma_conf->direction = dir;
1138 if (dma_conf->direction == DMA_DEV_TO_MEM) {
1139 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
1140 dma_conf->src_addr_width = buswidth;
1141 dma_conf->src_maxburst = maxburst;
1142
1143 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
1144 buswidth, maxburst);
1145 } else if (dma_conf->direction == DMA_MEM_TO_DEV) {
1146 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
1147 dma_conf->dst_addr_width = buswidth;
1148 dma_conf->dst_maxburst = maxburst;
1149
1150 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
1151 buswidth, maxburst);
1152 }
1153}
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
1164{
1165 unsigned long flags;
1166 u32 cr2 = 0;
1167
1168
1169 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1170 cr2 |= STM32F4_SPI_CR2_TXEIE;
1171 } else if (spi->cur_comm == SPI_FULL_DUPLEX ||
1172 spi->cur_comm == SPI_SIMPLEX_RX ||
1173 spi->cur_comm == SPI_3WIRE_RX) {
1174
1175
1176
1177
1178 cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE;
1179 } else {
1180 return -EINVAL;
1181 }
1182
1183 spin_lock_irqsave(&spi->lock, flags);
1184
1185 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
1186
1187 stm32_spi_enable(spi);
1188
1189
1190 if (spi->tx_buf)
1191 stm32f4_spi_write_tx(spi);
1192
1193 spin_unlock_irqrestore(&spi->lock, flags);
1194
1195 return 1;
1196}
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
1207{
1208 unsigned long flags;
1209 u32 ier = 0;
1210
1211
1212 if (spi->tx_buf && spi->rx_buf)
1213 ier |= STM32H7_SPI_IER_DXPIE;
1214 else if (spi->tx_buf)
1215 ier |= STM32H7_SPI_IER_TXPIE;
1216 else if (spi->rx_buf)
1217 ier |= STM32H7_SPI_IER_RXPIE;
1218
1219
1220 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
1221 STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1222
1223 spin_lock_irqsave(&spi->lock, flags);
1224
1225 stm32_spi_enable(spi);
1226
1227
1228 if (spi->tx_buf)
1229 stm32h7_spi_write_txfifo(spi);
1230
1231 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1232
1233 writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
1234
1235 spin_unlock_irqrestore(&spi->lock, flags);
1236
1237 return 1;
1238}
1239
1240
1241
1242
1243
1244
1245static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
1246{
1247
1248 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
1249 spi->cur_comm == SPI_FULL_DUPLEX) {
1250
1251
1252
1253
1254
1255 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
1256 }
1257
1258 stm32_spi_enable(spi);
1259}
1260
1261
1262
1263
1264
1265
1266static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
1267{
1268
1269 stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE |
1270 STM32H7_SPI_IER_TXTFIE |
1271 STM32H7_SPI_IER_OVRIE |
1272 STM32H7_SPI_IER_MODFIE);
1273
1274 stm32_spi_enable(spi);
1275
1276 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1277}
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
1288 struct spi_transfer *xfer)
1289{
1290 struct dma_slave_config tx_dma_conf, rx_dma_conf;
1291 struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
1292 unsigned long flags;
1293
1294 spin_lock_irqsave(&spi->lock, flags);
1295
1296 rx_dma_desc = NULL;
1297 if (spi->rx_buf && spi->dma_rx) {
1298 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
1299 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1300
1301
1302 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1303 spi->cfg->regs->dma_rx_en.mask);
1304
1305 rx_dma_desc = dmaengine_prep_slave_sg(
1306 spi->dma_rx, xfer->rx_sg.sgl,
1307 xfer->rx_sg.nents,
1308 rx_dma_conf.direction,
1309 DMA_PREP_INTERRUPT);
1310 }
1311
1312 tx_dma_desc = NULL;
1313 if (spi->tx_buf && spi->dma_tx) {
1314 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
1315 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
1316
1317 tx_dma_desc = dmaengine_prep_slave_sg(
1318 spi->dma_tx, xfer->tx_sg.sgl,
1319 xfer->tx_sg.nents,
1320 tx_dma_conf.direction,
1321 DMA_PREP_INTERRUPT);
1322 }
1323
1324 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
1325 (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
1326 goto dma_desc_error;
1327
1328 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
1329 goto dma_desc_error;
1330
1331 if (rx_dma_desc) {
1332 rx_dma_desc->callback = spi->cfg->dma_rx_cb;
1333 rx_dma_desc->callback_param = spi;
1334
1335 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
1336 dev_err(spi->dev, "Rx DMA submit failed\n");
1337 goto dma_desc_error;
1338 }
1339
1340 dma_async_issue_pending(spi->dma_rx);
1341 }
1342
1343 if (tx_dma_desc) {
1344 if (spi->cur_comm == SPI_SIMPLEX_TX ||
1345 spi->cur_comm == SPI_3WIRE_TX) {
1346 tx_dma_desc->callback = spi->cfg->dma_tx_cb;
1347 tx_dma_desc->callback_param = spi;
1348 }
1349
1350 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
1351 dev_err(spi->dev, "Tx DMA submit failed\n");
1352 goto dma_submit_error;
1353 }
1354
1355 dma_async_issue_pending(spi->dma_tx);
1356
1357
1358 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
1359 spi->cfg->regs->dma_tx_en.mask);
1360 }
1361
1362 spi->cfg->transfer_one_dma_start(spi);
1363
1364 spin_unlock_irqrestore(&spi->lock, flags);
1365
1366 return 1;
1367
1368dma_submit_error:
1369 if (spi->dma_rx)
1370 dmaengine_terminate_all(spi->dma_rx);
1371
1372dma_desc_error:
1373 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1374 spi->cfg->regs->dma_rx_en.mask);
1375
1376 spin_unlock_irqrestore(&spi->lock, flags);
1377
1378 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
1379
1380 spi->cur_usedma = false;
1381 return spi->cfg->transfer_one_irq(spi);
1382}
1383
1384
1385
1386
1387
1388static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
1389{
1390 if (spi->cur_bpw == 16)
1391 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1392 else
1393 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1394}
1395
1396
1397
1398
1399
1400static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
1401{
1402 u32 bpw, fthlv;
1403 u32 cfg1_clrb = 0, cfg1_setb = 0;
1404
1405 bpw = spi->cur_bpw - 1;
1406
1407 cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
1408 cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
1409 STM32H7_SPI_CFG1_DSIZE;
1410
1411 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
1412 fthlv = spi->cur_fthlv - 1;
1413
1414 cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
1415 cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
1416 STM32H7_SPI_CFG1_FTHLV;
1417
1418 writel_relaxed(
1419 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
1420 ~cfg1_clrb) | cfg1_setb,
1421 spi->base + STM32H7_SPI_CFG1);
1422}
1423
1424
1425
1426
1427
1428
1429static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
1430{
1431 u32 clrb = 0, setb = 0;
1432
1433 clrb |= spi->cfg->regs->br.mask;
1434 setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) &
1435 spi->cfg->regs->br.mask;
1436
1437 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
1438 ~clrb) | setb,
1439 spi->base + spi->cfg->regs->br.reg);
1440}
1441
1442
1443
1444
1445
1446
1447static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
1448 struct spi_transfer *transfer)
1449{
1450 unsigned int type = SPI_FULL_DUPLEX;
1451
1452 if (spi_dev->mode & SPI_3WIRE) {
1453
1454
1455
1456
1457
1458
1459 if (!transfer->tx_buf)
1460 type = SPI_3WIRE_RX;
1461 else
1462 type = SPI_3WIRE_TX;
1463 } else {
1464 if (!transfer->tx_buf)
1465 type = SPI_SIMPLEX_RX;
1466 else if (!transfer->rx_buf)
1467 type = SPI_SIMPLEX_TX;
1468 }
1469
1470 return type;
1471}
1472
1473
1474
1475
1476
1477
1478static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1479{
1480 if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) {
1481 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1482 STM32F4_SPI_CR1_BIDIMODE |
1483 STM32F4_SPI_CR1_BIDIOE);
1484 } else if (comm_type == SPI_FULL_DUPLEX ||
1485 comm_type == SPI_SIMPLEX_RX) {
1486 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1487 STM32F4_SPI_CR1_BIDIMODE |
1488 STM32F4_SPI_CR1_BIDIOE);
1489 } else if (comm_type == SPI_3WIRE_RX) {
1490 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1491 STM32F4_SPI_CR1_BIDIMODE);
1492 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1493 STM32F4_SPI_CR1_BIDIOE);
1494 } else {
1495 return -EINVAL;
1496 }
1497
1498 return 0;
1499}
1500
1501
1502
1503
1504
1505
1506static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1507{
1508 u32 mode;
1509 u32 cfg2_clrb = 0, cfg2_setb = 0;
1510
1511 if (comm_type == SPI_3WIRE_RX) {
1512 mode = STM32H7_SPI_HALF_DUPLEX;
1513 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1514 } else if (comm_type == SPI_3WIRE_TX) {
1515 mode = STM32H7_SPI_HALF_DUPLEX;
1516 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1517 } else if (comm_type == SPI_SIMPLEX_RX) {
1518 mode = STM32H7_SPI_SIMPLEX_RX;
1519 } else if (comm_type == SPI_SIMPLEX_TX) {
1520 mode = STM32H7_SPI_SIMPLEX_TX;
1521 } else {
1522 mode = STM32H7_SPI_FULL_DUPLEX;
1523 }
1524
1525 cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
1526 cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
1527 STM32H7_SPI_CFG2_COMM;
1528
1529 writel_relaxed(
1530 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1531 ~cfg2_clrb) | cfg2_setb,
1532 spi->base + STM32H7_SPI_CFG2);
1533
1534 return 0;
1535}
1536
1537
1538
1539
1540
1541
1542
1543static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
1544{
1545 u32 cfg2_clrb = 0, cfg2_setb = 0;
1546
1547 cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
1548 if ((len > 1) && (spi->cur_midi > 0)) {
1549 u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
1550 u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
1551 (u32)STM32H7_SPI_CFG2_MIDI >>
1552 STM32H7_SPI_CFG2_MIDI_SHIFT);
1553
1554 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
1555 sck_period_ns, midi, midi * sck_period_ns);
1556 cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
1557 STM32H7_SPI_CFG2_MIDI;
1558 }
1559
1560 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1561 ~cfg2_clrb) | cfg2_setb,
1562 spi->base + STM32H7_SPI_CFG2);
1563}
1564
1565
1566
1567
1568
1569
1570static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
1571{
1572 u32 cr2_clrb = 0, cr2_setb = 0;
1573
1574 if (nb_words <= (STM32H7_SPI_CR2_TSIZE >>
1575 STM32H7_SPI_CR2_TSIZE_SHIFT)) {
1576 cr2_clrb |= STM32H7_SPI_CR2_TSIZE;
1577 cr2_setb = nb_words << STM32H7_SPI_CR2_TSIZE_SHIFT;
1578 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) &
1579 ~cr2_clrb) | cr2_setb,
1580 spi->base + STM32H7_SPI_CR2);
1581 } else {
1582 return -EMSGSIZE;
1583 }
1584
1585 return 0;
1586}
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
1597 struct spi_device *spi_dev,
1598 struct spi_transfer *transfer)
1599{
1600 unsigned long flags;
1601 unsigned int comm_type;
1602 int nb_words, ret = 0;
1603 int mbr;
1604
1605 spin_lock_irqsave(&spi->lock, flags);
1606
1607 spi->cur_xferlen = transfer->len;
1608
1609 spi->cur_bpw = transfer->bits_per_word;
1610 spi->cfg->set_bpw(spi);
1611
1612
1613 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
1614 spi->cfg->baud_rate_div_min,
1615 spi->cfg->baud_rate_div_max);
1616 if (mbr < 0) {
1617 ret = mbr;
1618 goto out;
1619 }
1620
1621 transfer->speed_hz = spi->cur_speed;
1622 stm32_spi_set_mbr(spi, mbr);
1623
1624 comm_type = stm32_spi_communication_type(spi_dev, transfer);
1625 ret = spi->cfg->set_mode(spi, comm_type);
1626 if (ret < 0)
1627 goto out;
1628
1629 spi->cur_comm = comm_type;
1630
1631 if (spi->cfg->set_data_idleness)
1632 spi->cfg->set_data_idleness(spi, transfer->len);
1633
1634 if (spi->cur_bpw <= 8)
1635 nb_words = transfer->len;
1636 else if (spi->cur_bpw <= 16)
1637 nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
1638 else
1639 nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
1640
1641 if (spi->cfg->set_number_of_data) {
1642 ret = spi->cfg->set_number_of_data(spi, nb_words);
1643 if (ret < 0)
1644 goto out;
1645 }
1646
1647 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
1648 spi->cur_comm);
1649 dev_dbg(spi->dev,
1650 "data frame of %d-bit, data packet of %d data frames\n",
1651 spi->cur_bpw, spi->cur_fthlv);
1652 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
1653 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
1654 spi->cur_xferlen, nb_words);
1655 dev_dbg(spi->dev, "dma %s\n",
1656 (spi->cur_usedma) ? "enabled" : "disabled");
1657
1658out:
1659 spin_unlock_irqrestore(&spi->lock, flags);
1660
1661 return ret;
1662}
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673static int stm32_spi_transfer_one(struct spi_master *master,
1674 struct spi_device *spi_dev,
1675 struct spi_transfer *transfer)
1676{
1677 struct stm32_spi *spi = spi_master_get_devdata(master);
1678 int ret;
1679
1680 spi->tx_buf = transfer->tx_buf;
1681 spi->rx_buf = transfer->rx_buf;
1682 spi->tx_len = spi->tx_buf ? transfer->len : 0;
1683 spi->rx_len = spi->rx_buf ? transfer->len : 0;
1684
1685 spi->cur_usedma = (master->can_dma &&
1686 master->can_dma(master, spi_dev, transfer));
1687
1688 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1689 if (ret) {
1690 dev_err(spi->dev, "SPI transfer setup failed\n");
1691 return ret;
1692 }
1693
1694 if (spi->cur_usedma)
1695 return stm32_spi_transfer_one_dma(spi, transfer);
1696 else
1697 return spi->cfg->transfer_one_irq(spi);
1698}
1699
1700
1701
1702
1703
1704
1705static int stm32_spi_unprepare_msg(struct spi_master *master,
1706 struct spi_message *msg)
1707{
1708 struct stm32_spi *spi = spi_master_get_devdata(master);
1709
1710 spi->cfg->disable(spi);
1711
1712 return 0;
1713}
1714
1715
1716
1717
1718
1719static int stm32f4_spi_config(struct stm32_spi *spi)
1720{
1721 unsigned long flags;
1722
1723 spin_lock_irqsave(&spi->lock, flags);
1724
1725
1726 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
1727 STM32F4_SPI_I2SCFGR_I2SMOD);
1728
1729
1730
1731
1732
1733
1734
1735
1736 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
1737 STM32F4_SPI_CR1_BIDIOE |
1738 STM32F4_SPI_CR1_MSTR |
1739 STM32F4_SPI_CR1_SSM);
1740
1741 spin_unlock_irqrestore(&spi->lock, flags);
1742
1743 return 0;
1744}
1745
1746
1747
1748
1749
1750static int stm32h7_spi_config(struct stm32_spi *spi)
1751{
1752 unsigned long flags;
1753
1754 spin_lock_irqsave(&spi->lock, flags);
1755
1756
1757 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
1758 STM32H7_SPI_I2SCFGR_I2SMOD);
1759
1760
1761
1762
1763
1764
1765 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI |
1766 STM32H7_SPI_CR1_HDDIR |
1767 STM32H7_SPI_CR1_MASRX);
1768
1769
1770
1771
1772
1773
1774
1775 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER |
1776 STM32H7_SPI_CFG2_SSM |
1777 STM32H7_SPI_CFG2_AFCNTR);
1778
1779 spin_unlock_irqrestore(&spi->lock, flags);
1780
1781 return 0;
1782}
1783
1784static const struct stm32_spi_cfg stm32f4_spi_cfg = {
1785 .regs = &stm32f4_spi_regspec,
1786 .get_bpw_mask = stm32f4_spi_get_bpw_mask,
1787 .disable = stm32f4_spi_disable,
1788 .config = stm32f4_spi_config,
1789 .set_bpw = stm32f4_spi_set_bpw,
1790 .set_mode = stm32f4_spi_set_mode,
1791 .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start,
1792 .dma_tx_cb = stm32f4_spi_dma_tx_cb,
1793 .dma_rx_cb = stm32f4_spi_dma_rx_cb,
1794 .transfer_one_irq = stm32f4_spi_transfer_one_irq,
1795 .irq_handler_event = stm32f4_spi_irq_event,
1796 .irq_handler_thread = stm32f4_spi_irq_thread,
1797 .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN,
1798 .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX,
1799 .has_fifo = false,
1800};
1801
1802static const struct stm32_spi_cfg stm32h7_spi_cfg = {
1803 .regs = &stm32h7_spi_regspec,
1804 .get_fifo_size = stm32h7_spi_get_fifo_size,
1805 .get_bpw_mask = stm32h7_spi_get_bpw_mask,
1806 .disable = stm32h7_spi_disable,
1807 .config = stm32h7_spi_config,
1808 .set_bpw = stm32h7_spi_set_bpw,
1809 .set_mode = stm32h7_spi_set_mode,
1810 .set_data_idleness = stm32h7_spi_data_idleness,
1811 .set_number_of_data = stm32h7_spi_number_of_data,
1812 .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
1813 .dma_rx_cb = stm32h7_spi_dma_cb,
1814 .dma_tx_cb = stm32h7_spi_dma_cb,
1815 .transfer_one_irq = stm32h7_spi_transfer_one_irq,
1816 .irq_handler_thread = stm32h7_spi_irq_thread,
1817 .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
1818 .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
1819 .has_fifo = true,
1820};
1821
1822static const struct of_device_id stm32_spi_of_match[] = {
1823 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1824 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1825 {},
1826};
1827MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
1828
1829static int stm32_spi_probe(struct platform_device *pdev)
1830{
1831 struct spi_master *master;
1832 struct stm32_spi *spi;
1833 struct resource *res;
1834 int ret;
1835
1836 master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
1837 if (!master) {
1838 dev_err(&pdev->dev, "spi master allocation failed\n");
1839 return -ENOMEM;
1840 }
1841 platform_set_drvdata(pdev, master);
1842
1843 spi = spi_master_get_devdata(master);
1844 spi->dev = &pdev->dev;
1845 spi->master = master;
1846 spin_lock_init(&spi->lock);
1847
1848 spi->cfg = (const struct stm32_spi_cfg *)
1849 of_match_device(pdev->dev.driver->of_match_table,
1850 &pdev->dev)->data;
1851
1852 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1853 spi->base = devm_ioremap_resource(&pdev->dev, res);
1854 if (IS_ERR(spi->base)) {
1855 ret = PTR_ERR(spi->base);
1856 goto err_master_put;
1857 }
1858
1859 spi->phys_addr = (dma_addr_t)res->start;
1860
1861 spi->irq = platform_get_irq(pdev, 0);
1862 if (spi->irq <= 0) {
1863 ret = dev_err_probe(&pdev->dev, spi->irq, "failed to get irq\n");
1864 goto err_master_put;
1865 }
1866 ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
1867 spi->cfg->irq_handler_event,
1868 spi->cfg->irq_handler_thread,
1869 IRQF_ONESHOT, pdev->name, master);
1870 if (ret) {
1871 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1872 ret);
1873 goto err_master_put;
1874 }
1875
1876 spi->clk = devm_clk_get(&pdev->dev, NULL);
1877 if (IS_ERR(spi->clk)) {
1878 ret = PTR_ERR(spi->clk);
1879 dev_err(&pdev->dev, "clk get failed: %d\n", ret);
1880 goto err_master_put;
1881 }
1882
1883 ret = clk_prepare_enable(spi->clk);
1884 if (ret) {
1885 dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
1886 goto err_master_put;
1887 }
1888 spi->clk_rate = clk_get_rate(spi->clk);
1889 if (!spi->clk_rate) {
1890 dev_err(&pdev->dev, "clk rate = 0\n");
1891 ret = -EINVAL;
1892 goto err_clk_disable;
1893 }
1894
1895 spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1896 if (!IS_ERR(spi->rst)) {
1897 reset_control_assert(spi->rst);
1898 udelay(2);
1899 reset_control_deassert(spi->rst);
1900 }
1901
1902 if (spi->cfg->has_fifo)
1903 spi->fifo_size = spi->cfg->get_fifo_size(spi);
1904
1905 ret = spi->cfg->config(spi);
1906 if (ret) {
1907 dev_err(&pdev->dev, "controller configuration failed: %d\n",
1908 ret);
1909 goto err_clk_disable;
1910 }
1911
1912 master->dev.of_node = pdev->dev.of_node;
1913 master->auto_runtime_pm = true;
1914 master->bus_num = pdev->id;
1915 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
1916 SPI_3WIRE;
1917 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
1918 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
1919 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
1920 master->use_gpio_descriptors = true;
1921 master->prepare_message = stm32_spi_prepare_msg;
1922 master->transfer_one = stm32_spi_transfer_one;
1923 master->unprepare_message = stm32_spi_unprepare_msg;
1924 master->flags = SPI_MASTER_MUST_TX;
1925
1926 spi->dma_tx = dma_request_chan(spi->dev, "tx");
1927 if (IS_ERR(spi->dma_tx)) {
1928 ret = PTR_ERR(spi->dma_tx);
1929 spi->dma_tx = NULL;
1930 if (ret == -EPROBE_DEFER)
1931 goto err_clk_disable;
1932
1933 dev_warn(&pdev->dev, "failed to request tx dma channel\n");
1934 } else {
1935 master->dma_tx = spi->dma_tx;
1936 }
1937
1938 spi->dma_rx = dma_request_chan(spi->dev, "rx");
1939 if (IS_ERR(spi->dma_rx)) {
1940 ret = PTR_ERR(spi->dma_rx);
1941 spi->dma_rx = NULL;
1942 if (ret == -EPROBE_DEFER)
1943 goto err_dma_release;
1944
1945 dev_warn(&pdev->dev, "failed to request rx dma channel\n");
1946 } else {
1947 master->dma_rx = spi->dma_rx;
1948 }
1949
1950 if (spi->dma_tx || spi->dma_rx)
1951 master->can_dma = stm32_spi_can_dma;
1952
1953 pm_runtime_set_active(&pdev->dev);
1954 pm_runtime_enable(&pdev->dev);
1955
1956 ret = devm_spi_register_master(&pdev->dev, master);
1957 if (ret) {
1958 dev_err(&pdev->dev, "spi master registration failed: %d\n",
1959 ret);
1960 goto err_pm_disable;
1961 }
1962
1963 if (!master->cs_gpiods) {
1964 dev_err(&pdev->dev, "no CS gpios available\n");
1965 ret = -EINVAL;
1966 goto err_pm_disable;
1967 }
1968
1969 dev_info(&pdev->dev, "driver initialized\n");
1970
1971 return 0;
1972
1973err_pm_disable:
1974 pm_runtime_disable(&pdev->dev);
1975err_dma_release:
1976 if (spi->dma_tx)
1977 dma_release_channel(spi->dma_tx);
1978 if (spi->dma_rx)
1979 dma_release_channel(spi->dma_rx);
1980err_clk_disable:
1981 clk_disable_unprepare(spi->clk);
1982err_master_put:
1983 spi_master_put(master);
1984
1985 return ret;
1986}
1987
1988static int stm32_spi_remove(struct platform_device *pdev)
1989{
1990 struct spi_master *master = platform_get_drvdata(pdev);
1991 struct stm32_spi *spi = spi_master_get_devdata(master);
1992
1993 spi->cfg->disable(spi);
1994
1995 if (master->dma_tx)
1996 dma_release_channel(master->dma_tx);
1997 if (master->dma_rx)
1998 dma_release_channel(master->dma_rx);
1999
2000 clk_disable_unprepare(spi->clk);
2001
2002 pm_runtime_disable(&pdev->dev);
2003
2004 pinctrl_pm_select_sleep_state(&pdev->dev);
2005
2006 return 0;
2007}
2008
2009#ifdef CONFIG_PM
2010static int stm32_spi_runtime_suspend(struct device *dev)
2011{
2012 struct spi_master *master = dev_get_drvdata(dev);
2013 struct stm32_spi *spi = spi_master_get_devdata(master);
2014
2015 clk_disable_unprepare(spi->clk);
2016
2017 return pinctrl_pm_select_sleep_state(dev);
2018}
2019
2020static int stm32_spi_runtime_resume(struct device *dev)
2021{
2022 struct spi_master *master = dev_get_drvdata(dev);
2023 struct stm32_spi *spi = spi_master_get_devdata(master);
2024 int ret;
2025
2026 ret = pinctrl_pm_select_default_state(dev);
2027 if (ret)
2028 return ret;
2029
2030 return clk_prepare_enable(spi->clk);
2031}
2032#endif
2033
2034#ifdef CONFIG_PM_SLEEP
2035static int stm32_spi_suspend(struct device *dev)
2036{
2037 struct spi_master *master = dev_get_drvdata(dev);
2038 int ret;
2039
2040 ret = spi_master_suspend(master);
2041 if (ret)
2042 return ret;
2043
2044 return pm_runtime_force_suspend(dev);
2045}
2046
2047static int stm32_spi_resume(struct device *dev)
2048{
2049 struct spi_master *master = dev_get_drvdata(dev);
2050 struct stm32_spi *spi = spi_master_get_devdata(master);
2051 int ret;
2052
2053 ret = pm_runtime_force_resume(dev);
2054 if (ret)
2055 return ret;
2056
2057 ret = spi_master_resume(master);
2058 if (ret) {
2059 clk_disable_unprepare(spi->clk);
2060 return ret;
2061 }
2062
2063 ret = pm_runtime_get_sync(dev);
2064 if (ret < 0) {
2065 dev_err(dev, "Unable to power device:%d\n", ret);
2066 return ret;
2067 }
2068
2069 spi->cfg->config(spi);
2070
2071 pm_runtime_mark_last_busy(dev);
2072 pm_runtime_put_autosuspend(dev);
2073
2074 return 0;
2075}
2076#endif
2077
2078static const struct dev_pm_ops stm32_spi_pm_ops = {
2079 SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
2080 SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
2081 stm32_spi_runtime_resume, NULL)
2082};
2083
2084static struct platform_driver stm32_spi_driver = {
2085 .probe = stm32_spi_probe,
2086 .remove = stm32_spi_remove,
2087 .driver = {
2088 .name = DRIVER_NAME,
2089 .pm = &stm32_spi_pm_ops,
2090 .of_match_table = stm32_spi_of_match,
2091 },
2092};
2093
2094module_platform_driver(stm32_spi_driver);
2095
2096MODULE_ALIAS("platform:" DRIVER_NAME);
2097MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
2098MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
2099MODULE_LICENSE("GPL v2");
2100