linux/drivers/usb/host/xhci-ring.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * xHCI host controller driver
   4 *
   5 * Copyright (C) 2008 Intel Corp.
   6 *
   7 * Author: Sarah Sharp
   8 * Some code borrowed from the Linux EHCI driver.
   9 */
  10
  11/*
  12 * Ring initialization rules:
  13 * 1. Each segment is initialized to zero, except for link TRBs.
  14 * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  15 *    Consumer Cycle State (CCS), depending on ring function.
  16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  17 *
  18 * Ring behavior rules:
  19 * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  20 *    least one free TRB in the ring.  This is useful if you want to turn that
  21 *    into a link TRB and expand the ring.
  22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  23 *    link TRB, then load the pointer with the address in the link TRB.  If the
  24 *    link TRB had its toggle bit set, you may need to update the ring cycle
  25 *    state (see cycle bit rules).  You may have to do this multiple times
  26 *    until you reach a non-link TRB.
  27 * 3. A ring is full if enqueue++ (for the definition of increment above)
  28 *    equals the dequeue pointer.
  29 *
  30 * Cycle bit rules:
  31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  32 *    in a link TRB, it must toggle the ring cycle state.
  33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  34 *    in a link TRB, it must toggle the ring cycle state.
  35 *
  36 * Producer rules:
  37 * 1. Check if ring is full before you enqueue.
  38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  39 *    Update enqueue pointer between each write (which may update the ring
  40 *    cycle state).
  41 * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  42 *    and endpoint rings.  If HC is the producer for the event ring,
  43 *    and it generates an interrupt according to interrupt modulation rules.
  44 *
  45 * Consumer rules:
  46 * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  47 *    the TRB is owned by the consumer.
  48 * 2. Update dequeue pointer (which may update the ring cycle state) and
  49 *    continue processing TRBs until you reach a TRB which is not owned by you.
  50 * 3. Notify the producer.  SW is the consumer for the event ring, and it
  51 *   updates event ring dequeue pointer.  HC is the consumer for the command and
  52 *   endpoint rings; it generates events on the event ring for these.
  53 */
  54
  55#include <linux/scatterlist.h>
  56#include <linux/slab.h>
  57#include <linux/dma-mapping.h>
  58#include "xhci.h"
  59#include "xhci-trace.h"
  60#include "xhci-mtk.h"
  61
  62/*
  63 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  64 * address of the TRB.
  65 */
  66dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  67                union xhci_trb *trb)
  68{
  69        unsigned long segment_offset;
  70
  71        if (!seg || !trb || trb < seg->trbs)
  72                return 0;
  73        /* offset in TRBs */
  74        segment_offset = trb - seg->trbs;
  75        if (segment_offset >= TRBS_PER_SEGMENT)
  76                return 0;
  77        return seg->dma + (segment_offset * sizeof(*trb));
  78}
  79
  80static bool trb_is_noop(union xhci_trb *trb)
  81{
  82        return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
  83}
  84
  85static bool trb_is_link(union xhci_trb *trb)
  86{
  87        return TRB_TYPE_LINK_LE32(trb->link.control);
  88}
  89
  90static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
  91{
  92        return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
  93}
  94
  95static bool last_trb_on_ring(struct xhci_ring *ring,
  96                        struct xhci_segment *seg, union xhci_trb *trb)
  97{
  98        return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
  99}
 100
 101static bool link_trb_toggles_cycle(union xhci_trb *trb)
 102{
 103        return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104}
 105
 106static bool last_td_in_urb(struct xhci_td *td)
 107{
 108        struct urb_priv *urb_priv = td->urb->hcpriv;
 109
 110        return urb_priv->num_tds_done == urb_priv->num_tds;
 111}
 112
 113static void inc_td_cnt(struct urb *urb)
 114{
 115        struct urb_priv *urb_priv = urb->hcpriv;
 116
 117        urb_priv->num_tds_done++;
 118}
 119
 120static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
 121{
 122        if (trb_is_link(trb)) {
 123                /* unchain chained link TRBs */
 124                trb->link.control &= cpu_to_le32(~TRB_CHAIN);
 125        } else {
 126                trb->generic.field[0] = 0;
 127                trb->generic.field[1] = 0;
 128                trb->generic.field[2] = 0;
 129                /* Preserve only the cycle bit of this TRB */
 130                trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 131                trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
 132        }
 133}
 134
 135/* Updates trb to point to the next TRB in the ring, and updates seg if the next
 136 * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 137 * effect the ring dequeue or enqueue pointers.
 138 */
 139static void next_trb(struct xhci_hcd *xhci,
 140                struct xhci_ring *ring,
 141                struct xhci_segment **seg,
 142                union xhci_trb **trb)
 143{
 144        if (trb_is_link(*trb)) {
 145                *seg = (*seg)->next;
 146                *trb = ((*seg)->trbs);
 147        } else {
 148                (*trb)++;
 149        }
 150}
 151
 152/*
 153 * See Cycle bit rules. SW is the consumer for the event ring only.
 154 * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 155 */
 156void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 157{
 158        /* event ring doesn't have link trbs, check for last trb */
 159        if (ring->type == TYPE_EVENT) {
 160                if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
 161                        ring->dequeue++;
 162                        goto out;
 163                }
 164                if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
 165                        ring->cycle_state ^= 1;
 166                ring->deq_seg = ring->deq_seg->next;
 167                ring->dequeue = ring->deq_seg->trbs;
 168                goto out;
 169        }
 170
 171        /* All other rings have link trbs */
 172        if (!trb_is_link(ring->dequeue)) {
 173                ring->dequeue++;
 174                ring->num_trbs_free++;
 175        }
 176        while (trb_is_link(ring->dequeue)) {
 177                ring->deq_seg = ring->deq_seg->next;
 178                ring->dequeue = ring->deq_seg->trbs;
 179        }
 180
 181out:
 182        trace_xhci_inc_deq(ring);
 183
 184        return;
 185}
 186
 187/*
 188 * See Cycle bit rules. SW is the consumer for the event ring only.
 189 * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 190 *
 191 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 192 * chain bit is set), then set the chain bit in all the following link TRBs.
 193 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 194 * have their chain bit cleared (so that each Link TRB is a separate TD).
 195 *
 196 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 197 * set, but other sections talk about dealing with the chain bit set.  This was
 198 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 199 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 200 *
 201 * @more_trbs_coming:   Will you enqueue more TRBs before calling
 202 *                      prepare_transfer()?
 203 */
 204static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 205                        bool more_trbs_coming)
 206{
 207        u32 chain;
 208        union xhci_trb *next;
 209
 210        chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 211        /* If this is not event ring, there is one less usable TRB */
 212        if (!trb_is_link(ring->enqueue))
 213                ring->num_trbs_free--;
 214        next = ++(ring->enqueue);
 215
 216        /* Update the dequeue pointer further if that was a link TRB */
 217        while (trb_is_link(next)) {
 218
 219                /*
 220                 * If the caller doesn't plan on enqueueing more TDs before
 221                 * ringing the doorbell, then we don't want to give the link TRB
 222                 * to the hardware just yet. We'll give the link TRB back in
 223                 * prepare_ring() just before we enqueue the TD at the top of
 224                 * the ring.
 225                 */
 226                if (!chain && !more_trbs_coming)
 227                        break;
 228
 229                /* If we're not dealing with 0.95 hardware or isoc rings on
 230                 * AMD 0.96 host, carry over the chain bit of the previous TRB
 231                 * (which may mean the chain bit is cleared).
 232                 */
 233                if (!(ring->type == TYPE_ISOC &&
 234                      (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
 235                    !xhci_link_trb_quirk(xhci)) {
 236                        next->link.control &= cpu_to_le32(~TRB_CHAIN);
 237                        next->link.control |= cpu_to_le32(chain);
 238                }
 239                /* Give this link TRB to the hardware */
 240                wmb();
 241                next->link.control ^= cpu_to_le32(TRB_CYCLE);
 242
 243                /* Toggle the cycle bit after the last ring segment. */
 244                if (link_trb_toggles_cycle(next))
 245                        ring->cycle_state ^= 1;
 246
 247                ring->enq_seg = ring->enq_seg->next;
 248                ring->enqueue = ring->enq_seg->trbs;
 249                next = ring->enqueue;
 250        }
 251
 252        trace_xhci_inc_enq(ring);
 253}
 254
 255/*
 256 * Check to see if there's room to enqueue num_trbs on the ring and make sure
 257 * enqueue pointer will not advance into dequeue segment. See rules above.
 258 */
 259static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 260                unsigned int num_trbs)
 261{
 262        int num_trbs_in_deq_seg;
 263
 264        if (ring->num_trbs_free < num_trbs)
 265                return 0;
 266
 267        if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
 268                num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
 269                if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
 270                        return 0;
 271        }
 272
 273        return 1;
 274}
 275
 276/* Ring the host controller doorbell after placing a command on the ring */
 277void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 278{
 279        if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 280                return;
 281
 282        xhci_dbg(xhci, "// Ding dong!\n");
 283
 284        trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
 285
 286        writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 287        /* Flush PCI posted writes */
 288        readl(&xhci->dba->doorbell[0]);
 289}
 290
 291static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
 292{
 293        return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
 294}
 295
 296static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
 297{
 298        return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
 299                                        cmd_list);
 300}
 301
 302/*
 303 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
 304 * If there are other commands waiting then restart the ring and kick the timer.
 305 * This must be called with command ring stopped and xhci->lock held.
 306 */
 307static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
 308                                         struct xhci_command *cur_cmd)
 309{
 310        struct xhci_command *i_cmd;
 311
 312        /* Turn all aborted commands in list to no-ops, then restart */
 313        list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
 314
 315                if (i_cmd->status != COMP_COMMAND_ABORTED)
 316                        continue;
 317
 318                i_cmd->status = COMP_COMMAND_RING_STOPPED;
 319
 320                xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
 321                         i_cmd->command_trb);
 322
 323                trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
 324
 325                /*
 326                 * caller waiting for completion is called when command
 327                 *  completion event is received for these no-op commands
 328                 */
 329        }
 330
 331        xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
 332
 333        /* ring command ring doorbell to restart the command ring */
 334        if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
 335            !(xhci->xhc_state & XHCI_STATE_DYING)) {
 336                xhci->current_cmd = cur_cmd;
 337                xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
 338                xhci_ring_cmd_db(xhci);
 339        }
 340}
 341
 342/* Must be called with xhci->lock held, releases and aquires lock back */
 343static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
 344{
 345        u64 temp_64;
 346        int ret;
 347
 348        xhci_dbg(xhci, "Abort command ring\n");
 349
 350        reinit_completion(&xhci->cmd_ring_stop_completion);
 351
 352        temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 353        xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 354                        &xhci->op_regs->cmd_ring);
 355
 356        /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
 357         * completion of the Command Abort operation. If CRR is not negated in 5
 358         * seconds then driver handles it as if host died (-ENODEV).
 359         * In the future we should distinguish between -ENODEV and -ETIMEDOUT
 360         * and try to recover a -ETIMEDOUT with a host controller reset.
 361         */
 362        ret = xhci_handshake(&xhci->op_regs->cmd_ring,
 363                        CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 364        if (ret < 0) {
 365                xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
 366                xhci_halt(xhci);
 367                xhci_hc_died(xhci);
 368                return ret;
 369        }
 370        /*
 371         * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
 372         * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
 373         * but the completion event in never sent. Wait 2 secs (arbitrary
 374         * number) to handle those cases after negation of CMD_RING_RUNNING.
 375         */
 376        spin_unlock_irqrestore(&xhci->lock, flags);
 377        ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
 378                                          msecs_to_jiffies(2000));
 379        spin_lock_irqsave(&xhci->lock, flags);
 380        if (!ret) {
 381                xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
 382                xhci_cleanup_command_queue(xhci);
 383        } else {
 384                xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
 385        }
 386        return 0;
 387}
 388
 389void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 390                unsigned int slot_id,
 391                unsigned int ep_index,
 392                unsigned int stream_id)
 393{
 394        __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 395        struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 396        unsigned int ep_state = ep->ep_state;
 397
 398        /* Don't ring the doorbell for this endpoint if there are pending
 399         * cancellations because we don't want to interrupt processing.
 400         * We don't want to restart any stream rings if there's a set dequeue
 401         * pointer command pending because the device can choose to start any
 402         * stream once the endpoint is on the HW schedule.
 403         */
 404        if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 405            (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
 406                return;
 407
 408        trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
 409
 410        writel(DB_VALUE(ep_index, stream_id), db_addr);
 411        /* The CPU has better things to do at this point than wait for a
 412         * write-posting flush.  It'll get there soon enough.
 413         */
 414}
 415
 416/* Ring the doorbell for any rings with pending URBs */
 417static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 418                unsigned int slot_id,
 419                unsigned int ep_index)
 420{
 421        unsigned int stream_id;
 422        struct xhci_virt_ep *ep;
 423
 424        ep = &xhci->devs[slot_id]->eps[ep_index];
 425
 426        /* A ring has pending URBs if its TD list is not empty */
 427        if (!(ep->ep_state & EP_HAS_STREAMS)) {
 428                if (ep->ring && !(list_empty(&ep->ring->td_list)))
 429                        xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 430                return;
 431        }
 432
 433        for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 434                        stream_id++) {
 435                struct xhci_stream_info *stream_info = ep->stream_info;
 436                if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 437                        xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 438                                                stream_id);
 439        }
 440}
 441
 442void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 443                unsigned int slot_id,
 444                unsigned int ep_index)
 445{
 446        ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 447}
 448
 449/* Get the right ring for the given slot_id, ep_index and stream_id.
 450 * If the endpoint supports streams, boundary check the URB's stream ID.
 451 * If the endpoint doesn't support streams, return the singular endpoint ring.
 452 */
 453struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 454                unsigned int slot_id, unsigned int ep_index,
 455                unsigned int stream_id)
 456{
 457        struct xhci_virt_ep *ep;
 458
 459        ep = &xhci->devs[slot_id]->eps[ep_index];
 460        /* Common case: no streams */
 461        if (!(ep->ep_state & EP_HAS_STREAMS))
 462                return ep->ring;
 463
 464        if (stream_id == 0) {
 465                xhci_warn(xhci,
 466                                "WARN: Slot ID %u, ep index %u has streams, "
 467                                "but URB has no stream ID.\n",
 468                                slot_id, ep_index);
 469                return NULL;
 470        }
 471
 472        if (stream_id < ep->stream_info->num_streams)
 473                return ep->stream_info->stream_rings[stream_id];
 474
 475        xhci_warn(xhci,
 476                        "WARN: Slot ID %u, ep index %u has "
 477                        "stream IDs 1 to %u allocated, "
 478                        "but stream ID %u is requested.\n",
 479                        slot_id, ep_index,
 480                        ep->stream_info->num_streams - 1,
 481                        stream_id);
 482        return NULL;
 483}
 484
 485
 486/*
 487 * Get the hw dequeue pointer xHC stopped on, either directly from the
 488 * endpoint context, or if streams are in use from the stream context.
 489 * The returned hw_dequeue contains the lowest four bits with cycle state
 490 * and possbile stream context type.
 491 */
 492static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
 493                           unsigned int ep_index, unsigned int stream_id)
 494{
 495        struct xhci_ep_ctx *ep_ctx;
 496        struct xhci_stream_ctx *st_ctx;
 497        struct xhci_virt_ep *ep;
 498
 499        ep = &vdev->eps[ep_index];
 500
 501        if (ep->ep_state & EP_HAS_STREAMS) {
 502                st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
 503                return le64_to_cpu(st_ctx->stream_ring);
 504        }
 505        ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
 506        return le64_to_cpu(ep_ctx->deq);
 507}
 508
 509/*
 510 * Move the xHC's endpoint ring dequeue pointer past cur_td.
 511 * Record the new state of the xHC's endpoint ring dequeue segment,
 512 * dequeue pointer, stream id, and new consumer cycle state in state.
 513 * Update our internal representation of the ring's dequeue pointer.
 514 *
 515 * We do this in three jumps:
 516 *  - First we update our new ring state to be the same as when the xHC stopped.
 517 *  - Then we traverse the ring to find the segment that contains
 518 *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 519 *    any link TRBs with the toggle cycle bit set.
 520 *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 521 *    if we've moved it past a link TRB with the toggle cycle bit set.
 522 *
 523 * Some of the uses of xhci_generic_trb are grotty, but if they're done
 524 * with correct __le32 accesses they should work fine.  Only users of this are
 525 * in here.
 526 */
 527void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 528                unsigned int slot_id, unsigned int ep_index,
 529                unsigned int stream_id, struct xhci_td *cur_td,
 530                struct xhci_dequeue_state *state)
 531{
 532        struct xhci_virt_device *dev = xhci->devs[slot_id];
 533        struct xhci_virt_ep *ep = &dev->eps[ep_index];
 534        struct xhci_ring *ep_ring;
 535        struct xhci_segment *new_seg;
 536        union xhci_trb *new_deq;
 537        dma_addr_t addr;
 538        u64 hw_dequeue;
 539        bool cycle_found = false;
 540        bool td_last_trb_found = false;
 541
 542        ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 543                        ep_index, stream_id);
 544        if (!ep_ring) {
 545                xhci_warn(xhci, "WARN can't find new dequeue state "
 546                                "for invalid stream ID %u.\n",
 547                                stream_id);
 548                return;
 549        }
 550        /*
 551         * A cancelled TD can complete with a stall if HW cached the trb.
 552         * In this case driver can't find cur_td, but if the ring is empty we
 553         * can move the dequeue pointer to the current enqueue position.
 554         */
 555        if (!cur_td) {
 556                if (list_empty(&ep_ring->td_list)) {
 557                        state->new_deq_seg = ep_ring->enq_seg;
 558                        state->new_deq_ptr = ep_ring->enqueue;
 559                        state->new_cycle_state = ep_ring->cycle_state;
 560                        goto done;
 561                } else {
 562                        xhci_warn(xhci, "Can't find new dequeue state, missing cur_td\n");
 563                        return;
 564                }
 565        }
 566
 567        /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 568        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 569                        "Finding endpoint context");
 570
 571        hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
 572        new_seg = ep_ring->deq_seg;
 573        new_deq = ep_ring->dequeue;
 574        state->new_cycle_state = hw_dequeue & 0x1;
 575        state->stream_id = stream_id;
 576
 577        /*
 578         * We want to find the pointer, segment and cycle state of the new trb
 579         * (the one after current TD's last_trb). We know the cycle state at
 580         * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
 581         * found.
 582         */
 583        do {
 584                if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
 585                    == (dma_addr_t)(hw_dequeue & ~0xf)) {
 586                        cycle_found = true;
 587                        if (td_last_trb_found)
 588                                break;
 589                }
 590                if (new_deq == cur_td->last_trb)
 591                        td_last_trb_found = true;
 592
 593                if (cycle_found && trb_is_link(new_deq) &&
 594                    link_trb_toggles_cycle(new_deq))
 595                        state->new_cycle_state ^= 0x1;
 596
 597                next_trb(xhci, ep_ring, &new_seg, &new_deq);
 598
 599                /* Search wrapped around, bail out */
 600                if (new_deq == ep->ring->dequeue) {
 601                        xhci_err(xhci, "Error: Failed finding new dequeue state\n");
 602                        state->new_deq_seg = NULL;
 603                        state->new_deq_ptr = NULL;
 604                        return;
 605                }
 606
 607        } while (!cycle_found || !td_last_trb_found);
 608
 609        state->new_deq_seg = new_seg;
 610        state->new_deq_ptr = new_deq;
 611
 612done:
 613        /* Don't update the ring cycle state for the producer (us). */
 614        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 615                        "Cycle state = 0x%x", state->new_cycle_state);
 616
 617        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 618                        "New dequeue segment = %p (virtual)",
 619                        state->new_deq_seg);
 620        addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 621        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 622                        "New dequeue pointer = 0x%llx (DMA)",
 623                        (unsigned long long) addr);
 624}
 625
 626/* flip_cycle means flip the cycle bit of all but the first and last TRB.
 627 * (The last TRB actually points to the ring enqueue pointer, which is not part
 628 * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 629 */
 630static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 631                       struct xhci_td *td, bool flip_cycle)
 632{
 633        struct xhci_segment *seg        = td->start_seg;
 634        union xhci_trb *trb             = td->first_trb;
 635
 636        while (1) {
 637                trb_to_noop(trb, TRB_TR_NOOP);
 638
 639                /* flip cycle if asked to */
 640                if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
 641                        trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
 642
 643                if (trb == td->last_trb)
 644                        break;
 645
 646                next_trb(xhci, ep_ring, &seg, &trb);
 647        }
 648}
 649
 650static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 651                struct xhci_virt_ep *ep)
 652{
 653        ep->ep_state &= ~EP_STOP_CMD_PENDING;
 654        /* Can't del_timer_sync in interrupt */
 655        del_timer(&ep->stop_cmd_timer);
 656}
 657
 658/*
 659 * Must be called with xhci->lock held in interrupt context,
 660 * releases and re-acquires xhci->lock
 661 */
 662static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 663                                     struct xhci_td *cur_td, int status)
 664{
 665        struct urb      *urb            = cur_td->urb;
 666        struct urb_priv *urb_priv       = urb->hcpriv;
 667        struct usb_hcd  *hcd            = bus_to_hcd(urb->dev->bus);
 668
 669        if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 670                xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 671                if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 672                        if (xhci->quirks & XHCI_AMD_PLL_FIX)
 673                                usb_amd_quirk_pll_enable();
 674                }
 675        }
 676        xhci_urb_free_priv(urb_priv);
 677        usb_hcd_unlink_urb_from_ep(hcd, urb);
 678        trace_xhci_urb_giveback(urb);
 679        usb_hcd_giveback_urb(hcd, urb, status);
 680}
 681
 682static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
 683                struct xhci_ring *ring, struct xhci_td *td)
 684{
 685        struct device *dev = xhci_to_hcd(xhci)->self.controller;
 686        struct xhci_segment *seg = td->bounce_seg;
 687        struct urb *urb = td->urb;
 688        size_t len;
 689
 690        if (!ring || !seg || !urb)
 691                return;
 692
 693        if (usb_urb_dir_out(urb)) {
 694                dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
 695                                 DMA_TO_DEVICE);
 696                return;
 697        }
 698
 699        dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
 700                         DMA_FROM_DEVICE);
 701        /* for in tranfers we need to copy the data from bounce to sg */
 702        len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
 703                             seg->bounce_len, seg->bounce_offs);
 704        if (len != seg->bounce_len)
 705                xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
 706                                len, seg->bounce_len);
 707        seg->bounce_len = 0;
 708        seg->bounce_offs = 0;
 709}
 710
 711/*
 712 * When we get a command completion for a Stop Endpoint Command, we need to
 713 * unlink any cancelled TDs from the ring.  There are two ways to do that:
 714 *
 715 *  1. If the HW was in the middle of processing the TD that needs to be
 716 *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 717 *     in the TD with a Set Dequeue Pointer Command.
 718 *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 719 *     bit cleared) so that the HW will skip over them.
 720 */
 721static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
 722                union xhci_trb *trb, struct xhci_event_cmd *event)
 723{
 724        unsigned int ep_index;
 725        struct xhci_ring *ep_ring;
 726        struct xhci_virt_ep *ep;
 727        struct xhci_td *cur_td = NULL;
 728        struct xhci_td *last_unlinked_td;
 729        struct xhci_ep_ctx *ep_ctx;
 730        struct xhci_virt_device *vdev;
 731        u64 hw_deq;
 732        struct xhci_dequeue_state deq_state;
 733
 734        if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
 735                if (!xhci->devs[slot_id])
 736                        xhci_warn(xhci, "Stop endpoint command "
 737                                "completion for disabled slot %u\n",
 738                                slot_id);
 739                return;
 740        }
 741
 742        memset(&deq_state, 0, sizeof(deq_state));
 743        ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 744
 745        vdev = xhci->devs[slot_id];
 746        ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
 747        trace_xhci_handle_cmd_stop_ep(ep_ctx);
 748
 749        ep = &xhci->devs[slot_id]->eps[ep_index];
 750        last_unlinked_td = list_last_entry(&ep->cancelled_td_list,
 751                        struct xhci_td, cancelled_td_list);
 752
 753        if (list_empty(&ep->cancelled_td_list)) {
 754                xhci_stop_watchdog_timer_in_irq(xhci, ep);
 755                ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 756                return;
 757        }
 758
 759        /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 760         * We have the xHCI lock, so nothing can modify this list until we drop
 761         * it.  We're also in the event handler, so we can't get re-interrupted
 762         * if another Stop Endpoint command completes
 763         */
 764        list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) {
 765                xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 766                                "Removing canceled TD starting at 0x%llx (dma).",
 767                                (unsigned long long)xhci_trb_virt_to_dma(
 768                                        cur_td->start_seg, cur_td->first_trb));
 769                ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 770                if (!ep_ring) {
 771                        /* This shouldn't happen unless a driver is mucking
 772                         * with the stream ID after submission.  This will
 773                         * leave the TD on the hardware ring, and the hardware
 774                         * will try to execute it, and may access a buffer
 775                         * that has already been freed.  In the best case, the
 776                         * hardware will execute it, and the event handler will
 777                         * ignore the completion event for that TD, since it was
 778                         * removed from the td_list for that endpoint.  In
 779                         * short, don't muck with the stream ID after
 780                         * submission.
 781                         */
 782                        xhci_warn(xhci, "WARN Cancelled URB %p "
 783                                        "has invalid stream ID %u.\n",
 784                                        cur_td->urb,
 785                                        cur_td->urb->stream_id);
 786                        goto remove_finished_td;
 787                }
 788                /*
 789                 * If we stopped on the TD we need to cancel, then we have to
 790                 * move the xHC endpoint ring dequeue pointer past this TD.
 791                 */
 792                hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index,
 793                                         cur_td->urb->stream_id);
 794                hw_deq &= ~0xf;
 795
 796                if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb,
 797                              cur_td->last_trb, hw_deq, false)) {
 798                        xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 799                                                    cur_td->urb->stream_id,
 800                                                    cur_td, &deq_state);
 801                } else {
 802                        td_to_noop(xhci, ep_ring, cur_td, false);
 803                }
 804
 805remove_finished_td:
 806                /*
 807                 * The event handler won't see a completion for this TD anymore,
 808                 * so remove it from the endpoint ring's TD list.  Keep it in
 809                 * the cancelled TD list for URB completion later.
 810                 */
 811                list_del_init(&cur_td->td_list);
 812        }
 813
 814        xhci_stop_watchdog_timer_in_irq(xhci, ep);
 815
 816        /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 817        if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 818                xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
 819                                             &deq_state);
 820                xhci_ring_cmd_db(xhci);
 821        } else {
 822                /* Otherwise ring the doorbell(s) to restart queued transfers */
 823                ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 824        }
 825
 826        /*
 827         * Drop the lock and complete the URBs in the cancelled TD list.
 828         * New TDs to be cancelled might be added to the end of the list before
 829         * we can complete all the URBs for the TDs we already unlinked.
 830         * So stop when we've completed the URB for the last TD we unlinked.
 831         */
 832        do {
 833                cur_td = list_first_entry(&ep->cancelled_td_list,
 834                                struct xhci_td, cancelled_td_list);
 835                list_del_init(&cur_td->cancelled_td_list);
 836
 837                /* Clean up the cancelled URB */
 838                /* Doesn't matter what we pass for status, since the core will
 839                 * just overwrite it (because the URB has been unlinked).
 840                 */
 841                ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 842                xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
 843                inc_td_cnt(cur_td->urb);
 844                if (last_td_in_urb(cur_td))
 845                        xhci_giveback_urb_in_irq(xhci, cur_td, 0);
 846
 847                /* Stop processing the cancelled list if the watchdog timer is
 848                 * running.
 849                 */
 850                if (xhci->xhc_state & XHCI_STATE_DYING)
 851                        return;
 852        } while (cur_td != last_unlinked_td);
 853
 854        /* Return to the event handler with xhci->lock re-acquired */
 855}
 856
 857static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
 858{
 859        struct xhci_td *cur_td;
 860        struct xhci_td *tmp;
 861
 862        list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
 863                list_del_init(&cur_td->td_list);
 864
 865                if (!list_empty(&cur_td->cancelled_td_list))
 866                        list_del_init(&cur_td->cancelled_td_list);
 867
 868                xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
 869
 870                inc_td_cnt(cur_td->urb);
 871                if (last_td_in_urb(cur_td))
 872                        xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
 873        }
 874}
 875
 876static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
 877                int slot_id, int ep_index)
 878{
 879        struct xhci_td *cur_td;
 880        struct xhci_td *tmp;
 881        struct xhci_virt_ep *ep;
 882        struct xhci_ring *ring;
 883
 884        ep = &xhci->devs[slot_id]->eps[ep_index];
 885        if ((ep->ep_state & EP_HAS_STREAMS) ||
 886                        (ep->ep_state & EP_GETTING_NO_STREAMS)) {
 887                int stream_id;
 888
 889                for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 890                                stream_id++) {
 891                        ring = ep->stream_info->stream_rings[stream_id];
 892                        if (!ring)
 893                                continue;
 894
 895                        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 896                                        "Killing URBs for slot ID %u, ep index %u, stream %u",
 897                                        slot_id, ep_index, stream_id);
 898                        xhci_kill_ring_urbs(xhci, ring);
 899                }
 900        } else {
 901                ring = ep->ring;
 902                if (!ring)
 903                        return;
 904                xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 905                                "Killing URBs for slot ID %u, ep index %u",
 906                                slot_id, ep_index);
 907                xhci_kill_ring_urbs(xhci, ring);
 908        }
 909
 910        list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
 911                        cancelled_td_list) {
 912                list_del_init(&cur_td->cancelled_td_list);
 913                inc_td_cnt(cur_td->urb);
 914
 915                if (last_td_in_urb(cur_td))
 916                        xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
 917        }
 918}
 919
 920/*
 921 * host controller died, register read returns 0xffffffff
 922 * Complete pending commands, mark them ABORTED.
 923 * URBs need to be given back as usb core might be waiting with device locks
 924 * held for the URBs to finish during device disconnect, blocking host remove.
 925 *
 926 * Call with xhci->lock held.
 927 * lock is relased and re-acquired while giving back urb.
 928 */
 929void xhci_hc_died(struct xhci_hcd *xhci)
 930{
 931        int i, j;
 932
 933        if (xhci->xhc_state & XHCI_STATE_DYING)
 934                return;
 935
 936        xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
 937        xhci->xhc_state |= XHCI_STATE_DYING;
 938
 939        xhci_cleanup_command_queue(xhci);
 940
 941        /* return any pending urbs, remove may be waiting for them */
 942        for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 943                if (!xhci->devs[i])
 944                        continue;
 945                for (j = 0; j < 31; j++)
 946                        xhci_kill_endpoint_urbs(xhci, i, j);
 947        }
 948
 949        /* inform usb core hc died if PCI remove isn't already handling it */
 950        if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
 951                usb_hc_died(xhci_to_hcd(xhci));
 952}
 953
 954/* Watchdog timer function for when a stop endpoint command fails to complete.
 955 * In this case, we assume the host controller is broken or dying or dead.  The
 956 * host may still be completing some other events, so we have to be careful to
 957 * let the event ring handler and the URB dequeueing/enqueueing functions know
 958 * through xhci->state.
 959 *
 960 * The timer may also fire if the host takes a very long time to respond to the
 961 * command, and the stop endpoint command completion handler cannot delete the
 962 * timer before the timer function is called.  Another endpoint cancellation may
 963 * sneak in before the timer function can grab the lock, and that may queue
 964 * another stop endpoint command and add the timer back.  So we cannot use a
 965 * simple flag to say whether there is a pending stop endpoint command for a
 966 * particular endpoint.
 967 *
 968 * Instead we use a combination of that flag and checking if a new timer is
 969 * pending.
 970 */
 971void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
 972{
 973        struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
 974        struct xhci_hcd *xhci = ep->xhci;
 975        unsigned long flags;
 976        u32 usbsts;
 977
 978        spin_lock_irqsave(&xhci->lock, flags);
 979
 980        /* bail out if cmd completed but raced with stop ep watchdog timer.*/
 981        if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
 982            timer_pending(&ep->stop_cmd_timer)) {
 983                spin_unlock_irqrestore(&xhci->lock, flags);
 984                xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
 985                return;
 986        }
 987        usbsts = readl(&xhci->op_regs->status);
 988
 989        xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 990        xhci_warn(xhci, "USBSTS:%s\n", xhci_decode_usbsts(usbsts));
 991
 992        ep->ep_state &= ~EP_STOP_CMD_PENDING;
 993
 994        xhci_halt(xhci);
 995
 996        /*
 997         * handle a stop endpoint cmd timeout as if host died (-ENODEV).
 998         * In the future we could distinguish between -ENODEV and -ETIMEDOUT
 999         * and try to recover a -ETIMEDOUT with a host controller reset
1000         */
1001        xhci_hc_died(xhci);
1002
1003        spin_unlock_irqrestore(&xhci->lock, flags);
1004        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1005                        "xHCI host controller is dead.");
1006}
1007
1008static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1009                struct xhci_virt_device *dev,
1010                struct xhci_ring *ep_ring,
1011                unsigned int ep_index)
1012{
1013        union xhci_trb *dequeue_temp;
1014        int num_trbs_free_temp;
1015        bool revert = false;
1016
1017        num_trbs_free_temp = ep_ring->num_trbs_free;
1018        dequeue_temp = ep_ring->dequeue;
1019
1020        /* If we get two back-to-back stalls, and the first stalled transfer
1021         * ends just before a link TRB, the dequeue pointer will be left on
1022         * the link TRB by the code in the while loop.  So we have to update
1023         * the dequeue pointer one segment further, or we'll jump off
1024         * the segment into la-la-land.
1025         */
1026        if (trb_is_link(ep_ring->dequeue)) {
1027                ep_ring->deq_seg = ep_ring->deq_seg->next;
1028                ep_ring->dequeue = ep_ring->deq_seg->trbs;
1029        }
1030
1031        while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1032                /* We have more usable TRBs */
1033                ep_ring->num_trbs_free++;
1034                ep_ring->dequeue++;
1035                if (trb_is_link(ep_ring->dequeue)) {
1036                        if (ep_ring->dequeue ==
1037                                        dev->eps[ep_index].queued_deq_ptr)
1038                                break;
1039                        ep_ring->deq_seg = ep_ring->deq_seg->next;
1040                        ep_ring->dequeue = ep_ring->deq_seg->trbs;
1041                }
1042                if (ep_ring->dequeue == dequeue_temp) {
1043                        revert = true;
1044                        break;
1045                }
1046        }
1047
1048        if (revert) {
1049                xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1050                ep_ring->num_trbs_free = num_trbs_free_temp;
1051        }
1052}
1053
1054/*
1055 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1056 * we need to clear the set deq pending flag in the endpoint ring state, so that
1057 * the TD queueing code can ring the doorbell again.  We also need to ring the
1058 * endpoint doorbell to restart the ring, but only if there aren't more
1059 * cancellations pending.
1060 */
1061static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1062                union xhci_trb *trb, u32 cmd_comp_code)
1063{
1064        unsigned int ep_index;
1065        unsigned int stream_id;
1066        struct xhci_ring *ep_ring;
1067        struct xhci_virt_device *dev;
1068        struct xhci_virt_ep *ep;
1069        struct xhci_ep_ctx *ep_ctx;
1070        struct xhci_slot_ctx *slot_ctx;
1071
1072        ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1073        stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1074        dev = xhci->devs[slot_id];
1075        ep = &dev->eps[ep_index];
1076
1077        ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1078        if (!ep_ring) {
1079                xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1080                                stream_id);
1081                /* XXX: Harmless??? */
1082                goto cleanup;
1083        }
1084
1085        ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1086        slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1087        trace_xhci_handle_cmd_set_deq(slot_ctx);
1088        trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1089
1090        if (cmd_comp_code != COMP_SUCCESS) {
1091                unsigned int ep_state;
1092                unsigned int slot_state;
1093
1094                switch (cmd_comp_code) {
1095                case COMP_TRB_ERROR:
1096                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1097                        break;
1098                case COMP_CONTEXT_STATE_ERROR:
1099                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1100                        ep_state = GET_EP_CTX_STATE(ep_ctx);
1101                        slot_state = le32_to_cpu(slot_ctx->dev_state);
1102                        slot_state = GET_SLOT_STATE(slot_state);
1103                        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1104                                        "Slot state = %u, EP state = %u",
1105                                        slot_state, ep_state);
1106                        break;
1107                case COMP_SLOT_NOT_ENABLED_ERROR:
1108                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1109                                        slot_id);
1110                        break;
1111                default:
1112                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1113                                        cmd_comp_code);
1114                        break;
1115                }
1116                /* OK what do we do now?  The endpoint state is hosed, and we
1117                 * should never get to this point if the synchronization between
1118                 * queueing, and endpoint state are correct.  This might happen
1119                 * if the device gets disconnected after we've finished
1120                 * cancelling URBs, which might not be an error...
1121                 */
1122        } else {
1123                u64 deq;
1124                /* 4.6.10 deq ptr is written to the stream ctx for streams */
1125                if (ep->ep_state & EP_HAS_STREAMS) {
1126                        struct xhci_stream_ctx *ctx =
1127                                &ep->stream_info->stream_ctx_array[stream_id];
1128                        deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1129                } else {
1130                        deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1131                }
1132                xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1133                        "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1134                if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1135                                         ep->queued_deq_ptr) == deq) {
1136                        /* Update the ring's dequeue segment and dequeue pointer
1137                         * to reflect the new position.
1138                         */
1139                        update_ring_for_set_deq_completion(xhci, dev,
1140                                ep_ring, ep_index);
1141                } else {
1142                        xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1143                        xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1144                                  ep->queued_deq_seg, ep->queued_deq_ptr);
1145                }
1146        }
1147
1148cleanup:
1149        dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1150        dev->eps[ep_index].queued_deq_seg = NULL;
1151        dev->eps[ep_index].queued_deq_ptr = NULL;
1152        /* Restart any rings with pending URBs */
1153        ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1154}
1155
1156static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1157                union xhci_trb *trb, u32 cmd_comp_code)
1158{
1159        struct xhci_virt_device *vdev;
1160        struct xhci_ep_ctx *ep_ctx;
1161        unsigned int ep_index;
1162
1163        ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1164        vdev = xhci->devs[slot_id];
1165        ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
1166        trace_xhci_handle_cmd_reset_ep(ep_ctx);
1167
1168        /* This command will only fail if the endpoint wasn't halted,
1169         * but we don't care.
1170         */
1171        xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1172                "Ignoring reset ep completion code of %u", cmd_comp_code);
1173
1174        /* HW with the reset endpoint quirk needs to have a configure endpoint
1175         * command complete before the endpoint can be used.  Queue that here
1176         * because the HW can't handle two commands being queued in a row.
1177         */
1178        if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1179                struct xhci_command *command;
1180
1181                command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1182                if (!command)
1183                        return;
1184
1185                xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1186                                "Queueing configure endpoint command");
1187                xhci_queue_configure_endpoint(xhci, command,
1188                                xhci->devs[slot_id]->in_ctx->dma, slot_id,
1189                                false);
1190                xhci_ring_cmd_db(xhci);
1191        } else {
1192                /* Clear our internal halted state */
1193                xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1194        }
1195
1196        /* if this was a soft reset, then restart */
1197        if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1198                ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1199}
1200
1201static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1202                struct xhci_command *command, u32 cmd_comp_code)
1203{
1204        if (cmd_comp_code == COMP_SUCCESS)
1205                command->slot_id = slot_id;
1206        else
1207                command->slot_id = 0;
1208}
1209
1210static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1211{
1212        struct xhci_virt_device *virt_dev;
1213        struct xhci_slot_ctx *slot_ctx;
1214
1215        virt_dev = xhci->devs[slot_id];
1216        if (!virt_dev)
1217                return;
1218
1219        slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1220        trace_xhci_handle_cmd_disable_slot(slot_ctx);
1221
1222        if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1223                /* Delete default control endpoint resources */
1224                xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1225        xhci_free_virt_device(xhci, slot_id);
1226}
1227
1228static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1229                struct xhci_event_cmd *event, u32 cmd_comp_code)
1230{
1231        struct xhci_virt_device *virt_dev;
1232        struct xhci_input_control_ctx *ctrl_ctx;
1233        struct xhci_ep_ctx *ep_ctx;
1234        unsigned int ep_index;
1235        unsigned int ep_state;
1236        u32 add_flags, drop_flags;
1237
1238        /*
1239         * Configure endpoint commands can come from the USB core
1240         * configuration or alt setting changes, or because the HW
1241         * needed an extra configure endpoint command after a reset
1242         * endpoint command or streams were being configured.
1243         * If the command was for a halted endpoint, the xHCI driver
1244         * is not waiting on the configure endpoint command.
1245         */
1246        virt_dev = xhci->devs[slot_id];
1247        ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1248        if (!ctrl_ctx) {
1249                xhci_warn(xhci, "Could not get input context, bad type.\n");
1250                return;
1251        }
1252
1253        add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1254        drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1255        /* Input ctx add_flags are the endpoint index plus one */
1256        ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1257
1258        ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1259        trace_xhci_handle_cmd_config_ep(ep_ctx);
1260
1261        /* A usb_set_interface() call directly after clearing a halted
1262         * condition may race on this quirky hardware.  Not worth
1263         * worrying about, since this is prototype hardware.  Not sure
1264         * if this will work for streams, but streams support was
1265         * untested on this prototype.
1266         */
1267        if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1268                        ep_index != (unsigned int) -1 &&
1269                        add_flags - SLOT_FLAG == drop_flags) {
1270                ep_state = virt_dev->eps[ep_index].ep_state;
1271                if (!(ep_state & EP_HALTED))
1272                        return;
1273                xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1274                                "Completed config ep cmd - "
1275                                "last ep index = %d, state = %d",
1276                                ep_index, ep_state);
1277                /* Clear internal halted state and restart ring(s) */
1278                virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1279                ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1280                return;
1281        }
1282        return;
1283}
1284
1285static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1286{
1287        struct xhci_virt_device *vdev;
1288        struct xhci_slot_ctx *slot_ctx;
1289
1290        vdev = xhci->devs[slot_id];
1291        slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1292        trace_xhci_handle_cmd_addr_dev(slot_ctx);
1293}
1294
1295static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1296                struct xhci_event_cmd *event)
1297{
1298        struct xhci_virt_device *vdev;
1299        struct xhci_slot_ctx *slot_ctx;
1300
1301        vdev = xhci->devs[slot_id];
1302        slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1303        trace_xhci_handle_cmd_reset_dev(slot_ctx);
1304
1305        xhci_dbg(xhci, "Completed reset device command.\n");
1306        if (!xhci->devs[slot_id])
1307                xhci_warn(xhci, "Reset device command completion "
1308                                "for disabled slot %u\n", slot_id);
1309}
1310
1311static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1312                struct xhci_event_cmd *event)
1313{
1314        if (!(xhci->quirks & XHCI_NEC_HOST)) {
1315                xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1316                return;
1317        }
1318        xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1319                        "NEC firmware version %2x.%02x",
1320                        NEC_FW_MAJOR(le32_to_cpu(event->status)),
1321                        NEC_FW_MINOR(le32_to_cpu(event->status)));
1322}
1323
1324static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1325{
1326        list_del(&cmd->cmd_list);
1327
1328        if (cmd->completion) {
1329                cmd->status = status;
1330                complete(cmd->completion);
1331        } else {
1332                kfree(cmd);
1333        }
1334}
1335
1336void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1337{
1338        struct xhci_command *cur_cmd, *tmp_cmd;
1339        xhci->current_cmd = NULL;
1340        list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1341                xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1342}
1343
1344void xhci_handle_command_timeout(struct work_struct *work)
1345{
1346        struct xhci_hcd *xhci;
1347        unsigned long flags;
1348        u64 hw_ring_state;
1349
1350        xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1351
1352        spin_lock_irqsave(&xhci->lock, flags);
1353
1354        /*
1355         * If timeout work is pending, or current_cmd is NULL, it means we
1356         * raced with command completion. Command is handled so just return.
1357         */
1358        if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1359                spin_unlock_irqrestore(&xhci->lock, flags);
1360                return;
1361        }
1362        /* mark this command to be cancelled */
1363        xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1364
1365        /* Make sure command ring is running before aborting it */
1366        hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1367        if (hw_ring_state == ~(u64)0) {
1368                xhci_hc_died(xhci);
1369                goto time_out_completed;
1370        }
1371
1372        if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1373            (hw_ring_state & CMD_RING_RUNNING))  {
1374                /* Prevent new doorbell, and start command abort */
1375                xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1376                xhci_dbg(xhci, "Command timeout\n");
1377                xhci_abort_cmd_ring(xhci, flags);
1378                goto time_out_completed;
1379        }
1380
1381        /* host removed. Bail out */
1382        if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1383                xhci_dbg(xhci, "host removed, ring start fail?\n");
1384                xhci_cleanup_command_queue(xhci);
1385
1386                goto time_out_completed;
1387        }
1388
1389        /* command timeout on stopped ring, ring can't be aborted */
1390        xhci_dbg(xhci, "Command timeout on stopped ring\n");
1391        xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1392
1393time_out_completed:
1394        spin_unlock_irqrestore(&xhci->lock, flags);
1395        return;
1396}
1397
1398static void handle_cmd_completion(struct xhci_hcd *xhci,
1399                struct xhci_event_cmd *event)
1400{
1401        int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1402        u64 cmd_dma;
1403        dma_addr_t cmd_dequeue_dma;
1404        u32 cmd_comp_code;
1405        union xhci_trb *cmd_trb;
1406        struct xhci_command *cmd;
1407        u32 cmd_type;
1408
1409        cmd_dma = le64_to_cpu(event->cmd_trb);
1410        cmd_trb = xhci->cmd_ring->dequeue;
1411
1412        trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1413
1414        cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1415                        cmd_trb);
1416        /*
1417         * Check whether the completion event is for our internal kept
1418         * command.
1419         */
1420        if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1421                xhci_warn(xhci,
1422                          "ERROR mismatched command completion event\n");
1423                return;
1424        }
1425
1426        cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1427
1428        cancel_delayed_work(&xhci->cmd_timer);
1429
1430        cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1431
1432        /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1433        if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1434                complete_all(&xhci->cmd_ring_stop_completion);
1435                return;
1436        }
1437
1438        if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1439                xhci_err(xhci,
1440                         "Command completion event does not match command\n");
1441                return;
1442        }
1443
1444        /*
1445         * Host aborted the command ring, check if the current command was
1446         * supposed to be aborted, otherwise continue normally.
1447         * The command ring is stopped now, but the xHC will issue a Command
1448         * Ring Stopped event which will cause us to restart it.
1449         */
1450        if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1451                xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1452                if (cmd->status == COMP_COMMAND_ABORTED) {
1453                        if (xhci->current_cmd == cmd)
1454                                xhci->current_cmd = NULL;
1455                        goto event_handled;
1456                }
1457        }
1458
1459        cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1460        switch (cmd_type) {
1461        case TRB_ENABLE_SLOT:
1462                xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1463                break;
1464        case TRB_DISABLE_SLOT:
1465                xhci_handle_cmd_disable_slot(xhci, slot_id);
1466                break;
1467        case TRB_CONFIG_EP:
1468                if (!cmd->completion)
1469                        xhci_handle_cmd_config_ep(xhci, slot_id, event,
1470                                                  cmd_comp_code);
1471                break;
1472        case TRB_EVAL_CONTEXT:
1473                break;
1474        case TRB_ADDR_DEV:
1475                xhci_handle_cmd_addr_dev(xhci, slot_id);
1476                break;
1477        case TRB_STOP_RING:
1478                WARN_ON(slot_id != TRB_TO_SLOT_ID(
1479                                le32_to_cpu(cmd_trb->generic.field[3])));
1480                if (!cmd->completion)
1481                        xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1482                break;
1483        case TRB_SET_DEQ:
1484                WARN_ON(slot_id != TRB_TO_SLOT_ID(
1485                                le32_to_cpu(cmd_trb->generic.field[3])));
1486                xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1487                break;
1488        case TRB_CMD_NOOP:
1489                /* Is this an aborted command turned to NO-OP? */
1490                if (cmd->status == COMP_COMMAND_RING_STOPPED)
1491                        cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1492                break;
1493        case TRB_RESET_EP:
1494                WARN_ON(slot_id != TRB_TO_SLOT_ID(
1495                                le32_to_cpu(cmd_trb->generic.field[3])));
1496                xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1497                break;
1498        case TRB_RESET_DEV:
1499                /* SLOT_ID field in reset device cmd completion event TRB is 0.
1500                 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1501                 */
1502                slot_id = TRB_TO_SLOT_ID(
1503                                le32_to_cpu(cmd_trb->generic.field[3]));
1504                xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1505                break;
1506        case TRB_NEC_GET_FW:
1507                xhci_handle_cmd_nec_get_fw(xhci, event);
1508                break;
1509        default:
1510                /* Skip over unknown commands on the event ring */
1511                xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1512                break;
1513        }
1514
1515        /* restart timer if this wasn't the last command */
1516        if (!list_is_singular(&xhci->cmd_list)) {
1517                xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1518                                                struct xhci_command, cmd_list);
1519                xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1520        } else if (xhci->current_cmd == cmd) {
1521                xhci->current_cmd = NULL;
1522        }
1523
1524event_handled:
1525        xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1526
1527        inc_deq(xhci, xhci->cmd_ring);
1528}
1529
1530static void handle_vendor_event(struct xhci_hcd *xhci,
1531                union xhci_trb *event)
1532{
1533        u32 trb_type;
1534
1535        trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1536        xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1537        if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1538                handle_cmd_completion(xhci, &event->event_cmd);
1539}
1540
1541static void handle_device_notification(struct xhci_hcd *xhci,
1542                union xhci_trb *event)
1543{
1544        u32 slot_id;
1545        struct usb_device *udev;
1546
1547        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1548        if (!xhci->devs[slot_id]) {
1549                xhci_warn(xhci, "Device Notification event for "
1550                                "unused slot %u\n", slot_id);
1551                return;
1552        }
1553
1554        xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1555                        slot_id);
1556        udev = xhci->devs[slot_id]->udev;
1557        if (udev && udev->parent)
1558                usb_wakeup_notification(udev->parent, udev->portnum);
1559}
1560
1561/*
1562 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1563 * Controller.
1564 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1565 * If a connection to a USB 1 device is followed by another connection
1566 * to a USB 2 device.
1567 *
1568 * Reset the PHY after the USB device is disconnected if device speed
1569 * is less than HCD_USB3.
1570 * Retry the reset sequence max of 4 times checking the PLL lock status.
1571 *
1572 */
1573static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1574{
1575        struct usb_hcd *hcd = xhci_to_hcd(xhci);
1576        u32 pll_lock_check;
1577        u32 retry_count = 4;
1578
1579        do {
1580                /* Assert PHY reset */
1581                writel(0x6F, hcd->regs + 0x1048);
1582                udelay(10);
1583                /* De-assert the PHY reset */
1584                writel(0x7F, hcd->regs + 0x1048);
1585                udelay(200);
1586                pll_lock_check = readl(hcd->regs + 0x1070);
1587        } while (!(pll_lock_check & 0x1) && --retry_count);
1588}
1589
1590static void handle_port_status(struct xhci_hcd *xhci,
1591                union xhci_trb *event)
1592{
1593        struct usb_hcd *hcd;
1594        u32 port_id;
1595        u32 portsc, cmd_reg;
1596        int max_ports;
1597        int slot_id;
1598        unsigned int hcd_portnum;
1599        struct xhci_bus_state *bus_state;
1600        bool bogus_port_status = false;
1601        struct xhci_port *port;
1602
1603        /* Port status change events always have a successful completion code */
1604        if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1605                xhci_warn(xhci,
1606                          "WARN: xHC returned failed port status event\n");
1607
1608        port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1609        max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1610
1611        if ((port_id <= 0) || (port_id > max_ports)) {
1612                xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1613                          port_id);
1614                inc_deq(xhci, xhci->event_ring);
1615                return;
1616        }
1617
1618        port = &xhci->hw_ports[port_id - 1];
1619        if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1620                xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1621                          port_id);
1622                bogus_port_status = true;
1623                goto cleanup;
1624        }
1625
1626        /* We might get interrupts after shared_hcd is removed */
1627        if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1628                xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1629                bogus_port_status = true;
1630                goto cleanup;
1631        }
1632
1633        hcd = port->rhub->hcd;
1634        bus_state = &port->rhub->bus_state;
1635        hcd_portnum = port->hcd_portnum;
1636        portsc = readl(port->addr);
1637
1638        xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1639                 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1640
1641        trace_xhci_handle_port_status(hcd_portnum, portsc);
1642
1643        if (hcd->state == HC_STATE_SUSPENDED) {
1644                xhci_dbg(xhci, "resume root hub\n");
1645                usb_hcd_resume_root_hub(hcd);
1646        }
1647
1648        if (hcd->speed >= HCD_USB3 &&
1649            (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1650                slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1651                if (slot_id && xhci->devs[slot_id])
1652                        xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1653        }
1654
1655        if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1656                xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1657
1658                cmd_reg = readl(&xhci->op_regs->command);
1659                if (!(cmd_reg & CMD_RUN)) {
1660                        xhci_warn(xhci, "xHC is not running.\n");
1661                        goto cleanup;
1662                }
1663
1664                if (DEV_SUPERSPEED_ANY(portsc)) {
1665                        xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1666                        /* Set a flag to say the port signaled remote wakeup,
1667                         * so we can tell the difference between the end of
1668                         * device and host initiated resume.
1669                         */
1670                        bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1671                        xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1672                        usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1673                        xhci_set_link_state(xhci, port, XDEV_U0);
1674                        /* Need to wait until the next link state change
1675                         * indicates the device is actually in U0.
1676                         */
1677                        bogus_port_status = true;
1678                        goto cleanup;
1679                } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1680                        xhci_dbg(xhci, "resume HS port %d\n", port_id);
1681                        bus_state->resume_done[hcd_portnum] = jiffies +
1682                                msecs_to_jiffies(USB_RESUME_TIMEOUT);
1683                        set_bit(hcd_portnum, &bus_state->resuming_ports);
1684                        /* Do the rest in GetPortStatus after resume time delay.
1685                         * Avoid polling roothub status before that so that a
1686                         * usb device auto-resume latency around ~40ms.
1687                         */
1688                        set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1689                        mod_timer(&hcd->rh_timer,
1690                                  bus_state->resume_done[hcd_portnum]);
1691                        usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1692                        bogus_port_status = true;
1693                }
1694        }
1695
1696        if ((portsc & PORT_PLC) &&
1697            DEV_SUPERSPEED_ANY(portsc) &&
1698            ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1699             (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1700             (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1701                xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1702                complete(&bus_state->u3exit_done[hcd_portnum]);
1703                /* We've just brought the device into U0/1/2 through either the
1704                 * Resume state after a device remote wakeup, or through the
1705                 * U3Exit state after a host-initiated resume.  If it's a device
1706                 * initiated remote wake, don't pass up the link state change,
1707                 * so the roothub behavior is consistent with external
1708                 * USB 3.0 hub behavior.
1709                 */
1710                slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1711                if (slot_id && xhci->devs[slot_id])
1712                        xhci_ring_device(xhci, slot_id);
1713                if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1714                        xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1715                        usb_wakeup_notification(hcd->self.root_hub,
1716                                        hcd_portnum + 1);
1717                        bogus_port_status = true;
1718                        goto cleanup;
1719                }
1720        }
1721
1722        /*
1723         * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1724         * RExit to a disconnect state).  If so, let the the driver know it's
1725         * out of the RExit state.
1726         */
1727        if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1728                        test_and_clear_bit(hcd_portnum,
1729                                &bus_state->rexit_ports)) {
1730                complete(&bus_state->rexit_done[hcd_portnum]);
1731                bogus_port_status = true;
1732                goto cleanup;
1733        }
1734
1735        if (hcd->speed < HCD_USB3) {
1736                xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1737                if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1738                    (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1739                        xhci_cavium_reset_phy_quirk(xhci);
1740        }
1741
1742cleanup:
1743        /* Update event ring dequeue pointer before dropping the lock */
1744        inc_deq(xhci, xhci->event_ring);
1745
1746        /* Don't make the USB core poll the roothub if we got a bad port status
1747         * change event.  Besides, at that point we can't tell which roothub
1748         * (USB 2.0 or USB 3.0) to kick.
1749         */
1750        if (bogus_port_status)
1751                return;
1752
1753        /*
1754         * xHCI port-status-change events occur when the "or" of all the
1755         * status-change bits in the portsc register changes from 0 to 1.
1756         * New status changes won't cause an event if any other change
1757         * bits are still set.  When an event occurs, switch over to
1758         * polling to avoid losing status changes.
1759         */
1760        xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1761        set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1762        spin_unlock(&xhci->lock);
1763        /* Pass this up to the core */
1764        usb_hcd_poll_rh_status(hcd);
1765        spin_lock(&xhci->lock);
1766}
1767
1768/*
1769 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1770 * at end_trb, which may be in another segment.  If the suspect DMA address is a
1771 * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1772 * returns 0.
1773 */
1774struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1775                struct xhci_segment *start_seg,
1776                union xhci_trb  *start_trb,
1777                union xhci_trb  *end_trb,
1778                dma_addr_t      suspect_dma,
1779                bool            debug)
1780{
1781        dma_addr_t start_dma;
1782        dma_addr_t end_seg_dma;
1783        dma_addr_t end_trb_dma;
1784        struct xhci_segment *cur_seg;
1785
1786        start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1787        cur_seg = start_seg;
1788
1789        do {
1790                if (start_dma == 0)
1791                        return NULL;
1792                /* We may get an event for a Link TRB in the middle of a TD */
1793                end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1794                                &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1795                /* If the end TRB isn't in this segment, this is set to 0 */
1796                end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1797
1798                if (debug)
1799                        xhci_warn(xhci,
1800                                "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1801                                (unsigned long long)suspect_dma,
1802                                (unsigned long long)start_dma,
1803                                (unsigned long long)end_trb_dma,
1804                                (unsigned long long)cur_seg->dma,
1805                                (unsigned long long)end_seg_dma);
1806
1807                if (end_trb_dma > 0) {
1808                        /* The end TRB is in this segment, so suspect should be here */
1809                        if (start_dma <= end_trb_dma) {
1810                                if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1811                                        return cur_seg;
1812                        } else {
1813                                /* Case for one segment with
1814                                 * a TD wrapped around to the top
1815                                 */
1816                                if ((suspect_dma >= start_dma &&
1817                                                        suspect_dma <= end_seg_dma) ||
1818                                                (suspect_dma >= cur_seg->dma &&
1819                                                 suspect_dma <= end_trb_dma))
1820                                        return cur_seg;
1821                        }
1822                        return NULL;
1823                } else {
1824                        /* Might still be somewhere in this segment */
1825                        if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1826                                return cur_seg;
1827                }
1828                cur_seg = cur_seg->next;
1829                start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1830        } while (cur_seg != start_seg);
1831
1832        return NULL;
1833}
1834
1835static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
1836                struct xhci_virt_ep *ep)
1837{
1838        /*
1839         * As part of low/full-speed endpoint-halt processing
1840         * we must clear the TT buffer (USB 2.0 specification 11.17.5).
1841         */
1842        if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
1843            (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
1844            !(ep->ep_state & EP_CLEARING_TT)) {
1845                ep->ep_state |= EP_CLEARING_TT;
1846                td->urb->ep->hcpriv = td->urb->dev;
1847                if (usb_hub_clear_tt_buffer(td->urb))
1848                        ep->ep_state &= ~EP_CLEARING_TT;
1849        }
1850}
1851
1852static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1853                unsigned int slot_id, unsigned int ep_index,
1854                unsigned int stream_id, struct xhci_td *td,
1855                enum xhci_ep_reset_type reset_type)
1856{
1857        struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1858        struct xhci_command *command;
1859
1860        /*
1861         * Avoid resetting endpoint if link is inactive. Can cause host hang.
1862         * Device will be reset soon to recover the link so don't do anything
1863         */
1864        if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR)
1865                return;
1866
1867        command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1868        if (!command)
1869                return;
1870
1871        ep->ep_state |= EP_HALTED;
1872
1873        xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
1874
1875        if (reset_type == EP_HARD_RESET) {
1876                ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
1877                xhci_cleanup_stalled_ring(xhci, slot_id, ep_index, stream_id,
1878                                          td);
1879        }
1880        xhci_ring_cmd_db(xhci);
1881}
1882
1883/* Check if an error has halted the endpoint ring.  The class driver will
1884 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1885 * However, a babble and other errors also halt the endpoint ring, and the class
1886 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1887 * Ring Dequeue Pointer command manually.
1888 */
1889static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1890                struct xhci_ep_ctx *ep_ctx,
1891                unsigned int trb_comp_code)
1892{
1893        /* TRB completion codes that may require a manual halt cleanup */
1894        if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
1895                        trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
1896                        trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
1897                /* The 0.95 spec says a babbling control endpoint
1898                 * is not halted. The 0.96 spec says it is.  Some HW
1899                 * claims to be 0.95 compliant, but it halts the control
1900                 * endpoint anyway.  Check if a babble halted the
1901                 * endpoint.
1902                 */
1903                if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
1904                        return 1;
1905
1906        return 0;
1907}
1908
1909int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1910{
1911        if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1912                /* Vendor defined "informational" completion code,
1913                 * treat as not-an-error.
1914                 */
1915                xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1916                                trb_comp_code);
1917                xhci_dbg(xhci, "Treating code as success.\n");
1918                return 1;
1919        }
1920        return 0;
1921}
1922
1923static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
1924                struct xhci_ring *ep_ring, int *status)
1925{
1926        struct urb *urb = NULL;
1927
1928        /* Clean up the endpoint's TD list */
1929        urb = td->urb;
1930
1931        /* if a bounce buffer was used to align this td then unmap it */
1932        xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
1933
1934        /* Do one last check of the actual transfer length.
1935         * If the host controller said we transferred more data than the buffer
1936         * length, urb->actual_length will be a very big number (since it's
1937         * unsigned).  Play it safe and say we didn't transfer anything.
1938         */
1939        if (urb->actual_length > urb->transfer_buffer_length) {
1940                xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
1941                          urb->transfer_buffer_length, urb->actual_length);
1942                urb->actual_length = 0;
1943                *status = 0;
1944        }
1945        list_del_init(&td->td_list);
1946        /* Was this TD slated to be cancelled but completed anyway? */
1947        if (!list_empty(&td->cancelled_td_list))
1948                list_del_init(&td->cancelled_td_list);
1949
1950        inc_td_cnt(urb);
1951        /* Giveback the urb when all the tds are completed */
1952        if (last_td_in_urb(td)) {
1953                if ((urb->actual_length != urb->transfer_buffer_length &&
1954                     (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
1955                    (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
1956                        xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
1957                                 urb, urb->actual_length,
1958                                 urb->transfer_buffer_length, *status);
1959
1960                /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
1961                if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
1962                        *status = 0;
1963                xhci_giveback_urb_in_irq(xhci, td, *status);
1964        }
1965
1966        return 0;
1967}
1968
1969static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1970        struct xhci_transfer_event *event,
1971        struct xhci_virt_ep *ep, int *status)
1972{
1973        struct xhci_virt_device *xdev;
1974        struct xhci_ep_ctx *ep_ctx;
1975        struct xhci_ring *ep_ring;
1976        unsigned int slot_id;
1977        u32 trb_comp_code;
1978        int ep_index;
1979
1980        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1981        xdev = xhci->devs[slot_id];
1982        ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1983        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1984        ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1985        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1986
1987        if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
1988                        trb_comp_code == COMP_STOPPED ||
1989                        trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
1990                /* The Endpoint Stop Command completion will take care of any
1991                 * stopped TDs.  A stopped TD may be restarted, so don't update
1992                 * the ring dequeue pointer or take this TD off any lists yet.
1993                 */
1994                return 0;
1995        }
1996        if (trb_comp_code == COMP_STALL_ERROR ||
1997                xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1998                                                trb_comp_code)) {
1999                /*
2000                 * xhci internal endpoint state will go to a "halt" state for
2001                 * any stall, including default control pipe protocol stall.
2002                 * To clear the host side halt we need to issue a reset endpoint
2003                 * command, followed by a set dequeue command to move past the
2004                 * TD.
2005                 * Class drivers clear the device side halt from a functional
2006                 * stall later. Hub TT buffer should only be cleared for FS/LS
2007                 * devices behind HS hubs for functional stalls.
2008                 */
2009                if ((ep_index != 0) || (trb_comp_code != COMP_STALL_ERROR))
2010                        xhci_clear_hub_tt_buffer(xhci, td, ep);
2011                xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
2012                                        ep_ring->stream_id, td, EP_HARD_RESET);
2013        } else {
2014                /* Update ring dequeue pointer */
2015                while (ep_ring->dequeue != td->last_trb)
2016                        inc_deq(xhci, ep_ring);
2017                inc_deq(xhci, ep_ring);
2018        }
2019
2020        return xhci_td_cleanup(xhci, td, ep_ring, status);
2021}
2022
2023/* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2024static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2025                           union xhci_trb *stop_trb)
2026{
2027        u32 sum;
2028        union xhci_trb *trb = ring->dequeue;
2029        struct xhci_segment *seg = ring->deq_seg;
2030
2031        for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2032                if (!trb_is_noop(trb) && !trb_is_link(trb))
2033                        sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2034        }
2035        return sum;
2036}
2037
2038/*
2039 * Process control tds, update urb status and actual_length.
2040 */
2041static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2042        union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2043        struct xhci_virt_ep *ep, int *status)
2044{
2045        struct xhci_virt_device *xdev;
2046        unsigned int slot_id;
2047        int ep_index;
2048        struct xhci_ep_ctx *ep_ctx;
2049        u32 trb_comp_code;
2050        u32 remaining, requested;
2051        u32 trb_type;
2052
2053        trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2054        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2055        xdev = xhci->devs[slot_id];
2056        ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2057        ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2058        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2059        requested = td->urb->transfer_buffer_length;
2060        remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2061
2062        switch (trb_comp_code) {
2063        case COMP_SUCCESS:
2064                if (trb_type != TRB_STATUS) {
2065                        xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2066                                  (trb_type == TRB_DATA) ? "data" : "setup");
2067                        *status = -ESHUTDOWN;
2068                        break;
2069                }
2070                *status = 0;
2071                break;
2072        case COMP_SHORT_PACKET:
2073                *status = 0;
2074                break;
2075        case COMP_STOPPED_SHORT_PACKET:
2076                if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2077                        td->urb->actual_length = remaining;
2078                else
2079                        xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2080                goto finish_td;
2081        case COMP_STOPPED:
2082                switch (trb_type) {
2083                case TRB_SETUP:
2084                        td->urb->actual_length = 0;
2085                        goto finish_td;
2086                case TRB_DATA:
2087                case TRB_NORMAL:
2088                        td->urb->actual_length = requested - remaining;
2089                        goto finish_td;
2090                case TRB_STATUS:
2091                        td->urb->actual_length = requested;
2092                        goto finish_td;
2093                default:
2094                        xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2095                                  trb_type);
2096                        goto finish_td;
2097                }
2098        case COMP_STOPPED_LENGTH_INVALID:
2099                goto finish_td;
2100        default:
2101                if (!xhci_requires_manual_halt_cleanup(xhci,
2102                                                       ep_ctx, trb_comp_code))
2103                        break;
2104                xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2105                         trb_comp_code, ep_index);
2106                fallthrough;
2107        case COMP_STALL_ERROR:
2108                /* Did we transfer part of the data (middle) phase? */
2109                if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2110                        td->urb->actual_length = requested - remaining;
2111                else if (!td->urb_length_set)
2112                        td->urb->actual_length = 0;
2113                goto finish_td;
2114        }
2115
2116        /* stopped at setup stage, no data transferred */
2117        if (trb_type == TRB_SETUP)
2118                goto finish_td;
2119
2120        /*
2121         * if on data stage then update the actual_length of the URB and flag it
2122         * as set, so it won't be overwritten in the event for the last TRB.
2123         */
2124        if (trb_type == TRB_DATA ||
2125                trb_type == TRB_NORMAL) {
2126                td->urb_length_set = true;
2127                td->urb->actual_length = requested - remaining;
2128                xhci_dbg(xhci, "Waiting for status stage event\n");
2129                return 0;
2130        }
2131
2132        /* at status stage */
2133        if (!td->urb_length_set)
2134                td->urb->actual_length = requested;
2135
2136finish_td:
2137        return finish_td(xhci, td, event, ep, status);
2138}
2139
2140/*
2141 * Process isochronous tds, update urb packet status and actual_length.
2142 */
2143static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2144        union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2145        struct xhci_virt_ep *ep, int *status)
2146{
2147        struct xhci_ring *ep_ring;
2148        struct urb_priv *urb_priv;
2149        int idx;
2150        struct usb_iso_packet_descriptor *frame;
2151        u32 trb_comp_code;
2152        bool sum_trbs_for_length = false;
2153        u32 remaining, requested, ep_trb_len;
2154        int short_framestatus;
2155
2156        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2157        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2158        urb_priv = td->urb->hcpriv;
2159        idx = urb_priv->num_tds_done;
2160        frame = &td->urb->iso_frame_desc[idx];
2161        requested = frame->length;
2162        remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2163        ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2164        short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2165                -EREMOTEIO : 0;
2166
2167        /* handle completion code */
2168        switch (trb_comp_code) {
2169        case COMP_SUCCESS:
2170                if (remaining) {
2171                        frame->status = short_framestatus;
2172                        if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2173                                sum_trbs_for_length = true;
2174                        break;
2175                }
2176                frame->status = 0;
2177                break;
2178        case COMP_SHORT_PACKET:
2179                frame->status = short_framestatus;
2180                sum_trbs_for_length = true;
2181                break;
2182        case COMP_BANDWIDTH_OVERRUN_ERROR:
2183                frame->status = -ECOMM;
2184                break;
2185        case COMP_ISOCH_BUFFER_OVERRUN:
2186        case COMP_BABBLE_DETECTED_ERROR:
2187                frame->status = -EOVERFLOW;
2188                break;
2189        case COMP_INCOMPATIBLE_DEVICE_ERROR:
2190        case COMP_STALL_ERROR:
2191                frame->status = -EPROTO;
2192                break;
2193        case COMP_USB_TRANSACTION_ERROR:
2194                frame->status = -EPROTO;
2195                if (ep_trb != td->last_trb)
2196                        return 0;
2197                break;
2198        case COMP_STOPPED:
2199                sum_trbs_for_length = true;
2200                break;
2201        case COMP_STOPPED_SHORT_PACKET:
2202                /* field normally containing residue now contains tranferred */
2203                frame->status = short_framestatus;
2204                requested = remaining;
2205                break;
2206        case COMP_STOPPED_LENGTH_INVALID:
2207                requested = 0;
2208                remaining = 0;
2209                break;
2210        default:
2211                sum_trbs_for_length = true;
2212                frame->status = -1;
2213                break;
2214        }
2215
2216        if (sum_trbs_for_length)
2217                frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) +
2218                        ep_trb_len - remaining;
2219        else
2220                frame->actual_length = requested;
2221
2222        td->urb->actual_length += frame->actual_length;
2223
2224        return finish_td(xhci, td, event, ep, status);
2225}
2226
2227static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2228                        struct xhci_transfer_event *event,
2229                        struct xhci_virt_ep *ep, int *status)
2230{
2231        struct xhci_ring *ep_ring;
2232        struct urb_priv *urb_priv;
2233        struct usb_iso_packet_descriptor *frame;
2234        int idx;
2235
2236        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2237        urb_priv = td->urb->hcpriv;
2238        idx = urb_priv->num_tds_done;
2239        frame = &td->urb->iso_frame_desc[idx];
2240
2241        /* The transfer is partly done. */
2242        frame->status = -EXDEV;
2243
2244        /* calc actual length */
2245        frame->actual_length = 0;
2246
2247        /* Update ring dequeue pointer */
2248        while (ep_ring->dequeue != td->last_trb)
2249                inc_deq(xhci, ep_ring);
2250        inc_deq(xhci, ep_ring);
2251
2252        return xhci_td_cleanup(xhci, td, ep_ring, status);
2253}
2254
2255/*
2256 * Process bulk and interrupt tds, update urb status and actual_length.
2257 */
2258static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2259        union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2260        struct xhci_virt_ep *ep, int *status)
2261{
2262        struct xhci_slot_ctx *slot_ctx;
2263        struct xhci_ring *ep_ring;
2264        u32 trb_comp_code;
2265        u32 remaining, requested, ep_trb_len;
2266        unsigned int slot_id;
2267        int ep_index;
2268
2269        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2270        slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[slot_id]->out_ctx);
2271        ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2272        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2273        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2274        remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2275        ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2276        requested = td->urb->transfer_buffer_length;
2277
2278        switch (trb_comp_code) {
2279        case COMP_SUCCESS:
2280                ep_ring->err_count = 0;
2281                /* handle success with untransferred data as short packet */
2282                if (ep_trb != td->last_trb || remaining) {
2283                        xhci_warn(xhci, "WARN Successful completion on short TX\n");
2284                        xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2285                                 td->urb->ep->desc.bEndpointAddress,
2286                                 requested, remaining);
2287                }
2288                *status = 0;
2289                break;
2290        case COMP_SHORT_PACKET:
2291                xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2292                         td->urb->ep->desc.bEndpointAddress,
2293                         requested, remaining);
2294                *status = 0;
2295                break;
2296        case COMP_STOPPED_SHORT_PACKET:
2297                td->urb->actual_length = remaining;
2298                goto finish_td;
2299        case COMP_STOPPED_LENGTH_INVALID:
2300                /* stopped on ep trb with invalid length, exclude it */
2301                ep_trb_len      = 0;
2302                remaining       = 0;
2303                break;
2304        case COMP_USB_TRANSACTION_ERROR:
2305                if ((ep_ring->err_count++ > MAX_SOFT_RETRY) ||
2306                    le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2307                        break;
2308                *status = 0;
2309                xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
2310                                        ep_ring->stream_id, td, EP_SOFT_RESET);
2311                return 0;
2312        default:
2313                /* do nothing */
2314                break;
2315        }
2316
2317        if (ep_trb == td->last_trb)
2318                td->urb->actual_length = requested - remaining;
2319        else
2320                td->urb->actual_length =
2321                        sum_trb_lengths(xhci, ep_ring, ep_trb) +
2322                        ep_trb_len - remaining;
2323finish_td:
2324        if (remaining > requested) {
2325                xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2326                          remaining);
2327                td->urb->actual_length = 0;
2328        }
2329        return finish_td(xhci, td, event, ep, status);
2330}
2331
2332/*
2333 * If this function returns an error condition, it means it got a Transfer
2334 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2335 * At this point, the host controller is probably hosed and should be reset.
2336 */
2337static int handle_tx_event(struct xhci_hcd *xhci,
2338                struct xhci_transfer_event *event)
2339{
2340        struct xhci_virt_device *xdev;
2341        struct xhci_virt_ep *ep;
2342        struct xhci_ring *ep_ring;
2343        unsigned int slot_id;
2344        int ep_index;
2345        struct xhci_td *td = NULL;
2346        dma_addr_t ep_trb_dma;
2347        struct xhci_segment *ep_seg;
2348        union xhci_trb *ep_trb;
2349        int status = -EINPROGRESS;
2350        struct xhci_ep_ctx *ep_ctx;
2351        struct list_head *tmp;
2352        u32 trb_comp_code;
2353        int td_num = 0;
2354        bool handling_skipped_tds = false;
2355
2356        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2357        ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2358        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2359        ep_trb_dma = le64_to_cpu(event->buffer);
2360
2361        xdev = xhci->devs[slot_id];
2362        if (!xdev) {
2363                xhci_err(xhci, "ERROR Transfer event pointed to bad slot %u\n",
2364                         slot_id);
2365                goto err_out;
2366        }
2367
2368        ep = &xdev->eps[ep_index];
2369        ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2370        ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2371
2372        if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2373                xhci_err(xhci,
2374                         "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2375                          slot_id, ep_index);
2376                goto err_out;
2377        }
2378
2379        /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2380        if (!ep_ring) {
2381                switch (trb_comp_code) {
2382                case COMP_STALL_ERROR:
2383                case COMP_USB_TRANSACTION_ERROR:
2384                case COMP_INVALID_STREAM_TYPE_ERROR:
2385                case COMP_INVALID_STREAM_ID_ERROR:
2386                        xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0,
2387                                                     NULL, EP_SOFT_RESET);
2388                        goto cleanup;
2389                case COMP_RING_UNDERRUN:
2390                case COMP_RING_OVERRUN:
2391                case COMP_STOPPED_LENGTH_INVALID:
2392                        goto cleanup;
2393                default:
2394                        xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2395                                 slot_id, ep_index);
2396                        goto err_out;
2397                }
2398        }
2399
2400        /* Count current td numbers if ep->skip is set */
2401        if (ep->skip) {
2402                list_for_each(tmp, &ep_ring->td_list)
2403                        td_num++;
2404        }
2405
2406        /* Look for common error cases */
2407        switch (trb_comp_code) {
2408        /* Skip codes that require special handling depending on
2409         * transfer type
2410         */
2411        case COMP_SUCCESS:
2412                if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2413                        break;
2414                if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2415                    ep_ring->last_td_was_short)
2416                        trb_comp_code = COMP_SHORT_PACKET;
2417                else
2418                        xhci_warn_ratelimited(xhci,
2419                                              "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2420                                              slot_id, ep_index);
2421        case COMP_SHORT_PACKET:
2422                break;
2423        /* Completion codes for endpoint stopped state */
2424        case COMP_STOPPED:
2425                xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2426                         slot_id, ep_index);
2427                break;
2428        case COMP_STOPPED_LENGTH_INVALID:
2429                xhci_dbg(xhci,
2430                         "Stopped on No-op or Link TRB for slot %u ep %u\n",
2431                         slot_id, ep_index);
2432                break;
2433        case COMP_STOPPED_SHORT_PACKET:
2434                xhci_dbg(xhci,
2435                         "Stopped with short packet transfer detected for slot %u ep %u\n",
2436                         slot_id, ep_index);
2437                break;
2438        /* Completion codes for endpoint halted state */
2439        case COMP_STALL_ERROR:
2440                xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2441                         ep_index);
2442                ep->ep_state |= EP_HALTED;
2443                status = -EPIPE;
2444                break;
2445        case COMP_SPLIT_TRANSACTION_ERROR:
2446                xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2447                         slot_id, ep_index);
2448                status = -EPROTO;
2449                break;
2450        case COMP_USB_TRANSACTION_ERROR:
2451                xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2452                         slot_id, ep_index);
2453                status = -EPROTO;
2454                break;
2455        case COMP_BABBLE_DETECTED_ERROR:
2456                xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2457                         slot_id, ep_index);
2458                status = -EOVERFLOW;
2459                break;
2460        /* Completion codes for endpoint error state */
2461        case COMP_TRB_ERROR:
2462                xhci_warn(xhci,
2463                          "WARN: TRB error for slot %u ep %u on endpoint\n",
2464                          slot_id, ep_index);
2465                status = -EILSEQ;
2466                break;
2467        /* completion codes not indicating endpoint state change */
2468        case COMP_DATA_BUFFER_ERROR:
2469                xhci_warn(xhci,
2470                          "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2471                          slot_id, ep_index);
2472                status = -ENOSR;
2473                break;
2474        case COMP_BANDWIDTH_OVERRUN_ERROR:
2475                xhci_warn(xhci,
2476                          "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2477                          slot_id, ep_index);
2478                break;
2479        case COMP_ISOCH_BUFFER_OVERRUN:
2480                xhci_warn(xhci,
2481                          "WARN: buffer overrun event for slot %u ep %u on endpoint",
2482                          slot_id, ep_index);
2483                break;
2484        case COMP_RING_UNDERRUN:
2485                /*
2486                 * When the Isoch ring is empty, the xHC will generate
2487                 * a Ring Overrun Event for IN Isoch endpoint or Ring
2488                 * Underrun Event for OUT Isoch endpoint.
2489                 */
2490                xhci_dbg(xhci, "underrun event on endpoint\n");
2491                if (!list_empty(&ep_ring->td_list))
2492                        xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2493                                        "still with TDs queued?\n",
2494                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2495                                 ep_index);
2496                goto cleanup;
2497        case COMP_RING_OVERRUN:
2498                xhci_dbg(xhci, "overrun event on endpoint\n");
2499                if (!list_empty(&ep_ring->td_list))
2500                        xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2501                                        "still with TDs queued?\n",
2502                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2503                                 ep_index);
2504                goto cleanup;
2505        case COMP_MISSED_SERVICE_ERROR:
2506                /*
2507                 * When encounter missed service error, one or more isoc tds
2508                 * may be missed by xHC.
2509                 * Set skip flag of the ep_ring; Complete the missed tds as
2510                 * short transfer when process the ep_ring next time.
2511                 */
2512                ep->skip = true;
2513                xhci_dbg(xhci,
2514                         "Miss service interval error for slot %u ep %u, set skip flag\n",
2515                         slot_id, ep_index);
2516                goto cleanup;
2517        case COMP_NO_PING_RESPONSE_ERROR:
2518                ep->skip = true;
2519                xhci_dbg(xhci,
2520                         "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2521                         slot_id, ep_index);
2522                goto cleanup;
2523
2524        case COMP_INCOMPATIBLE_DEVICE_ERROR:
2525                /* needs disable slot command to recover */
2526                xhci_warn(xhci,
2527                          "WARN: detect an incompatible device for slot %u ep %u",
2528                          slot_id, ep_index);
2529                status = -EPROTO;
2530                break;
2531        default:
2532                if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2533                        status = 0;
2534                        break;
2535                }
2536                xhci_warn(xhci,
2537                          "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2538                          trb_comp_code, slot_id, ep_index);
2539                goto cleanup;
2540        }
2541
2542        do {
2543                /* This TRB should be in the TD at the head of this ring's
2544                 * TD list.
2545                 */
2546                if (list_empty(&ep_ring->td_list)) {
2547                        /*
2548                         * Don't print wanings if it's due to a stopped endpoint
2549                         * generating an extra completion event if the device
2550                         * was suspended. Or, a event for the last TRB of a
2551                         * short TD we already got a short event for.
2552                         * The short TD is already removed from the TD list.
2553                         */
2554
2555                        if (!(trb_comp_code == COMP_STOPPED ||
2556                              trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2557                              ep_ring->last_td_was_short)) {
2558                                xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2559                                                TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2560                                                ep_index);
2561                        }
2562                        if (ep->skip) {
2563                                ep->skip = false;
2564                                xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2565                                         slot_id, ep_index);
2566                        }
2567                        if (trb_comp_code == COMP_STALL_ERROR ||
2568                            xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2569                                                              trb_comp_code)) {
2570                                xhci_cleanup_halted_endpoint(xhci, slot_id,
2571                                                             ep_index,
2572                                                             ep_ring->stream_id,
2573                                                             NULL,
2574                                                             EP_HARD_RESET);
2575                        }
2576                        goto cleanup;
2577                }
2578
2579                /* We've skipped all the TDs on the ep ring when ep->skip set */
2580                if (ep->skip && td_num == 0) {
2581                        ep->skip = false;
2582                        xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2583                                 slot_id, ep_index);
2584                        goto cleanup;
2585                }
2586
2587                td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2588                                      td_list);
2589                if (ep->skip)
2590                        td_num--;
2591
2592                /* Is this a TRB in the currently executing TD? */
2593                ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2594                                td->last_trb, ep_trb_dma, false);
2595
2596                /*
2597                 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2598                 * is not in the current TD pointed by ep_ring->dequeue because
2599                 * that the hardware dequeue pointer still at the previous TRB
2600                 * of the current TD. The previous TRB maybe a Link TD or the
2601                 * last TRB of the previous TD. The command completion handle
2602                 * will take care the rest.
2603                 */
2604                if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2605                           trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2606                        goto cleanup;
2607                }
2608
2609                if (!ep_seg) {
2610                        if (!ep->skip ||
2611                            !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2612                                /* Some host controllers give a spurious
2613                                 * successful event after a short transfer.
2614                                 * Ignore it.
2615                                 */
2616                                if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2617                                                ep_ring->last_td_was_short) {
2618                                        ep_ring->last_td_was_short = false;
2619                                        goto cleanup;
2620                                }
2621                                /* HC is busted, give up! */
2622                                xhci_err(xhci,
2623                                        "ERROR Transfer event TRB DMA ptr not "
2624                                        "part of current TD ep_index %d "
2625                                        "comp_code %u\n", ep_index,
2626                                        trb_comp_code);
2627                                trb_in_td(xhci, ep_ring->deq_seg,
2628                                          ep_ring->dequeue, td->last_trb,
2629                                          ep_trb_dma, true);
2630                                return -ESHUTDOWN;
2631                        }
2632
2633                        skip_isoc_td(xhci, td, event, ep, &status);
2634                        goto cleanup;
2635                }
2636                if (trb_comp_code == COMP_SHORT_PACKET)
2637                        ep_ring->last_td_was_short = true;
2638                else
2639                        ep_ring->last_td_was_short = false;
2640
2641                if (ep->skip) {
2642                        xhci_dbg(xhci,
2643                                 "Found td. Clear skip flag for slot %u ep %u.\n",
2644                                 slot_id, ep_index);
2645                        ep->skip = false;
2646                }
2647
2648                ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2649                                                sizeof(*ep_trb)];
2650
2651                trace_xhci_handle_transfer(ep_ring,
2652                                (struct xhci_generic_trb *) ep_trb);
2653
2654                /*
2655                 * No-op TRB could trigger interrupts in a case where
2656                 * a URB was killed and a STALL_ERROR happens right
2657                 * after the endpoint ring stopped. Reset the halted
2658                 * endpoint. Otherwise, the endpoint remains stalled
2659                 * indefinitely.
2660                 */
2661                if (trb_is_noop(ep_trb)) {
2662                        if (trb_comp_code == COMP_STALL_ERROR ||
2663                            xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2664                                                              trb_comp_code))
2665                                xhci_cleanup_halted_endpoint(xhci, slot_id,
2666                                                             ep_index,
2667                                                             ep_ring->stream_id,
2668                                                             td, EP_HARD_RESET);
2669                        goto cleanup;
2670                }
2671
2672                /* update the urb's actual_length and give back to the core */
2673                if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2674                        process_ctrl_td(xhci, td, ep_trb, event, ep, &status);
2675                else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2676                        process_isoc_td(xhci, td, ep_trb, event, ep, &status);
2677                else
2678                        process_bulk_intr_td(xhci, td, ep_trb, event, ep,
2679                                             &status);
2680cleanup:
2681                handling_skipped_tds = ep->skip &&
2682                        trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2683                        trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2684
2685                /*
2686                 * Do not update event ring dequeue pointer if we're in a loop
2687                 * processing missed tds.
2688                 */
2689                if (!handling_skipped_tds)
2690                        inc_deq(xhci, xhci->event_ring);
2691
2692        /*
2693         * If ep->skip is set, it means there are missed tds on the
2694         * endpoint ring need to take care of.
2695         * Process them as short transfer until reach the td pointed by
2696         * the event.
2697         */
2698        } while (handling_skipped_tds);
2699
2700        return 0;
2701
2702err_out:
2703        xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2704                 (unsigned long long) xhci_trb_virt_to_dma(
2705                         xhci->event_ring->deq_seg,
2706                         xhci->event_ring->dequeue),
2707                 lower_32_bits(le64_to_cpu(event->buffer)),
2708                 upper_32_bits(le64_to_cpu(event->buffer)),
2709                 le32_to_cpu(event->transfer_len),
2710                 le32_to_cpu(event->flags));
2711        return -ENODEV;
2712}
2713
2714/*
2715 * This function handles all OS-owned events on the event ring.  It may drop
2716 * xhci->lock between event processing (e.g. to pass up port status changes).
2717 * Returns >0 for "possibly more events to process" (caller should call again),
2718 * otherwise 0 if done.  In future, <0 returns should indicate error code.
2719 */
2720static int xhci_handle_event(struct xhci_hcd *xhci)
2721{
2722        union xhci_trb *event;
2723        int update_ptrs = 1;
2724        int ret;
2725
2726        /* Event ring hasn't been allocated yet. */
2727        if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2728                xhci_err(xhci, "ERROR event ring not ready\n");
2729                return -ENOMEM;
2730        }
2731
2732        event = xhci->event_ring->dequeue;
2733        /* Does the HC or OS own the TRB? */
2734        if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2735            xhci->event_ring->cycle_state)
2736                return 0;
2737
2738        trace_xhci_handle_event(xhci->event_ring, &event->generic);
2739
2740        /*
2741         * Barrier between reading the TRB_CYCLE (valid) flag above and any
2742         * speculative reads of the event's flags/data below.
2743         */
2744        rmb();
2745        /* FIXME: Handle more event types. */
2746        switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) {
2747        case TRB_TYPE(TRB_COMPLETION):
2748                handle_cmd_completion(xhci, &event->event_cmd);
2749                break;
2750        case TRB_TYPE(TRB_PORT_STATUS):
2751                handle_port_status(xhci, event);
2752                update_ptrs = 0;
2753                break;
2754        case TRB_TYPE(TRB_TRANSFER):
2755                ret = handle_tx_event(xhci, &event->trans_event);
2756                if (ret >= 0)
2757                        update_ptrs = 0;
2758                break;
2759        case TRB_TYPE(TRB_DEV_NOTE):
2760                handle_device_notification(xhci, event);
2761                break;
2762        default:
2763                if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2764                    TRB_TYPE(48))
2765                        handle_vendor_event(xhci, event);
2766                else
2767                        xhci_warn(xhci, "ERROR unknown event type %d\n",
2768                                  TRB_FIELD_TO_TYPE(
2769                                  le32_to_cpu(event->event_cmd.flags)));
2770        }
2771        /* Any of the above functions may drop and re-acquire the lock, so check
2772         * to make sure a watchdog timer didn't mark the host as non-responsive.
2773         */
2774        if (xhci->xhc_state & XHCI_STATE_DYING) {
2775                xhci_dbg(xhci, "xHCI host dying, returning from "
2776                                "event handler.\n");
2777                return 0;
2778        }
2779
2780        if (update_ptrs)
2781                /* Update SW event ring dequeue pointer */
2782                inc_deq(xhci, xhci->event_ring);
2783
2784        /* Are there more items on the event ring?  Caller will call us again to
2785         * check.
2786         */
2787        return 1;
2788}
2789
2790/*
2791 * Update Event Ring Dequeue Pointer:
2792 * - When all events have finished
2793 * - To avoid "Event Ring Full Error" condition
2794 */
2795static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
2796                union xhci_trb *event_ring_deq)
2797{
2798        u64 temp_64;
2799        dma_addr_t deq;
2800
2801        temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2802        /* If necessary, update the HW's version of the event ring deq ptr. */
2803        if (event_ring_deq != xhci->event_ring->dequeue) {
2804                deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2805                                xhci->event_ring->dequeue);
2806                if (deq == 0)
2807                        xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
2808                /*
2809                 * Per 4.9.4, Software writes to the ERDP register shall
2810                 * always advance the Event Ring Dequeue Pointer value.
2811                 */
2812                if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
2813                                ((u64) deq & (u64) ~ERST_PTR_MASK))
2814                        return;
2815
2816                /* Update HC event ring dequeue pointer */
2817                temp_64 &= ERST_PTR_MASK;
2818                temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2819        }
2820
2821        /* Clear the event handler busy flag (RW1C) */
2822        temp_64 |= ERST_EHB;
2823        xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2824}
2825
2826/*
2827 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2828 * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2829 * indicators of an event TRB error, but we check the status *first* to be safe.
2830 */
2831irqreturn_t xhci_irq(struct usb_hcd *hcd)
2832{
2833        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2834        union xhci_trb *event_ring_deq;
2835        irqreturn_t ret = IRQ_NONE;
2836        unsigned long flags;
2837        u64 temp_64;
2838        u32 status;
2839        int event_loop = 0;
2840
2841        spin_lock_irqsave(&xhci->lock, flags);
2842        /* Check if the xHC generated the interrupt, or the irq is shared */
2843        status = readl(&xhci->op_regs->status);
2844        if (status == ~(u32)0) {
2845                xhci_hc_died(xhci);
2846                ret = IRQ_HANDLED;
2847                goto out;
2848        }
2849
2850        if (!(status & STS_EINT))
2851                goto out;
2852
2853        if (status & STS_FATAL) {
2854                xhci_warn(xhci, "WARNING: Host System Error\n");
2855                xhci_halt(xhci);
2856                ret = IRQ_HANDLED;
2857                goto out;
2858        }
2859
2860        /*
2861         * Clear the op reg interrupt status first,
2862         * so we can receive interrupts from other MSI-X interrupters.
2863         * Write 1 to clear the interrupt status.
2864         */
2865        status |= STS_EINT;
2866        writel(status, &xhci->op_regs->status);
2867
2868        if (!hcd->msi_enabled) {
2869                u32 irq_pending;
2870                irq_pending = readl(&xhci->ir_set->irq_pending);
2871                irq_pending |= IMAN_IP;
2872                writel(irq_pending, &xhci->ir_set->irq_pending);
2873        }
2874
2875        if (xhci->xhc_state & XHCI_STATE_DYING ||
2876            xhci->xhc_state & XHCI_STATE_HALTED) {
2877                xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2878                                "Shouldn't IRQs be disabled?\n");
2879                /* Clear the event handler busy flag (RW1C);
2880                 * the event ring should be empty.
2881                 */
2882                temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2883                xhci_write_64(xhci, temp_64 | ERST_EHB,
2884                                &xhci->ir_set->erst_dequeue);
2885                ret = IRQ_HANDLED;
2886                goto out;
2887        }
2888
2889        event_ring_deq = xhci->event_ring->dequeue;
2890        /* FIXME this should be a delayed service routine
2891         * that clears the EHB.
2892         */
2893        while (xhci_handle_event(xhci) > 0) {
2894                if (event_loop++ < TRBS_PER_SEGMENT / 2)
2895                        continue;
2896                xhci_update_erst_dequeue(xhci, event_ring_deq);
2897                event_loop = 0;
2898        }
2899
2900        xhci_update_erst_dequeue(xhci, event_ring_deq);
2901        ret = IRQ_HANDLED;
2902
2903out:
2904        spin_unlock_irqrestore(&xhci->lock, flags);
2905
2906        return ret;
2907}
2908
2909irqreturn_t xhci_msi_irq(int irq, void *hcd)
2910{
2911        return xhci_irq(hcd);
2912}
2913
2914/****           Endpoint Ring Operations        ****/
2915
2916/*
2917 * Generic function for queueing a TRB on a ring.
2918 * The caller must have checked to make sure there's room on the ring.
2919 *
2920 * @more_trbs_coming:   Will you enqueue more TRBs before calling
2921 *                      prepare_transfer()?
2922 */
2923static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2924                bool more_trbs_coming,
2925                u32 field1, u32 field2, u32 field3, u32 field4)
2926{
2927        struct xhci_generic_trb *trb;
2928
2929        trb = &ring->enqueue->generic;
2930        trb->field[0] = cpu_to_le32(field1);
2931        trb->field[1] = cpu_to_le32(field2);
2932        trb->field[2] = cpu_to_le32(field3);
2933        trb->field[3] = cpu_to_le32(field4);
2934
2935        trace_xhci_queue_trb(ring, trb);
2936
2937        inc_enq(xhci, ring, more_trbs_coming);
2938}
2939
2940/*
2941 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2942 * FIXME allocate segments if the ring is full.
2943 */
2944static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2945                u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2946{
2947        unsigned int num_trbs_needed;
2948
2949        /* Make sure the endpoint has been added to xHC schedule */
2950        switch (ep_state) {
2951        case EP_STATE_DISABLED:
2952                /*
2953                 * USB core changed config/interfaces without notifying us,
2954                 * or hardware is reporting the wrong state.
2955                 */
2956                xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2957                return -ENOENT;
2958        case EP_STATE_ERROR:
2959                xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2960                /* FIXME event handling code for error needs to clear it */
2961                /* XXX not sure if this should be -ENOENT or not */
2962                return -EINVAL;
2963        case EP_STATE_HALTED:
2964                xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2965        case EP_STATE_STOPPED:
2966        case EP_STATE_RUNNING:
2967                break;
2968        default:
2969                xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2970                /*
2971                 * FIXME issue Configure Endpoint command to try to get the HC
2972                 * back into a known state.
2973                 */
2974                return -EINVAL;
2975        }
2976
2977        while (1) {
2978                if (room_on_ring(xhci, ep_ring, num_trbs))
2979                        break;
2980
2981                if (ep_ring == xhci->cmd_ring) {
2982                        xhci_err(xhci, "Do not support expand command ring\n");
2983                        return -ENOMEM;
2984                }
2985
2986                xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2987                                "ERROR no room on ep ring, try ring expansion");
2988                num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2989                if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2990                                        mem_flags)) {
2991                        xhci_err(xhci, "Ring expansion failed\n");
2992                        return -ENOMEM;
2993                }
2994        }
2995
2996        while (trb_is_link(ep_ring->enqueue)) {
2997                /* If we're not dealing with 0.95 hardware or isoc rings
2998                 * on AMD 0.96 host, clear the chain bit.
2999                 */
3000                if (!xhci_link_trb_quirk(xhci) &&
3001                    !(ep_ring->type == TYPE_ISOC &&
3002                      (xhci->quirks & XHCI_AMD_0x96_HOST)))
3003                        ep_ring->enqueue->link.control &=
3004                                cpu_to_le32(~TRB_CHAIN);
3005                else
3006                        ep_ring->enqueue->link.control |=
3007                                cpu_to_le32(TRB_CHAIN);
3008
3009                wmb();
3010                ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3011
3012                /* Toggle the cycle bit after the last ring segment. */
3013                if (link_trb_toggles_cycle(ep_ring->enqueue))
3014                        ep_ring->cycle_state ^= 1;
3015
3016                ep_ring->enq_seg = ep_ring->enq_seg->next;
3017                ep_ring->enqueue = ep_ring->enq_seg->trbs;
3018        }
3019        return 0;
3020}
3021
3022static int prepare_transfer(struct xhci_hcd *xhci,
3023                struct xhci_virt_device *xdev,
3024                unsigned int ep_index,
3025                unsigned int stream_id,
3026                unsigned int num_trbs,
3027                struct urb *urb,
3028                unsigned int td_index,
3029                gfp_t mem_flags)
3030{
3031        int ret;
3032        struct urb_priv *urb_priv;
3033        struct xhci_td  *td;
3034        struct xhci_ring *ep_ring;
3035        struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3036
3037        ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
3038        if (!ep_ring) {
3039                xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3040                                stream_id);
3041                return -EINVAL;
3042        }
3043
3044        ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3045                           num_trbs, mem_flags);
3046        if (ret)
3047                return ret;
3048
3049        urb_priv = urb->hcpriv;
3050        td = &urb_priv->td[td_index];
3051
3052        INIT_LIST_HEAD(&td->td_list);
3053        INIT_LIST_HEAD(&td->cancelled_td_list);
3054
3055        if (td_index == 0) {
3056                ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3057                if (unlikely(ret))
3058                        return ret;
3059        }
3060
3061        td->urb = urb;
3062        /* Add this TD to the tail of the endpoint ring's TD list */
3063        list_add_tail(&td->td_list, &ep_ring->td_list);
3064        td->start_seg = ep_ring->enq_seg;
3065        td->first_trb = ep_ring->enqueue;
3066
3067        return 0;
3068}
3069
3070unsigned int count_trbs(u64 addr, u64 len)
3071{
3072        unsigned int num_trbs;
3073
3074        num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3075                        TRB_MAX_BUFF_SIZE);
3076        if (num_trbs == 0)
3077                num_trbs++;
3078
3079        return num_trbs;
3080}
3081
3082static inline unsigned int count_trbs_needed(struct urb *urb)
3083{
3084        return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3085}
3086
3087static unsigned int count_sg_trbs_needed(struct urb *urb)
3088{
3089        struct scatterlist *sg;
3090        unsigned int i, len, full_len, num_trbs = 0;
3091
3092        full_len = urb->transfer_buffer_length;
3093
3094        for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3095                len = sg_dma_len(sg);
3096                num_trbs += count_trbs(sg_dma_address(sg), len);
3097                len = min_t(unsigned int, len, full_len);
3098                full_len -= len;
3099                if (full_len == 0)
3100                        break;
3101        }
3102
3103        return num_trbs;
3104}
3105
3106static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3107{
3108        u64 addr, len;
3109
3110        addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3111        len = urb->iso_frame_desc[i].length;
3112
3113        return count_trbs(addr, len);
3114}
3115
3116static void check_trb_math(struct urb *urb, int running_total)
3117{
3118        if (unlikely(running_total != urb->transfer_buffer_length))
3119                dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3120                                "queued %#x (%d), asked for %#x (%d)\n",
3121                                __func__,
3122                                urb->ep->desc.bEndpointAddress,
3123                                running_total, running_total,
3124                                urb->transfer_buffer_length,
3125                                urb->transfer_buffer_length);
3126}
3127
3128static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3129                unsigned int ep_index, unsigned int stream_id, int start_cycle,
3130                struct xhci_generic_trb *start_trb)
3131{
3132        /*
3133         * Pass all the TRBs to the hardware at once and make sure this write
3134         * isn't reordered.
3135         */
3136        wmb();
3137        if (start_cycle)
3138                start_trb->field[3] |= cpu_to_le32(start_cycle);
3139        else
3140                start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3141        xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3142}
3143
3144static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3145                                                struct xhci_ep_ctx *ep_ctx)
3146{
3147        int xhci_interval;
3148        int ep_interval;
3149
3150        xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3151        ep_interval = urb->interval;
3152
3153        /* Convert to microframes */
3154        if (urb->dev->speed == USB_SPEED_LOW ||
3155                        urb->dev->speed == USB_SPEED_FULL)
3156                ep_interval *= 8;
3157
3158        /* FIXME change this to a warning and a suggestion to use the new API
3159         * to set the polling interval (once the API is added).
3160         */
3161        if (xhci_interval != ep_interval) {
3162                dev_dbg_ratelimited(&urb->dev->dev,
3163                                "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3164                                ep_interval, ep_interval == 1 ? "" : "s",
3165                                xhci_interval, xhci_interval == 1 ? "" : "s");
3166                urb->interval = xhci_interval;
3167                /* Convert back to frames for LS/FS devices */
3168                if (urb->dev->speed == USB_SPEED_LOW ||
3169                                urb->dev->speed == USB_SPEED_FULL)
3170                        urb->interval /= 8;
3171        }
3172}
3173
3174/*
3175 * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3176 * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3177 * (comprised of sg list entries) can take several service intervals to
3178 * transmit.
3179 */
3180int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3181                struct urb *urb, int slot_id, unsigned int ep_index)
3182{
3183        struct xhci_ep_ctx *ep_ctx;
3184
3185        ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3186        check_interval(xhci, urb, ep_ctx);
3187
3188        return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3189}
3190
3191/*
3192 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3193 * packets remaining in the TD (*not* including this TRB).
3194 *
3195 * Total TD packet count = total_packet_count =
3196 *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3197 *
3198 * Packets transferred up to and including this TRB = packets_transferred =
3199 *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3200 *
3201 * TD size = total_packet_count - packets_transferred
3202 *
3203 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3204 * including this TRB, right shifted by 10
3205 *
3206 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3207 * This is taken care of in the TRB_TD_SIZE() macro
3208 *
3209 * The last TRB in a TD must have the TD size set to zero.
3210 */
3211static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3212                              int trb_buff_len, unsigned int td_total_len,
3213                              struct urb *urb, bool more_trbs_coming)
3214{
3215        u32 maxp, total_packet_count;
3216
3217        /* MTK xHCI 0.96 contains some features from 1.0 */
3218        if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3219                return ((td_total_len - transferred) >> 10);
3220
3221        /* One TRB with a zero-length data packet. */
3222        if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3223            trb_buff_len == td_total_len)
3224                return 0;
3225
3226        /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3227        if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3228                trb_buff_len = 0;
3229
3230        maxp = usb_endpoint_maxp(&urb->ep->desc);
3231        total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3232
3233        /* Queueing functions don't count the current TRB into transferred */
3234        return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3235}
3236
3237
3238static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3239                         u32 *trb_buff_len, struct xhci_segment *seg)
3240{
3241        struct device *dev = xhci_to_hcd(xhci)->self.controller;
3242        unsigned int unalign;
3243        unsigned int max_pkt;
3244        u32 new_buff_len;
3245        size_t len;
3246
3247        max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3248        unalign = (enqd_len + *trb_buff_len) % max_pkt;
3249
3250        /* we got lucky, last normal TRB data on segment is packet aligned */
3251        if (unalign == 0)
3252                return 0;
3253
3254        xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3255                 unalign, *trb_buff_len);
3256
3257        /* is the last nornal TRB alignable by splitting it */
3258        if (*trb_buff_len > unalign) {
3259                *trb_buff_len -= unalign;
3260                xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3261                return 0;
3262        }
3263
3264        /*
3265         * We want enqd_len + trb_buff_len to sum up to a number aligned to
3266         * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3267         * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3268         */
3269        new_buff_len = max_pkt - (enqd_len % max_pkt);
3270
3271        if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3272                new_buff_len = (urb->transfer_buffer_length - enqd_len);
3273
3274        /* create a max max_pkt sized bounce buffer pointed to by last trb */
3275        if (usb_urb_dir_out(urb)) {
3276                len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3277                                   seg->bounce_buf, new_buff_len, enqd_len);
3278                if (len != new_buff_len)
3279                        xhci_warn(xhci,
3280                                "WARN Wrong bounce buffer write length: %zu != %d\n",
3281                                len, new_buff_len);
3282                seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3283                                                 max_pkt, DMA_TO_DEVICE);
3284        } else {
3285                seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3286                                                 max_pkt, DMA_FROM_DEVICE);
3287        }
3288
3289        if (dma_mapping_error(dev, seg->bounce_dma)) {
3290                /* try without aligning. Some host controllers survive */
3291                xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3292                return 0;
3293        }
3294        *trb_buff_len = new_buff_len;
3295        seg->bounce_len = new_buff_len;
3296        seg->bounce_offs = enqd_len;
3297
3298        xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3299
3300        return 1;
3301}
3302
3303/* This is very similar to what ehci-q.c qtd_fill() does */
3304int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3305                struct urb *urb, int slot_id, unsigned int ep_index)
3306{
3307        struct xhci_ring *ring;
3308        struct urb_priv *urb_priv;
3309        struct xhci_td *td;
3310        struct xhci_generic_trb *start_trb;
3311        struct scatterlist *sg = NULL;
3312        bool more_trbs_coming = true;
3313        bool need_zero_pkt = false;
3314        bool first_trb = true;
3315        unsigned int num_trbs;
3316        unsigned int start_cycle, num_sgs = 0;
3317        unsigned int enqd_len, block_len, trb_buff_len, full_len;
3318        int sent_len, ret;
3319        u32 field, length_field, remainder;
3320        u64 addr, send_addr;
3321
3322        ring = xhci_urb_to_transfer_ring(xhci, urb);
3323        if (!ring)
3324                return -EINVAL;
3325
3326        full_len = urb->transfer_buffer_length;
3327        /* If we have scatter/gather list, we use it. */
3328        if (urb->num_sgs) {
3329                num_sgs = urb->num_mapped_sgs;
3330                sg = urb->sg;
3331                addr = (u64) sg_dma_address(sg);
3332                block_len = sg_dma_len(sg);
3333                num_trbs = count_sg_trbs_needed(urb);
3334        } else {
3335                num_trbs = count_trbs_needed(urb);
3336                addr = (u64) urb->transfer_dma;
3337                block_len = full_len;
3338        }
3339        ret = prepare_transfer(xhci, xhci->devs[slot_id],
3340                        ep_index, urb->stream_id,
3341                        num_trbs, urb, 0, mem_flags);
3342        if (unlikely(ret < 0))
3343                return ret;
3344
3345        urb_priv = urb->hcpriv;
3346
3347        /* Deal with URB_ZERO_PACKET - need one more td/trb */
3348        if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3349                need_zero_pkt = true;
3350
3351        td = &urb_priv->td[0];
3352
3353        /*
3354         * Don't give the first TRB to the hardware (by toggling the cycle bit)
3355         * until we've finished creating all the other TRBs.  The ring's cycle
3356         * state may change as we enqueue the other TRBs, so save it too.
3357         */
3358        start_trb = &ring->enqueue->generic;
3359        start_cycle = ring->cycle_state;
3360        send_addr = addr;
3361
3362        /* Queue the TRBs, even if they are zero-length */
3363        for (enqd_len = 0; first_trb || enqd_len < full_len;
3364                        enqd_len += trb_buff_len) {
3365                field = TRB_TYPE(TRB_NORMAL);
3366
3367                /* TRB buffer should not cross 64KB boundaries */
3368                trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3369                trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3370
3371                if (enqd_len + trb_buff_len > full_len)
3372                        trb_buff_len = full_len - enqd_len;
3373
3374                /* Don't change the cycle bit of the first TRB until later */
3375                if (first_trb) {
3376                        first_trb = false;
3377                        if (start_cycle == 0)
3378                                field |= TRB_CYCLE;
3379                } else
3380                        field |= ring->cycle_state;
3381
3382                /* Chain all the TRBs together; clear the chain bit in the last
3383                 * TRB to indicate it's the last TRB in the chain.
3384                 */
3385                if (enqd_len + trb_buff_len < full_len) {
3386                        field |= TRB_CHAIN;
3387                        if (trb_is_link(ring->enqueue + 1)) {
3388                                if (xhci_align_td(xhci, urb, enqd_len,
3389                                                  &trb_buff_len,
3390                                                  ring->enq_seg)) {
3391                                        send_addr = ring->enq_seg->bounce_dma;
3392                                        /* assuming TD won't span 2 segs */
3393                                        td->bounce_seg = ring->enq_seg;
3394                                }
3395                        }
3396                }
3397                if (enqd_len + trb_buff_len >= full_len) {
3398                        field &= ~TRB_CHAIN;
3399                        field |= TRB_IOC;
3400                        more_trbs_coming = false;
3401                        td->last_trb = ring->enqueue;
3402
3403                        if (xhci_urb_suitable_for_idt(urb)) {
3404                                memcpy(&send_addr, urb->transfer_buffer,
3405                                       trb_buff_len);
3406                                le64_to_cpus(&send_addr);
3407                                field |= TRB_IDT;
3408                        }
3409                }
3410
3411                /* Only set interrupt on short packet for IN endpoints */
3412                if (usb_urb_dir_in(urb))
3413                        field |= TRB_ISP;
3414
3415                /* Set the TRB length, TD size, and interrupter fields. */
3416                remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3417                                              full_len, urb, more_trbs_coming);
3418
3419                length_field = TRB_LEN(trb_buff_len) |
3420                        TRB_TD_SIZE(remainder) |
3421                        TRB_INTR_TARGET(0);
3422
3423                queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3424                                lower_32_bits(send_addr),
3425                                upper_32_bits(send_addr),
3426                                length_field,
3427                                field);
3428
3429                addr += trb_buff_len;
3430                sent_len = trb_buff_len;
3431
3432                while (sg && sent_len >= block_len) {
3433                        /* New sg entry */
3434                        --num_sgs;
3435                        sent_len -= block_len;
3436                        sg = sg_next(sg);
3437                        if (num_sgs != 0 && sg) {
3438                                block_len = sg_dma_len(sg);
3439                                addr = (u64) sg_dma_address(sg);
3440                                addr += sent_len;
3441                        }
3442                }
3443                block_len -= sent_len;
3444                send_addr = addr;
3445        }
3446
3447        if (need_zero_pkt) {
3448                ret = prepare_transfer(xhci, xhci->devs[slot_id],
3449                                       ep_index, urb->stream_id,
3450                                       1, urb, 1, mem_flags);
3451                urb_priv->td[1].last_trb = ring->enqueue;
3452                field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3453                queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3454        }
3455
3456        check_trb_math(urb, enqd_len);
3457        giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3458                        start_cycle, start_trb);
3459        return 0;
3460}
3461
3462/* Caller must have locked xhci->lock */
3463int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3464                struct urb *urb, int slot_id, unsigned int ep_index)
3465{
3466        struct xhci_ring *ep_ring;
3467        int num_trbs;
3468        int ret;
3469        struct usb_ctrlrequest *setup;
3470        struct xhci_generic_trb *start_trb;
3471        int start_cycle;
3472        u32 field;
3473        struct urb_priv *urb_priv;
3474        struct xhci_td *td;
3475
3476        ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3477        if (!ep_ring)
3478                return -EINVAL;
3479
3480        /*
3481         * Need to copy setup packet into setup TRB, so we can't use the setup
3482         * DMA address.
3483         */
3484        if (!urb->setup_packet)
3485                return -EINVAL;
3486
3487        /* 1 TRB for setup, 1 for status */
3488        num_trbs = 2;
3489        /*
3490         * Don't need to check if we need additional event data and normal TRBs,
3491         * since data in control transfers will never get bigger than 16MB
3492         * XXX: can we get a buffer that crosses 64KB boundaries?
3493         */
3494        if (urb->transfer_buffer_length > 0)
3495                num_trbs++;
3496        ret = prepare_transfer(xhci, xhci->devs[slot_id],
3497                        ep_index, urb->stream_id,
3498                        num_trbs, urb, 0, mem_flags);
3499        if (ret < 0)
3500                return ret;
3501
3502        urb_priv = urb->hcpriv;
3503        td = &urb_priv->td[0];
3504
3505        /*
3506         * Don't give the first TRB to the hardware (by toggling the cycle bit)
3507         * until we've finished creating all the other TRBs.  The ring's cycle
3508         * state may change as we enqueue the other TRBs, so save it too.
3509         */
3510        start_trb = &ep_ring->enqueue->generic;
3511        start_cycle = ep_ring->cycle_state;
3512
3513        /* Queue setup TRB - see section 6.4.1.2.1 */
3514        /* FIXME better way to translate setup_packet into two u32 fields? */
3515        setup = (struct usb_ctrlrequest *) urb->setup_packet;
3516        field = 0;
3517        field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3518        if (start_cycle == 0)
3519                field |= 0x1;
3520
3521        /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3522        if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3523                if (urb->transfer_buffer_length > 0) {
3524                        if (setup->bRequestType & USB_DIR_IN)
3525                                field |= TRB_TX_TYPE(TRB_DATA_IN);
3526                        else
3527                                field |= TRB_TX_TYPE(TRB_DATA_OUT);
3528                }
3529        }
3530
3531        queue_trb(xhci, ep_ring, true,
3532                  setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3533                  le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3534                  TRB_LEN(8) | TRB_INTR_TARGET(0),
3535                  /* Immediate data in pointer */
3536                  field);
3537
3538        /* If there's data, queue data TRBs */
3539        /* Only set interrupt on short packet for IN endpoints */
3540        if (usb_urb_dir_in(urb))
3541                field = TRB_ISP | TRB_TYPE(TRB_DATA);
3542        else
3543                field = TRB_TYPE(TRB_DATA);
3544
3545        if (urb->transfer_buffer_length > 0) {
3546                u32 length_field, remainder;
3547                u64 addr;
3548
3549                if (xhci_urb_suitable_for_idt(urb)) {
3550                        memcpy(&addr, urb->transfer_buffer,
3551                               urb->transfer_buffer_length);
3552                        le64_to_cpus(&addr);
3553                        field |= TRB_IDT;
3554                } else {
3555                        addr = (u64) urb->transfer_dma;
3556                }
3557
3558                remainder = xhci_td_remainder(xhci, 0,
3559                                urb->transfer_buffer_length,
3560                                urb->transfer_buffer_length,
3561                                urb, 1);
3562                length_field = TRB_LEN(urb->transfer_buffer_length) |
3563                                TRB_TD_SIZE(remainder) |
3564                                TRB_INTR_TARGET(0);
3565                if (setup->bRequestType & USB_DIR_IN)
3566                        field |= TRB_DIR_IN;
3567                queue_trb(xhci, ep_ring, true,
3568                                lower_32_bits(addr),
3569                                upper_32_bits(addr),
3570                                length_field,
3571                                field | ep_ring->cycle_state);
3572        }
3573
3574        /* Save the DMA address of the last TRB in the TD */
3575        td->last_trb = ep_ring->enqueue;
3576
3577        /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3578        /* If the device sent data, the status stage is an OUT transfer */
3579        if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3580                field = 0;
3581        else
3582                field = TRB_DIR_IN;
3583        queue_trb(xhci, ep_ring, false,
3584                        0,
3585                        0,
3586                        TRB_INTR_TARGET(0),
3587                        /* Event on completion */
3588                        field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3589
3590        giveback_first_trb(xhci, slot_id, ep_index, 0,
3591                        start_cycle, start_trb);
3592        return 0;
3593}
3594
3595/*
3596 * The transfer burst count field of the isochronous TRB defines the number of
3597 * bursts that are required to move all packets in this TD.  Only SuperSpeed
3598 * devices can burst up to bMaxBurst number of packets per service interval.
3599 * This field is zero based, meaning a value of zero in the field means one
3600 * burst.  Basically, for everything but SuperSpeed devices, this field will be
3601 * zero.  Only xHCI 1.0 host controllers support this field.
3602 */
3603static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3604                struct urb *urb, unsigned int total_packet_count)
3605{
3606        unsigned int max_burst;
3607
3608        if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3609                return 0;
3610
3611        max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3612        return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3613}
3614
3615/*
3616 * Returns the number of packets in the last "burst" of packets.  This field is
3617 * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3618 * the last burst packet count is equal to the total number of packets in the
3619 * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3620 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3621 * contain 1 to (bMaxBurst + 1) packets.
3622 */
3623static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3624                struct urb *urb, unsigned int total_packet_count)
3625{
3626        unsigned int max_burst;
3627        unsigned int residue;
3628
3629        if (xhci->hci_version < 0x100)
3630                return 0;
3631
3632        if (urb->dev->speed >= USB_SPEED_SUPER) {
3633                /* bMaxBurst is zero based: 0 means 1 packet per burst */
3634                max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3635                residue = total_packet_count % (max_burst + 1);
3636                /* If residue is zero, the last burst contains (max_burst + 1)
3637                 * number of packets, but the TLBPC field is zero-based.
3638                 */
3639                if (residue == 0)
3640                        return max_burst;
3641                return residue - 1;
3642        }
3643        if (total_packet_count == 0)
3644                return 0;
3645        return total_packet_count - 1;
3646}
3647
3648/*
3649 * Calculates Frame ID field of the isochronous TRB identifies the
3650 * target frame that the Interval associated with this Isochronous
3651 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3652 *
3653 * Returns actual frame id on success, negative value on error.
3654 */
3655static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3656                struct urb *urb, int index)
3657{
3658        int start_frame, ist, ret = 0;
3659        int start_frame_id, end_frame_id, current_frame_id;
3660
3661        if (urb->dev->speed == USB_SPEED_LOW ||
3662                        urb->dev->speed == USB_SPEED_FULL)
3663                start_frame = urb->start_frame + index * urb->interval;
3664        else
3665                start_frame = (urb->start_frame + index * urb->interval) >> 3;
3666
3667        /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3668         *
3669         * If bit [3] of IST is cleared to '0', software can add a TRB no
3670         * later than IST[2:0] Microframes before that TRB is scheduled to
3671         * be executed.
3672         * If bit [3] of IST is set to '1', software can add a TRB no later
3673         * than IST[2:0] Frames before that TRB is scheduled to be executed.
3674         */
3675        ist = HCS_IST(xhci->hcs_params2) & 0x7;
3676        if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3677                ist <<= 3;
3678
3679        /* Software shall not schedule an Isoch TD with a Frame ID value that
3680         * is less than the Start Frame ID or greater than the End Frame ID,
3681         * where:
3682         *
3683         * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3684         * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3685         *
3686         * Both the End Frame ID and Start Frame ID values are calculated
3687         * in microframes. When software determines the valid Frame ID value;
3688         * The End Frame ID value should be rounded down to the nearest Frame
3689         * boundary, and the Start Frame ID value should be rounded up to the
3690         * nearest Frame boundary.
3691         */
3692        current_frame_id = readl(&xhci->run_regs->microframe_index);
3693        start_frame_id = roundup(current_frame_id + ist + 1, 8);
3694        end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3695
3696        start_frame &= 0x7ff;
3697        start_frame_id = (start_frame_id >> 3) & 0x7ff;
3698        end_frame_id = (end_frame_id >> 3) & 0x7ff;
3699
3700        xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3701                 __func__, index, readl(&xhci->run_regs->microframe_index),
3702                 start_frame_id, end_frame_id, start_frame);
3703
3704        if (start_frame_id < end_frame_id) {
3705                if (start_frame > end_frame_id ||
3706                                start_frame < start_frame_id)
3707                        ret = -EINVAL;
3708        } else if (start_frame_id > end_frame_id) {
3709                if ((start_frame > end_frame_id &&
3710                                start_frame < start_frame_id))
3711                        ret = -EINVAL;
3712        } else {
3713                        ret = -EINVAL;
3714        }
3715
3716        if (index == 0) {
3717                if (ret == -EINVAL || start_frame == start_frame_id) {
3718                        start_frame = start_frame_id + 1;
3719                        if (urb->dev->speed == USB_SPEED_LOW ||
3720                                        urb->dev->speed == USB_SPEED_FULL)
3721                                urb->start_frame = start_frame;
3722                        else
3723                                urb->start_frame = start_frame << 3;
3724                        ret = 0;
3725                }
3726        }
3727
3728        if (ret) {
3729                xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3730                                start_frame, current_frame_id, index,
3731                                start_frame_id, end_frame_id);
3732                xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3733                return ret;
3734        }
3735
3736        return start_frame;
3737}
3738
3739/* Check if we should generate event interrupt for a TD in an isoc URB */
3740static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i)
3741{
3742        if (xhci->hci_version < 0x100)
3743                return false;
3744        /* always generate an event interrupt for the last TD */
3745        if (i == num_tds - 1)
3746                return false;
3747        /*
3748         * If AVOID_BEI is set the host handles full event rings poorly,
3749         * generate an event at least every 8th TD to clear the event ring
3750         */
3751        if (i && xhci->quirks & XHCI_AVOID_BEI)
3752                return !!(i % 8);
3753
3754        return true;
3755}
3756
3757/* This is for isoc transfer */
3758static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3759                struct urb *urb, int slot_id, unsigned int ep_index)
3760{
3761        struct xhci_ring *ep_ring;
3762        struct urb_priv *urb_priv;
3763        struct xhci_td *td;
3764        int num_tds, trbs_per_td;
3765        struct xhci_generic_trb *start_trb;
3766        bool first_trb;
3767        int start_cycle;
3768        u32 field, length_field;
3769        int running_total, trb_buff_len, td_len, td_remain_len, ret;
3770        u64 start_addr, addr;
3771        int i, j;
3772        bool more_trbs_coming;
3773        struct xhci_virt_ep *xep;
3774        int frame_id;
3775
3776        xep = &xhci->devs[slot_id]->eps[ep_index];
3777        ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3778
3779        num_tds = urb->number_of_packets;
3780        if (num_tds < 1) {
3781                xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3782                return -EINVAL;
3783        }
3784        start_addr = (u64) urb->transfer_dma;
3785        start_trb = &ep_ring->enqueue->generic;
3786        start_cycle = ep_ring->cycle_state;
3787
3788        urb_priv = urb->hcpriv;
3789        /* Queue the TRBs for each TD, even if they are zero-length */
3790        for (i = 0; i < num_tds; i++) {
3791                unsigned int total_pkt_count, max_pkt;
3792                unsigned int burst_count, last_burst_pkt_count;
3793                u32 sia_frame_id;
3794
3795                first_trb = true;
3796                running_total = 0;
3797                addr = start_addr + urb->iso_frame_desc[i].offset;
3798                td_len = urb->iso_frame_desc[i].length;
3799                td_remain_len = td_len;
3800                max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3801                total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3802
3803                /* A zero-length transfer still involves at least one packet. */
3804                if (total_pkt_count == 0)
3805                        total_pkt_count++;
3806                burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3807                last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3808                                                        urb, total_pkt_count);
3809
3810                trbs_per_td = count_isoc_trbs_needed(urb, i);
3811
3812                ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3813                                urb->stream_id, trbs_per_td, urb, i, mem_flags);
3814                if (ret < 0) {
3815                        if (i == 0)
3816                                return ret;
3817                        goto cleanup;
3818                }
3819                td = &urb_priv->td[i];
3820
3821                /* use SIA as default, if frame id is used overwrite it */
3822                sia_frame_id = TRB_SIA;
3823                if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3824                    HCC_CFC(xhci->hcc_params)) {
3825                        frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3826                        if (frame_id >= 0)
3827                                sia_frame_id = TRB_FRAME_ID(frame_id);
3828                }
3829                /*
3830                 * Set isoc specific data for the first TRB in a TD.
3831                 * Prevent HW from getting the TRBs by keeping the cycle state
3832                 * inverted in the first TDs isoc TRB.
3833                 */
3834                field = TRB_TYPE(TRB_ISOC) |
3835                        TRB_TLBPC(last_burst_pkt_count) |
3836                        sia_frame_id |
3837                        (i ? ep_ring->cycle_state : !start_cycle);
3838
3839                /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3840                if (!xep->use_extended_tbc)
3841                        field |= TRB_TBC(burst_count);
3842
3843                /* fill the rest of the TRB fields, and remaining normal TRBs */
3844                for (j = 0; j < trbs_per_td; j++) {
3845                        u32 remainder = 0;
3846
3847                        /* only first TRB is isoc, overwrite otherwise */
3848                        if (!first_trb)
3849                                field = TRB_TYPE(TRB_NORMAL) |
3850                                        ep_ring->cycle_state;
3851
3852                        /* Only set interrupt on short packet for IN EPs */
3853                        if (usb_urb_dir_in(urb))
3854                                field |= TRB_ISP;
3855
3856                        /* Set the chain bit for all except the last TRB  */
3857                        if (j < trbs_per_td - 1) {
3858                                more_trbs_coming = true;
3859                                field |= TRB_CHAIN;
3860                        } else {
3861                                more_trbs_coming = false;
3862                                td->last_trb = ep_ring->enqueue;
3863                                field |= TRB_IOC;
3864                                if (trb_block_event_intr(xhci, num_tds, i))
3865                                        field |= TRB_BEI;
3866                        }
3867                        /* Calculate TRB length */
3868                        trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3869                        if (trb_buff_len > td_remain_len)
3870                                trb_buff_len = td_remain_len;
3871
3872                        /* Set the TRB length, TD size, & interrupter fields. */
3873                        remainder = xhci_td_remainder(xhci, running_total,
3874                                                   trb_buff_len, td_len,
3875                                                   urb, more_trbs_coming);
3876
3877                        length_field = TRB_LEN(trb_buff_len) |
3878                                TRB_INTR_TARGET(0);
3879
3880                        /* xhci 1.1 with ETE uses TD Size field for TBC */
3881                        if (first_trb && xep->use_extended_tbc)
3882                                length_field |= TRB_TD_SIZE_TBC(burst_count);
3883                        else
3884                                length_field |= TRB_TD_SIZE(remainder);
3885                        first_trb = false;
3886
3887                        queue_trb(xhci, ep_ring, more_trbs_coming,
3888                                lower_32_bits(addr),
3889                                upper_32_bits(addr),
3890                                length_field,
3891                                field);
3892                        running_total += trb_buff_len;
3893
3894                        addr += trb_buff_len;
3895                        td_remain_len -= trb_buff_len;
3896                }
3897
3898                /* Check TD length */
3899                if (running_total != td_len) {
3900                        xhci_err(xhci, "ISOC TD length unmatch\n");
3901                        ret = -EINVAL;
3902                        goto cleanup;
3903                }
3904        }
3905
3906        /* store the next frame id */
3907        if (HCC_CFC(xhci->hcc_params))
3908                xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3909
3910        if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3911                if (xhci->quirks & XHCI_AMD_PLL_FIX)
3912                        usb_amd_quirk_pll_disable();
3913        }
3914        xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3915
3916        giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3917                        start_cycle, start_trb);
3918        return 0;
3919cleanup:
3920        /* Clean up a partially enqueued isoc transfer. */
3921
3922        for (i--; i >= 0; i--)
3923                list_del_init(&urb_priv->td[i].td_list);
3924
3925        /* Use the first TD as a temporary variable to turn the TDs we've queued
3926         * into No-ops with a software-owned cycle bit. That way the hardware
3927         * won't accidentally start executing bogus TDs when we partially
3928         * overwrite them.  td->first_trb and td->start_seg are already set.
3929         */
3930        urb_priv->td[0].last_trb = ep_ring->enqueue;
3931        /* Every TRB except the first & last will have its cycle bit flipped. */
3932        td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
3933
3934        /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3935        ep_ring->enqueue = urb_priv->td[0].first_trb;
3936        ep_ring->enq_seg = urb_priv->td[0].start_seg;
3937        ep_ring->cycle_state = start_cycle;
3938        ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3939        usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3940        return ret;
3941}
3942
3943/*
3944 * Check transfer ring to guarantee there is enough room for the urb.
3945 * Update ISO URB start_frame and interval.
3946 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3947 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3948 * Contiguous Frame ID is not supported by HC.
3949 */
3950int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3951                struct urb *urb, int slot_id, unsigned int ep_index)
3952{
3953        struct xhci_virt_device *xdev;
3954        struct xhci_ring *ep_ring;
3955        struct xhci_ep_ctx *ep_ctx;
3956        int start_frame;
3957        int num_tds, num_trbs, i;
3958        int ret;
3959        struct xhci_virt_ep *xep;
3960        int ist;
3961
3962        xdev = xhci->devs[slot_id];
3963        xep = &xhci->devs[slot_id]->eps[ep_index];
3964        ep_ring = xdev->eps[ep_index].ring;
3965        ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3966
3967        num_trbs = 0;
3968        num_tds = urb->number_of_packets;
3969        for (i = 0; i < num_tds; i++)
3970                num_trbs += count_isoc_trbs_needed(urb, i);
3971
3972        /* Check the ring to guarantee there is enough room for the whole urb.
3973         * Do not insert any td of the urb to the ring if the check failed.
3974         */
3975        ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3976                           num_trbs, mem_flags);
3977        if (ret)
3978                return ret;
3979
3980        /*
3981         * Check interval value. This should be done before we start to
3982         * calculate the start frame value.
3983         */
3984        check_interval(xhci, urb, ep_ctx);
3985
3986        /* Calculate the start frame and put it in urb->start_frame. */
3987        if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3988                if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
3989                        urb->start_frame = xep->next_frame_id;
3990                        goto skip_start_over;
3991                }
3992        }
3993
3994        start_frame = readl(&xhci->run_regs->microframe_index);
3995        start_frame &= 0x3fff;
3996        /*
3997         * Round up to the next frame and consider the time before trb really
3998         * gets scheduled by hardare.
3999         */
4000        ist = HCS_IST(xhci->hcs_params2) & 0x7;
4001        if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4002                ist <<= 3;
4003        start_frame += ist + XHCI_CFC_DELAY;
4004        start_frame = roundup(start_frame, 8);
4005
4006        /*
4007         * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4008         * is greate than 8 microframes.
4009         */
4010        if (urb->dev->speed == USB_SPEED_LOW ||
4011                        urb->dev->speed == USB_SPEED_FULL) {
4012                start_frame = roundup(start_frame, urb->interval << 3);
4013                urb->start_frame = start_frame >> 3;
4014        } else {
4015                start_frame = roundup(start_frame, urb->interval);
4016                urb->start_frame = start_frame;
4017        }
4018
4019skip_start_over:
4020        ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4021
4022        return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4023}
4024
4025/****           Command Ring Operations         ****/
4026
4027/* Generic function for queueing a command TRB on the command ring.
4028 * Check to make sure there's room on the command ring for one command TRB.
4029 * Also check that there's room reserved for commands that must not fail.
4030 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4031 * then only check for the number of reserved spots.
4032 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4033 * because the command event handler may want to resubmit a failed command.
4034 */
4035static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4036                         u32 field1, u32 field2,
4037                         u32 field3, u32 field4, bool command_must_succeed)
4038{
4039        int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4040        int ret;
4041
4042        if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4043                (xhci->xhc_state & XHCI_STATE_HALTED)) {
4044                xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4045                return -ESHUTDOWN;
4046        }
4047
4048        if (!command_must_succeed)
4049                reserved_trbs++;
4050
4051        ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4052                        reserved_trbs, GFP_ATOMIC);
4053        if (ret < 0) {
4054                xhci_err(xhci, "ERR: No room for command on command ring\n");
4055                if (command_must_succeed)
4056                        xhci_err(xhci, "ERR: Reserved TRB counting for "
4057                                        "unfailable commands failed.\n");
4058                return ret;
4059        }
4060
4061        cmd->command_trb = xhci->cmd_ring->enqueue;
4062
4063        /* if there are no other commands queued we start the timeout timer */
4064        if (list_empty(&xhci->cmd_list)) {
4065                xhci->current_cmd = cmd;
4066                xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
4067        }
4068
4069        list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4070
4071        queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4072                        field4 | xhci->cmd_ring->cycle_state);
4073        return 0;
4074}
4075
4076/* Queue a slot enable or disable request on the command ring */
4077int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4078                u32 trb_type, u32 slot_id)
4079{
4080        return queue_command(xhci, cmd, 0, 0, 0,
4081                        TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4082}
4083
4084/* Queue an address device command TRB */
4085int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4086                dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4087{
4088        return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4089                        upper_32_bits(in_ctx_ptr), 0,
4090                        TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4091                        | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4092}
4093
4094int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4095                u32 field1, u32 field2, u32 field3, u32 field4)
4096{
4097        return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4098}
4099
4100/* Queue a reset device command TRB */
4101int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4102                u32 slot_id)
4103{
4104        return queue_command(xhci, cmd, 0, 0, 0,
4105                        TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4106                        false);
4107}
4108
4109/* Queue a configure endpoint command TRB */
4110int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4111                struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4112                u32 slot_id, bool command_must_succeed)
4113{
4114        return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4115                        upper_32_bits(in_ctx_ptr), 0,
4116                        TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4117                        command_must_succeed);
4118}
4119
4120/* Queue an evaluate context command TRB */
4121int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4122                dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4123{
4124        return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4125                        upper_32_bits(in_ctx_ptr), 0,
4126                        TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4127                        command_must_succeed);
4128}
4129
4130/*
4131 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4132 * activity on an endpoint that is about to be suspended.
4133 */
4134int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4135                             int slot_id, unsigned int ep_index, int suspend)
4136{
4137        u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4138        u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4139        u32 type = TRB_TYPE(TRB_STOP_RING);
4140        u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4141
4142        return queue_command(xhci, cmd, 0, 0, 0,
4143                        trb_slot_id | trb_ep_index | type | trb_suspend, false);
4144}
4145
4146/* Set Transfer Ring Dequeue Pointer command */
4147void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4148                unsigned int slot_id, unsigned int ep_index,
4149                struct xhci_dequeue_state *deq_state)
4150{
4151        dma_addr_t addr;
4152        u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4153        u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4154        u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id);
4155        u32 trb_sct = 0;
4156        u32 type = TRB_TYPE(TRB_SET_DEQ);
4157        struct xhci_virt_ep *ep;
4158        struct xhci_command *cmd;
4159        int ret;
4160
4161        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4162                "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4163                deq_state->new_deq_seg,
4164                (unsigned long long)deq_state->new_deq_seg->dma,
4165                deq_state->new_deq_ptr,
4166                (unsigned long long)xhci_trb_virt_to_dma(
4167                        deq_state->new_deq_seg, deq_state->new_deq_ptr),
4168                deq_state->new_cycle_state);
4169
4170        addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4171                                    deq_state->new_deq_ptr);
4172        if (addr == 0) {
4173                xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4174                xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4175                          deq_state->new_deq_seg, deq_state->new_deq_ptr);
4176                return;
4177        }
4178        ep = &xhci->devs[slot_id]->eps[ep_index];
4179        if ((ep->ep_state & SET_DEQ_PENDING)) {
4180                xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4181                xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4182                return;
4183        }
4184
4185        /* This function gets called from contexts where it cannot sleep */
4186        cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
4187        if (!cmd)
4188                return;
4189
4190        ep->queued_deq_seg = deq_state->new_deq_seg;
4191        ep->queued_deq_ptr = deq_state->new_deq_ptr;
4192        if (deq_state->stream_id)
4193                trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4194        ret = queue_command(xhci, cmd,
4195                lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4196                upper_32_bits(addr), trb_stream_id,
4197                trb_slot_id | trb_ep_index | type, false);
4198        if (ret < 0) {
4199                xhci_free_command(xhci, cmd);
4200                return;
4201        }
4202
4203        /* Stop the TD queueing code from ringing the doorbell until
4204         * this command completes.  The HC won't set the dequeue pointer
4205         * if the ring is running, and ringing the doorbell starts the
4206         * ring running.
4207         */
4208        ep->ep_state |= SET_DEQ_PENDING;
4209}
4210
4211int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4212                        int slot_id, unsigned int ep_index,
4213                        enum xhci_ep_reset_type reset_type)
4214{
4215        u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4216        u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4217        u32 type = TRB_TYPE(TRB_RESET_EP);
4218
4219        if (reset_type == EP_SOFT_RESET)
4220                type |= TRB_TSP;
4221
4222        return queue_command(xhci, cmd, 0, 0, 0,
4223                        trb_slot_id | trb_ep_index | type, false);
4224}
4225