1
2
3
4#ifndef __MLX5_VDPA_IFC_H_
5#define __MLX5_VDPA_IFC_H_
6
7#include <linux/mlx5/mlx5_ifc.h>
8
9enum {
10 MLX5_VIRTIO_Q_EVENT_MODE_NO_MSIX_MODE = 0x0,
11 MLX5_VIRTIO_Q_EVENT_MODE_QP_MODE = 0x1,
12 MLX5_VIRTIO_Q_EVENT_MODE_MSIX_MODE = 0x2,
13};
14
15enum {
16 MLX5_VIRTIO_EMULATION_CAP_VIRTIO_QUEUE_TYPE_SPLIT = 0x1,
17 MLX5_VIRTIO_EMULATION_CAP_VIRTIO_QUEUE_TYPE_PACKED = 0x2,
18};
19
20enum {
21 MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_SPLIT = 0,
22 MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_PACKED = 1,
23};
24
25struct mlx5_ifc_virtio_q_bits {
26 u8 virtio_q_type[0x8];
27 u8 reserved_at_8[0x5];
28 u8 event_mode[0x3];
29 u8 queue_index[0x10];
30
31 u8 full_emulation[0x1];
32 u8 virtio_version_1_0[0x1];
33 u8 reserved_at_22[0x2];
34 u8 offload_type[0x4];
35 u8 event_qpn_or_msix[0x18];
36
37 u8 doorbell_stride_index[0x10];
38 u8 queue_size[0x10];
39
40 u8 device_emulation_id[0x20];
41
42 u8 desc_addr[0x40];
43
44 u8 used_addr[0x40];
45
46 u8 available_addr[0x40];
47
48 u8 virtio_q_mkey[0x20];
49
50 u8 max_tunnel_desc[0x10];
51 u8 reserved_at_170[0x8];
52 u8 error_type[0x8];
53
54 u8 umem_1_id[0x20];
55
56 u8 umem_1_size[0x20];
57
58 u8 umem_1_offset[0x40];
59
60 u8 umem_2_id[0x20];
61
62 u8 umem_2_size[0x20];
63
64 u8 umem_2_offset[0x40];
65
66 u8 umem_3_id[0x20];
67
68 u8 umem_3_size[0x20];
69
70 u8 umem_3_offset[0x40];
71
72 u8 counter_set_id[0x20];
73
74 u8 reserved_at_320[0x8];
75 u8 pd[0x18];
76
77 u8 reserved_at_340[0xc0];
78};
79
80struct mlx5_ifc_virtio_net_q_object_bits {
81 u8 modify_field_select[0x40];
82
83 u8 reserved_at_40[0x20];
84
85 u8 vhca_id[0x10];
86 u8 reserved_at_70[0x10];
87
88 u8 queue_feature_bit_mask_12_3[0xa];
89 u8 dirty_bitmap_dump_enable[0x1];
90 u8 vhost_log_page[0x5];
91 u8 reserved_at_90[0xc];
92 u8 state[0x4];
93
94 u8 reserved_at_a0[0x5];
95 u8 queue_feature_bit_mask_2_0[0x3];
96 u8 tisn_or_qpn[0x18];
97
98 u8 dirty_bitmap_mkey[0x20];
99
100 u8 dirty_bitmap_size[0x20];
101
102 u8 dirty_bitmap_addr[0x40];
103
104 u8 hw_available_index[0x10];
105 u8 hw_used_index[0x10];
106
107 u8 reserved_at_160[0xa0];
108
109 struct mlx5_ifc_virtio_q_bits virtio_q_context;
110};
111
112struct mlx5_ifc_create_virtio_net_q_in_bits {
113 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
114
115 struct mlx5_ifc_virtio_net_q_object_bits obj_context;
116};
117
118struct mlx5_ifc_create_virtio_net_q_out_bits {
119 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
120};
121
122struct mlx5_ifc_destroy_virtio_net_q_in_bits {
123 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_out_cmd_hdr;
124};
125
126struct mlx5_ifc_destroy_virtio_net_q_out_bits {
127 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
128};
129
130struct mlx5_ifc_query_virtio_net_q_in_bits {
131 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
132};
133
134struct mlx5_ifc_query_virtio_net_q_out_bits {
135 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
136
137 struct mlx5_ifc_virtio_net_q_object_bits obj_context;
138};
139
140enum {
141 MLX5_VIRTQ_MODIFY_MASK_STATE = (u64)1 << 0,
142 MLX5_VIRTQ_MODIFY_MASK_DIRTY_BITMAP_PARAMS = (u64)1 << 3,
143 MLX5_VIRTQ_MODIFY_MASK_DIRTY_BITMAP_DUMP_ENABLE = (u64)1 << 4,
144};
145
146enum {
147 MLX5_VIRTIO_NET_Q_OBJECT_STATE_INIT = 0x0,
148 MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY = 0x1,
149 MLX5_VIRTIO_NET_Q_OBJECT_STATE_SUSPEND = 0x2,
150 MLX5_VIRTIO_NET_Q_OBJECT_STATE_ERR = 0x3,
151};
152
153enum {
154 MLX5_RQTC_LIST_Q_TYPE_RQ = 0x0,
155 MLX5_RQTC_LIST_Q_TYPE_VIRTIO_NET_Q = 0x1,
156};
157
158struct mlx5_ifc_modify_virtio_net_q_in_bits {
159 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
160
161 struct mlx5_ifc_virtio_net_q_object_bits obj_context;
162};
163
164struct mlx5_ifc_modify_virtio_net_q_out_bits {
165 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
166};
167
168#endif
169
