1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * NetChip 2280 high/full speed USB device controller. 4 * Unlike many such controllers, this one talks PCI. 5 * 6 * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com) 7 * Copyright (C) 2003 David Brownell 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 */ 23 24#ifndef __LINUX_USB_NET2280_H 25#define __LINUX_USB_NET2280_H 26 27/*-------------------------------------------------------------------------*/ 28 29/* NET2280 MEMORY MAPPED REGISTERS 30 * 31 * The register layout came from the chip documentation, and the bit 32 * number definitions were extracted from chip specification. 33 * 34 * Use the shift operator ('<<') to build bit masks, with readl/writel 35 * to access the registers through PCI. 36 */ 37 38/* main registers, BAR0 + 0x0000 */ 39struct net2280_regs { 40 /* offset 0x0000 */ 41 u32 devinit; 42#define LOCAL_CLOCK_FREQUENCY 8 43#define FORCE_PCI_RESET 7 44#define PCI_ID 6 45#define PCI_ENABLE 5 46#define FIFO_SOFT_RESET 4 47#define CFG_SOFT_RESET 3 48#define PCI_SOFT_RESET 2 49#define USB_SOFT_RESET 1 50#define M8051_RESET 0 51 u32 eectl; 52#define EEPROM_ADDRESS_WIDTH 23 53#define EEPROM_CHIP_SELECT_ACTIVE 22 54#define EEPROM_PRESENT 21 55#define EEPROM_VALID 20 56#define EEPROM_BUSY 19 57#define EEPROM_CHIP_SELECT_ENABLE 18 58#define EEPROM_BYTE_READ_START 17 59#define EEPROM_BYTE_WRITE_START 16 60#define EEPROM_READ_DATA 8 61#define EEPROM_WRITE_DATA 0 62 u32 eeclkfreq; 63 u32 _unused0; 64 /* offset 0x0010 */ 65 66 u32 pciirqenb0; /* interrupt PCI master ... */ 67#define SETUP_PACKET_INTERRUPT_ENABLE 7 68#define ENDPOINT_F_INTERRUPT_ENABLE 6 69#define ENDPOINT_E_INTERRUPT_ENABLE 5 70#define ENDPOINT_D_INTERRUPT_ENABLE 4 71#define ENDPOINT_C_INTERRUPT_ENABLE 3 72#define ENDPOINT_B_INTERRUPT_ENABLE 2 73#define ENDPOINT_A_INTERRUPT_ENABLE 1 74#define ENDPOINT_0_INTERRUPT_ENABLE 0 75 u32 pciirqenb1; 76#define PCI_INTERRUPT_ENABLE 31 77#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 78#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 79#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 80#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 81#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 82#define PCI_TARGET_ABORT_ASSERTED_INTERRUPT_ENABLE 18 83#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 84#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 85#define GPIO_INTERRUPT_ENABLE 13 86#define DMA_D_INTERRUPT_ENABLE 12 87#define DMA_C_INTERRUPT_ENABLE 11 88#define DMA_B_INTERRUPT_ENABLE 10 89#define DMA_A_INTERRUPT_ENABLE 9 90#define EEPROM_DONE_INTERRUPT_ENABLE 8 91#define VBUS_INTERRUPT_ENABLE 7 92#define CONTROL_STATUS_INTERRUPT_ENABLE 6 93#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 94#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 95#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 96#define RESUME_INTERRUPT_ENABLE 1 97#define SOF_INTERRUPT_ENABLE 0 98 u32 cpu_irqenb0; /* ... or onboard 8051 */ 99#define SETUP_PACKET_INTERRUPT_ENABLE 7 100#define ENDPOINT_F_INTERRUPT_ENABLE 6 101#define ENDPOINT_E_INTERRUPT_ENABLE 5 102#define ENDPOINT_D_INTERRUPT_ENABLE 4 103#define ENDPOINT_C_INTERRUPT_ENABLE 3 104#define ENDPOINT_B_INTERRUPT_ENABLE 2 105#define ENDPOINT_A_INTERRUPT_ENABLE 1 106#define ENDPOINT_0_INTERRUPT_ENABLE 0 107 u32 cpu_irqenb1; 108#define CPU_INTERRUPT_ENABLE 31 109#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 110#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 111#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 112#define PCI_INTA_INTERRUPT_ENABLE 24 113#define PCI_PME_INTERRUPT_ENABLE 23 114#define PCI_SERR_INTERRUPT_ENABLE 22 115#define PCI_PERR_INTERRUPT_ENABLE 21 116#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 117#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 118#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 119#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 120#define GPIO_INTERRUPT_ENABLE 13 121#define DMA_D_INTERRUPT_ENABLE 12 122#define DMA_C_INTERRUPT_ENABLE 11 123#define DMA_B_INTERRUPT_ENABLE 10 124#define DMA_A_INTERRUPT_ENABLE 9 125#define EEPROM_DONE_INTERRUPT_ENABLE 8 126#define VBUS_INTERRUPT_ENABLE 7 127#define CONTROL_STATUS_INTERRUPT_ENABLE 6 128#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 129#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 130#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 131#define RESUME_INTERRUPT_ENABLE 1 132#define SOF_INTERRUPT_ENABLE 0 133 134 /* offset 0x0020 */ 135 u32 _unused1; 136 u32 usbirqenb1; 137#define USB_INTERRUPT_ENABLE 31 138#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 139#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 140#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 141#define PCI_INTA_INTERRUPT_ENABLE 24 142#define PCI_PME_INTERRUPT_ENABLE 23 143#define PCI_SERR_INTERRUPT_ENABLE 22 144#define PCI_PERR_INTERRUPT_ENABLE 21 145#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 146#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 147#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 148#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 149#define GPIO_INTERRUPT_ENABLE 13 150#define DMA_D_INTERRUPT_ENABLE 12 151#define DMA_C_INTERRUPT_ENABLE 11 152#define DMA_B_INTERRUPT_ENABLE 10 153#define DMA_A_INTERRUPT_ENABLE 9 154#define EEPROM_DONE_INTERRUPT_ENABLE 8 155#define VBUS_INTERRUPT_ENABLE 7 156#define CONTROL_STATUS_INTERRUPT_ENABLE 6 157#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 158#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 159#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 160#define RESUME_INTERRUPT_ENABLE 1 161#define SOF_INTERRUPT_ENABLE 0 162 u32 irqstat0; 163#define INTA_ASSERTED 12 164#define SETUP_PACKET_INTERRUPT 7 165#define ENDPOINT_F_INTERRUPT 6 166#define ENDPOINT_E_INTERRUPT 5 167#define ENDPOINT_D_INTERRUPT 4 168#define ENDPOINT_C_INTERRUPT 3 169#define ENDPOINT_B_INTERRUPT 2 170#define ENDPOINT_A_INTERRUPT 1 171#define ENDPOINT_0_INTERRUPT 0 172#define USB3380_IRQSTAT0_EP_INTR_MASK_IN (0xF << 17) 173#define USB3380_IRQSTAT0_EP_INTR_MASK_OUT (0xF << 1) 174 175 u32 irqstat1; 176#define POWER_STATE_CHANGE_INTERRUPT 27 177#define PCI_ARBITER_TIMEOUT_INTERRUPT 26 178#define PCI_PARITY_ERROR_INTERRUPT 25 179#define PCI_INTA_INTERRUPT 24 180#define PCI_PME_INTERRUPT 23 181#define PCI_SERR_INTERRUPT 22 182#define PCI_PERR_INTERRUPT 21 183#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT 20 184#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT 19 185#define PCI_RETRY_ABORT_INTERRUPT 17 186#define PCI_MASTER_CYCLE_DONE_INTERRUPT 16 187#define SOF_DOWN_INTERRUPT 14 188#define GPIO_INTERRUPT 13 189#define DMA_D_INTERRUPT 12 190#define DMA_C_INTERRUPT 11 191#define DMA_B_INTERRUPT 10 192#define DMA_A_INTERRUPT 9 193#define EEPROM_DONE_INTERRUPT 8 194#define VBUS_INTERRUPT 7 195#define CONTROL_STATUS_INTERRUPT 6 196#define ROOT_PORT_RESET_INTERRUPT 4 197#define SUSPEND_REQUEST_INTERRUPT 3 198#define SUSPEND_REQUEST_CHANGE_INTERRUPT 2 199#define RESUME_INTERRUPT 1 200#define SOF_INTERRUPT 0 201 /* offset 0x0030 */ 202 u32 idxaddr; 203 u32 idxdata; 204 u32 fifoctl; 205#define PCI_BASE2_RANGE 16 206#define IGNORE_FIFO_AVAILABILITY 3 207#define PCI_BASE2_SELECT 2 208#define FIFO_CONFIGURATION_SELECT 0 209 u32 _unused2; 210 /* offset 0x0040 */ 211 u32 memaddr; 212#define START 28 213#define DIRECTION 27 214#define FIFO_DIAGNOSTIC_SELECT 24 215#define MEMORY_ADDRESS 0 216 u32 memdata0; 217 u32 memdata1; 218 u32 _unused3; 219 /* offset 0x0050 */ 220 u32 gpioctl; 221#define GPIO3_LED_SELECT 12 222#define GPIO3_INTERRUPT_ENABLE 11 223#define GPIO2_INTERRUPT_ENABLE 10 224#define GPIO1_INTERRUPT_ENABLE 9 225#define GPIO0_INTERRUPT_ENABLE 8 226#define GPIO3_OUTPUT_ENABLE 7 227#define GPIO2_OUTPUT_ENABLE 6 228#define GPIO1_OUTPUT_ENABLE 5 229#define GPIO0_OUTPUT_ENABLE 4 230#define GPIO3_DATA 3 231#define GPIO2_DATA 2 232#define GPIO1_DATA 1 233#define GPIO0_DATA 0 234 u32 gpiostat; 235#define GPIO3_INTERRUPT 3 236#define GPIO2_INTERRUPT 2 237#define GPIO1_INTERRUPT 1 238#define GPIO0_INTERRUPT 0 239} __attribute__ ((packed)); 240 241/* usb control, BAR0 + 0x0080 */ 242struct net2280_usb_regs { 243 /* offset 0x0080 */ 244 u32 stdrsp; 245#define STALL_UNSUPPORTED_REQUESTS 31 246#define SET_TEST_MODE 16 247#define GET_OTHER_SPEED_CONFIGURATION 15 248#define GET_DEVICE_QUALIFIER 14 249#define SET_ADDRESS 13 250#define ENDPOINT_SET_CLEAR_HALT 12 251#define DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP 11 252#define GET_STRING_DESCRIPTOR_2 10 253#define GET_STRING_DESCRIPTOR_1 9 254#define GET_STRING_DESCRIPTOR_0 8 255#define GET_SET_INTERFACE 6 256#define GET_SET_CONFIGURATION 5 257#define GET_CONFIGURATION_DESCRIPTOR 4 258#define GET_DEVICE_DESCRIPTOR 3 259#define GET_ENDPOINT_STATUS 2 260#define GET_INTERFACE_STATUS 1 261#define GET_DEVICE_STATUS 0 262 u32 prodvendid; 263#define PRODUCT_ID 16 264#define VENDOR_ID 0 265 u32 relnum; 266 u32 usbctl; 267#define SERIAL_NUMBER_INDEX 16 268#define PRODUCT_ID_STRING_ENABLE 13 269#define VENDOR_ID_STRING_ENABLE 12 270#define USB_ROOT_PORT_WAKEUP_ENABLE 11 271#define VBUS_PIN 10 272#define TIMED_DISCONNECT 9 273#define SUSPEND_IMMEDIATELY 7 274#define SELF_POWERED_USB_DEVICE 6 275#define REMOTE_WAKEUP_SUPPORT 5 276#define PME_POLARITY 4 277#define USB_DETECT_ENABLE 3 278#define PME_WAKEUP_ENABLE 2 279#define DEVICE_REMOTE_WAKEUP_ENABLE 1 280#define SELF_POWERED_STATUS 0 281 /* offset 0x0090 */ 282 u32 usbstat; 283#define HIGH_SPEED 7 284#define FULL_SPEED 6 285#define GENERATE_RESUME 5 286#define GENERATE_DEVICE_REMOTE_WAKEUP 4 287 u32 xcvrdiag; 288#define FORCE_HIGH_SPEED_MODE 31 289#define FORCE_FULL_SPEED_MODE 30 290#define USB_TEST_MODE 24 291#define LINE_STATE 16 292#define TRANSCEIVER_OPERATION_MODE 2 293#define TRANSCEIVER_SELECT 1 294#define TERMINATION_SELECT 0 295 u32 setup0123; 296 u32 setup4567; 297 /* offset 0x0090 */ 298 u32 _unused0; 299 u32 ouraddr; 300#define FORCE_IMMEDIATE 7 301#define OUR_USB_ADDRESS 0 302 u32 ourconfig; 303} __attribute__ ((packed)); 304 305/* pci control, BAR0 + 0x0100 */ 306struct net2280_pci_regs { 307 /* offset 0x0100 */ 308 u32 pcimstctl; 309#define PCI_ARBITER_PARK_SELECT 13 310#define PCI_MULTI LEVEL_ARBITER 12 311#define PCI_RETRY_ABORT_ENABLE 11 312#define DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE 10 313#define DMA_READ_MULTIPLE_ENABLE 9 314#define DMA_READ_LINE_ENABLE 8 315#define PCI_MASTER_COMMAND_SELECT 6 316#define MEM_READ_OR_WRITE 0 317#define IO_READ_OR_WRITE 1 318#define CFG_READ_OR_WRITE 2 319#define PCI_MASTER_START 5 320#define PCI_MASTER_READ_WRITE 4 321#define PCI_MASTER_WRITE 0 322#define PCI_MASTER_READ 1 323#define PCI_MASTER_BYTE_WRITE_ENABLES 0 324 u32 pcimstaddr; 325 u32 pcimstdata; 326 u32 pcimststat; 327#define PCI_ARBITER_CLEAR 2 328#define PCI_EXTERNAL_ARBITER 1 329#define PCI_HOST_MODE 0 330} __attribute__ ((packed)); 331 332/* dma control, BAR0 + 0x0180 ... array of four structs like this, 333 * for channels 0..3. see also struct net2280_dma: descriptor 334 * that can be loaded into some of these registers. 335 */ 336struct net2280_dma_regs { /* [11.7] */ 337 /* offset 0x0180, 0x01a0, 0x01c0, 0x01e0, */ 338 u32 dmactl; 339#define DMA_SCATTER_GATHER_DONE_INTERRUPT_ENABLE 25 340#define DMA_CLEAR_COUNT_ENABLE 21 341#define DESCRIPTOR_POLLING_RATE 19 342#define POLL_CONTINUOUS 0 343#define POLL_1_USEC 1 344#define POLL_100_USEC 2 345#define POLL_1_MSEC 3 346#define DMA_VALID_BIT_POLLING_ENABLE 18 347#define DMA_VALID_BIT_ENABLE 17 348#define DMA_SCATTER_GATHER_ENABLE 16 349#define DMA_OUT_AUTO_START_ENABLE 4 350#define DMA_PREEMPT_ENABLE 3 351#define DMA_FIFO_VALIDATE 2 352#define DMA_ENABLE 1 353#define DMA_ADDRESS_HOLD 0 354 u32 dmastat; 355#define DMA_ABORT_DONE_INTERRUPT 27 356#define DMA_SCATTER_GATHER_DONE_INTERRUPT 25 357#define DMA_TRANSACTION_DONE_INTERRUPT 24 358#define DMA_ABORT 1 359#define DMA_START 0 360 u32 _unused0[2]; 361 /* offset 0x0190, 0x01b0, 0x01d0, 0x01f0, */ 362 u32 dmacount; 363#define VALID_BIT 31 364#define DMA_DIRECTION 30 365#define DMA_DONE_INTERRUPT_ENABLE 29 366#define END_OF_CHAIN 28 367#define DMA_BYTE_COUNT_MASK ((1<<24)-1) 368#define DMA_BYTE_COUNT 0 369 u32 dmaaddr; 370 u32 dmadesc; 371 u32 _unused1; 372} __attribute__ ((packed)); 373 374/* dedicated endpoint registers, BAR0 + 0x0200 */ 375 376struct net2280_dep_regs { /* [11.8] */ 377 /* offset 0x0200, 0x0210, 0x220, 0x230, 0x240 */ 378 u32 dep_cfg; 379 /* offset 0x0204, 0x0214, 0x224, 0x234, 0x244 */ 380 u32 dep_rsp; 381 u32 _unused[2]; 382} __attribute__ ((packed)); 383 384/* configurable endpoint registers, BAR0 + 0x0300 ... array of seven structs 385 * like this, for ep0 then the configurable endpoints A..F 386 * ep0 reserved for control; E and F have only 64 bytes of fifo 387 */ 388struct net2280_ep_regs { /* [11.9] */ 389 /* offset 0x0300, 0x0320, 0x0340, 0x0360, 0x0380, 0x03a0, 0x03c0 */ 390 u32 ep_cfg; 391#define ENDPOINT_BYTE_COUNT 16 392#define ENDPOINT_ENABLE 10 393#define ENDPOINT_TYPE 8 394#define ENDPOINT_DIRECTION 7 395#define ENDPOINT_NUMBER 0 396 u32 ep_rsp; 397#define SET_NAK_OUT_PACKETS 15 398#define SET_EP_HIDE_STATUS_PHASE 14 399#define SET_EP_FORCE_CRC_ERROR 13 400#define SET_INTERRUPT_MODE 12 401#define SET_CONTROL_STATUS_PHASE_HANDSHAKE 11 402#define SET_NAK_OUT_PACKETS_MODE 10 403#define SET_ENDPOINT_TOGGLE 9 404#define SET_ENDPOINT_HALT 8 405#define CLEAR_NAK_OUT_PACKETS 7 406#define CLEAR_EP_HIDE_STATUS_PHASE 6 407#define CLEAR_EP_FORCE_CRC_ERROR 5 408#define CLEAR_INTERRUPT_MODE 4 409#define CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE 3 410#define CLEAR_NAK_OUT_PACKETS_MODE 2 411#define CLEAR_ENDPOINT_TOGGLE 1 412#define CLEAR_ENDPOINT_HALT 0 413 u32 ep_irqenb; 414#define SHORT_PACKET_OUT_DONE_INTERRUPT_ENABLE 6 415#define SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE 5 416#define DATA_PACKET_RECEIVED_INTERRUPT_ENABLE 3 417#define DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE 2 418#define DATA_OUT_PING_TOKEN_INTERRUPT_ENABLE 1 419#define DATA_IN_TOKEN_INTERRUPT_ENABLE 0 420 u32 ep_stat; 421#define FIFO_VALID_COUNT 24 422#define HIGH_BANDWIDTH_OUT_TRANSACTION_PID 22 423#define TIMEOUT 21 424#define USB_STALL_SENT 20 425#define USB_IN_NAK_SENT 19 426#define USB_IN_ACK_RCVD 18 427#define USB_OUT_PING_NAK_SENT 17 428#define USB_OUT_ACK_SENT 16 429#define FIFO_OVERFLOW 13 430#define FIFO_UNDERFLOW 12 431#define FIFO_FULL 11 432#define FIFO_EMPTY 10 433#define FIFO_FLUSH 9 434#define SHORT_PACKET_OUT_DONE_INTERRUPT 6 435#define SHORT_PACKET_TRANSFERRED_INTERRUPT 5 436#define NAK_OUT_PACKETS 4 437#define DATA_PACKET_RECEIVED_INTERRUPT 3 438#define DATA_PACKET_TRANSMITTED_INTERRUPT 2 439#define DATA_OUT_PING_TOKEN_INTERRUPT 1 440#define DATA_IN_TOKEN_INTERRUPT 0 441 /* offset 0x0310, 0x0330, 0x0350, 0x0370, 0x0390, 0x03b0, 0x03d0 */ 442 u32 ep_avail; 443 u32 ep_data; 444 u32 _unused0[2]; 445} __attribute__ ((packed)); 446 447#endif /* __LINUX_USB_NET2280_H */ 448