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11#ifndef _ASM_POWERPC_QE_H
12#define _ASM_POWERPC_QE_H
13#ifdef __KERNEL__
14
15#include <linux/compiler.h>
16#include <linux/genalloc.h>
17#include <linux/spinlock.h>
18#include <linux/errno.h>
19#include <linux/err.h>
20#include <soc/fsl/cpm.h>
21#include <soc/fsl/qe/immap_qe.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/types.h>
25
26#define QE_NUM_OF_SNUM 256
27#define QE_NUM_OF_BRGS 16
28#define QE_NUM_OF_PORTS 1024
29
30
31
32#define MEM_PART_SYSTEM 0
33#define MEM_PART_SECONDARY 1
34#define MEM_PART_MURAM 2
35
36
37enum qe_clock {
38 QE_CLK_NONE = 0,
39 QE_BRG1,
40 QE_BRG2,
41 QE_BRG3,
42 QE_BRG4,
43 QE_BRG5,
44 QE_BRG6,
45 QE_BRG7,
46 QE_BRG8,
47 QE_BRG9,
48 QE_BRG10,
49 QE_BRG11,
50 QE_BRG12,
51 QE_BRG13,
52 QE_BRG14,
53 QE_BRG15,
54 QE_BRG16,
55 QE_CLK1,
56 QE_CLK2,
57 QE_CLK3,
58 QE_CLK4,
59 QE_CLK5,
60 QE_CLK6,
61 QE_CLK7,
62 QE_CLK8,
63 QE_CLK9,
64 QE_CLK10,
65 QE_CLK11,
66 QE_CLK12,
67 QE_CLK13,
68 QE_CLK14,
69 QE_CLK15,
70 QE_CLK16,
71 QE_CLK17,
72 QE_CLK18,
73 QE_CLK19,
74 QE_CLK20,
75 QE_CLK21,
76 QE_CLK22,
77 QE_CLK23,
78 QE_CLK24,
79 QE_RSYNC_PIN,
80 QE_TSYNC_PIN,
81 QE_CLK_DUMMY
82};
83
84static inline bool qe_clock_is_brg(enum qe_clock clk)
85{
86 return clk >= QE_BRG1 && clk <= QE_BRG16;
87}
88
89extern spinlock_t cmxgcr_lock;
90
91
92#ifdef CONFIG_QUICC_ENGINE
93extern void qe_reset(void);
94#else
95static inline void qe_reset(void) {}
96#endif
97
98int cpm_muram_init(void);
99
100#if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
101s32 cpm_muram_alloc(unsigned long size, unsigned long align);
102void cpm_muram_free(s32 offset);
103s32 cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
104void __iomem *cpm_muram_addr(unsigned long offset);
105unsigned long cpm_muram_offset(void __iomem *addr);
106dma_addr_t cpm_muram_dma(void __iomem *addr);
107#else
108static inline s32 cpm_muram_alloc(unsigned long size,
109 unsigned long align)
110{
111 return -ENOSYS;
112}
113
114static inline void cpm_muram_free(s32 offset)
115{
116}
117
118static inline s32 cpm_muram_alloc_fixed(unsigned long offset,
119 unsigned long size)
120{
121 return -ENOSYS;
122}
123
124static inline void __iomem *cpm_muram_addr(unsigned long offset)
125{
126 return NULL;
127}
128
129static inline unsigned long cpm_muram_offset(void __iomem *addr)
130{
131 return -ENOSYS;
132}
133
134static inline dma_addr_t cpm_muram_dma(void __iomem *addr)
135{
136 return 0;
137}
138#endif
139
140
141#define QE_PIO_PINS 32
142
143struct qe_pio_regs {
144 __be32 cpodr;
145 __be32 cpdata;
146 __be32 cpdir1;
147 __be32 cpdir2;
148 __be32 cppar1;
149 __be32 cppar2;
150#ifdef CONFIG_PPC_85xx
151 u8 pad[8];
152#endif
153};
154
155#define QE_PIO_DIR_IN 2
156#define QE_PIO_DIR_OUT 1
157extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
158 int dir, int open_drain, int assignment,
159 int has_irq);
160#ifdef CONFIG_QUICC_ENGINE
161extern int par_io_init(struct device_node *np);
162extern int par_io_of_config(struct device_node *np);
163extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
164 int assignment, int has_irq);
165extern int par_io_data_set(u8 port, u8 pin, u8 val);
166#else
167static inline int par_io_init(struct device_node *np) { return -ENOSYS; }
168static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }
169static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
170 int assignment, int has_irq) { return -ENOSYS; }
171static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }
172#endif
173
174
175
176
177struct qe_pin;
178#ifdef CONFIG_QE_GPIO
179extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
180extern void qe_pin_free(struct qe_pin *qe_pin);
181extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
182extern void qe_pin_set_dedicated(struct qe_pin *pin);
183#else
184static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
185{
186 return ERR_PTR(-ENOSYS);
187}
188static inline void qe_pin_free(struct qe_pin *qe_pin) {}
189static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
190static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
191#endif
192
193#ifdef CONFIG_QUICC_ENGINE
194int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
195#else
196static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
197 u32 cmd_input)
198{
199 return -ENOSYS;
200}
201#endif
202
203
204enum qe_clock qe_clock_source(const char *source);
205unsigned int qe_get_brg_clk(void);
206int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
207int qe_get_snum(void);
208void qe_put_snum(u8 snum);
209unsigned int qe_get_num_of_risc(void);
210unsigned int qe_get_num_of_snums(void);
211
212static inline int qe_alive_during_sleep(void)
213{
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225
226
227#ifdef CONFIG_PPC_85xx
228 return 0;
229#else
230 return 1;
231#endif
232}
233
234
235#define qe_muram_init cpm_muram_init
236#define qe_muram_alloc cpm_muram_alloc
237#define qe_muram_alloc_fixed cpm_muram_alloc_fixed
238#define qe_muram_free cpm_muram_free
239#define qe_muram_addr cpm_muram_addr
240#define qe_muram_offset cpm_muram_offset
241#define qe_muram_dma cpm_muram_dma
242
243#ifdef CONFIG_PPC32
244#define qe_iowrite8(val, addr) out_8(addr, val)
245#define qe_iowrite16be(val, addr) out_be16(addr, val)
246#define qe_iowrite32be(val, addr) out_be32(addr, val)
247#define qe_ioread8(addr) in_8(addr)
248#define qe_ioread16be(addr) in_be16(addr)
249#define qe_ioread32be(addr) in_be32(addr)
250#else
251#define qe_iowrite8(val, addr) iowrite8(val, addr)
252#define qe_iowrite16be(val, addr) iowrite16be(val, addr)
253#define qe_iowrite32be(val, addr) iowrite32be(val, addr)
254#define qe_ioread8(addr) ioread8(addr)
255#define qe_ioread16be(addr) ioread16be(addr)
256#define qe_ioread32be(addr) ioread32be(addr)
257#endif
258
259#define qe_setbits_be32(_addr, _v) qe_iowrite32be(qe_ioread32be(_addr) | (_v), (_addr))
260#define qe_clrbits_be32(_addr, _v) qe_iowrite32be(qe_ioread32be(_addr) & ~(_v), (_addr))
261
262#define qe_setbits_be16(_addr, _v) qe_iowrite16be(qe_ioread16be(_addr) | (_v), (_addr))
263#define qe_clrbits_be16(_addr, _v) qe_iowrite16be(qe_ioread16be(_addr) & ~(_v), (_addr))
264
265#define qe_setbits_8(_addr, _v) qe_iowrite8(qe_ioread8(_addr) | (_v), (_addr))
266#define qe_clrbits_8(_addr, _v) qe_iowrite8(qe_ioread8(_addr) & ~(_v), (_addr))
267
268#define qe_clrsetbits_be32(addr, clear, set) \
269 qe_iowrite32be((qe_ioread32be(addr) & ~(clear)) | (set), (addr))
270#define qe_clrsetbits_be16(addr, clear, set) \
271 qe_iowrite16be((qe_ioread16be(addr) & ~(clear)) | (set), (addr))
272#define qe_clrsetbits_8(addr, clear, set) \
273 qe_iowrite8((qe_ioread8(addr) & ~(clear)) | (set), (addr))
274
275
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278
279
280struct qe_firmware {
281 struct qe_header {
282 __be32 length;
283 u8 magic[3];
284 u8 version;
285 } header;
286 u8 id[62];
287 u8 split;
288 u8 count;
289 struct {
290 __be16 model;
291 u8 major;
292 u8 minor;
293 } __attribute__ ((packed)) soc;
294 u8 padding[4];
295 __be64 extended_modes;
296 __be32 vtraps[8];
297 u8 reserved[4];
298 struct qe_microcode {
299 u8 id[32];
300 __be32 traps[16];
301 __be32 eccr;
302 __be32 iram_offset;
303 __be32 count;
304 __be32 code_offset;
305 u8 major;
306 u8 minor;
307 u8 revision;
308 u8 padding;
309 u8 reserved[4];
310 } __packed microcode[];
311
312
313} __attribute__ ((packed));
314
315struct qe_firmware_info {
316 char id[64];
317 u32 vtraps[8];
318 u64 extended_modes;
319};
320
321#ifdef CONFIG_QUICC_ENGINE
322
323int qe_upload_firmware(const struct qe_firmware *firmware);
324#else
325static inline int qe_upload_firmware(const struct qe_firmware *firmware)
326{
327 return -ENOSYS;
328}
329#endif
330
331
332struct qe_firmware_info *qe_get_firmware_info(void);
333
334
335int qe_usb_clock_set(enum qe_clock clk, int rate);
336
337
338struct qe_bd {
339 __be16 status;
340 __be16 length;
341 __be32 buf;
342} __attribute__ ((packed));
343
344#define BD_STATUS_MASK 0xffff0000
345#define BD_LENGTH_MASK 0x0000ffff
346
347
348#define QE_INTR_TABLE_ALIGN 16
349#define QE_ALIGNMENT_OF_BD 8
350#define QE_ALIGNMENT_OF_PRAM 64
351
352
353#define QE_RISC_ALLOCATION_RISC1 0x1
354#define QE_RISC_ALLOCATION_RISC2 0x2
355#define QE_RISC_ALLOCATION_RISC3 0x4
356#define QE_RISC_ALLOCATION_RISC4 0x8
357#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
358 QE_RISC_ALLOCATION_RISC2)
359#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
360 QE_RISC_ALLOCATION_RISC2 | \
361 QE_RISC_ALLOCATION_RISC3 | \
362 QE_RISC_ALLOCATION_RISC4)
363
364
365enum qe_fltr_tbl_lookup_key_size {
366 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
367 = 0x3f,
368
369 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
370 = 0x5f,
371
372};
373
374
375enum qe_fltr_largest_external_tbl_lookup_key_size {
376 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
377 = 0x0,
378 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
379 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES,
380 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
381 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES,
382};
383
384
385struct qe_timer_tables {
386 u16 tm_base;
387 u16 tm_ptr;
388 u16 r_tmr;
389 u16 r_tmv;
390 u32 tm_cmd;
391 u32 tm_cnt;
392} __attribute__ ((packed));
393
394#define QE_FLTR_TAD_SIZE 8
395
396
397struct qe_fltr_tad {
398 u8 serialized[QE_FLTR_TAD_SIZE];
399} __attribute__ ((packed));
400
401
402enum comm_dir {
403 COMM_DIR_NONE = 0,
404 COMM_DIR_RX = 1,
405 COMM_DIR_TX = 2,
406 COMM_DIR_RX_AND_TX = 3
407};
408
409
410
411
412
413#define QE_CMXUCR_MII_ENET_MNG 0x00007000
414#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
415#define QE_CMXUCR_GRANT 0x00008000
416#define QE_CMXUCR_TSA 0x00004000
417#define QE_CMXUCR_BKPT 0x00000100
418#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
419
420
421
422#define QE_CMXGCR_MII_ENET_MNG 0x00007000
423#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
424#define QE_CMXGCR_USBCS 0x0000000f
425#define QE_CMXGCR_USBCS_CLK3 0x1
426#define QE_CMXGCR_USBCS_CLK5 0x2
427#define QE_CMXGCR_USBCS_CLK7 0x3
428#define QE_CMXGCR_USBCS_CLK9 0x4
429#define QE_CMXGCR_USBCS_CLK13 0x5
430#define QE_CMXGCR_USBCS_CLK17 0x6
431#define QE_CMXGCR_USBCS_CLK19 0x7
432#define QE_CMXGCR_USBCS_CLK21 0x8
433#define QE_CMXGCR_USBCS_BRG9 0x9
434#define QE_CMXGCR_USBCS_BRG10 0xa
435
436
437
438#define QE_CR_FLG 0x00010000
439#define QE_RESET 0x80000000
440#define QE_INIT_TX_RX 0x00000000
441#define QE_INIT_RX 0x00000001
442#define QE_INIT_TX 0x00000002
443#define QE_ENTER_HUNT_MODE 0x00000003
444#define QE_STOP_TX 0x00000004
445#define QE_GRACEFUL_STOP_TX 0x00000005
446#define QE_RESTART_TX 0x00000006
447#define QE_CLOSE_RX_BD 0x00000007
448#define QE_SWITCH_COMMAND 0x00000007
449#define QE_SET_GROUP_ADDRESS 0x00000008
450#define QE_START_IDMA 0x00000009
451#define QE_MCC_STOP_RX 0x00000009
452#define QE_ATM_TRANSMIT 0x0000000a
453#define QE_HPAC_CLEAR_ALL 0x0000000b
454#define QE_GRACEFUL_STOP_RX 0x0000001a
455#define QE_RESTART_RX 0x0000001b
456#define QE_HPAC_SET_PRIORITY 0x0000010b
457#define QE_HPAC_STOP_TX 0x0000020b
458#define QE_HPAC_STOP_RX 0x0000030b
459#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
460#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
461#define QE_HPAC_START_TX 0x0000060b
462#define QE_HPAC_START_RX 0x0000070b
463#define QE_USB_STOP_TX 0x0000000a
464#define QE_USB_RESTART_TX 0x0000000c
465#define QE_QMC_STOP_TX 0x0000000c
466#define QE_QMC_STOP_RX 0x0000000d
467#define QE_SS7_SU_FIL_RESET 0x0000000e
468
469#define QE_RESET_BCS 0x0000000a
470#define QE_MCC_INIT_TX_RX_16 0x00000003
471#define QE_MCC_STOP_TX 0x00000004
472#define QE_MCC_INIT_TX_1 0x00000005
473#define QE_MCC_INIT_RX_1 0x00000006
474#define QE_MCC_RESET 0x00000007
475#define QE_SET_TIMER 0x00000008
476#define QE_RANDOM_NUMBER 0x0000000c
477#define QE_ATM_MULTI_THREAD_INIT 0x00000011
478#define QE_ASSIGN_PAGE 0x00000012
479#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
480#define QE_START_FLOW_CONTROL 0x00000014
481#define QE_STOP_FLOW_CONTROL 0x00000015
482#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
483
484#define QE_ASSIGN_RISC 0x00000010
485#define QE_CR_MCN_NORMAL_SHIFT 6
486#define QE_CR_MCN_USB_SHIFT 4
487#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
488#define QE_CR_SNUM_SHIFT 17
489
490
491
492#define QE_CR_SUBBLOCK_INVALID 0x00000000
493#define QE_CR_SUBBLOCK_USB 0x03200000
494#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
495#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
496#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
497#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
498#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
499#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
500#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
501#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
502#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
503#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
504#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
505#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
506#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
507#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
508#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
509#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
510#define QE_CR_SUBBLOCK_MCC1 0x03800000
511#define QE_CR_SUBBLOCK_MCC2 0x03a00000
512#define QE_CR_SUBBLOCK_MCC3 0x03000000
513#define QE_CR_SUBBLOCK_IDMA1 0x02800000
514#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
515#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
516#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
517#define QE_CR_SUBBLOCK_HPAC 0x01e00000
518#define QE_CR_SUBBLOCK_SPI1 0x01400000
519#define QE_CR_SUBBLOCK_SPI2 0x01600000
520#define QE_CR_SUBBLOCK_RAND 0x01c00000
521#define QE_CR_SUBBLOCK_TIMER 0x01e00000
522#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
523
524
525#define QE_CR_PROTOCOL_UNSPECIFIED 0x00
526#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
527#define QE_CR_PROTOCOL_QMC 0x02
528#define QE_CR_PROTOCOL_UART 0x04
529#define QE_CR_PROTOCOL_ATM_POS 0x0A
530#define QE_CR_PROTOCOL_ETHERNET 0x0C
531#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
532
533
534#define QE_BRGC_ENABLE 0x00010000
535#define QE_BRGC_DIVISOR_SHIFT 1
536#define QE_BRGC_DIVISOR_MAX 0xFFF
537#define QE_BRGC_DIV16 1
538
539
540#define QE_GTCFR1_PCAS 0x80
541#define QE_GTCFR1_STP2 0x20
542#define QE_GTCFR1_RST2 0x10
543#define QE_GTCFR1_GM2 0x08
544#define QE_GTCFR1_GM1 0x04
545#define QE_GTCFR1_STP1 0x02
546#define QE_GTCFR1_RST1 0x01
547
548
549#define QE_SDSR_BER1 0x02000000
550#define QE_SDSR_BER2 0x01000000
551
552#define QE_SDMR_GLB_1_MSK 0x80000000
553#define QE_SDMR_ADR_SEL 0x20000000
554#define QE_SDMR_BER1_MSK 0x02000000
555#define QE_SDMR_BER2_MSK 0x01000000
556#define QE_SDMR_EB1_MSK 0x00800000
557#define QE_SDMR_ER1_MSK 0x00080000
558#define QE_SDMR_ER2_MSK 0x00040000
559#define QE_SDMR_CEN_MASK 0x0000E000
560#define QE_SDMR_SBER_1 0x00000200
561#define QE_SDMR_SBER_2 0x00000200
562#define QE_SDMR_EB1_PR_MASK 0x000000C0
563#define QE_SDMR_ER1_PR 0x00000008
564
565#define QE_SDMR_CEN_SHIFT 13
566#define QE_SDMR_EB1_PR_SHIFT 6
567
568#define QE_SDTM_MSNUM_SHIFT 24
569
570#define QE_SDEBCR_BA_MASK 0x01FFFFFF
571
572
573#define QE_CP_CERCR_MEE 0x8000
574#define QE_CP_CERCR_IEE 0x4000
575#define QE_CP_CERCR_CIR 0x0800
576
577
578#define QE_IRAM_IADD_AIE 0x80000000
579#define QE_IRAM_IADD_BADDR 0x00080000
580#define QE_IRAM_READY 0x80000000
581
582
583#define UPGCR_PROTOCOL 0x80000000
584#define UPGCR_TMS 0x40000000
585#define UPGCR_RMS 0x20000000
586#define UPGCR_ADDR 0x10000000
587#define UPGCR_DIAG 0x01000000
588
589
590#define UCC_GUEMR_MODE_MASK_RX 0x02
591#define UCC_GUEMR_MODE_FAST_RX 0x02
592#define UCC_GUEMR_MODE_SLOW_RX 0x00
593#define UCC_GUEMR_MODE_MASK_TX 0x01
594#define UCC_GUEMR_MODE_FAST_TX 0x01
595#define UCC_GUEMR_MODE_SLOW_TX 0x00
596#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
597#define UCC_GUEMR_SET_RESERVED3 0x10
598
599
600
601struct ucc_slow_pram {
602 __be16 rbase;
603 __be16 tbase;
604 u8 rbmr;
605 u8 tbmr;
606 __be16 mrblr;
607 __be32 rstate;
608 __be32 rptr;
609 __be16 rbptr;
610 __be16 rcount;
611 __be32 rtemp;
612 __be32 tstate;
613 __be32 tptr;
614 __be16 tbptr;
615 __be16 tcount;
616 __be32 ttemp;
617 __be32 rcrc;
618 __be32 tcrc;
619} __attribute__ ((packed));
620
621
622#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
623#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
624#define UCC_SLOW_GUMR_H_REVD 0x00002000
625#define UCC_SLOW_GUMR_H_TRX 0x00001000
626#define UCC_SLOW_GUMR_H_TTX 0x00000800
627#define UCC_SLOW_GUMR_H_CDP 0x00000400
628#define UCC_SLOW_GUMR_H_CTSP 0x00000200
629#define UCC_SLOW_GUMR_H_CDS 0x00000100
630#define UCC_SLOW_GUMR_H_CTSS 0x00000080
631#define UCC_SLOW_GUMR_H_TFL 0x00000040
632#define UCC_SLOW_GUMR_H_RFW 0x00000020
633#define UCC_SLOW_GUMR_H_TXSY 0x00000010
634#define UCC_SLOW_GUMR_H_4SYNC 0x00000004
635#define UCC_SLOW_GUMR_H_8SYNC 0x00000008
636#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
637#define UCC_SLOW_GUMR_H_RTSM 0x00000002
638#define UCC_SLOW_GUMR_H_RSYN 0x00000001
639
640#define UCC_SLOW_GUMR_L_TCI 0x10000000
641#define UCC_SLOW_GUMR_L_RINV 0x02000000
642#define UCC_SLOW_GUMR_L_TINV 0x01000000
643#define UCC_SLOW_GUMR_L_TEND 0x00040000
644#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
645#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
646#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
647#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
648#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
649#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
650#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
651#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
652#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
653#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
654#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
655#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
656#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
657#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
658#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
659#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
660#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
661#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
662#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
663#define UCC_SLOW_GUMR_L_ENR 0x00000020
664#define UCC_SLOW_GUMR_L_ENT 0x00000010
665#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
666#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
667#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
668#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
669#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
670
671
672#define UCC_FAST_GUMR_LOOPBACK 0x40000000
673#define UCC_FAST_GUMR_TCI 0x20000000
674#define UCC_FAST_GUMR_TRX 0x10000000
675#define UCC_FAST_GUMR_TTX 0x08000000
676#define UCC_FAST_GUMR_CDP 0x04000000
677#define UCC_FAST_GUMR_CTSP 0x02000000
678#define UCC_FAST_GUMR_CDS 0x01000000
679#define UCC_FAST_GUMR_CTSS 0x00800000
680#define UCC_FAST_GUMR_TXSY 0x00020000
681#define UCC_FAST_GUMR_RSYN 0x00010000
682#define UCC_FAST_GUMR_SYNL_MASK 0x0000C000
683#define UCC_FAST_GUMR_SYNL_16 0x0000C000
684#define UCC_FAST_GUMR_SYNL_8 0x00008000
685#define UCC_FAST_GUMR_SYNL_AUTO 0x00004000
686#define UCC_FAST_GUMR_RTSM 0x00002000
687#define UCC_FAST_GUMR_REVD 0x00000400
688#define UCC_FAST_GUMR_ENR 0x00000020
689#define UCC_FAST_GUMR_ENT 0x00000010
690
691
692#define UCC_UART_UCCE_AB 0x0200
693#define UCC_UART_UCCE_IDLE 0x0100
694#define UCC_UART_UCCE_GRA 0x0080
695#define UCC_UART_UCCE_BRKE 0x0040
696#define UCC_UART_UCCE_BRKS 0x0020
697#define UCC_UART_UCCE_CCR 0x0008
698#define UCC_UART_UCCE_BSY 0x0004
699#define UCC_UART_UCCE_TX 0x0002
700#define UCC_UART_UCCE_RX 0x0001
701
702
703#define UCC_HDLC_UCCE_GLR 0x1000
704#define UCC_HDLC_UCCE_GLT 0x0800
705#define UCC_HDLC_UCCE_IDLE 0x0100
706#define UCC_HDLC_UCCE_BRKE 0x0040
707#define UCC_HDLC_UCCE_BRKS 0x0020
708#define UCC_HDLC_UCCE_TXE 0x0010
709#define UCC_HDLC_UCCE_RXF 0x0008
710#define UCC_HDLC_UCCE_BSY 0x0004
711#define UCC_HDLC_UCCE_TXB 0x0002
712#define UCC_HDLC_UCCE_RXB 0x0001
713
714
715#define UCC_BISYNC_UCCE_GRA 0x0080
716#define UCC_BISYNC_UCCE_TXE 0x0010
717#define UCC_BISYNC_UCCE_RCH 0x0008
718#define UCC_BISYNC_UCCE_BSY 0x0004
719#define UCC_BISYNC_UCCE_TXB 0x0002
720#define UCC_BISYNC_UCCE_RXB 0x0001
721
722
723#define UCC_GETH_UCCE_MPD 0x80000000
724#define UCC_GETH_UCCE_SCAR 0x40000000
725#define UCC_GETH_UCCE_GRA 0x20000000
726#define UCC_GETH_UCCE_CBPR 0x10000000
727#define UCC_GETH_UCCE_BSY 0x08000000
728#define UCC_GETH_UCCE_RXC 0x04000000
729#define UCC_GETH_UCCE_TXC 0x02000000
730#define UCC_GETH_UCCE_TXE 0x01000000
731#define UCC_GETH_UCCE_TXB7 0x00800000
732#define UCC_GETH_UCCE_TXB6 0x00400000
733#define UCC_GETH_UCCE_TXB5 0x00200000
734#define UCC_GETH_UCCE_TXB4 0x00100000
735#define UCC_GETH_UCCE_TXB3 0x00080000
736#define UCC_GETH_UCCE_TXB2 0x00040000
737#define UCC_GETH_UCCE_TXB1 0x00020000
738#define UCC_GETH_UCCE_TXB0 0x00010000
739#define UCC_GETH_UCCE_RXB7 0x00008000
740#define UCC_GETH_UCCE_RXB6 0x00004000
741#define UCC_GETH_UCCE_RXB5 0x00002000
742#define UCC_GETH_UCCE_RXB4 0x00001000
743#define UCC_GETH_UCCE_RXB3 0x00000800
744#define UCC_GETH_UCCE_RXB2 0x00000400
745#define UCC_GETH_UCCE_RXB1 0x00000200
746#define UCC_GETH_UCCE_RXB0 0x00000100
747#define UCC_GETH_UCCE_RXF7 0x00000080
748#define UCC_GETH_UCCE_RXF6 0x00000040
749#define UCC_GETH_UCCE_RXF5 0x00000020
750#define UCC_GETH_UCCE_RXF4 0x00000010
751#define UCC_GETH_UCCE_RXF3 0x00000008
752#define UCC_GETH_UCCE_RXF2 0x00000004
753#define UCC_GETH_UCCE_RXF1 0x00000002
754#define UCC_GETH_UCCE_RXF0 0x00000001
755
756
757#define UCC_UART_UPSMR_FLC 0x8000
758#define UCC_UART_UPSMR_SL 0x4000
759#define UCC_UART_UPSMR_CL_MASK 0x3000
760#define UCC_UART_UPSMR_CL_8 0x3000
761#define UCC_UART_UPSMR_CL_7 0x2000
762#define UCC_UART_UPSMR_CL_6 0x1000
763#define UCC_UART_UPSMR_CL_5 0x0000
764#define UCC_UART_UPSMR_UM_MASK 0x0c00
765#define UCC_UART_UPSMR_UM_NORMAL 0x0000
766#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
767#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
768#define UCC_UART_UPSMR_FRZ 0x0200
769#define UCC_UART_UPSMR_RZS 0x0100
770#define UCC_UART_UPSMR_SYN 0x0080
771#define UCC_UART_UPSMR_DRT 0x0040
772#define UCC_UART_UPSMR_PEN 0x0010
773#define UCC_UART_UPSMR_RPM_MASK 0x000c
774#define UCC_UART_UPSMR_RPM_ODD 0x0000
775#define UCC_UART_UPSMR_RPM_LOW 0x0004
776#define UCC_UART_UPSMR_RPM_EVEN 0x0008
777#define UCC_UART_UPSMR_RPM_HIGH 0x000C
778#define UCC_UART_UPSMR_TPM_MASK 0x0003
779#define UCC_UART_UPSMR_TPM_ODD 0x0000
780#define UCC_UART_UPSMR_TPM_LOW 0x0001
781#define UCC_UART_UPSMR_TPM_EVEN 0x0002
782#define UCC_UART_UPSMR_TPM_HIGH 0x0003
783
784
785#define UCC_GETH_UPSMR_FTFE 0x80000000
786#define UCC_GETH_UPSMR_PTPE 0x40000000
787#define UCC_GETH_UPSMR_ECM 0x04000000
788#define UCC_GETH_UPSMR_HSE 0x02000000
789#define UCC_GETH_UPSMR_PRO 0x00400000
790#define UCC_GETH_UPSMR_CAP 0x00200000
791#define UCC_GETH_UPSMR_RSH 0x00100000
792#define UCC_GETH_UPSMR_RPM 0x00080000
793#define UCC_GETH_UPSMR_R10M 0x00040000
794#define UCC_GETH_UPSMR_RLPB 0x00020000
795#define UCC_GETH_UPSMR_TBIM 0x00010000
796#define UCC_GETH_UPSMR_RES1 0x00002000
797#define UCC_GETH_UPSMR_RMM 0x00001000
798#define UCC_GETH_UPSMR_CAM 0x00000400
799#define UCC_GETH_UPSMR_BRO 0x00000200
800#define UCC_GETH_UPSMR_SMM 0x00000080
801#define UCC_GETH_UPSMR_SGMM 0x00000020
802
803
804#define UCC_HDLC_UPSMR_RTE 0x02000000
805#define UCC_HDLC_UPSMR_BUS 0x00200000
806#define UCC_HDLC_UPSMR_CW8 0x00007000
807
808
809#define UCC_SLOW_TOD 0x8000
810#define UCC_FAST_TOD 0x8000
811
812
813
814#define UCC_BMR_GBL 0x20
815#define UCC_BMR_BO_BE 0x10
816#define UCC_BMR_CETM 0x04
817#define UCC_BMR_DTB 0x02
818#define UCC_BMR_BDB 0x01
819
820
821#define FC_GBL 0x20
822#define FC_DTB_LCL 0x02
823#define UCC_FAST_FUNCTION_CODE_GBL 0x20
824#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
825#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
826
827#endif
828#endif
829