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6#include <linux/interrupt.h>
7#include <linux/module.h>
8#include <linux/of.h>
9#include <linux/irqdomain.h>
10#include <linux/irqchip.h>
11#include <asm/irq.h>
12
13#define NR_CPU_IRQS 32
14#define TIMER0_IRQ 3
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24void arc_init_IRQ(void)
25{
26 unsigned int level_mask = 0, i;
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29 level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ;
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35 write_aux_reg(AUX_IRQ_LEV, level_mask);
36
37 if (level_mask)
38 pr_info("Level-2 interrupts bitset %x\n", level_mask);
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43
44 for (i = TIMER0_IRQ; i < NR_CPU_IRQS; i++) {
45 unsigned int ienb;
46
47 ienb = read_aux_reg(AUX_IENABLE);
48 ienb &= ~(1 << i);
49 write_aux_reg(AUX_IENABLE, ienb);
50 }
51}
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63
64static void arc_irq_mask(struct irq_data *data)
65{
66 unsigned int ienb;
67
68 ienb = read_aux_reg(AUX_IENABLE);
69 ienb &= ~(1 << data->hwirq);
70 write_aux_reg(AUX_IENABLE, ienb);
71}
72
73static void arc_irq_unmask(struct irq_data *data)
74{
75 unsigned int ienb;
76
77 ienb = read_aux_reg(AUX_IENABLE);
78 ienb |= (1 << data->hwirq);
79 write_aux_reg(AUX_IENABLE, ienb);
80}
81
82static struct irq_chip onchip_intc = {
83 .name = "ARC In-core Intc",
84 .irq_mask = arc_irq_mask,
85 .irq_unmask = arc_irq_unmask,
86};
87
88static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
89 irq_hw_number_t hw)
90{
91 switch (hw) {
92 case TIMER0_IRQ:
93 irq_set_percpu_devid(irq);
94 irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
95 break;
96 default:
97 irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);
98 }
99 return 0;
100}
101
102static const struct irq_domain_ops arc_intc_domain_ops = {
103 .xlate = irq_domain_xlate_onecell,
104 .map = arc_intc_domain_map,
105};
106
107static int __init
108init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
109{
110 struct irq_domain *root_domain;
111
112 if (parent)
113 panic("DeviceTree incore intc not a root irq controller\n");
114
115 root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS,
116 &arc_intc_domain_ops, NULL);
117 if (!root_domain)
118 panic("root irq domain not avail\n");
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124 irq_set_default_host(root_domain);
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126 return 0;
127}
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129IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
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155#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
156
157void arch_local_irq_enable(void)
158{
159 unsigned long flags = arch_local_save_flags();
160
161 if (flags & STATUS_A2_MASK)
162 flags |= STATUS_E2_MASK;
163 else if (flags & STATUS_A1_MASK)
164 flags |= STATUS_E1_MASK;
165
166 arch_local_irq_restore(flags);
167}
168
169EXPORT_SYMBOL(arch_local_irq_enable);
170#endif
171