LXR linux/arch/arm/mach-exynos/mcpm-exynos.c

   1// SPDX-License-Identifier: GPL-2.0
   2// Copyright (c) 2014 Samsung Electronics Co., Ltd.
   3//              http://www.samsung.com
   4//
   5// Based on arch/arm/mach-vexpress/dcscb.c
   6
   7#include <linux/arm-cci.h>
   8#include <linux/delay.h>
   9#include <linux/io.h>
  10#include <linux/of_address.h>
  11#include <linux/syscore_ops.h>
  12#include <linux/soc/samsung/exynos-regs-pmu.h>
  13
  14#include <asm/cputype.h>
  15#include <asm/cp15.h>
  16#include <asm/mcpm.h>
  17#include <asm/smp_plat.h>
  18
  19#include "common.h"
  20
  21#define EXYNOS5420_CPUS_PER_CLUSTER     4
  22#define EXYNOS5420_NR_CLUSTERS          2
  23
  24#define EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN   BIT(9)
  25#define EXYNOS5420_USE_ARM_CORE_DOWN_STATE      BIT(29)
  26#define EXYNOS5420_USE_L2_COMMON_UP_STATE       BIT(30)
  27
  28static void __iomem *ns_sram_base_addr __ro_after_init;
  29static bool secure_firmware __ro_after_init;
  30
  31/*
  32 * The common v7_exit_coherency_flush API could not be used because of the
  33 * Erratum 799270 workaround. This macro is the same as the common one (in
  34 * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
  35 */
  36#define exynos_v7_exit_coherency_flush(level) \
  37        asm volatile( \
  38        "stmfd  sp!, {fp, ip}\n\t"\
  39        "mrc    p15, 0, r0, c1, c0, 0   @ get SCTLR\n\t" \
  40        "bic    r0, r0, #"__stringify(CR_C)"\n\t" \
  41        "mcr    p15, 0, r0, c1, c0, 0   @ set SCTLR\n\t" \
  42        "isb\n\t"\
  43        "bl     v7_flush_dcache_"__stringify(level)"\n\t" \
  44        "mrc    p15, 0, r0, c1, c0, 1   @ get ACTLR\n\t" \
  45        "bic    r0, r0, #(1 << 6)       @ disable local coherency\n\t" \
  46        /* Dummy Load of a device register to avoid Erratum 799270 */ \
  47        "ldr    r4, [%0]\n\t" \
  48        "and    r4, r4, #0\n\t" \
  49        "orr    r0, r0, r4\n\t" \
  50        "mcr    p15, 0, r0, c1, c0, 1   @ set ACTLR\n\t" \
  51        "isb\n\t" \
  52        "dsb\n\t" \
  53        "ldmfd  sp!, {fp, ip}" \
  54        : \
  55        : "Ir" (pmu_base_addr + S5P_INFORM0) \
  56        : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
  57          "r9", "r10", "lr", "memory")
  58
  59static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster)
  60{
  61        unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
  62        bool state;
  63
  64        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
  65        if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
  66                cluster >= EXYNOS5420_NR_CLUSTERS)
  67                return -EINVAL;
  68
  69        state = exynos_cpu_power_state(cpunr);
  70        exynos_cpu_power_up(cpunr);
  71        if (!state && secure_firmware) {
  72                /*
  73                 * This assumes the cluster number of the big cores(Cortex A15)
  74                 * is 0 and the Little cores(Cortex A7) is 1.
  75                 * When the system was booted from the Little core,
  76                 * they should be reset during power up cpu.
  77                 */
  78                if (cluster &&
  79                    cluster == MPIDR_AFFINITY_LEVEL(cpu_logical_map(0), 1)) {
  80                        unsigned int timeout = 16;
  81
  82                        /*
  83                         * Before we reset the Little cores, we should wait
  84                         * the SPARE2 register is set to 1 because the init
  85                         * codes of the iROM will set the register after
  86                         * initialization.
  87                         */
  88                        while (timeout && !pmu_raw_readl(S5P_PMU_SPARE2)) {
  89                                timeout--;
  90                                udelay(10);
  91                        }
  92
  93                        if (timeout == 0) {
  94                                pr_err("cpu %u cluster %u powerup failed\n",
  95                                       cpu, cluster);
  96                                exynos_cpu_power_down(cpunr);
  97                                return -ETIMEDOUT;
  98                        }
  99
 100                        pmu_raw_writel(EXYNOS5420_KFC_CORE_RESET(cpu),
 101                                        EXYNOS_SWRESET);
 102                }
 103        }
 104
 105        return 0;
 106}
 107
 108static int exynos_cluster_powerup(unsigned int cluster)
 109{
 110        pr_debug("%s: cluster %u\n", __func__, cluster);
 111        if (cluster >= EXYNOS5420_NR_CLUSTERS)
 112                return -EINVAL;
 113
 114        exynos_cluster_power_up(cluster);
 115        return 0;
 116}
 117
 118static void exynos_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
 119{
 120        unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
 121
 122        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
 123        BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
 124                        cluster >= EXYNOS5420_NR_CLUSTERS);
 125        exynos_cpu_power_down(cpunr);
 126}
 127
 128static void exynos_cluster_powerdown_prepare(unsigned int cluster)
 129{
 130        pr_debug("%s: cluster %u\n", __func__, cluster);
 131        BUG_ON(cluster >= EXYNOS5420_NR_CLUSTERS);
 132        exynos_cluster_power_down(cluster);
 133}
 134
 135static void exynos_cpu_cache_disable(void)
 136{
 137        /* Disable and flush the local CPU cache. */
 138        exynos_v7_exit_coherency_flush(louis);
 139}
 140
 141static void exynos_cluster_cache_disable(void)
 142{
 143        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
 144                /*
 145                 * On the Cortex-A15 we need to disable
 146                 * L2 prefetching before flushing the cache.
 147                 */
 148                asm volatile(
 149                "mcr    p15, 1, %0, c15, c0, 3\n\t"
 150                "isb\n\t"
 151                "dsb"
 152                : : "r" (0x400));
 153        }
 154
 155        /* Flush all cache levels for this cluster. */
 156        exynos_v7_exit_coherency_flush(all);
 157
 158        /*
 159         * Disable cluster-level coherency by masking
 160         * incoming snoops and DVM messages:
 161         */
 162        cci_disable_port_by_cpu(read_cpuid_mpidr());
 163}
 164
 165static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
 166{
 167        unsigned int tries = 100;
 168        unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
 169
 170        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
 171        BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
 172                        cluster >= EXYNOS5420_NR_CLUSTERS);
 173
 174        /* Wait for the core state to be OFF */
 175        while (tries--) {
 176                if ((exynos_cpu_power_state(cpunr) == 0))
 177                        return 0; /* success: the CPU is halted */
 178
 179                /* Otherwise, wait and retry: */
 180                msleep(1);
 181        }
 182
 183        return -ETIMEDOUT; /* timeout */
 184}
 185
 186static void exynos_cpu_is_up(unsigned int cpu, unsigned int cluster)
 187{
 188        /* especially when resuming: make sure power control is set */
 189        exynos_cpu_powerup(cpu, cluster);
 190}
 191
 192static const struct mcpm_platform_ops exynos_power_ops = {
 193        .cpu_powerup            = exynos_cpu_powerup,
 194        .cluster_powerup        = exynos_cluster_powerup,
 195        .cpu_powerdown_prepare  = exynos_cpu_powerdown_prepare,
 196        .cluster_powerdown_prepare = exynos_cluster_powerdown_prepare,
 197        .cpu_cache_disable      = exynos_cpu_cache_disable,
 198        .cluster_cache_disable  = exynos_cluster_cache_disable,
 199        .wait_for_powerdown     = exynos_wait_for_powerdown,
 200        .cpu_is_up              = exynos_cpu_is_up,
 201};
 202
 203/*
 204 * Enable cluster-level coherency, in preparation for turning on the MMU.
 205 */
 206static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
 207{
 208        asm volatile ("\n"
 209        "cmp    r0, #1\n"
 210        "bxne   lr\n"
 211        "b      cci_enable_port_for_self");
 212}
 213
 214static const struct of_device_id exynos_dt_mcpm_match[] = {
 215        { .compatible = "samsung,exynos5420" },
 216        { .compatible = "samsung,exynos5800" },
 217        {},
 218};
 219
 220static void exynos_mcpm_setup_entry_point(void)
 221{
 222        /*
 223         * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
 224         * as part of secondary_cpu_start().  Let's redirect it to the
 225         * mcpm_entry_point(). This is done during both secondary boot-up as
 226         * well as system resume.
 227         */
 228        __raw_writel(0xe59f0000, ns_sram_base_addr);     /* ldr r0, [pc, #0] */
 229        __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx  r0 */
 230        __raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8);
 231}
 232
 233static struct syscore_ops exynos_mcpm_syscore_ops = {
 234        .resume = exynos_mcpm_setup_entry_point,
 235};
 236
 237static int __init exynos_mcpm_init(void)
 238{
 239        struct device_node *node;
 240        unsigned int value, i;
 241        int ret;
 242
 243        node = of_find_matching_node(NULL, exynos_dt_mcpm_match);
 244        if (!node)
 245                return -ENODEV;
 246        of_node_put(node);
 247
 248        if (!cci_probed())
 249                return -ENODEV;
 250
 251        node = of_find_compatible_node(NULL, NULL,
 252                        "samsung,exynos4210-sysram-ns");
 253        if (!node)
 254                return -ENODEV;
 255
 256        ns_sram_base_addr = of_iomap(node, 0);
 257        of_node_put(node);
 258        if (!ns_sram_base_addr) {
 259                pr_err("failed to map non-secure iRAM base address\n");
 260                return -ENOMEM;
 261        }
 262
 263        secure_firmware = exynos_secure_firmware_available();
 264
 265        /*
 266         * To increase the stability of KFC reset we need to program
 267         * the PMU SPARE3 register
 268         */
 269        pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
 270
 271        ret = mcpm_platform_register(&exynos_power_ops);
 272        if (!ret)
 273                ret = mcpm_sync_init(exynos_pm_power_up_setup);
 274        if (!ret)
 275                ret = mcpm_loopback(exynos_cluster_cache_disable); /* turn on the CCI */
 276        if (ret) {
 277                iounmap(ns_sram_base_addr);
 278                return ret;
 279        }
 280
 281        mcpm_smp_set_ops();
 282
 283        pr_info("Exynos MCPM support installed\n");
 284
 285        /*
 286         * On Exynos5420/5800 for the A15 and A7 clusters:
 287         *
 288         * EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN ensures that all the cores
 289         * in a cluster are turned off before turning off the cluster L2.
 290         *
 291         * EXYNOS5420_USE_ARM_CORE_DOWN_STATE ensures that a cores is powered
 292         * off before waking it up.
 293         *
 294         * EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 will be
 295         * turned on before the first man is powered up.
 296         */
 297        for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
 298                value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
 299                value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
 300                         EXYNOS5420_USE_ARM_CORE_DOWN_STATE    |
 301                         EXYNOS5420_USE_L2_COMMON_UP_STATE;
 302                pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
 303        }
 304
 305        exynos_mcpm_setup_entry_point();
 306
 307        register_syscore_ops(&exynos_mcpm_syscore_ops);
 308
 309        return ret;
 310}
 311
 312early_initcall(exynos_mcpm_init);
 313