LXR linux/arch/ia64/include/asm/iosapic.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef __ASM_IA64_IOSAPIC_H
   3#define __ASM_IA64_IOSAPIC_H
   4
   5#define IOSAPIC_REG_SELECT      0x0
   6#define IOSAPIC_WINDOW          0x10
   7#define IOSAPIC_EOI             0x40
   8
   9#define IOSAPIC_VERSION         0x1
  10
  11/*
  12 * Redirection table entry
  13 */
  14#define IOSAPIC_RTE_LOW(i)      (0x10+i*2)
  15#define IOSAPIC_RTE_HIGH(i)     (0x11+i*2)
  16
  17#define IOSAPIC_DEST_SHIFT              16
  18
  19/*
  20 * Delivery mode
  21 */
  22#define IOSAPIC_DELIVERY_SHIFT          8
  23#define IOSAPIC_FIXED                   0x0
  24#define IOSAPIC_LOWEST_PRIORITY 0x1
  25#define IOSAPIC_PMI                     0x2
  26#define IOSAPIC_NMI                     0x4
  27#define IOSAPIC_INIT                    0x5
  28#define IOSAPIC_EXTINT                  0x7
  29
  30/*
  31 * Interrupt polarity
  32 */
  33#define IOSAPIC_POLARITY_SHIFT          13
  34#define IOSAPIC_POL_HIGH                0
  35#define IOSAPIC_POL_LOW         1
  36
  37/*
  38 * Trigger mode
  39 */
  40#define IOSAPIC_TRIGGER_SHIFT           15
  41#define IOSAPIC_EDGE                    0
  42#define IOSAPIC_LEVEL                   1
  43
  44/*
  45 * Mask bit
  46 */
  47
  48#define IOSAPIC_MASK_SHIFT              16
  49#define IOSAPIC_MASK                    (1<<IOSAPIC_MASK_SHIFT)
  50
  51#define IOSAPIC_VECTOR_MASK             0xffffff00
  52
  53#ifndef __ASSEMBLY__
  54
  55#define NR_IOSAPICS                     256
  56
  57#define iosapic_pcat_compat_init        ia64_native_iosapic_pcat_compat_init
  58#define __iosapic_read                  __ia64_native_iosapic_read
  59#define __iosapic_write                 __ia64_native_iosapic_write
  60#define iosapic_get_irq_chip            ia64_native_iosapic_get_irq_chip
  61
  62extern void __init ia64_native_iosapic_pcat_compat_init(void);
  63extern struct irq_chip *ia64_native_iosapic_get_irq_chip(unsigned long trigger);
  64
  65static inline unsigned int
  66__ia64_native_iosapic_read(char __iomem *iosapic, unsigned int reg)
  67{
  68        writel(reg, iosapic + IOSAPIC_REG_SELECT);
  69        return readl(iosapic + IOSAPIC_WINDOW);
  70}
  71
  72static inline void
  73__ia64_native_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
  74{
  75        writel(reg, iosapic + IOSAPIC_REG_SELECT);
  76        writel(val, iosapic + IOSAPIC_WINDOW);
  77}
  78
  79static inline void iosapic_eoi(char __iomem *iosapic, u32 vector)
  80{
  81        writel(vector, iosapic + IOSAPIC_EOI);
  82}
  83
  84extern void __init iosapic_system_init (int pcat_compat);
  85extern int iosapic_init (unsigned long address, unsigned int gsi_base);
  86extern int iosapic_remove (unsigned int gsi_base);
  87extern int gsi_to_irq (unsigned int gsi);
  88extern int iosapic_register_intr (unsigned int gsi, unsigned long polarity,
  89                                  unsigned long trigger);
  90extern void iosapic_unregister_intr (unsigned int irq);
  91extern void iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
  92                                      unsigned long polarity,
  93                                      unsigned long trigger);
  94extern int __init iosapic_register_platform_intr (u32 int_type,
  95                                           unsigned int gsi,
  96                                           int pmi_vector,
  97                                           u16 eid, u16 id,
  98                                           unsigned long polarity,
  99                                           unsigned long trigger);
 100
 101#ifdef CONFIG_NUMA
 102extern void map_iosapic_to_node (unsigned int, int);
 103#endif
 104
 105# endif /* !__ASSEMBLY__ */
 106#endif /* __ASM_IA64_IOSAPIC_H */
 107