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28#include <linux/init.h>
29#include <linux/ioport.h>
30#include <linux/mm.h>
31
32#include <asm/dma-coherence.h>
33#include <asm/mipsregs.h>
34
35#include <au1000.h>
36
37extern void __init board_setup(void);
38extern void __init alchemy_set_lpj(void);
39
40void __init plat_mem_setup(void)
41{
42 alchemy_set_lpj();
43
44 if (au1xxx_cpu_needs_config_od())
45
46 set_c0_config(1 << 19);
47 else
48
49 clear_c0_config(1 << 19);
50
51 hw_coherentio = 0;
52 coherentio = IO_COHERENCE_ENABLED;
53 switch (alchemy_get_cputype()) {
54 case ALCHEMY_CPU_AU1000:
55 case ALCHEMY_CPU_AU1500:
56 case ALCHEMY_CPU_AU1100:
57 coherentio = IO_COHERENCE_DISABLED;
58 break;
59 case ALCHEMY_CPU_AU1200:
60
61 if (0 == (read_c0_prid() & PRID_REV_MASK))
62 coherentio = IO_COHERENCE_DISABLED;
63 break;
64 }
65
66 board_setup();
67
68
69 set_io_port_base(0);
70 ioport_resource.start = IOPORT_RESOURCE_START;
71 ioport_resource.end = IOPORT_RESOURCE_END;
72 iomem_resource.start = IOMEM_RESOURCE_START;
73 iomem_resource.end = IOMEM_RESOURCE_END;
74}
75
76#ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR
77
78phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
79{
80 unsigned long start = ALCHEMY_PCI_MEMWIN_START;
81 unsigned long end = ALCHEMY_PCI_MEMWIN_END;
82
83
84 if ((phys_addr >> 32) != 0)
85 return phys_addr;
86
87
88 if (phys_addr >= start && (phys_addr + size - 1) <= end)
89 return (phys_addr_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);
90
91
92 return phys_addr;
93}
94
95int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr,
96 unsigned long pfn, unsigned long size, pgprot_t prot)
97{
98 phys_addr_t phys_addr = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
99
100 return remap_pfn_range(vma, vaddr, phys_addr >> PAGE_SHIFT, size, prot);
101}
102EXPORT_SYMBOL(io_remap_pfn_range);
103#endif
104