linux/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
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   1/***********************license start***************
   2 * Author: Cavium Networks
   3 *
   4 * Contact: support@caviumnetworks.com
   5 * This file is part of the OCTEON SDK
   6 *
   7 * Copyright (c) 2003-2012 Cavium Networks
   8 *
   9 * This file is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License, Version 2, as
  11 * published by the Free Software Foundation.
  12 *
  13 * This file is distributed in the hope that it will be useful, but
  14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16 * NONINFRINGEMENT.  See the GNU General Public License for more
  17 * details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this file; if not, write to the Free Software
  21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22 * or visit http://www.gnu.org/licenses/.
  23 *
  24 * This file may also be available under a different license from Cavium.
  25 * Contact Cavium Networks for more information
  26 ***********************license end**************************************/
  27
  28#ifndef __CVMX_RNM_DEFS_H__
  29#define __CVMX_RNM_DEFS_H__
  30
  31#define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull))
  32#define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull))
  33#define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull))
  34#define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull))
  35#define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull))
  36
  37union cvmx_rnm_bist_status {
  38        uint64_t u64;
  39        struct cvmx_rnm_bist_status_s {
  40#ifdef __BIG_ENDIAN_BITFIELD
  41                uint64_t reserved_2_63:62;
  42                uint64_t rrc:1;
  43                uint64_t mem:1;
  44#else
  45                uint64_t mem:1;
  46                uint64_t rrc:1;
  47                uint64_t reserved_2_63:62;
  48#endif
  49        } s;
  50};
  51
  52union cvmx_rnm_ctl_status {
  53        uint64_t u64;
  54        struct cvmx_rnm_ctl_status_s {
  55#ifdef __BIG_ENDIAN_BITFIELD
  56                uint64_t reserved_12_63:52;
  57                uint64_t dis_mak:1;
  58                uint64_t eer_lck:1;
  59                uint64_t eer_val:1;
  60                uint64_t ent_sel:4;
  61                uint64_t exp_ent:1;
  62                uint64_t rng_rst:1;
  63                uint64_t rnm_rst:1;
  64                uint64_t rng_en:1;
  65                uint64_t ent_en:1;
  66#else
  67                uint64_t ent_en:1;
  68                uint64_t rng_en:1;
  69                uint64_t rnm_rst:1;
  70                uint64_t rng_rst:1;
  71                uint64_t exp_ent:1;
  72                uint64_t ent_sel:4;
  73                uint64_t eer_val:1;
  74                uint64_t eer_lck:1;
  75                uint64_t dis_mak:1;
  76                uint64_t reserved_12_63:52;
  77#endif
  78        } s;
  79        struct cvmx_rnm_ctl_status_cn30xx {
  80#ifdef __BIG_ENDIAN_BITFIELD
  81                uint64_t reserved_4_63:60;
  82                uint64_t rng_rst:1;
  83                uint64_t rnm_rst:1;
  84                uint64_t rng_en:1;
  85                uint64_t ent_en:1;
  86#else
  87                uint64_t ent_en:1;
  88                uint64_t rng_en:1;
  89                uint64_t rnm_rst:1;
  90                uint64_t rng_rst:1;
  91                uint64_t reserved_4_63:60;
  92#endif
  93        } cn30xx;
  94        struct cvmx_rnm_ctl_status_cn50xx {
  95#ifdef __BIG_ENDIAN_BITFIELD
  96                uint64_t reserved_9_63:55;
  97                uint64_t ent_sel:4;
  98                uint64_t exp_ent:1;
  99                uint64_t rng_rst:1;
 100                uint64_t rnm_rst:1;
 101                uint64_t rng_en:1;
 102                uint64_t ent_en:1;
 103#else
 104                uint64_t ent_en:1;
 105                uint64_t rng_en:1;
 106                uint64_t rnm_rst:1;
 107                uint64_t rng_rst:1;
 108                uint64_t exp_ent:1;
 109                uint64_t ent_sel:4;
 110                uint64_t reserved_9_63:55;
 111#endif
 112        } cn50xx;
 113        struct cvmx_rnm_ctl_status_cn63xx {
 114#ifdef __BIG_ENDIAN_BITFIELD
 115                uint64_t reserved_11_63:53;
 116                uint64_t eer_lck:1;
 117                uint64_t eer_val:1;
 118                uint64_t ent_sel:4;
 119                uint64_t exp_ent:1;
 120                uint64_t rng_rst:1;
 121                uint64_t rnm_rst:1;
 122                uint64_t rng_en:1;
 123                uint64_t ent_en:1;
 124#else
 125                uint64_t ent_en:1;
 126                uint64_t rng_en:1;
 127                uint64_t rnm_rst:1;
 128                uint64_t rng_rst:1;
 129                uint64_t exp_ent:1;
 130                uint64_t ent_sel:4;
 131                uint64_t eer_val:1;
 132                uint64_t eer_lck:1;
 133                uint64_t reserved_11_63:53;
 134#endif
 135        } cn63xx;
 136};
 137
 138union cvmx_rnm_eer_dbg {
 139        uint64_t u64;
 140        struct cvmx_rnm_eer_dbg_s {
 141#ifdef __BIG_ENDIAN_BITFIELD
 142                uint64_t dat:64;
 143#else
 144                uint64_t dat:64;
 145#endif
 146        } s;
 147};
 148
 149union cvmx_rnm_eer_key {
 150        uint64_t u64;
 151        struct cvmx_rnm_eer_key_s {
 152#ifdef __BIG_ENDIAN_BITFIELD
 153                uint64_t key:64;
 154#else
 155                uint64_t key:64;
 156#endif
 157        } s;
 158};
 159
 160union cvmx_rnm_serial_num {
 161        uint64_t u64;
 162        struct cvmx_rnm_serial_num_s {
 163#ifdef __BIG_ENDIAN_BITFIELD
 164                uint64_t dat:64;
 165#else
 166                uint64_t dat:64;
 167#endif
 168        } s;
 169};
 170
 171#endif
 172