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11#undef DEBUG
12
13#include <linux/sched.h>
14#include <linux/kernel.h>
15#include <linux/mm.h>
16#include <linux/stddef.h>
17#include <linux/export.h>
18#include <linux/unistd.h>
19#include <linux/user.h>
20#include <linux/reboot.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/irq.h>
24#include <linux/seq_file.h>
25#include <linux/root_dev.h>
26#include <linux/console.h>
27#include <linux/mutex.h>
28#include <linux/memory_hotplug.h>
29#include <linux/of_platform.h>
30
31#include <asm/mmu.h>
32#include <asm/processor.h>
33#include <asm/io.h>
34#include <asm/prom.h>
35#include <asm/rtas.h>
36#include <asm/pci-bridge.h>
37#include <asm/iommu.h>
38#include <asm/dma.h>
39#include <asm/machdep.h>
40#include <asm/time.h>
41#include <asm/nvram.h>
42#include <asm/cputable.h>
43#include <asm/ppc-pci.h>
44#include <asm/irq.h>
45#include <asm/spu.h>
46#include <asm/spu_priv1.h>
47#include <asm/udbg.h>
48#include <asm/mpic.h>
49#include <asm/cell-regs.h>
50#include <asm/io-workarounds.h>
51
52#include "cell.h"
53#include "interrupt.h"
54#include "pervasive.h"
55#include "ras.h"
56
57#ifdef DEBUG
58#define DBG(fmt...) udbg_printf(fmt)
59#else
60#define DBG(fmt...)
61#endif
62
63static void cell_show_cpuinfo(struct seq_file *m)
64{
65 struct device_node *root;
66 const char *model = "";
67
68 root = of_find_node_by_path("/");
69 if (root)
70 model = of_get_property(root, "model", NULL);
71 seq_printf(m, "machine\t\t: CHRP %s\n", model);
72 of_node_put(root);
73}
74
75static void cell_progress(char *s, unsigned short hex)
76{
77 printk("*** %04x : %s\n", hex, s ? s : "");
78}
79
80static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev)
81{
82 struct pci_controller *hose;
83 const char *s;
84 int i;
85
86 if (!machine_is(cell))
87 return;
88
89
90 if (dev->bus->self != NULL || dev->devfn != 0)
91 return;
92
93 hose = pci_bus_to_host(dev->bus);
94 if (hose == NULL)
95 return;
96
97
98 if (!of_device_is_compatible(hose->dn, "pciex"))
99 return;
100
101
102 s = of_get_property(hose->dn, "model", NULL);
103 if (!s || strcmp(s, "Axon") != 0)
104 return;
105
106 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
107 dev->resource[i].start = dev->resource[i].end = 0;
108 dev->resource[i].flags = 0;
109 }
110
111 printk(KERN_DEBUG "PCI: Hiding resources on Axon PCIE RC %s\n",
112 pci_name(dev));
113}
114DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex);
115
116static int cell_setup_phb(struct pci_controller *phb)
117{
118 const char *model;
119 struct device_node *np;
120
121 int rc = rtas_setup_phb(phb);
122 if (rc)
123 return rc;
124
125 phb->controller_ops = cell_pci_controller_ops;
126
127 np = phb->dn;
128 model = of_get_property(np, "model", NULL);
129 if (model == NULL || !of_node_name_eq(np, "pci"))
130 return 0;
131
132
133 if (strcmp(model, "Spider"))
134 return 0;
135
136 iowa_register_bus(phb, &spiderpci_ops, &spiderpci_iowa_init,
137 (void *)SPIDER_PCI_REG_BASE);
138 return 0;
139}
140
141static const struct of_device_id cell_bus_ids[] __initconst = {
142 { .type = "soc", },
143 { .compatible = "soc", },
144 { .type = "spider", },
145 { .type = "axon", },
146 { .type = "plb5", },
147 { .type = "plb4", },
148 { .type = "opb", },
149 { .type = "ebc", },
150 {},
151};
152
153static int __init cell_publish_devices(void)
154{
155 struct device_node *root = of_find_node_by_path("/");
156 struct device_node *np;
157 int node;
158
159
160 of_platform_bus_probe(NULL, cell_bus_ids, NULL);
161
162
163
164
165 for_each_child_of_node(root, np) {
166 if (!of_node_is_type(np, "pci") && !of_node_is_type(np, "pciex"))
167 continue;
168 of_platform_device_create(np, NULL, NULL);
169 }
170
171
172
173
174 for_each_online_node(node) {
175 if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL)
176 continue;
177 platform_device_register_simple("cbe-mic", node, NULL, 0);
178 }
179
180 return 0;
181}
182machine_subsys_initcall(cell, cell_publish_devices);
183
184static void __init mpic_init_IRQ(void)
185{
186 struct device_node *dn;
187 struct mpic *mpic;
188
189 for_each_node_by_name(dn, "interrupt-controller") {
190 if (!of_device_is_compatible(dn, "CBEA,platform-open-pic"))
191 continue;
192
193
194
195
196 mpic = mpic_alloc(dn, 0, MPIC_SECONDARY | MPIC_NO_RESET,
197 0, 0, " MPIC ");
198 if (mpic == NULL)
199 continue;
200 mpic_init(mpic);
201 }
202}
203
204
205static void __init cell_init_irq(void)
206{
207 iic_init_IRQ();
208 spider_init_IRQ();
209 mpic_init_IRQ();
210}
211
212static void __init cell_set_dabrx(void)
213{
214 mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER);
215}
216
217static void __init cell_setup_arch(void)
218{
219#ifdef CONFIG_SPU_BASE
220 spu_priv1_ops = &spu_priv1_mmio_ops;
221 spu_management_ops = &spu_management_of_ops;
222#endif
223
224 cbe_regs_init();
225
226 cell_set_dabrx();
227
228#ifdef CONFIG_CBE_RAS
229 cbe_ras_init();
230#endif
231
232#ifdef CONFIG_SMP
233 smp_init_cell();
234#endif
235
236 loops_per_jiffy = 50000000;
237
238
239 init_pci_config_tokens();
240
241 cbe_pervasive_init();
242
243 mmio_nvram_init();
244}
245
246static int __init cell_probe(void)
247{
248 if (!of_machine_is_compatible("IBM,CBEA") &&
249 !of_machine_is_compatible("IBM,CPBW-1.0"))
250 return 0;
251
252 pm_power_off = rtas_power_off;
253
254 return 1;
255}
256
257define_machine(cell) {
258 .name = "Cell",
259 .probe = cell_probe,
260 .setup_arch = cell_setup_arch,
261 .show_cpuinfo = cell_show_cpuinfo,
262 .restart = rtas_restart,
263 .halt = rtas_halt,
264 .get_boot_time = rtas_get_boot_time,
265 .get_rtc_time = rtas_get_rtc_time,
266 .set_rtc_time = rtas_set_rtc_time,
267 .calibrate_decr = generic_calibrate_decr,
268 .progress = cell_progress,
269 .init_IRQ = cell_init_irq,
270 .pci_setup_phb = cell_setup_phb,
271};
272
273struct pci_controller_ops cell_pci_controller_ops;
274
