1
2#ifndef __SVM_H
3#define __SVM_H
4
5#include <uapi/asm/svm.h>
6#include <uapi/asm/kvm.h>
7
8
9
10
11
12
13enum intercept_words {
14 INTERCEPT_CR = 0,
15 INTERCEPT_DR,
16 INTERCEPT_EXCEPTION,
17 INTERCEPT_WORD3,
18 INTERCEPT_WORD4,
19 INTERCEPT_WORD5,
20 MAX_INTERCEPT,
21};
22
23enum {
24
25 INTERCEPT_CR0_READ = 0,
26 INTERCEPT_CR3_READ = 3,
27 INTERCEPT_CR4_READ = 4,
28 INTERCEPT_CR8_READ = 8,
29 INTERCEPT_CR0_WRITE = 16,
30 INTERCEPT_CR3_WRITE = 16 + 3,
31 INTERCEPT_CR4_WRITE = 16 + 4,
32 INTERCEPT_CR8_WRITE = 16 + 8,
33
34 INTERCEPT_DR0_READ = 32,
35 INTERCEPT_DR1_READ,
36 INTERCEPT_DR2_READ,
37 INTERCEPT_DR3_READ,
38 INTERCEPT_DR4_READ,
39 INTERCEPT_DR5_READ,
40 INTERCEPT_DR6_READ,
41 INTERCEPT_DR7_READ,
42 INTERCEPT_DR0_WRITE = 48,
43 INTERCEPT_DR1_WRITE,
44 INTERCEPT_DR2_WRITE,
45 INTERCEPT_DR3_WRITE,
46 INTERCEPT_DR4_WRITE,
47 INTERCEPT_DR5_WRITE,
48 INTERCEPT_DR6_WRITE,
49 INTERCEPT_DR7_WRITE,
50
51 INTERCEPT_EXCEPTION_OFFSET = 64,
52
53 INTERCEPT_INTR = 96,
54 INTERCEPT_NMI,
55 INTERCEPT_SMI,
56 INTERCEPT_INIT,
57 INTERCEPT_VINTR,
58 INTERCEPT_SELECTIVE_CR0,
59 INTERCEPT_STORE_IDTR,
60 INTERCEPT_STORE_GDTR,
61 INTERCEPT_STORE_LDTR,
62 INTERCEPT_STORE_TR,
63 INTERCEPT_LOAD_IDTR,
64 INTERCEPT_LOAD_GDTR,
65 INTERCEPT_LOAD_LDTR,
66 INTERCEPT_LOAD_TR,
67 INTERCEPT_RDTSC,
68 INTERCEPT_RDPMC,
69 INTERCEPT_PUSHF,
70 INTERCEPT_POPF,
71 INTERCEPT_CPUID,
72 INTERCEPT_RSM,
73 INTERCEPT_IRET,
74 INTERCEPT_INTn,
75 INTERCEPT_INVD,
76 INTERCEPT_PAUSE,
77 INTERCEPT_HLT,
78 INTERCEPT_INVLPG,
79 INTERCEPT_INVLPGA,
80 INTERCEPT_IOIO_PROT,
81 INTERCEPT_MSR_PROT,
82 INTERCEPT_TASK_SWITCH,
83 INTERCEPT_FERR_FREEZE,
84 INTERCEPT_SHUTDOWN,
85
86 INTERCEPT_VMRUN = 128,
87 INTERCEPT_VMMCALL,
88 INTERCEPT_VMLOAD,
89 INTERCEPT_VMSAVE,
90 INTERCEPT_STGI,
91 INTERCEPT_CLGI,
92 INTERCEPT_SKINIT,
93 INTERCEPT_RDTSCP,
94 INTERCEPT_ICEBP,
95 INTERCEPT_WBINVD,
96 INTERCEPT_MONITOR,
97 INTERCEPT_MWAIT,
98 INTERCEPT_MWAIT_COND,
99 INTERCEPT_XSETBV,
100 INTERCEPT_RDPRU,
101 TRAP_EFER_WRITE,
102 TRAP_CR0_WRITE,
103 TRAP_CR1_WRITE,
104 TRAP_CR2_WRITE,
105 TRAP_CR3_WRITE,
106 TRAP_CR4_WRITE,
107 TRAP_CR5_WRITE,
108 TRAP_CR6_WRITE,
109 TRAP_CR7_WRITE,
110 TRAP_CR8_WRITE,
111
112 INTERCEPT_INVLPGB = 160,
113 INTERCEPT_INVLPGB_ILLEGAL,
114 INTERCEPT_INVPCID,
115 INTERCEPT_MCOMMIT,
116 INTERCEPT_TLBSYNC,
117};
118
119
120struct __attribute__ ((__packed__)) vmcb_control_area {
121 u32 intercepts[MAX_INTERCEPT];
122 u32 reserved_1[15 - MAX_INTERCEPT];
123 u16 pause_filter_thresh;
124 u16 pause_filter_count;
125 u64 iopm_base_pa;
126 u64 msrpm_base_pa;
127 u64 tsc_offset;
128 u32 asid;
129 u8 tlb_ctl;
130 u8 reserved_2[3];
131 u32 int_ctl;
132 u32 int_vector;
133 u32 int_state;
134 u8 reserved_3[4];
135 u32 exit_code;
136 u32 exit_code_hi;
137 u64 exit_info_1;
138 u64 exit_info_2;
139 u32 exit_int_info;
140 u32 exit_int_info_err;
141 u64 nested_ctl;
142 u64 avic_vapic_bar;
143 u64 ghcb_gpa;
144 u32 event_inj;
145 u32 event_inj_err;
146 u64 nested_cr3;
147 u64 virt_ext;
148 u32 clean;
149 u32 reserved_5;
150 u64 next_rip;
151 u8 insn_len;
152 u8 insn_bytes[15];
153 u64 avic_backing_page;
154 u8 reserved_6[8];
155 u64 avic_logical_id;
156 u64 avic_physical_id;
157 u8 reserved_7[8];
158 u64 vmsa_pa;
159};
160
161
162#define TLB_CONTROL_DO_NOTHING 0
163#define TLB_CONTROL_FLUSH_ALL_ASID 1
164#define TLB_CONTROL_FLUSH_ASID 3
165#define TLB_CONTROL_FLUSH_ASID_LOCAL 7
166
167#define V_TPR_MASK 0x0f
168
169#define V_IRQ_SHIFT 8
170#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
171
172#define V_GIF_SHIFT 9
173#define V_GIF_MASK (1 << V_GIF_SHIFT)
174
175#define V_INTR_PRIO_SHIFT 16
176#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
177
178#define V_IGN_TPR_SHIFT 20
179#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
180
181#define V_INTR_MASKING_SHIFT 24
182#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
183
184#define V_GIF_ENABLE_SHIFT 25
185#define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
186
187#define AVIC_ENABLE_SHIFT 31
188#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
189
190#define LBR_CTL_ENABLE_MASK BIT_ULL(0)
191#define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
192
193#define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0)
194#define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1)
195
196#define SVM_IOIO_STR_SHIFT 2
197#define SVM_IOIO_REP_SHIFT 3
198#define SVM_IOIO_SIZE_SHIFT 4
199#define SVM_IOIO_ASIZE_SHIFT 7
200
201#define SVM_IOIO_TYPE_MASK 1
202#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
203#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
204#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
205#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
206
207#define SVM_VM_CR_VALID_MASK 0x001fULL
208#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
209#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
210
211#define SVM_NESTED_CTL_NP_ENABLE BIT(0)
212#define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
213#define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2)
214
215struct vmcb_seg {
216 u16 selector;
217 u16 attrib;
218 u32 limit;
219 u64 base;
220} __packed;
221
222struct vmcb_save_area {
223 struct vmcb_seg es;
224 struct vmcb_seg cs;
225 struct vmcb_seg ss;
226 struct vmcb_seg ds;
227 struct vmcb_seg fs;
228 struct vmcb_seg gs;
229 struct vmcb_seg gdtr;
230 struct vmcb_seg ldtr;
231 struct vmcb_seg idtr;
232 struct vmcb_seg tr;
233 u8 reserved_1[43];
234 u8 cpl;
235 u8 reserved_2[4];
236 u64 efer;
237 u8 reserved_3[104];
238 u64 xss;
239 u64 cr4;
240 u64 cr3;
241 u64 cr0;
242 u64 dr7;
243 u64 dr6;
244 u64 rflags;
245 u64 rip;
246 u8 reserved_4[88];
247 u64 rsp;
248 u8 reserved_5[24];
249 u64 rax;
250 u64 star;
251 u64 lstar;
252 u64 cstar;
253 u64 sfmask;
254 u64 kernel_gs_base;
255 u64 sysenter_cs;
256 u64 sysenter_esp;
257 u64 sysenter_eip;
258 u64 cr2;
259 u8 reserved_6[32];
260 u64 g_pat;
261 u64 dbgctl;
262 u64 br_from;
263 u64 br_to;
264 u64 last_excp_from;
265 u64 last_excp_to;
266
267
268
269
270
271
272 u8 reserved_7[80];
273 u32 pkru;
274 u8 reserved_7a[20];
275 u64 reserved_8;
276 u64 rcx;
277 u64 rdx;
278 u64 rbx;
279 u64 reserved_9;
280 u64 rbp;
281 u64 rsi;
282 u64 rdi;
283 u64 r8;
284 u64 r9;
285 u64 r10;
286 u64 r11;
287 u64 r12;
288 u64 r13;
289 u64 r14;
290 u64 r15;
291 u8 reserved_10[16];
292 u64 sw_exit_code;
293 u64 sw_exit_info_1;
294 u64 sw_exit_info_2;
295 u64 sw_scratch;
296 u8 reserved_11[56];
297 u64 xcr0;
298 u8 valid_bitmap[16];
299 u64 x87_state_gpa;
300} __packed;
301
302struct ghcb {
303 struct vmcb_save_area save;
304 u8 reserved_save[2048 - sizeof(struct vmcb_save_area)];
305
306 u8 shared_buffer[2032];
307
308 u8 reserved_1[10];
309 u16 protocol_version;
310 u32 ghcb_usage;
311} __packed;
312
313
314#define EXPECTED_VMCB_SAVE_AREA_SIZE 1032
315#define EXPECTED_VMCB_CONTROL_AREA_SIZE 272
316#define EXPECTED_GHCB_SIZE PAGE_SIZE
317
318static inline void __unused_size_checks(void)
319{
320 BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE);
321 BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
322 BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE);
323}
324
325struct vmcb {
326 struct vmcb_control_area control;
327 u8 reserved_control[1024 - sizeof(struct vmcb_control_area)];
328 struct vmcb_save_area save;
329} __packed;
330
331#define SVM_CPUID_FUNC 0x8000000a
332
333#define SVM_VM_CR_SVM_DISABLE 4
334
335#define SVM_SELECTOR_S_SHIFT 4
336#define SVM_SELECTOR_DPL_SHIFT 5
337#define SVM_SELECTOR_P_SHIFT 7
338#define SVM_SELECTOR_AVL_SHIFT 8
339#define SVM_SELECTOR_L_SHIFT 9
340#define SVM_SELECTOR_DB_SHIFT 10
341#define SVM_SELECTOR_G_SHIFT 11
342
343#define SVM_SELECTOR_TYPE_MASK (0xf)
344#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
345#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
346#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
347#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
348#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
349#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
350#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
351
352#define SVM_SELECTOR_WRITE_MASK (1 << 1)
353#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
354#define SVM_SELECTOR_CODE_MASK (1 << 3)
355
356#define SVM_EVTINJ_VEC_MASK 0xff
357
358#define SVM_EVTINJ_TYPE_SHIFT 8
359#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
360
361#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
362#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
363#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
364#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
365
366#define SVM_EVTINJ_VALID (1 << 31)
367#define SVM_EVTINJ_VALID_ERR (1 << 11)
368
369#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
370#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
371
372#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
373#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
374#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
375#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
376
377#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
378#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
379
380#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
381#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
382#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
383
384#define SVM_EXITINFO_REG_MASK 0x0F
385
386#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
387
388
389
390#define GHCB_BITMAP_IDX(field) \
391 (offsetof(struct vmcb_save_area, field) / sizeof(u64))
392
393#define DEFINE_GHCB_ACCESSORS(field) \
394 static inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
395 { \
396 return test_bit(GHCB_BITMAP_IDX(field), \
397 (unsigned long *)&ghcb->save.valid_bitmap); \
398 } \
399 \
400 static inline u64 ghcb_get_##field(struct ghcb *ghcb) \
401 { \
402 return ghcb->save.field; \
403 } \
404 \
405 static inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \
406 { \
407 return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0; \
408 } \
409 \
410 static inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \
411 { \
412 __set_bit(GHCB_BITMAP_IDX(field), \
413 (unsigned long *)&ghcb->save.valid_bitmap); \
414 ghcb->save.field = value; \
415 }
416
417DEFINE_GHCB_ACCESSORS(cpl)
418DEFINE_GHCB_ACCESSORS(rip)
419DEFINE_GHCB_ACCESSORS(rsp)
420DEFINE_GHCB_ACCESSORS(rax)
421DEFINE_GHCB_ACCESSORS(rcx)
422DEFINE_GHCB_ACCESSORS(rdx)
423DEFINE_GHCB_ACCESSORS(rbx)
424DEFINE_GHCB_ACCESSORS(rbp)
425DEFINE_GHCB_ACCESSORS(rsi)
426DEFINE_GHCB_ACCESSORS(rdi)
427DEFINE_GHCB_ACCESSORS(r8)
428DEFINE_GHCB_ACCESSORS(r9)
429DEFINE_GHCB_ACCESSORS(r10)
430DEFINE_GHCB_ACCESSORS(r11)
431DEFINE_GHCB_ACCESSORS(r12)
432DEFINE_GHCB_ACCESSORS(r13)
433DEFINE_GHCB_ACCESSORS(r14)
434DEFINE_GHCB_ACCESSORS(r15)
435DEFINE_GHCB_ACCESSORS(sw_exit_code)
436DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
437DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
438DEFINE_GHCB_ACCESSORS(sw_scratch)
439DEFINE_GHCB_ACCESSORS(xcr0)
440
441#endif
442