1
2#ifndef ARCH_X86_KVM_X86_H
3#define ARCH_X86_KVM_X86_H
4
5#include <linux/kvm_host.h>
6#include <asm/mce.h>
7#include <asm/pvclock.h>
8#include "kvm_cache_regs.h"
9#include "kvm_emulate.h"
10
11#define KVM_DEFAULT_PLE_GAP 128
12#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
13#define KVM_DEFAULT_PLE_WINDOW_GROW 2
14#define KVM_DEFAULT_PLE_WINDOW_SHRINK 0
15#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX
16#define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX
17#define KVM_SVM_DEFAULT_PLE_WINDOW 3000
18
19static inline unsigned int __grow_ple_window(unsigned int val,
20 unsigned int base, unsigned int modifier, unsigned int max)
21{
22 u64 ret = val;
23
24 if (modifier < 1)
25 return base;
26
27 if (modifier < base)
28 ret *= modifier;
29 else
30 ret += modifier;
31
32 return min(ret, (u64)max);
33}
34
35static inline unsigned int __shrink_ple_window(unsigned int val,
36 unsigned int base, unsigned int modifier, unsigned int min)
37{
38 if (modifier < 1)
39 return base;
40
41 if (modifier < base)
42 val /= modifier;
43 else
44 val -= modifier;
45
46 return max(val, min);
47}
48
49#define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL
50
51static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
52{
53 vcpu->arch.exception.pending = false;
54 vcpu->arch.exception.injected = false;
55}
56
57static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
58 bool soft)
59{
60 vcpu->arch.interrupt.injected = true;
61 vcpu->arch.interrupt.soft = soft;
62 vcpu->arch.interrupt.nr = vector;
63}
64
65static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
66{
67 vcpu->arch.interrupt.injected = false;
68}
69
70static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
71{
72 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected ||
73 vcpu->arch.nmi_injected;
74}
75
76static inline bool kvm_exception_is_soft(unsigned int nr)
77{
78 return (nr == BP_VECTOR) || (nr == OF_VECTOR);
79}
80
81static inline bool is_protmode(struct kvm_vcpu *vcpu)
82{
83 return kvm_read_cr0_bits(vcpu, X86_CR0_PE);
84}
85
86static inline int is_long_mode(struct kvm_vcpu *vcpu)
87{
88#ifdef CONFIG_X86_64
89 return vcpu->arch.efer & EFER_LMA;
90#else
91 return 0;
92#endif
93}
94
95static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu)
96{
97 int cs_db, cs_l;
98
99 if (!is_long_mode(vcpu))
100 return false;
101 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
102 return cs_l;
103}
104
105static inline bool is_la57_mode(struct kvm_vcpu *vcpu)
106{
107#ifdef CONFIG_X86_64
108 return (vcpu->arch.efer & EFER_LMA) &&
109 kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
110#else
111 return 0;
112#endif
113}
114
115static inline bool x86_exception_has_error_code(unsigned int vector)
116{
117 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) |
118 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) |
119 BIT(PF_VECTOR) | BIT(AC_VECTOR);
120
121 return (1U << vector) & exception_has_error_code;
122}
123
124static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
125{
126 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
127}
128
129static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
130{
131 ++vcpu->stat.tlb_flush;
132 kvm_x86_ops.tlb_flush_current(vcpu);
133}
134
135static inline int is_pae(struct kvm_vcpu *vcpu)
136{
137 return kvm_read_cr4_bits(vcpu, X86_CR4_PAE);
138}
139
140static inline int is_pse(struct kvm_vcpu *vcpu)
141{
142 return kvm_read_cr4_bits(vcpu, X86_CR4_PSE);
143}
144
145static inline int is_paging(struct kvm_vcpu *vcpu)
146{
147 return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG));
148}
149
150static inline bool is_pae_paging(struct kvm_vcpu *vcpu)
151{
152 return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu);
153}
154
155static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
156{
157 return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
158}
159
160static inline u64 get_canonical(u64 la, u8 vaddr_bits)
161{
162 return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits);
163}
164
165static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
166{
167 return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la;
168}
169
170static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
171 gva_t gva, gfn_t gfn, unsigned access)
172{
173 u64 gen = kvm_memslots(vcpu->kvm)->generation;
174
175 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
176 return;
177
178
179
180
181
182 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
183 vcpu->arch.mmio_access = access;
184 vcpu->arch.mmio_gfn = gfn;
185 vcpu->arch.mmio_gen = gen;
186}
187
188static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
189{
190 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation;
191}
192
193
194
195
196
197#define MMIO_GVA_ANY (~(gva_t)0)
198
199static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
200{
201 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
202 return;
203
204 vcpu->arch.mmio_gva = 0;
205}
206
207static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
208{
209 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
210 vcpu->arch.mmio_gva == (gva & PAGE_MASK))
211 return true;
212
213 return false;
214}
215
216static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
217{
218 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
219 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
220 return true;
221
222 return false;
223}
224
225static inline unsigned long kvm_register_readl(struct kvm_vcpu *vcpu, int reg)
226{
227 unsigned long val = kvm_register_read(vcpu, reg);
228
229 return is_64_bit_mode(vcpu) ? val : (u32)val;
230}
231
232static inline void kvm_register_writel(struct kvm_vcpu *vcpu,
233 int reg, unsigned long val)
234{
235 if (!is_64_bit_mode(vcpu))
236 val = (u32)val;
237 return kvm_register_write(vcpu, reg, val);
238}
239
240static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
241{
242 return !(kvm->arch.disabled_quirks & quirk);
243}
244
245static inline bool kvm_vcpu_latch_init(struct kvm_vcpu *vcpu)
246{
247 return is_smm(vcpu) || kvm_x86_ops.apic_init_signal_blocked(vcpu);
248}
249
250void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
251
252void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr);
253u64 get_kvmclock_ns(struct kvm *kvm);
254
255int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
256 gva_t addr, void *val, unsigned int bytes,
257 struct x86_exception *exception);
258
259int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu,
260 gva_t addr, void *val, unsigned int bytes,
261 struct x86_exception *exception);
262
263int handle_ud(struct kvm_vcpu *vcpu);
264
265void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu);
266
267void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu);
268u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
269bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
270int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
271int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
272bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn,
273 int page_num);
274bool kvm_vector_hashing_enabled(void);
275void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code);
276int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
277 int emulation_type, void *insn, int insn_len);
278fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu);
279
280extern u64 host_xcr0;
281extern u64 supported_xcr0;
282extern u64 host_xss;
283extern u64 supported_xss;
284
285static inline bool kvm_mpx_supported(void)
286{
287 return (supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
288 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
289}
290
291extern unsigned int min_timer_period_us;
292
293extern bool enable_vmware_backdoor;
294
295extern int pi_inject_timer;
296
297extern struct static_key kvm_no_apic_vcpu;
298
299static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
300{
301 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
302 vcpu->arch.virtual_tsc_shift);
303}
304
305
306
307
308
309
310#define do_shl32_div32(n, base) \
311 ({ \
312 u32 __quot, __rem; \
313 asm("divl %2" : "=a" (__quot), "=d" (__rem) \
314 : "rm" (base), "0" (0), "1" ((u32) n)); \
315 n = __quot; \
316 __rem; \
317 })
318
319static inline bool kvm_mwait_in_guest(struct kvm *kvm)
320{
321 return kvm->arch.mwait_in_guest;
322}
323
324static inline bool kvm_hlt_in_guest(struct kvm *kvm)
325{
326 return kvm->arch.hlt_in_guest;
327}
328
329static inline bool kvm_pause_in_guest(struct kvm *kvm)
330{
331 return kvm->arch.pause_in_guest;
332}
333
334static inline bool kvm_cstate_in_guest(struct kvm *kvm)
335{
336 return kvm->arch.cstate_in_guest;
337}
338
339DECLARE_PER_CPU(struct kvm_vcpu *, current_vcpu);
340
341static inline void kvm_before_interrupt(struct kvm_vcpu *vcpu)
342{
343 __this_cpu_write(current_vcpu, vcpu);
344}
345
346static inline void kvm_after_interrupt(struct kvm_vcpu *vcpu)
347{
348 __this_cpu_write(current_vcpu, NULL);
349}
350
351
352static inline bool kvm_pat_valid(u64 data)
353{
354 if (data & 0xF8F8F8F8F8F8F8F8ull)
355 return false;
356
357 return (data | ((data & 0x0202020202020202ull) << 1)) == data;
358}
359
360static inline bool kvm_dr7_valid(u64 data)
361{
362
363 return !(data >> 32);
364}
365static inline bool kvm_dr6_valid(u64 data)
366{
367
368 return !(data >> 32);
369}
370
371
372
373
374
375
376
377
378static inline void kvm_machine_check(void)
379{
380#if defined(CONFIG_X86_MCE)
381 struct pt_regs regs = {
382 .cs = 3,
383 .flags = X86_EFLAGS_IF,
384 };
385
386 do_machine_check(®s);
387#endif
388}
389
390void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu);
391void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu);
392int kvm_spec_ctrl_test_value(u64 value);
393bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
394bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu);
395int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
396 struct x86_exception *e);
397int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva);
398bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type);
399
400
401
402
403
404
405#define KVM_MSR_RET_INVALID 2
406#define KVM_MSR_RET_FILTERED 3
407
408#define __cr4_reserved_bits(__cpu_has, __c) \
409({ \
410 u64 __reserved_bits = CR4_RESERVED_BITS; \
411 \
412 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
413 __reserved_bits |= X86_CR4_OSXSAVE; \
414 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
415 __reserved_bits |= X86_CR4_SMEP; \
416 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
417 __reserved_bits |= X86_CR4_SMAP; \
418 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
419 __reserved_bits |= X86_CR4_FSGSBASE; \
420 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
421 __reserved_bits |= X86_CR4_PKE; \
422 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
423 __reserved_bits |= X86_CR4_LA57; \
424 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \
425 __reserved_bits |= X86_CR4_UMIP; \
426 if (!__cpu_has(__c, X86_FEATURE_VMX)) \
427 __reserved_bits |= X86_CR4_VMXE; \
428 if (!__cpu_has(__c, X86_FEATURE_PCID)) \
429 __reserved_bits |= X86_CR4_PCIDE; \
430 __reserved_bits; \
431})
432
433int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
434 void *dst);
435int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
436 void *dst);
437int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
438 unsigned int port, void *data, unsigned int count,
439 int in);
440
441#endif
442