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10#include <linux/suspend.h>
11#include <linux/export.h>
12#include <linux/smp.h>
13#include <linux/perf_event.h>
14#include <linux/tboot.h>
15#include <linux/dmi.h>
16#include <linux/pgtable.h>
17
18#include <asm/proto.h>
19#include <asm/mtrr.h>
20#include <asm/page.h>
21#include <asm/mce.h>
22#include <asm/suspend.h>
23#include <asm/fpu/internal.h>
24#include <asm/debugreg.h>
25#include <asm/cpu.h>
26#include <asm/mmu_context.h>
27#include <asm/cpu_device_id.h>
28
29#ifdef CONFIG_X86_32
30__visible unsigned long saved_context_ebx;
31__visible unsigned long saved_context_esp, saved_context_ebp;
32__visible unsigned long saved_context_esi, saved_context_edi;
33__visible unsigned long saved_context_eflags;
34#endif
35struct saved_context saved_context;
36
37static void msr_save_context(struct saved_context *ctxt)
38{
39 struct saved_msr *msr = ctxt->saved_msrs.array;
40 struct saved_msr *end = msr + ctxt->saved_msrs.num;
41
42 while (msr < end) {
43 msr->valid = !rdmsrl_safe(msr->info.msr_no, &msr->info.reg.q);
44 msr++;
45 }
46}
47
48static void msr_restore_context(struct saved_context *ctxt)
49{
50 struct saved_msr *msr = ctxt->saved_msrs.array;
51 struct saved_msr *end = msr + ctxt->saved_msrs.num;
52
53 while (msr < end) {
54 if (msr->valid)
55 wrmsrl(msr->info.msr_no, msr->info.reg.q);
56 msr++;
57 }
58}
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74
75static void __save_processor_state(struct saved_context *ctxt)
76{
77#ifdef CONFIG_X86_32
78 mtrr_save_fixed_ranges(NULL);
79#endif
80 kernel_fpu_begin();
81
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85 store_idt(&ctxt->idt);
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92
93 ctxt->gdt_desc.size = GDT_SIZE - 1;
94 ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_rw(smp_processor_id());
95
96 store_tr(ctxt->tr);
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101
102#ifdef CONFIG_X86_32_LAZY_GS
103 savesegment(gs, ctxt->gs);
104#endif
105#ifdef CONFIG_X86_64
106 savesegment(gs, ctxt->gs);
107 savesegment(fs, ctxt->fs);
108 savesegment(ds, ctxt->ds);
109 savesegment(es, ctxt->es);
110
111 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
112 rdmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
113 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
114 mtrr_save_fixed_ranges(NULL);
115
116 rdmsrl(MSR_EFER, ctxt->efer);
117#endif
118
119
120
121
122 ctxt->cr0 = read_cr0();
123 ctxt->cr2 = read_cr2();
124 ctxt->cr3 = __read_cr3();
125 ctxt->cr4 = __read_cr4();
126 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
127 &ctxt->misc_enable);
128 msr_save_context(ctxt);
129}
130
131
132void save_processor_state(void)
133{
134 __save_processor_state(&saved_context);
135 x86_platform.save_sched_clock_state();
136}
137#ifdef CONFIG_X86_32
138EXPORT_SYMBOL(save_processor_state);
139#endif
140
141static void do_fpu_end(void)
142{
143
144
145
146 kernel_fpu_end();
147}
148
149static void fix_processor_context(void)
150{
151 int cpu = smp_processor_id();
152#ifdef CONFIG_X86_64
153 struct desc_struct *desc = get_cpu_gdt_rw(cpu);
154 tss_desc tss;
155#endif
156
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164 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
165
166#ifdef CONFIG_X86_64
167 memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
168 tss.type = 0x9;
169 write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
170
171 syscall_init();
172#else
173 if (boot_cpu_has(X86_FEATURE_SEP))
174 enable_sep_cpu();
175#endif
176 load_TR_desc();
177 load_mm_ldt(current->active_mm);
178 initialize_tlbstate_and_flush();
179
180 fpu__resume_cpu();
181
182
183 load_fixmap_gdt(cpu);
184}
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193
194static void notrace __restore_processor_state(struct saved_context *ctxt)
195{
196 struct cpuinfo_x86 *c;
197
198 if (ctxt->misc_enable_saved)
199 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
200
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203
204#ifdef CONFIG_X86_32
205 if (ctxt->cr4)
206 __write_cr4(ctxt->cr4);
207#else
208
209 wrmsrl(MSR_EFER, ctxt->efer);
210 __write_cr4(ctxt->cr4);
211#endif
212 write_cr3(ctxt->cr3);
213 write_cr2(ctxt->cr2);
214 write_cr0(ctxt->cr0);
215
216
217 load_idt(&ctxt->idt);
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222
223 loadsegment(ss, __KERNEL_DS);
224 loadsegment(ds, __USER_DS);
225 loadsegment(es, __USER_DS);
226
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230
231#ifdef CONFIG_X86_64
232 wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
233#else
234 loadsegment(fs, __KERNEL_PERCPU);
235 loadsegment(gs, __KERNEL_STACK_CANARY);
236#endif
237
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239 fix_processor_context();
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244
245#ifdef CONFIG_X86_64
246 loadsegment(ds, ctxt->es);
247 loadsegment(es, ctxt->es);
248 loadsegment(fs, ctxt->fs);
249 load_gs_index(ctxt->gs);
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256 wrmsrl(MSR_FS_BASE, ctxt->fs_base);
257 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
258#elif defined(CONFIG_X86_32_LAZY_GS)
259 loadsegment(gs, ctxt->gs);
260#endif
261
262 do_fpu_end();
263 tsc_verify_tsc_adjust(true);
264 x86_platform.restore_sched_clock_state();
265 mtrr_bp_restore();
266 perf_restore_debug_store();
267 msr_restore_context(ctxt);
268
269 c = &cpu_data(smp_processor_id());
270 if (cpu_has(c, X86_FEATURE_MSR_IA32_FEAT_CTL))
271 init_ia32_feat_ctl(c);
272}
273
274
275void notrace restore_processor_state(void)
276{
277 __restore_processor_state(&saved_context);
278}
279#ifdef CONFIG_X86_32
280EXPORT_SYMBOL(restore_processor_state);
281#endif
282
283#if defined(CONFIG_HIBERNATION) && defined(CONFIG_HOTPLUG_CPU)
284static void resume_play_dead(void)
285{
286 play_dead_common();
287 tboot_shutdown(TB_SHUTDOWN_WFS);
288 hlt_play_dead();
289}
290
291int hibernate_resume_nonboot_cpu_disable(void)
292{
293 void (*play_dead)(void) = smp_ops.play_dead;
294 int ret;
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312 ret = cpuhp_smt_enable();
313 if (ret)
314 return ret;
315 smp_ops.play_dead = resume_play_dead;
316 ret = freeze_secondary_cpus(0);
317 smp_ops.play_dead = play_dead;
318 return ret;
319}
320#endif
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326
327static int bsp_check(void)
328{
329 if (cpumask_first(cpu_online_mask) != 0) {
330 pr_warn("CPU0 is offline.\n");
331 return -ENODEV;
332 }
333
334 return 0;
335}
336
337static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
338 void *ptr)
339{
340 int ret = 0;
341
342 switch (action) {
343 case PM_SUSPEND_PREPARE:
344 case PM_HIBERNATION_PREPARE:
345 ret = bsp_check();
346 break;
347#ifdef CONFIG_DEBUG_HOTPLUG_CPU0
348 case PM_RESTORE_PREPARE:
349
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353
354 if (!cpu_online(0))
355 _debug_hotplug_cpu(0, 1);
356 break;
357 case PM_POST_RESTORE:
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381 _debug_hotplug_cpu(0, 0);
382 break;
383#endif
384 default:
385 break;
386 }
387 return notifier_from_errno(ret);
388}
389
390static int __init bsp_pm_check_init(void)
391{
392
393
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395
396
397 pm_notifier(bsp_pm_callback, -INT_MAX);
398 return 0;
399}
400
401core_initcall(bsp_pm_check_init);
402
403static int msr_build_context(const u32 *msr_id, const int num)
404{
405 struct saved_msrs *saved_msrs = &saved_context.saved_msrs;
406 struct saved_msr *msr_array;
407 int total_num;
408 int i, j;
409
410 total_num = saved_msrs->num + num;
411
412 msr_array = kmalloc_array(total_num, sizeof(struct saved_msr), GFP_KERNEL);
413 if (!msr_array) {
414 pr_err("x86/pm: Can not allocate memory to save/restore MSRs during suspend.\n");
415 return -ENOMEM;
416 }
417
418 if (saved_msrs->array) {
419
420
421
422
423 memcpy(msr_array, saved_msrs->array,
424 sizeof(struct saved_msr) * saved_msrs->num);
425
426 kfree(saved_msrs->array);
427 }
428
429 for (i = saved_msrs->num, j = 0; i < total_num; i++, j++) {
430 msr_array[i].info.msr_no = msr_id[j];
431 msr_array[i].valid = false;
432 msr_array[i].info.reg.q = 0;
433 }
434 saved_msrs->num = total_num;
435 saved_msrs->array = msr_array;
436
437 return 0;
438}
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450static int msr_initialize_bdw(const struct dmi_system_id *d)
451{
452
453 u32 bdw_msr_id[] = { MSR_IA32_THERM_CONTROL };
454
455 pr_info("x86/pm: %s detected, MSR saving is needed during suspending.\n", d->ident);
456 return msr_build_context(bdw_msr_id, ARRAY_SIZE(bdw_msr_id));
457}
458
459static const struct dmi_system_id msr_save_dmi_table[] = {
460 {
461 .callback = msr_initialize_bdw,
462 .ident = "BROADWELL BDX_EP",
463 .matches = {
464 DMI_MATCH(DMI_PRODUCT_NAME, "GRANTLEY"),
465 DMI_MATCH(DMI_PRODUCT_VERSION, "E63448-400"),
466 },
467 },
468 {}
469};
470
471static int msr_save_cpuid_features(const struct x86_cpu_id *c)
472{
473 u32 cpuid_msr_id[] = {
474 MSR_AMD64_CPUID_FN_1,
475 };
476
477 pr_info("x86/pm: family %#hx cpu detected, MSR saving is needed during suspending.\n",
478 c->family);
479
480 return msr_build_context(cpuid_msr_id, ARRAY_SIZE(cpuid_msr_id));
481}
482
483static const struct x86_cpu_id msr_save_cpu_table[] = {
484 X86_MATCH_VENDOR_FAM(AMD, 0x15, &msr_save_cpuid_features),
485 X86_MATCH_VENDOR_FAM(AMD, 0x16, &msr_save_cpuid_features),
486 {}
487};
488
489typedef int (*pm_cpu_match_t)(const struct x86_cpu_id *);
490static int pm_cpu_check(const struct x86_cpu_id *c)
491{
492 const struct x86_cpu_id *m;
493 int ret = 0;
494
495 m = x86_match_cpu(msr_save_cpu_table);
496 if (m) {
497 pm_cpu_match_t fn;
498
499 fn = (pm_cpu_match_t)m->driver_data;
500 ret = fn(m);
501 }
502
503 return ret;
504}
505
506static int pm_check_save_msr(void)
507{
508 dmi_check_system(msr_save_dmi_table);
509 pm_cpu_check(msr_save_cpu_table);
510
511 return 0;
512}
513
514device_initcall(pm_check_save_msr);
515