1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright 2016 Icenowy Zheng <icenowy@aosc.io> 4 */ 5 6#ifndef _CCU_SUN50I_H6_H_ 7#define _CCU_SUN50I_H6_H_ 8 9#include <dt-bindings/clock/sun50i-h6-ccu.h> 10#include <dt-bindings/reset/sun50i-h6-ccu.h> 11 12#define CLK_OSC12M 0 13#define CLK_PLL_CPUX 1 14#define CLK_PLL_DDR0 2 15 16/* PLL_PERIPH0 exported for PRCM */ 17 18#define CLK_PLL_PERIPH0_2X 4 19#define CLK_PLL_PERIPH0_4X 5 20#define CLK_PLL_PERIPH1 6 21#define CLK_PLL_PERIPH1_2X 7 22#define CLK_PLL_PERIPH1_4X 8 23#define CLK_PLL_GPU 9 24#define CLK_PLL_VIDEO0 10 25#define CLK_PLL_VIDEO0_4X 11 26#define CLK_PLL_VIDEO1 12 27#define CLK_PLL_VIDEO1_4X 13 28#define CLK_PLL_VE 14 29#define CLK_PLL_DE 15 30#define CLK_PLL_HSIC 16 31#define CLK_PLL_AUDIO_BASE 17 32#define CLK_PLL_AUDIO 18 33#define CLK_PLL_AUDIO_2X 19 34#define CLK_PLL_AUDIO_4X 20 35 36/* CPUX clock exported for DVFS */ 37 38#define CLK_AXI 22 39#define CLK_CPUX_APB 23 40#define CLK_PSI_AHB1_AHB2 24 41#define CLK_AHB3 25 42 43/* APB1 clock exported for PIO */ 44 45#define CLK_APB2 27 46#define CLK_MBUS 28 47 48/* All module clocks and bus gates are exported except DRAM */ 49 50#define CLK_DRAM 52 51 52#define CLK_BUS_DRAM 60 53 54#define CLK_NUMBER (CLK_BUS_HDCP + 1) 55 56#endif /* _CCU_SUN50I_H6_H_ */ 57