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24#ifndef __AMDGPU_IRQ_H__
25#define __AMDGPU_IRQ_H__
26
27#include <linux/irqdomain.h>
28#include "soc15_ih_clientid.h"
29#include "amdgpu_ih.h"
30
31#define AMDGPU_MAX_IRQ_SRC_ID 0x100
32#define AMDGPU_MAX_IRQ_CLIENT_ID 0x100
33
34#define AMDGPU_IRQ_CLIENTID_LEGACY 0
35#define AMDGPU_IRQ_CLIENTID_MAX SOC15_IH_CLIENTID_MAX
36
37#define AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW 4
38
39struct amdgpu_device;
40
41enum amdgpu_interrupt_state {
42 AMDGPU_IRQ_STATE_DISABLE,
43 AMDGPU_IRQ_STATE_ENABLE,
44};
45
46struct amdgpu_iv_entry {
47 struct amdgpu_ih_ring *ih;
48 unsigned client_id;
49 unsigned src_id;
50 unsigned ring_id;
51 unsigned vmid;
52 unsigned vmid_src;
53 uint64_t timestamp;
54 unsigned timestamp_src;
55 unsigned pasid;
56 unsigned pasid_src;
57 unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW];
58 const uint32_t *iv_entry;
59};
60
61struct amdgpu_irq_src {
62 unsigned num_types;
63 atomic_t *enabled_types;
64 const struct amdgpu_irq_src_funcs *funcs;
65 void *data;
66};
67
68struct amdgpu_irq_client {
69 struct amdgpu_irq_src **sources;
70};
71
72
73struct amdgpu_irq_src_funcs {
74 int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
75 unsigned type, enum amdgpu_interrupt_state state);
76
77 int (*process)(struct amdgpu_device *adev,
78 struct amdgpu_irq_src *source,
79 struct amdgpu_iv_entry *entry);
80};
81
82struct amdgpu_irq {
83 bool installed;
84 spinlock_t lock;
85
86 struct amdgpu_irq_client client[AMDGPU_IRQ_CLIENTID_MAX];
87
88
89 bool msi_enabled;
90
91
92 struct amdgpu_ih_ring ih, ih1, ih2, ih_soft;
93 const struct amdgpu_ih_funcs *ih_funcs;
94 struct work_struct ih1_work, ih2_work, ih_soft_work;
95 struct amdgpu_irq_src self_irq;
96
97
98 struct irq_domain *domain;
99 unsigned virq[AMDGPU_MAX_IRQ_SRC_ID];
100 uint32_t srbm_soft_reset;
101};
102
103void amdgpu_irq_disable_all(struct amdgpu_device *adev);
104irqreturn_t amdgpu_irq_handler(int irq, void *arg);
105
106int amdgpu_irq_init(struct amdgpu_device *adev);
107void amdgpu_irq_fini(struct amdgpu_device *adev);
108int amdgpu_irq_add_id(struct amdgpu_device *adev,
109 unsigned client_id, unsigned src_id,
110 struct amdgpu_irq_src *source);
111void amdgpu_irq_dispatch(struct amdgpu_device *adev,
112 struct amdgpu_ih_ring *ih);
113void amdgpu_irq_delegate(struct amdgpu_device *adev,
114 struct amdgpu_iv_entry *entry,
115 unsigned int num_dw);
116int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
117 unsigned type);
118int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
119 unsigned type);
120int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
121 unsigned type);
122bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
123 unsigned type);
124void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev);
125
126int amdgpu_irq_add_domain(struct amdgpu_device *adev);
127void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
128unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);
129
130#endif
131