LXR linux/drivers/gpu/drm/amd/amdgpu/athub_v2

   1/*
   2 * Copyright 2019 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#include "amdgpu.h"
  25#include "athub_v2_0.h"
  26
  27#include "athub/athub_2_0_0_offset.h"
  28#include "athub/athub_2_0_0_sh_mask.h"
  29#include "athub/athub_2_0_0_default.h"
  30#include "navi10_enum.h"
  31
  32#include "soc15_common.h"
  33
  34static void
  35athub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
  36                                            bool enable)
  37{
  38        uint32_t def, data;
  39
  40        def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
  41
  42        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
  43                data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
  44        else
  45                data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
  46
  47        if (def != data)
  48                WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
  49}
  50
  51static void
  52athub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
  53                                           bool enable)
  54{
  55        uint32_t def, data;
  56
  57        def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
  58
  59        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
  60            (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
  61                data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
  62        else
  63                data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
  64
  65        if (def != data)
  66                WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
  67}
  68
  69int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
  70                               enum amd_clockgating_state state)
  71{
  72        if (amdgpu_sriov_vf(adev))
  73                return 0;
  74
  75        switch (adev->asic_type) {
  76        case CHIP_NAVI10:
  77        case CHIP_NAVI14:
  78        case CHIP_NAVI12:
  79                athub_v2_0_update_medium_grain_clock_gating(adev,
  80                                state == AMD_CG_STATE_GATE);
  81                athub_v2_0_update_medium_grain_light_sleep(adev,
  82                                state == AMD_CG_STATE_GATE);
  83                break;
  84        default:
  85                break;
  86        }
  87
  88        return 0;
  89}
  90
  91void athub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
  92{
  93        int data;
  94
  95        /* AMD_CG_SUPPORT_ATHUB_MGCG */
  96        data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
  97        if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
  98                *flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
  99
 100        /* AMD_CG_SUPPORT_ATHUB_LS */
 101        if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
 102                *flags |= AMD_CG_SUPPORT_ATHUB_LS;
 103}
 104