LXR linux/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory

   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include "dm_services.h"
  27#include "include/gpio_types.h"
  28#include "../hw_factory.h"
  29
  30#include "hw_factory_dce80.h"
  31
  32#include "../hw_gpio.h"
  33#include "../hw_ddc.h"
  34#include "../hw_hpd.h"
  35#include "../hw_generic.h"
  36
  37#include "dce/dce_8_0_d.h"
  38#include "dce/dce_8_0_sh_mask.h"
  39
  40
  41#define REG(reg_name)\
  42                mm ## reg_name
  43
  44#include "reg_helper.h"
  45#include "../hpd_regs.h"
  46
  47#define HPD_REG_LIST_DCE8(id) \
  48        HPD_GPIO_REG_LIST(id), \
  49        .int_status = mmDC_HPD ## id ## _INT_STATUS,\
  50        .toggle_filt_cntl = mmDC_HPD ## id ## _TOGGLE_FILT_CNTL
  51
  52#define HPD_MASK_SH_LIST_DCE8(mask_sh) \
  53                .DC_HPD_SENSE_DELAYED = DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED ## mask_sh,\
  54                .DC_HPD_SENSE = DC_HPD1_INT_STATUS__DC_HPD1_SENSE ## mask_sh,\
  55                .DC_HPD_CONNECT_INT_DELAY = DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY ## mask_sh,\
  56                .DC_HPD_DISCONNECT_INT_DELAY = DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY ## mask_sh
  57
  58#define hpd_regs(id) \
  59{\
  60        HPD_REG_LIST_DCE8(id)\
  61}
  62
  63static const struct hpd_registers hpd_regs[] = {
  64        hpd_regs(1),
  65        hpd_regs(2),
  66        hpd_regs(3),
  67        hpd_regs(4),
  68        hpd_regs(5),
  69        hpd_regs(6)
  70};
  71
  72static const struct hpd_sh_mask hpd_shift = {
  73                HPD_MASK_SH_LIST_DCE8(__SHIFT)
  74};
  75
  76static const struct hpd_sh_mask hpd_mask = {
  77                HPD_MASK_SH_LIST_DCE8(_MASK)
  78};
  79
  80#include "../ddc_regs.h"
  81
  82 /* set field name */
  83#define SF_DDC(reg_name, field_name, post_fix)\
  84        .field_name = reg_name ## __ ## field_name ## post_fix
  85
  86static const struct ddc_registers ddc_data_regs[] = {
  87        ddc_data_regs(1),
  88        ddc_data_regs(2),
  89        ddc_data_regs(3),
  90        ddc_data_regs(4),
  91        ddc_data_regs(5),
  92        ddc_data_regs(6),
  93        ddc_vga_data_regs,
  94        ddc_i2c_data_regs
  95};
  96
  97static const struct ddc_registers ddc_clk_regs[] = {
  98        ddc_clk_regs(1),
  99        ddc_clk_regs(2),
 100        ddc_clk_regs(3),
 101        ddc_clk_regs(4),
 102        ddc_clk_regs(5),
 103        ddc_clk_regs(6),
 104        ddc_vga_clk_regs,
 105        ddc_i2c_clk_regs
 106};
 107
 108static const struct ddc_sh_mask ddc_shift = {
 109                DDC_MASK_SH_LIST(__SHIFT)
 110};
 111
 112static const struct ddc_sh_mask ddc_mask = {
 113                DDC_MASK_SH_LIST(_MASK)
 114};
 115
 116static void define_ddc_registers(
 117                struct hw_gpio_pin *pin,
 118                uint32_t en)
 119{
 120        struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
 121
 122        switch (pin->id) {
 123        case GPIO_ID_DDC_DATA:
 124                ddc->regs = &ddc_data_regs[en];
 125                ddc->base.regs = &ddc_data_regs[en].gpio;
 126                break;
 127        case GPIO_ID_DDC_CLOCK:
 128                ddc->regs = &ddc_clk_regs[en];
 129                ddc->base.regs = &ddc_clk_regs[en].gpio;
 130                break;
 131        default:
 132                ASSERT_CRITICAL(false);
 133                return;
 134        }
 135
 136        ddc->shifts = &ddc_shift;
 137        ddc->masks = &ddc_mask;
 138
 139}
 140
 141static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
 142{
 143        struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
 144
 145        hpd->regs = &hpd_regs[en];
 146        hpd->shifts = &hpd_shift;
 147        hpd->masks = &hpd_mask;
 148        hpd->base.regs = &hpd_regs[en].gpio;
 149}
 150
 151static const struct hw_factory_funcs funcs = {
 152        .init_ddc_data = dal_hw_ddc_init,
 153        .init_generic = NULL,
 154        .init_hpd = dal_hw_hpd_init,
 155        .get_ddc_pin = dal_hw_ddc_get_pin,
 156        .get_hpd_pin = dal_hw_hpd_get_pin,
 157        .get_generic_pin = NULL,
 158        .define_hpd_registers = define_hpd_registers,
 159        .define_ddc_registers = define_ddc_registers
 160};
 161
 162void dal_hw_factory_dce80_init(
 163        struct hw_factory *factory)
 164{
 165        factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
 166        factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
 167        factory->number_of_pins[GPIO_ID_GENERIC] = 7;
 168        factory->number_of_pins[GPIO_ID_HPD] = 6;
 169        factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
 170        factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
 171        factory->number_of_pins[GPIO_ID_SYNC] = 2;
 172        factory->number_of_pins[GPIO_ID_GSL] = 4;
 173
 174        factory->funcs = &funcs;
 175}
 176