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24#define SWSMU_CODE_LAYER_L2
25
26#include "amdgpu.h"
27#include "amdgpu_smu.h"
28#include "smu_v12_0_ppsmc.h"
29#include "smu12_driver_if.h"
30#include "smu_v12_0.h"
31#include "renoir_ppt.h"
32#include "smu_cmn.h"
33
34
35
36
37
38
39#undef pr_err
40#undef pr_warn
41#undef pr_info
42#undef pr_debug
43
44static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
45 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
46 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
47 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
48 MSG_MAP(PowerUpGfx, PPSMC_MSG_PowerUpGfx, 1),
49 MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1),
50 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1),
51 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1),
52 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1),
53 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
54 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
55 MSG_MAP(PowerDownSdma, PPSMC_MSG_PowerDownSdma, 1),
56 MSG_MAP(PowerUpSdma, PPSMC_MSG_PowerUpSdma, 1),
57 MSG_MAP(SetHardMinIspclkByFreq, PPSMC_MSG_SetHardMinIspclkByFreq, 1),
58 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
59 MSG_MAP(Spare1, PPSMC_MSG_spare1, 1),
60 MSG_MAP(Spare2, PPSMC_MSG_spare2, 1),
61 MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch, 1),
62 MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1),
63 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1),
64 MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy, 1),
65 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1),
66 MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount, 1),
67 MSG_MAP(QueryPowerLimit, PPSMC_MSG_QueryPowerLimit, 1),
68 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
69 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
70 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
71 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
72 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
73 MSG_MAP(SetGfxclkOverdriveByFreqVid, PPSMC_MSG_SetGfxclkOverdriveByFreqVid, 1),
74 MSG_MAP(SetHardMinDcfclkByFreq, PPSMC_MSG_SetHardMinDcfclkByFreq, 1),
75 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1),
76 MSG_MAP(ControlIgpuATS, PPSMC_MSG_ControlIgpuATS, 1),
77 MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1),
78 MSG_MAP(SetMinDeepSleepDcfclk, PPSMC_MSG_SetMinDeepSleepDcfclk, 1),
79 MSG_MAP(ForcePowerDownGfx, PPSMC_MSG_ForcePowerDownGfx, 1),
80 MSG_MAP(SetPhyclkVoltageByFreq, PPSMC_MSG_SetPhyclkVoltageByFreq, 1),
81 MSG_MAP(SetDppclkVoltageByFreq, PPSMC_MSG_SetDppclkVoltageByFreq, 1),
82 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
83 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1),
84 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
85 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1),
86 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxclkFrequency, 1),
87 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxclkFrequency, 1),
88 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 1),
89 MSG_MAP(SetGfxCGPG, PPSMC_MSG_SetGfxCGPG, 1),
90 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
91 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
92 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
93 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1),
94 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
95 MSG_MAP(PowerGateMmHub, PPSMC_MSG_PowerGateMmHub, 1),
96 MSG_MAP(UpdatePmeRestore, PPSMC_MSG_UpdatePmeRestore, 1),
97 MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1),
98 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1),
99 MSG_MAP(ForceGfxContentSave, PPSMC_MSG_ForceGfxContentSave, 1),
100 MSG_MAP(EnableTmdp48MHzRefclkPwrDown, PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1),
101 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
102 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
103 MSG_MAP(PowerGateAtHub, PPSMC_MSG_PowerGateAtHub, 1),
104 MSG_MAP(SetSoftMinJpeg, PPSMC_MSG_SetSoftMinJpeg, 1),
105 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1),
106};
107
108static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = {
109 CLK_MAP(GFXCLK, CLOCK_GFXCLK),
110 CLK_MAP(SCLK, CLOCK_GFXCLK),
111 CLK_MAP(SOCCLK, CLOCK_SOCCLK),
112 CLK_MAP(UCLK, CLOCK_FCLK),
113 CLK_MAP(MCLK, CLOCK_FCLK),
114};
115
116static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = {
117 TAB_MAP_VALID(WATERMARKS),
118 TAB_MAP_INVALID(CUSTOM_DPM),
119 TAB_MAP_VALID(DPMCLOCKS),
120 TAB_MAP_VALID(SMU_METRICS),
121};
122
123static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
124 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
125 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
126 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
127 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
128 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
129};
130
131static int renoir_init_smc_tables(struct smu_context *smu)
132{
133 struct smu_table_context *smu_table = &smu->smu_table;
134 struct smu_table *tables = smu_table->tables;
135
136 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
137 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
138 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
139 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
140 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
141 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
142
143 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
144 if (!smu_table->clocks_table)
145 goto err0_out;
146
147 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
148 if (!smu_table->metrics_table)
149 goto err1_out;
150 smu_table->metrics_time = 0;
151
152 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
153 if (!smu_table->watermarks_table)
154 goto err2_out;
155
156 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0);
157 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
158 if (!smu_table->gpu_metrics_table)
159 goto err3_out;
160
161 return 0;
162
163err3_out:
164 kfree(smu_table->watermarks_table);
165err2_out:
166 kfree(smu_table->metrics_table);
167err1_out:
168 kfree(smu_table->clocks_table);
169err0_out:
170 return -ENOMEM;
171}
172
173
174
175
176
177static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
178 uint32_t dpm_level, uint32_t *freq)
179{
180 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
181
182 if (!clk_table || clk_type >= SMU_CLK_COUNT)
183 return -EINVAL;
184
185 switch (clk_type) {
186 case SMU_SOCCLK:
187 if (dpm_level >= NUM_SOCCLK_DPM_LEVELS)
188 return -EINVAL;
189 *freq = clk_table->SocClocks[dpm_level].Freq;
190 break;
191 case SMU_UCLK:
192 case SMU_MCLK:
193 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
194 return -EINVAL;
195 *freq = clk_table->FClocks[dpm_level].Freq;
196 break;
197 case SMU_DCEFCLK:
198 if (dpm_level >= NUM_DCFCLK_DPM_LEVELS)
199 return -EINVAL;
200 *freq = clk_table->DcfClocks[dpm_level].Freq;
201 break;
202 case SMU_FCLK:
203 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
204 return -EINVAL;
205 *freq = clk_table->FClocks[dpm_level].Freq;
206 break;
207 default:
208 return -EINVAL;
209 }
210
211 return 0;
212}
213
214static int renoir_get_profiling_clk_mask(struct smu_context *smu,
215 enum amd_dpm_forced_level level,
216 uint32_t *sclk_mask,
217 uint32_t *mclk_mask,
218 uint32_t *soc_mask)
219{
220
221 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
222 if (sclk_mask)
223 *sclk_mask = 0;
224 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
225 if (mclk_mask)
226
227 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
228 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
229 if(sclk_mask)
230
231 *sclk_mask = 3 - 1;
232
233 if(mclk_mask)
234
235 *mclk_mask = 0;
236
237 if(soc_mask)
238 *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
239 }
240
241 return 0;
242}
243
244static int renoir_get_dpm_ultimate_freq(struct smu_context *smu,
245 enum smu_clk_type clk_type,
246 uint32_t *min,
247 uint32_t *max)
248{
249 int ret = 0;
250 uint32_t mclk_mask, soc_mask;
251 uint32_t clock_limit;
252
253 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
254 switch (clk_type) {
255 case SMU_MCLK:
256 case SMU_UCLK:
257 clock_limit = smu->smu_table.boot_values.uclk;
258 break;
259 case SMU_GFXCLK:
260 case SMU_SCLK:
261 clock_limit = smu->smu_table.boot_values.gfxclk;
262 break;
263 case SMU_SOCCLK:
264 clock_limit = smu->smu_table.boot_values.socclk;
265 break;
266 default:
267 clock_limit = 0;
268 break;
269 }
270
271
272 if (min)
273 *min = clock_limit / 100;
274 if (max)
275 *max = clock_limit / 100;
276
277 return 0;
278 }
279
280 if (max) {
281 ret = renoir_get_profiling_clk_mask(smu,
282 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
283 NULL,
284 &mclk_mask,
285 &soc_mask);
286 if (ret)
287 goto failed;
288
289 switch (clk_type) {
290 case SMU_GFXCLK:
291 case SMU_SCLK:
292 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);
293 if (ret) {
294 dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");
295 goto failed;
296 }
297 break;
298 case SMU_UCLK:
299 case SMU_FCLK:
300 case SMU_MCLK:
301 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
302 if (ret)
303 goto failed;
304 break;
305 case SMU_SOCCLK:
306 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
307 if (ret)
308 goto failed;
309 break;
310 default:
311 ret = -EINVAL;
312 goto failed;
313 }
314 }
315
316 if (min) {
317 switch (clk_type) {
318 case SMU_GFXCLK:
319 case SMU_SCLK:
320 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);
321 if (ret) {
322 dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");
323 goto failed;
324 }
325 break;
326 case SMU_UCLK:
327 case SMU_FCLK:
328 case SMU_MCLK:
329 ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min);
330 if (ret)
331 goto failed;
332 break;
333 case SMU_SOCCLK:
334 ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);
335 if (ret)
336 goto failed;
337 break;
338 default:
339 ret = -EINVAL;
340 goto failed;
341 }
342 }
343failed:
344 return ret;
345}
346
347static int renoir_print_clk_levels(struct smu_context *smu,
348 enum smu_clk_type clk_type, char *buf)
349{
350 int i, size = 0, ret = 0;
351 uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
352 SmuMetrics_t metrics;
353 bool cur_value_match_level = false;
354
355 memset(&metrics, 0, sizeof(metrics));
356
357 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
358 if (ret)
359 return ret;
360
361 switch (clk_type) {
362 case SMU_GFXCLK:
363 case SMU_SCLK:
364
365 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
366 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);
367 if (!ret) {
368
369 if (cur_value == max)
370 i = 2;
371 else if (cur_value == min)
372 i = 0;
373 else
374 i = 1;
375
376 size += sprintf(buf + size, "0: %uMhz %s\n", min,
377 i == 0 ? "*" : "");
378 size += sprintf(buf + size, "1: %uMhz %s\n",
379 i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK,
380 i == 1 ? "*" : "");
381 size += sprintf(buf + size, "2: %uMhz %s\n", max,
382 i == 2 ? "*" : "");
383 }
384 return size;
385 case SMU_SOCCLK:
386 count = NUM_SOCCLK_DPM_LEVELS;
387 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK];
388 break;
389 case SMU_MCLK:
390 count = NUM_MEMCLK_DPM_LEVELS;
391 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
392 break;
393 case SMU_DCEFCLK:
394 count = NUM_DCFCLK_DPM_LEVELS;
395 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK];
396 break;
397 case SMU_FCLK:
398 count = NUM_FCLK_DPM_LEVELS;
399 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
400 break;
401 default:
402 return -EINVAL;
403 }
404
405 for (i = 0; i < count; i++) {
406 ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value);
407 if (ret)
408 return ret;
409 if (!value)
410 continue;
411 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
412 cur_value == value ? "*" : "");
413 if (cur_value == value)
414 cur_value_match_level = true;
415 }
416
417 if (!cur_value_match_level)
418 size += sprintf(buf + size, " %uMhz *\n", cur_value);
419
420 return size;
421}
422
423static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu)
424{
425 enum amd_pm_state_type pm_type;
426 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
427
428 if (!smu_dpm_ctx->dpm_context ||
429 !smu_dpm_ctx->dpm_current_power_state)
430 return -EINVAL;
431
432 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
433 case SMU_STATE_UI_LABEL_BATTERY:
434 pm_type = POWER_STATE_TYPE_BATTERY;
435 break;
436 case SMU_STATE_UI_LABEL_BALLANCED:
437 pm_type = POWER_STATE_TYPE_BALANCED;
438 break;
439 case SMU_STATE_UI_LABEL_PERFORMANCE:
440 pm_type = POWER_STATE_TYPE_PERFORMANCE;
441 break;
442 default:
443 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
444 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
445 else
446 pm_type = POWER_STATE_TYPE_DEFAULT;
447 break;
448 }
449
450 return pm_type;
451}
452
453static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
454{
455 int ret = 0;
456
457 if (enable) {
458
459 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
460 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
461 if (ret)
462 return ret;
463 }
464 } else {
465 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
466 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
467 if (ret)
468 return ret;
469 }
470 }
471
472 return ret;
473}
474
475static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
476{
477 int ret = 0;
478
479 if (enable) {
480 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
481 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
482 if (ret)
483 return ret;
484 }
485 } else {
486 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
487 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
488 if (ret)
489 return ret;
490 }
491 }
492
493 return ret;
494}
495
496static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
497{
498 int ret = 0, i = 0;
499 uint32_t min_freq, max_freq, force_freq;
500 enum smu_clk_type clk_type;
501
502 enum smu_clk_type clks[] = {
503 SMU_GFXCLK,
504 SMU_MCLK,
505 SMU_SOCCLK,
506 };
507
508 for (i = 0; i < ARRAY_SIZE(clks); i++) {
509 clk_type = clks[i];
510 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
511 if (ret)
512 return ret;
513
514 force_freq = highest ? max_freq : min_freq;
515 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
516 if (ret)
517 return ret;
518 }
519
520 return ret;
521}
522
523static int renoir_unforce_dpm_levels(struct smu_context *smu) {
524
525 int ret = 0, i = 0;
526 uint32_t min_freq, max_freq;
527 enum smu_clk_type clk_type;
528
529 struct clk_feature_map {
530 enum smu_clk_type clk_type;
531 uint32_t feature;
532 } clk_feature_map[] = {
533 {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
534 {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT},
535 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
536 };
537
538 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
539 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
540 continue;
541
542 clk_type = clk_feature_map[i].clk_type;
543
544 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
545 if (ret)
546 return ret;
547
548 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
549 if (ret)
550 return ret;
551 }
552
553 return ret;
554}
555
556
557
558
559static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
560{
561 DpmClocks_t *table = smu->smu_table.clocks_table;
562 int i;
563
564 if (!clock_table || !table)
565 return -EINVAL;
566
567 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) {
568 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
569 clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol;
570 }
571
572 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
573 clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
574 clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol;
575 }
576
577 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
578 clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
579 clock_table->FClocks[i].Vol = table->FClocks[i].Vol;
580 }
581
582 for (i = 0; i< NUM_MEMCLK_DPM_LEVELS; i++) {
583 clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq;
584 clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
585 }
586
587 return 0;
588}
589
590static int renoir_force_clk_levels(struct smu_context *smu,
591 enum smu_clk_type clk_type, uint32_t mask)
592{
593
594 int ret = 0 ;
595 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
596
597 soft_min_level = mask ? (ffs(mask) - 1) : 0;
598 soft_max_level = mask ? (fls(mask) - 1) : 0;
599
600 switch (clk_type) {
601 case SMU_GFXCLK:
602 case SMU_SCLK:
603 if (soft_min_level > 2 || soft_max_level > 2) {
604 dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n");
605 return -EINVAL;
606 }
607
608 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);
609 if (ret)
610 return ret;
611 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
612 soft_max_level == 0 ? min_freq :
613 soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq,
614 NULL);
615 if (ret)
616 return ret;
617 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
618 soft_min_level == 2 ? max_freq :
619 soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq,
620 NULL);
621 if (ret)
622 return ret;
623 break;
624 case SMU_SOCCLK:
625 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
626 if (ret)
627 return ret;
628 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
629 if (ret)
630 return ret;
631 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL);
632 if (ret)
633 return ret;
634 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL);
635 if (ret)
636 return ret;
637 break;
638 case SMU_MCLK:
639 case SMU_FCLK:
640 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
641 if (ret)
642 return ret;
643 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
644 if (ret)
645 return ret;
646 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL);
647 if (ret)
648 return ret;
649 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL);
650 if (ret)
651 return ret;
652 break;
653 default:
654 break;
655 }
656
657 return ret;
658}
659
660static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
661{
662 int workload_type, ret;
663 uint32_t profile_mode = input[size];
664
665 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
666 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
667 return -EINVAL;
668 }
669
670
671 workload_type = smu_cmn_to_asic_specific_index(smu,
672 CMN2ASIC_MAPPING_WORKLOAD,
673 profile_mode);
674 if (workload_type < 0) {
675
676
677
678
679 dev_err_once(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode);
680 return -EINVAL;
681 }
682
683 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
684 1 << workload_type,
685 NULL);
686 if (ret) {
687 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
688 return ret;
689 }
690
691 smu->power_profile_mode = profile_mode;
692
693 return 0;
694}
695
696static int renoir_set_peak_clock_by_device(struct smu_context *smu)
697{
698 int ret = 0;
699 uint32_t sclk_freq = 0, uclk_freq = 0;
700
701 ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq);
702 if (ret)
703 return ret;
704
705 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
706 if (ret)
707 return ret;
708
709 ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq);
710 if (ret)
711 return ret;
712
713 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
714 if (ret)
715 return ret;
716
717 return ret;
718}
719
720static int renoir_set_performance_level(struct smu_context *smu,
721 enum amd_dpm_forced_level level)
722{
723 int ret = 0;
724 uint32_t sclk_mask, mclk_mask, soc_mask;
725
726 switch (level) {
727 case AMD_DPM_FORCED_LEVEL_HIGH:
728 ret = renoir_force_dpm_limit_value(smu, true);
729 break;
730 case AMD_DPM_FORCED_LEVEL_LOW:
731 ret = renoir_force_dpm_limit_value(smu, false);
732 break;
733 case AMD_DPM_FORCED_LEVEL_AUTO:
734 ret = renoir_unforce_dpm_levels(smu);
735 break;
736 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
737 ret = smu_cmn_send_smc_msg_with_param(smu,
738 SMU_MSG_SetHardMinGfxClk,
739 RENOIR_UMD_PSTATE_GFXCLK,
740 NULL);
741 if (ret)
742 return ret;
743 ret = smu_cmn_send_smc_msg_with_param(smu,
744 SMU_MSG_SetHardMinFclkByFreq,
745 RENOIR_UMD_PSTATE_FCLK,
746 NULL);
747 if (ret)
748 return ret;
749 ret = smu_cmn_send_smc_msg_with_param(smu,
750 SMU_MSG_SetHardMinSocclkByFreq,
751 RENOIR_UMD_PSTATE_SOCCLK,
752 NULL);
753 if (ret)
754 return ret;
755 ret = smu_cmn_send_smc_msg_with_param(smu,
756 SMU_MSG_SetHardMinVcn,
757 RENOIR_UMD_PSTATE_VCNCLK,
758 NULL);
759 if (ret)
760 return ret;
761
762 ret = smu_cmn_send_smc_msg_with_param(smu,
763 SMU_MSG_SetSoftMaxGfxClk,
764 RENOIR_UMD_PSTATE_GFXCLK,
765 NULL);
766 if (ret)
767 return ret;
768 ret = smu_cmn_send_smc_msg_with_param(smu,
769 SMU_MSG_SetSoftMaxFclkByFreq,
770 RENOIR_UMD_PSTATE_FCLK,
771 NULL);
772 if (ret)
773 return ret;
774 ret = smu_cmn_send_smc_msg_with_param(smu,
775 SMU_MSG_SetSoftMaxSocclkByFreq,
776 RENOIR_UMD_PSTATE_SOCCLK,
777 NULL);
778 if (ret)
779 return ret;
780 ret = smu_cmn_send_smc_msg_with_param(smu,
781 SMU_MSG_SetSoftMaxVcn,
782 RENOIR_UMD_PSTATE_VCNCLK,
783 NULL);
784 if (ret)
785 return ret;
786 break;
787 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
788 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
789 ret = renoir_get_profiling_clk_mask(smu, level,
790 &sclk_mask,
791 &mclk_mask,
792 &soc_mask);
793 if (ret)
794 return ret;
795 renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
796 renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
797 renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
798 break;
799 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
800 ret = renoir_set_peak_clock_by_device(smu);
801 break;
802 case AMD_DPM_FORCED_LEVEL_MANUAL:
803 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
804 default:
805 break;
806 }
807 return ret;
808}
809
810
811
812
813static int renoir_set_watermarks_table(
814 struct smu_context *smu,
815 struct pp_smu_wm_range_sets *clock_ranges)
816{
817 Watermarks_t *table = smu->smu_table.watermarks_table;
818 int ret = 0;
819 int i;
820
821 if (clock_ranges) {
822 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
823 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
824 return -EINVAL;
825
826
827 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
828 table->WatermarkRow[WM_DCFCLK][i].MinClock =
829 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
830 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
831 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
832 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
833 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
834 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
835 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
836
837 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
838 clock_ranges->reader_wm_sets[i].wm_inst;
839 table->WatermarkRow[WM_DCFCLK][i].WmType =
840 clock_ranges->reader_wm_sets[i].wm_type;
841 }
842
843 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
844 table->WatermarkRow[WM_SOCCLK][i].MinClock =
845 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
846 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
847 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
848 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
849 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
850 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
851 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
852
853 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
854 clock_ranges->writer_wm_sets[i].wm_inst;
855 table->WatermarkRow[WM_SOCCLK][i].WmType =
856 clock_ranges->writer_wm_sets[i].wm_type;
857 }
858
859 smu->watermarks_bitmap |= WATERMARKS_EXIST;
860 }
861
862
863 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
864 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
865 ret = smu_cmn_write_watermarks_table(smu);
866 if (ret) {
867 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
868 return ret;
869 }
870 smu->watermarks_bitmap |= WATERMARKS_LOADED;
871 }
872
873 return 0;
874}
875
876static int renoir_get_power_profile_mode(struct smu_context *smu,
877 char *buf)
878{
879 static const char *profile_name[] = {
880 "BOOTUP_DEFAULT",
881 "3D_FULL_SCREEN",
882 "POWER_SAVING",
883 "VIDEO",
884 "VR",
885 "COMPUTE",
886 "CUSTOM"};
887 uint32_t i, size = 0;
888 int16_t workload_type = 0;
889
890 if (!buf)
891 return -EINVAL;
892
893 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
894
895
896
897
898 workload_type = smu_cmn_to_asic_specific_index(smu,
899 CMN2ASIC_MAPPING_WORKLOAD,
900 i);
901 if (workload_type < 0)
902 continue;
903
904 size += sprintf(buf + size, "%2d %14s%s\n",
905 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
906 }
907
908 return size;
909}
910
911static int renoir_get_smu_metrics_data(struct smu_context *smu,
912 MetricsMember_t member,
913 uint32_t *value)
914{
915 struct smu_table_context *smu_table = &smu->smu_table;
916
917 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
918 int ret = 0;
919
920 mutex_lock(&smu->metrics_lock);
921
922 ret = smu_cmn_get_metrics_table_locked(smu,
923 NULL,
924 false);
925 if (ret) {
926 mutex_unlock(&smu->metrics_lock);
927 return ret;
928 }
929
930 switch (member) {
931 case METRICS_AVERAGE_GFXCLK:
932 *value = metrics->ClockFrequency[CLOCK_GFXCLK];
933 break;
934 case METRICS_AVERAGE_SOCCLK:
935 *value = metrics->ClockFrequency[CLOCK_SOCCLK];
936 break;
937 case METRICS_AVERAGE_UCLK:
938 *value = metrics->ClockFrequency[CLOCK_FCLK];
939 break;
940 case METRICS_AVERAGE_GFXACTIVITY:
941 *value = metrics->AverageGfxActivity / 100;
942 break;
943 case METRICS_AVERAGE_VCNACTIVITY:
944 *value = metrics->AverageUvdActivity / 100;
945 break;
946 case METRICS_AVERAGE_SOCKETPOWER:
947 *value = metrics->CurrentSocketPower << 8;
948 break;
949 case METRICS_TEMPERATURE_EDGE:
950 *value = (metrics->GfxTemperature / 100) *
951 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
952 break;
953 case METRICS_TEMPERATURE_HOTSPOT:
954 *value = (metrics->SocTemperature / 100) *
955 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
956 break;
957 case METRICS_THROTTLER_STATUS:
958 *value = metrics->ThrottlerStatus;
959 break;
960 case METRICS_VOLTAGE_VDDGFX:
961 *value = metrics->Voltage[0];
962 break;
963 case METRICS_VOLTAGE_VDDSOC:
964 *value = metrics->Voltage[1];
965 break;
966 default:
967 *value = UINT_MAX;
968 break;
969 }
970
971 mutex_unlock(&smu->metrics_lock);
972
973 return ret;
974}
975
976static int renoir_read_sensor(struct smu_context *smu,
977 enum amd_pp_sensors sensor,
978 void *data, uint32_t *size)
979{
980 int ret = 0;
981
982 if (!data || !size)
983 return -EINVAL;
984
985 mutex_lock(&smu->sensor_lock);
986 switch (sensor) {
987 case AMDGPU_PP_SENSOR_GPU_LOAD:
988 ret = renoir_get_smu_metrics_data(smu,
989 METRICS_AVERAGE_GFXACTIVITY,
990 (uint32_t *)data);
991 *size = 4;
992 break;
993 case AMDGPU_PP_SENSOR_EDGE_TEMP:
994 ret = renoir_get_smu_metrics_data(smu,
995 METRICS_TEMPERATURE_EDGE,
996 (uint32_t *)data);
997 *size = 4;
998 break;
999 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1000 ret = renoir_get_smu_metrics_data(smu,
1001 METRICS_TEMPERATURE_HOTSPOT,
1002 (uint32_t *)data);
1003 *size = 4;
1004 break;
1005 case AMDGPU_PP_SENSOR_GFX_MCLK:
1006 ret = renoir_get_smu_metrics_data(smu,
1007 METRICS_AVERAGE_UCLK,
1008 (uint32_t *)data);
1009 *(uint32_t *)data *= 100;
1010 *size = 4;
1011 break;
1012 case AMDGPU_PP_SENSOR_GFX_SCLK:
1013 ret = renoir_get_smu_metrics_data(smu,
1014 METRICS_AVERAGE_GFXCLK,
1015 (uint32_t *)data);
1016 *(uint32_t *)data *= 100;
1017 *size = 4;
1018 break;
1019 case AMDGPU_PP_SENSOR_VDDGFX:
1020 ret = renoir_get_smu_metrics_data(smu,
1021 METRICS_VOLTAGE_VDDGFX,
1022 (uint32_t *)data);
1023 *size = 4;
1024 break;
1025 case AMDGPU_PP_SENSOR_VDDNB:
1026 ret = renoir_get_smu_metrics_data(smu,
1027 METRICS_VOLTAGE_VDDSOC,
1028 (uint32_t *)data);
1029 *size = 4;
1030 break;
1031 case AMDGPU_PP_SENSOR_GPU_POWER:
1032 ret = renoir_get_smu_metrics_data(smu,
1033 METRICS_AVERAGE_SOCKETPOWER,
1034 (uint32_t *)data);
1035 *size = 4;
1036 break;
1037 default:
1038 ret = -EOPNOTSUPP;
1039 break;
1040 }
1041 mutex_unlock(&smu->sensor_lock);
1042
1043 return ret;
1044}
1045
1046static bool renoir_is_dpm_running(struct smu_context *smu)
1047{
1048 struct amdgpu_device *adev = smu->adev;
1049
1050
1051
1052
1053
1054
1055 if (adev->in_suspend)
1056 return false;
1057 else
1058 return true;
1059
1060}
1061
1062static ssize_t renoir_get_gpu_metrics(struct smu_context *smu,
1063 void **table)
1064{
1065 struct smu_table_context *smu_table = &smu->smu_table;
1066 struct gpu_metrics_v2_0 *gpu_metrics =
1067 (struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table;
1068 SmuMetrics_t metrics;
1069 int ret = 0;
1070
1071 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1072 if (ret)
1073 return ret;
1074
1075 smu_v12_0_init_gpu_metrics_v2_0(gpu_metrics);
1076
1077 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1078 gpu_metrics->temperature_soc = metrics.SocTemperature;
1079 memcpy(&gpu_metrics->temperature_core[0],
1080 &metrics.CoreTemperature[0],
1081 sizeof(uint16_t) * 8);
1082 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1083 gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1];
1084
1085 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1086 gpu_metrics->average_mm_activity = metrics.AverageUvdActivity;
1087
1088 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1089 gpu_metrics->average_cpu_power = metrics.Power[0];
1090 gpu_metrics->average_soc_power = metrics.Power[1];
1091 memcpy(&gpu_metrics->average_core_power[0],
1092 &metrics.CorePower[0],
1093 sizeof(uint16_t) * 8);
1094
1095 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1096 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1097 gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency;
1098 gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency;
1099
1100 gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK];
1101 gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK];
1102 gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK];
1103 gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK];
1104 gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK];
1105 gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK];
1106 memcpy(&gpu_metrics->current_coreclk[0],
1107 &metrics.CoreFrequency[0],
1108 sizeof(uint16_t) * 8);
1109 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1110 gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1];
1111
1112 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1113
1114 gpu_metrics->fan_pwm = metrics.FanPwm;
1115
1116 *table = (void *)gpu_metrics;
1117
1118 return sizeof(struct gpu_metrics_v2_0);
1119}
1120
1121static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)
1122{
1123
1124 return 0;
1125}
1126
1127static const struct pptable_funcs renoir_ppt_funcs = {
1128 .set_power_state = NULL,
1129 .print_clk_levels = renoir_print_clk_levels,
1130 .get_current_power_state = renoir_get_current_power_state,
1131 .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable,
1132 .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
1133 .force_clk_levels = renoir_force_clk_levels,
1134 .set_power_profile_mode = renoir_set_power_profile_mode,
1135 .set_performance_level = renoir_set_performance_level,
1136 .get_dpm_clock_table = renoir_get_dpm_clock_table,
1137 .set_watermarks_table = renoir_set_watermarks_table,
1138 .get_power_profile_mode = renoir_get_power_profile_mode,
1139 .read_sensor = renoir_read_sensor,
1140 .check_fw_status = smu_v12_0_check_fw_status,
1141 .check_fw_version = smu_v12_0_check_fw_version,
1142 .powergate_sdma = smu_v12_0_powergate_sdma,
1143 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1144 .send_smc_msg = smu_cmn_send_smc_msg,
1145 .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
1146 .gfx_off_control = smu_v12_0_gfx_off_control,
1147 .get_gfx_off_status = smu_v12_0_get_gfxoff_status,
1148 .init_smc_tables = renoir_init_smc_tables,
1149 .fini_smc_tables = smu_v12_0_fini_smc_tables,
1150 .set_default_dpm_table = smu_v12_0_set_default_dpm_tables,
1151 .get_enabled_mask = smu_cmn_get_enabled_mask,
1152 .feature_is_enabled = smu_cmn_feature_is_enabled,
1153 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1154 .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,
1155 .mode2_reset = smu_v12_0_mode2_reset,
1156 .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
1157 .set_driver_table_location = smu_v12_0_set_driver_table_location,
1158 .is_dpm_running = renoir_is_dpm_running,
1159 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1160 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1161 .get_gpu_metrics = renoir_get_gpu_metrics,
1162 .gfx_state_change_set = renoir_gfx_state_change_set,
1163};
1164
1165void renoir_set_ppt_funcs(struct smu_context *smu)
1166{
1167 smu->ppt_funcs = &renoir_ppt_funcs;
1168 smu->message_map = renoir_message_map;
1169 smu->clock_map = renoir_clk_map;
1170 smu->table_map = renoir_table_map;
1171 smu->workload_map = renoir_workload_map;
1172 smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION;
1173 smu->is_apu = true;
1174}
1175
