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25#ifndef _INTEL_DISPLAY_H_
26#define _INTEL_DISPLAY_H_
27
28#include <drm/drm_util.h>
29
30enum link_m_n_set;
31enum drm_scaling_filter;
32struct dpll;
33struct drm_connector;
34struct drm_device;
35struct drm_display_mode;
36struct drm_encoder;
37struct drm_file;
38struct drm_format_info;
39struct drm_framebuffer;
40struct drm_i915_error_state_buf;
41struct drm_i915_gem_object;
42struct drm_i915_private;
43struct drm_mode_fb_cmd2;
44struct drm_modeset_acquire_ctx;
45struct drm_plane;
46struct drm_plane_state;
47struct i915_ggtt_view;
48struct intel_atomic_state;
49struct intel_crtc;
50struct intel_crtc_state;
51struct intel_crtc_state;
52struct intel_digital_port;
53struct intel_dp;
54struct intel_encoder;
55struct intel_load_detect_pipe;
56struct intel_plane;
57struct intel_plane_state;
58struct intel_remapped_info;
59struct intel_rotation_info;
60
61enum i915_gpio {
62 GPIOA,
63 GPIOB,
64 GPIOC,
65 GPIOD,
66 GPIOE,
67 GPIOF,
68 GPIOG,
69 GPIOH,
70 __GPIOI_UNUSED,
71 GPIOJ,
72 GPIOK,
73 GPIOL,
74 GPIOM,
75 GPION,
76 GPIOO,
77};
78
79
80
81
82
83
84enum pipe {
85 INVALID_PIPE = -1,
86
87 PIPE_A = 0,
88 PIPE_B,
89 PIPE_C,
90 PIPE_D,
91 _PIPE_EDP,
92
93 I915_MAX_PIPES = _PIPE_EDP
94};
95
96#define pipe_name(p) ((p) + 'A')
97
98enum transcoder {
99 INVALID_TRANSCODER = -1,
100
101
102
103
104
105
106 TRANSCODER_A = PIPE_A,
107 TRANSCODER_B = PIPE_B,
108 TRANSCODER_C = PIPE_C,
109 TRANSCODER_D = PIPE_D,
110
111
112
113
114
115 TRANSCODER_EDP,
116 TRANSCODER_DSI_0,
117 TRANSCODER_DSI_1,
118 TRANSCODER_DSI_A = TRANSCODER_DSI_0,
119 TRANSCODER_DSI_C = TRANSCODER_DSI_1,
120
121 I915_MAX_TRANSCODERS
122};
123
124static inline const char *transcoder_name(enum transcoder transcoder)
125{
126 switch (transcoder) {
127 case TRANSCODER_A:
128 return "A";
129 case TRANSCODER_B:
130 return "B";
131 case TRANSCODER_C:
132 return "C";
133 case TRANSCODER_D:
134 return "D";
135 case TRANSCODER_EDP:
136 return "EDP";
137 case TRANSCODER_DSI_A:
138 return "DSI A";
139 case TRANSCODER_DSI_C:
140 return "DSI C";
141 default:
142 return "<invalid>";
143 }
144}
145
146static inline bool transcoder_is_dsi(enum transcoder transcoder)
147{
148 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
149}
150
151
152
153
154
155enum i9xx_plane_id {
156 PLANE_A,
157 PLANE_B,
158 PLANE_C,
159};
160
161#define plane_name(p) ((p) + 'A')
162#define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
163
164
165
166
167
168
169
170
171
172
173
174enum plane_id {
175 PLANE_PRIMARY,
176 PLANE_SPRITE0,
177 PLANE_SPRITE1,
178 PLANE_SPRITE2,
179 PLANE_SPRITE3,
180 PLANE_SPRITE4,
181 PLANE_SPRITE5,
182 PLANE_CURSOR,
183
184 I915_MAX_PLANES,
185};
186
187#define for_each_plane_id_on_crtc(__crtc, __p) \
188 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
189 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
190
191#define for_each_dbuf_slice_in_mask(__slice, __mask) \
192 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
193 for_each_if((BIT(__slice)) & (__mask))
194
195#define for_each_dbuf_slice(__slice) \
196 for_each_dbuf_slice_in_mask(__slice, BIT(I915_MAX_DBUF_SLICES) - 1)
197
198enum port {
199 PORT_NONE = -1,
200
201 PORT_A = 0,
202 PORT_B,
203 PORT_C,
204 PORT_D,
205 PORT_E,
206 PORT_F,
207 PORT_G,
208 PORT_H,
209 PORT_I,
210
211
212 PORT_TC1 = PORT_D,
213 PORT_TC2,
214 PORT_TC3,
215 PORT_TC4,
216 PORT_TC5,
217 PORT_TC6,
218
219 I915_MAX_PORTS
220};
221
222#define port_name(p) ((p) + 'A')
223
224
225
226
227
228static inline const char *port_identifier(enum port port)
229{
230 switch (port) {
231 case PORT_A:
232 return "Port A";
233 case PORT_B:
234 return "Port B";
235 case PORT_C:
236 return "Port C";
237 case PORT_D:
238 return "Port D";
239 case PORT_E:
240 return "Port E";
241 case PORT_F:
242 return "Port F";
243 case PORT_G:
244 return "Port G";
245 case PORT_H:
246 return "Port H";
247 case PORT_I:
248 return "Port I";
249 default:
250 return "<invalid>";
251 }
252}
253
254enum tc_port {
255 TC_PORT_NONE = -1,
256
257 TC_PORT_1 = 0,
258 TC_PORT_2,
259 TC_PORT_3,
260 TC_PORT_4,
261 TC_PORT_5,
262 TC_PORT_6,
263
264 I915_MAX_TC_PORTS
265};
266
267enum tc_port_mode {
268 TC_PORT_TBT_ALT,
269 TC_PORT_DP_ALT,
270 TC_PORT_LEGACY,
271};
272
273enum dpio_channel {
274 DPIO_CH0,
275 DPIO_CH1
276};
277
278enum dpio_phy {
279 DPIO_PHY0,
280 DPIO_PHY1,
281 DPIO_PHY2,
282};
283
284enum aux_ch {
285 AUX_CH_A,
286 AUX_CH_B,
287 AUX_CH_C,
288 AUX_CH_D,
289 AUX_CH_E,
290 AUX_CH_F,
291 AUX_CH_G,
292 AUX_CH_H,
293 AUX_CH_I,
294
295
296 AUX_CH_USBC1 = AUX_CH_D,
297 AUX_CH_USBC2,
298 AUX_CH_USBC3,
299 AUX_CH_USBC4,
300 AUX_CH_USBC5,
301 AUX_CH_USBC6,
302};
303
304#define aux_ch_name(a) ((a) + 'A')
305
306
307struct intel_link_m_n {
308 u32 tu;
309 u32 gmch_m;
310 u32 gmch_n;
311 u32 link_m;
312 u32 link_n;
313};
314
315enum phy {
316 PHY_NONE = -1,
317
318 PHY_A = 0,
319 PHY_B,
320 PHY_C,
321 PHY_D,
322 PHY_E,
323 PHY_F,
324 PHY_G,
325 PHY_H,
326 PHY_I,
327
328 I915_MAX_PHYS
329};
330
331#define phy_name(a) ((a) + 'A')
332
333enum phy_fia {
334 FIA1,
335 FIA2,
336 FIA3,
337};
338
339#define for_each_pipe(__dev_priv, __p) \
340 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
341 for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p))
342
343#define for_each_pipe_masked(__dev_priv, __p, __mask) \
344 for_each_pipe(__dev_priv, __p) \
345 for_each_if((__mask) & BIT(__p))
346
347#define for_each_cpu_transcoder(__dev_priv, __t) \
348 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
349 for_each_if (INTEL_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
350
351#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
352 for_each_cpu_transcoder(__dev_priv, __t) \
353 for_each_if ((__mask) & BIT(__t))
354
355#define for_each_universal_plane(__dev_priv, __pipe, __p) \
356 for ((__p) = 0; \
357 (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
358 (__p)++)
359
360#define for_each_sprite(__dev_priv, __p, __s) \
361 for ((__s) = 0; \
362 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
363 (__s)++)
364
365#define for_each_port(__port) \
366 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
367
368#define for_each_port_masked(__port, __ports_mask) \
369 for_each_port(__port) \
370 for_each_if((__ports_mask) & BIT(__port))
371
372#define for_each_phy_masked(__phy, __phys_mask) \
373 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
374 for_each_if((__phys_mask) & BIT(__phy))
375
376#define for_each_crtc(dev, crtc) \
377 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
378
379#define for_each_intel_plane(dev, intel_plane) \
380 list_for_each_entry(intel_plane, \
381 &(dev)->mode_config.plane_list, \
382 base.head)
383
384#define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
385 list_for_each_entry(intel_plane, \
386 &(dev)->mode_config.plane_list, \
387 base.head) \
388 for_each_if((plane_mask) & \
389 drm_plane_mask(&intel_plane->base))
390
391#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
392 list_for_each_entry(intel_plane, \
393 &(dev)->mode_config.plane_list, \
394 base.head) \
395 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
396
397#define for_each_intel_crtc(dev, intel_crtc) \
398 list_for_each_entry(intel_crtc, \
399 &(dev)->mode_config.crtc_list, \
400 base.head)
401
402#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
403 list_for_each_entry(intel_crtc, \
404 &(dev)->mode_config.crtc_list, \
405 base.head) \
406 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
407
408#define for_each_intel_encoder(dev, intel_encoder) \
409 list_for_each_entry(intel_encoder, \
410 &(dev)->mode_config.encoder_list, \
411 base.head)
412
413#define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \
414 list_for_each_entry(intel_encoder, \
415 &(dev)->mode_config.encoder_list, \
416 base.head) \
417 for_each_if((encoder_mask) & \
418 drm_encoder_mask(&intel_encoder->base))
419
420#define for_each_intel_dp(dev, intel_encoder) \
421 for_each_intel_encoder(dev, intel_encoder) \
422 for_each_if(intel_encoder_is_dp(intel_encoder))
423
424#define for_each_intel_connector_iter(intel_connector, iter) \
425 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
426
427#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
428 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
429 for_each_if((intel_encoder)->base.crtc == (__crtc))
430
431#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
432 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
433 for_each_if((intel_connector)->base.encoder == (__encoder))
434
435#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
436 for ((__i) = 0; \
437 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
438 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
439 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
440 (__i)++) \
441 for_each_if(plane)
442
443#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
444 for ((__i) = 0; \
445 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
446 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
447 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
448 (__i)++) \
449 for_each_if(plane)
450
451#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
452 for ((__i) = 0; \
453 (__i) < (__state)->base.dev->mode_config.num_crtc && \
454 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
455 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
456 (__i)++) \
457 for_each_if(crtc)
458
459#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
460 for ((__i) = 0; \
461 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
462 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
463 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
464 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
465 (__i)++) \
466 for_each_if(plane)
467
468#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
469 for ((__i) = 0; \
470 (__i) < (__state)->base.dev->mode_config.num_crtc && \
471 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
472 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
473 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
474 (__i)++) \
475 for_each_if(crtc)
476
477#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
478 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
479 (__i) >= 0 && \
480 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
481 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
482 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
483 (__i)--) \
484 for_each_if(crtc)
485
486#define intel_atomic_crtc_state_for_each_plane_state( \
487 plane, plane_state, \
488 crtc_state) \
489 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
490 ((crtc_state)->uapi.plane_mask)) \
491 for_each_if ((plane_state = \
492 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
493
494#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
495 for ((__i) = 0; \
496 (__i) < (__state)->base.num_connector; \
497 (__i)++) \
498 for_each_if ((__state)->base.connectors[__i].ptr && \
499 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
500 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
501
502u8 intel_calc_active_pipes(struct intel_atomic_state *state,
503 u8 active_pipes);
504void intel_link_compute_m_n(u16 bpp, int nlanes,
505 int pixel_clock, int link_clock,
506 struct intel_link_m_n *m_n,
507 bool constant_n, bool fec_enable);
508bool is_ccs_modifier(u64 modifier);
509int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane);
510void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
511u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
512 u32 pixel_format, u64 modifier);
513bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
514enum drm_mode_status
515intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
516 const struct drm_display_mode *mode,
517 bool bigjoiner);
518enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
519bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
520
521void intel_plane_destroy(struct drm_plane *plane);
522void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state);
523void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state);
524void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
525void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
526enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
527int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
528int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
529 const char *name, u32 reg, int ref_freq);
530int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
531 const char *name, u32 reg);
532void lpt_pch_enable(const struct intel_crtc_state *crtc_state);
533void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
534void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
535void intel_init_display_hooks(struct drm_i915_private *dev_priv);
536unsigned int intel_fb_xy_to_linear(int x, int y,
537 const struct intel_plane_state *state,
538 int plane);
539unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
540 int color_plane, unsigned int height);
541void intel_add_fb_offsets(int *x, int *y,
542 const struct intel_plane_state *state, int plane);
543unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
544unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
545bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
546int intel_display_suspend(struct drm_device *dev);
547void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
548void intel_encoder_destroy(struct drm_encoder *encoder);
549struct drm_display_mode *
550intel_encoder_current_mode(struct intel_encoder *encoder);
551bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
552bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
553enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
554 enum port port);
555int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
556 struct drm_file *file_priv);
557u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
558void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state);
559void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);
560
561int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
562void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
563 struct intel_digital_port *dig_port,
564 unsigned int expected_mask);
565int intel_get_load_detect_pipe(struct drm_connector *connector,
566 struct intel_load_detect_pipe *old,
567 struct drm_modeset_acquire_ctx *ctx);
568void intel_release_load_detect_pipe(struct drm_connector *connector,
569 struct intel_load_detect_pipe *old,
570 struct drm_modeset_acquire_ctx *ctx);
571struct i915_vma *
572intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
573 const struct i915_ggtt_view *view,
574 bool uses_fence,
575 unsigned long *out_flags);
576void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
577struct drm_framebuffer *
578intel_framebuffer_create(struct drm_i915_gem_object *obj,
579 struct drm_mode_fb_cmd2 *mode_cmd);
580int intel_prepare_plane_fb(struct drm_plane *plane,
581 struct drm_plane_state *new_state);
582void intel_cleanup_plane_fb(struct drm_plane *plane,
583 struct drm_plane_state *old_state);
584
585void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
586 enum pipe pipe);
587
588int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
589 const struct dpll *dpll);
590void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
591int lpt_get_iclkip(struct drm_i915_private *dev_priv);
592bool intel_fuzzy_clock_check(int clock1, int clock2);
593
594void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
595void intel_display_finish_reset(struct drm_i915_private *dev_priv);
596void intel_dp_get_m_n(struct intel_crtc *crtc,
597 struct intel_crtc_state *pipe_config);
598void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
599 enum link_m_n_set m_n);
600int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
601bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
602 struct dpll *best_clock);
603int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
604
605bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
606void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
607void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
608enum intel_display_power_domain intel_port_to_power_domain(enum port port);
609enum intel_display_power_domain
610intel_aux_power_domain(struct intel_digital_port *dig_port);
611enum intel_display_power_domain
612intel_legacy_aux_to_power_domain(enum aux_ch aux_ch);
613void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
614 struct intel_crtc_state *crtc_state);
615
616u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
617void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);
618u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set);
619void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
620 int id, int set, enum drm_scaling_filter filter);
621void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
622u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
623 const struct intel_plane_state *plane_state);
624u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
625u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
626 const struct intel_plane_state *plane_state);
627u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
628u32 skl_plane_stride(const struct intel_plane_state *plane_state,
629 int plane);
630int skl_check_plane_surface(struct intel_plane_state *plane_state);
631int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
632int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
633unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
634 u32 pixel_format, u64 modifier,
635 unsigned int rotation);
636int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
637unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
638
639struct intel_display_error_state *
640intel_display_capture_error_state(struct drm_i915_private *dev_priv);
641void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
642 struct intel_display_error_state *error);
643
644bool
645intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
646 uint64_t modifier);
647
648
649void intel_modeset_init_hw(struct drm_i915_private *i915);
650int intel_modeset_init_noirq(struct drm_i915_private *i915);
651int intel_modeset_init_nogem(struct drm_i915_private *i915);
652int intel_modeset_init(struct drm_i915_private *i915);
653void intel_modeset_driver_remove(struct drm_i915_private *i915);
654void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
655void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
656void intel_display_resume(struct drm_device *dev);
657void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
658
659
660void assert_panel_unlocked(struct drm_i915_private *dev_priv,
661 enum pipe pipe);
662void assert_pll(struct drm_i915_private *dev_priv,
663 enum pipe pipe, bool state);
664#define assert_pll_enabled(d, p) assert_pll(d, p, true)
665#define assert_pll_disabled(d, p) assert_pll(d, p, false)
666void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
667#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
668#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
669void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
670 enum pipe pipe, bool state);
671#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
672#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
673void assert_pipe(struct drm_i915_private *dev_priv,
674 enum transcoder cpu_transcoder, bool state);
675#define assert_pipe_enabled(d, t) assert_pipe(d, t, true)
676#define assert_pipe_disabled(d, t) assert_pipe(d, t, false)
677
678
679
680
681
682
683
684
685#define I915_STATE_WARN(condition, format...) ({ \
686 int __ret_warn_on = !!(condition); \
687 if (unlikely(__ret_warn_on)) \
688 if (!WARN(i915_modparams.verbose_state_checks, format)) \
689 DRM_ERROR(format); \
690 unlikely(__ret_warn_on); \
691})
692
693#define I915_STATE_WARN_ON(x) \
694 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
695
696#endif
697