LXR linux/drivers/gpu/drm/i915/intel

   1/* SPDX-License-Identifier: MIT */
   2/*
   3 * Copyright © 2019 Intel Corporation
   4 */
   5
   6#ifndef __INTEL_PM_H__
   7#define __INTEL_PM_H__
   8
   9#include <linux/types.h>
  10
  11#include "display/intel_bw.h"
  12#include "display/intel_global_state.h"
  13
  14#include "i915_reg.h"
  15
  16struct drm_device;
  17struct drm_i915_private;
  18struct i915_request;
  19struct intel_atomic_state;
  20struct intel_crtc;
  21struct intel_crtc_state;
  22struct intel_plane;
  23struct skl_ddb_entry;
  24struct skl_pipe_wm;
  25struct skl_wm_level;
  26
  27void intel_init_clock_gating(struct drm_i915_private *dev_priv);
  28void intel_suspend_hw(struct drm_i915_private *dev_priv);
  29int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
  30void intel_update_watermarks(struct intel_crtc *crtc);
  31void intel_init_pm(struct drm_i915_private *dev_priv);
  32void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
  33void intel_pm_setup(struct drm_i915_private *dev_priv);
  34void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
  35void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
  36void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
  37void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
  38u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
  39void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
  40                               struct skl_ddb_entry *ddb_y,
  41                               struct skl_ddb_entry *ddb_uv);
  42void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
  43u16 intel_get_ddb_size(struct drm_i915_private *dev_priv);
  44u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
  45                            const struct skl_ddb_entry *entry);
  46void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
  47                              struct skl_pipe_wm *out);
  48void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
  49void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
  50bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
  51                           const struct intel_bw_state *bw_state);
  52void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
  53void intel_sagv_post_plane_update(struct intel_atomic_state *state);
  54bool skl_wm_level_equals(const struct skl_wm_level *l1,
  55                         const struct skl_wm_level *l2);
  56bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
  57                                 const struct skl_ddb_entry *entries,
  58                                 int num_entries, int ignore_idx);
  59void skl_write_plane_wm(struct intel_plane *plane,
  60                        const struct intel_crtc_state *crtc_state);
  61void skl_write_cursor_wm(struct intel_plane *plane,
  62                         const struct intel_crtc_state *crtc_state);
  63bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
  64void intel_init_ipc(struct drm_i915_private *dev_priv);
  65void intel_enable_ipc(struct drm_i915_private *dev_priv);
  66
  67bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
  68
  69struct intel_dbuf_state {
  70        struct intel_global_state base;
  71
  72        u8 enabled_slices;
  73        u8 active_pipes;
  74};
  75
  76int intel_dbuf_init(struct drm_i915_private *dev_priv);
  77
  78struct intel_dbuf_state *
  79intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
  80
  81#define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
  82#define intel_atomic_get_old_dbuf_state(state) \
  83        to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
  84#define intel_atomic_get_new_dbuf_state(state) \
  85        to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
  86
  87int intel_dbuf_init(struct drm_i915_private *dev_priv);
  88void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
  89void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
  90
  91#endif /* __INTEL_PM_H__ */
  92