1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24#define gf119_pmu_code gk104_pmu_code
25#define gf119_pmu_data gk104_pmu_data
26#include "priv.h"
27#include "fuc/gf119.fuc4.h"
28
29#include <core/option.h>
30#include <subdev/fuse.h>
31#include <subdev/timer.h>
32
33static void
34magic_(struct nvkm_device *device, u32 ctrl, int size)
35{
36 nvkm_wr32(device, 0x00c800, 0x00000000);
37 nvkm_wr32(device, 0x00c808, 0x00000000);
38 nvkm_wr32(device, 0x00c800, ctrl);
39 nvkm_msec(device, 2000,
40 if (nvkm_rd32(device, 0x00c800) & 0x40000000) {
41 while (size--)
42 nvkm_wr32(device, 0x00c804, 0x00000000);
43 break;
44 }
45 );
46 nvkm_wr32(device, 0x00c800, 0x00000000);
47}
48
49static void
50magic(struct nvkm_device *device, u32 ctrl)
51{
52 magic_(device, 0x8000a41f | ctrl, 6);
53 magic_(device, 0x80000421 | ctrl, 1);
54}
55
56static void
57gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
58{
59 struct nvkm_device *device = pmu->subdev.device;
60
61 if (!(nvkm_fuse_read(device->fuse, 0x31c) & 0x00000001))
62 return;
63
64 nvkm_mask(device, 0x000200, 0x00001000, 0x00000000);
65 nvkm_rd32(device, 0x000200);
66 nvkm_mask(device, 0x000200, 0x08000000, 0x08000000);
67 msleep(50);
68
69 nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000002);
70 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001);
71 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000);
72
73 nvkm_mask(device, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000);
74 msleep(50);
75
76 nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000000);
77 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001);
78 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000);
79
80 nvkm_mask(device, 0x000200, 0x08000000, 0x00000000);
81 nvkm_mask(device, 0x000200, 0x00001000, 0x00001000);
82 nvkm_rd32(device, 0x000200);
83
84 if (nvkm_boolopt(device->cfgopt, "War00C800_0", true)) {
85 switch (device->chipset) {
86 case 0xe4:
87 magic(device, 0x04000000);
88 magic(device, 0x06000000);
89 magic(device, 0x0c000000);
90 magic(device, 0x0e000000);
91 break;
92 case 0xe6:
93 magic(device, 0x02000000);
94 magic(device, 0x04000000);
95 magic(device, 0x0a000000);
96 break;
97 case 0xe7:
98 magic(device, 0x02000000);
99 break;
100 default:
101 break;
102 }
103 }
104}
105
106static const struct nvkm_pmu_func
107gk104_pmu = {
108 .flcn = >215_pmu_flcn,
109 .code.data = gk104_pmu_code,
110 .code.size = sizeof(gk104_pmu_code),
111 .data.data = gk104_pmu_data,
112 .data.size = sizeof(gk104_pmu_data),
113 .enabled = gf100_pmu_enabled,
114 .reset = gf100_pmu_reset,
115 .init = gt215_pmu_init,
116 .fini = gt215_pmu_fini,
117 .intr = gt215_pmu_intr,
118 .send = gt215_pmu_send,
119 .recv = gt215_pmu_recv,
120 .pgob = gk104_pmu_pgob,
121};
122
123static const struct nvkm_pmu_fwif
124gk104_pmu_fwif[] = {
125 { -1, gf100_pmu_nofw, &gk104_pmu },
126 {}
127};
128
129int
130gk104_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
131{
132 return nvkm_pmu_new_(gk104_pmu_fwif, device, index, ppmu);
133}
134