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24#include <linux/hwmon-sysfs.h>
25#include <linux/hwmon.h>
26#include <linux/pci.h>
27#include <linux/power_supply.h>
28
29#include <drm/drm_debugfs.h>
30#include <drm/drm_vblank.h>
31
32#include "atom.h"
33#include "avivod.h"
34#include "r600_dpm.h"
35#include "radeon.h"
36#include "radeon_pm.h"
37
38#define RADEON_IDLE_LOOP_MS 100
39#define RADEON_RECLOCK_DELAY_MS 200
40#define RADEON_WAIT_VBLANK_TIMEOUT 200
41
42static const char *radeon_pm_state_type_name[5] = {
43 "",
44 "Powersave",
45 "Battery",
46 "Balanced",
47 "Performance",
48};
49
50static void radeon_dynpm_idle_work_handler(struct work_struct *work);
51static int radeon_debugfs_pm_init(struct radeon_device *rdev);
52static bool radeon_pm_in_vbl(struct radeon_device *rdev);
53static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
54static void radeon_pm_update_profile(struct radeon_device *rdev);
55static void radeon_pm_set_clocks(struct radeon_device *rdev);
56
57int radeon_pm_get_type_index(struct radeon_device *rdev,
58 enum radeon_pm_state_type ps_type,
59 int instance)
60{
61 int i;
62 int found_instance = -1;
63
64 for (i = 0; i < rdev->pm.num_power_states; i++) {
65 if (rdev->pm.power_state[i].type == ps_type) {
66 found_instance++;
67 if (found_instance == instance)
68 return i;
69 }
70 }
71
72 return rdev->pm.default_power_state_index;
73}
74
75void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
76{
77 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
78 mutex_lock(&rdev->pm.mutex);
79 if (power_supply_is_system_supplied() > 0)
80 rdev->pm.dpm.ac_power = true;
81 else
82 rdev->pm.dpm.ac_power = false;
83 if (rdev->family == CHIP_ARUBA) {
84 if (rdev->asic->dpm.enable_bapm)
85 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
86 }
87 mutex_unlock(&rdev->pm.mutex);
88 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
89 if (rdev->pm.profile == PM_PROFILE_AUTO) {
90 mutex_lock(&rdev->pm.mutex);
91 radeon_pm_update_profile(rdev);
92 radeon_pm_set_clocks(rdev);
93 mutex_unlock(&rdev->pm.mutex);
94 }
95 }
96}
97
98static void radeon_pm_update_profile(struct radeon_device *rdev)
99{
100 switch (rdev->pm.profile) {
101 case PM_PROFILE_DEFAULT:
102 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
103 break;
104 case PM_PROFILE_AUTO:
105 if (power_supply_is_system_supplied() > 0) {
106 if (rdev->pm.active_crtc_count > 1)
107 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
108 else
109 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
110 } else {
111 if (rdev->pm.active_crtc_count > 1)
112 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
113 else
114 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
115 }
116 break;
117 case PM_PROFILE_LOW:
118 if (rdev->pm.active_crtc_count > 1)
119 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
120 else
121 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
122 break;
123 case PM_PROFILE_MID:
124 if (rdev->pm.active_crtc_count > 1)
125 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
126 else
127 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
128 break;
129 case PM_PROFILE_HIGH:
130 if (rdev->pm.active_crtc_count > 1)
131 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
132 else
133 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
134 break;
135 }
136
137 if (rdev->pm.active_crtc_count == 0) {
138 rdev->pm.requested_power_state_index =
139 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
140 rdev->pm.requested_clock_mode_index =
141 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
142 } else {
143 rdev->pm.requested_power_state_index =
144 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
145 rdev->pm.requested_clock_mode_index =
146 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
147 }
148}
149
150static void radeon_unmap_vram_bos(struct radeon_device *rdev)
151{
152 struct radeon_bo *bo, *n;
153
154 if (list_empty(&rdev->gem.objects))
155 return;
156
157 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
158 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
159 ttm_bo_unmap_virtual(&bo->tbo);
160 }
161}
162
163static void radeon_sync_with_vblank(struct radeon_device *rdev)
164{
165 if (rdev->pm.active_crtcs) {
166 rdev->pm.vblank_sync = false;
167 wait_event_timeout(
168 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
169 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
170 }
171}
172
173static void radeon_set_power_state(struct radeon_device *rdev)
174{
175 u32 sclk, mclk;
176 bool misc_after = false;
177
178 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
179 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
180 return;
181
182 if (radeon_gui_idle(rdev)) {
183 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
184 clock_info[rdev->pm.requested_clock_mode_index].sclk;
185 if (sclk > rdev->pm.default_sclk)
186 sclk = rdev->pm.default_sclk;
187
188
189
190
191
192 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
193 (rdev->family >= CHIP_BARTS) &&
194 rdev->pm.active_crtc_count &&
195 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
196 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
197 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
198 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
199 else
200 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
201 clock_info[rdev->pm.requested_clock_mode_index].mclk;
202
203 if (mclk > rdev->pm.default_mclk)
204 mclk = rdev->pm.default_mclk;
205
206
207 if (sclk < rdev->pm.current_sclk)
208 misc_after = true;
209
210 radeon_sync_with_vblank(rdev);
211
212 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
213 if (!radeon_pm_in_vbl(rdev))
214 return;
215 }
216
217 radeon_pm_prepare(rdev);
218
219 if (!misc_after)
220
221 radeon_pm_misc(rdev);
222
223
224 if (sclk != rdev->pm.current_sclk) {
225 radeon_pm_debug_check_in_vbl(rdev, false);
226 radeon_set_engine_clock(rdev, sclk);
227 radeon_pm_debug_check_in_vbl(rdev, true);
228 rdev->pm.current_sclk = sclk;
229 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
230 }
231
232
233 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
234 radeon_pm_debug_check_in_vbl(rdev, false);
235 radeon_set_memory_clock(rdev, mclk);
236 radeon_pm_debug_check_in_vbl(rdev, true);
237 rdev->pm.current_mclk = mclk;
238 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
239 }
240
241 if (misc_after)
242
243 radeon_pm_misc(rdev);
244
245 radeon_pm_finish(rdev);
246
247 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
248 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
249 } else
250 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
251}
252
253static void radeon_pm_set_clocks(struct radeon_device *rdev)
254{
255 struct drm_crtc *crtc;
256 int i, r;
257
258
259 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
260 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
261 return;
262
263 down_write(&rdev->pm.mclk_lock);
264 mutex_lock(&rdev->ring_lock);
265
266
267 for (i = 0; i < RADEON_NUM_RINGS; i++) {
268 struct radeon_ring *ring = &rdev->ring[i];
269 if (!ring->ready) {
270 continue;
271 }
272 r = radeon_fence_wait_empty(rdev, i);
273 if (r) {
274
275 mutex_unlock(&rdev->ring_lock);
276 up_write(&rdev->pm.mclk_lock);
277 return;
278 }
279 }
280
281 radeon_unmap_vram_bos(rdev);
282
283 if (rdev->irq.installed) {
284 i = 0;
285 drm_for_each_crtc(crtc, rdev->ddev) {
286 if (rdev->pm.active_crtcs & (1 << i)) {
287
288 if (drm_crtc_vblank_get(crtc) == 0)
289 rdev->pm.req_vblank |= (1 << i);
290 else
291 DRM_DEBUG_DRIVER("crtc %d no vblank, can glitch\n",
292 i);
293 }
294 i++;
295 }
296 }
297
298 radeon_set_power_state(rdev);
299
300 if (rdev->irq.installed) {
301 i = 0;
302 drm_for_each_crtc(crtc, rdev->ddev) {
303 if (rdev->pm.req_vblank & (1 << i)) {
304 rdev->pm.req_vblank &= ~(1 << i);
305 drm_crtc_vblank_put(crtc);
306 }
307 i++;
308 }
309 }
310
311
312 radeon_update_bandwidth_info(rdev);
313 if (rdev->pm.active_crtc_count)
314 radeon_bandwidth_update(rdev);
315
316 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
317
318 mutex_unlock(&rdev->ring_lock);
319 up_write(&rdev->pm.mclk_lock);
320}
321
322static void radeon_pm_print_states(struct radeon_device *rdev)
323{
324 int i, j;
325 struct radeon_power_state *power_state;
326 struct radeon_pm_clock_info *clock_info;
327
328 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
329 for (i = 0; i < rdev->pm.num_power_states; i++) {
330 power_state = &rdev->pm.power_state[i];
331 DRM_DEBUG_DRIVER("State %d: %s\n", i,
332 radeon_pm_state_type_name[power_state->type]);
333 if (i == rdev->pm.default_power_state_index)
334 DRM_DEBUG_DRIVER("\tDefault");
335 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
336 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
337 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
338 DRM_DEBUG_DRIVER("\tSingle display only\n");
339 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
340 for (j = 0; j < power_state->num_clock_modes; j++) {
341 clock_info = &(power_state->clock_info[j]);
342 if (rdev->flags & RADEON_IS_IGP)
343 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
344 j,
345 clock_info->sclk * 10);
346 else
347 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
348 j,
349 clock_info->sclk * 10,
350 clock_info->mclk * 10,
351 clock_info->voltage.voltage);
352 }
353 }
354}
355
356static ssize_t radeon_get_pm_profile(struct device *dev,
357 struct device_attribute *attr,
358 char *buf)
359{
360 struct drm_device *ddev = dev_get_drvdata(dev);
361 struct radeon_device *rdev = ddev->dev_private;
362 int cp = rdev->pm.profile;
363
364 return snprintf(buf, PAGE_SIZE, "%s\n",
365 (cp == PM_PROFILE_AUTO) ? "auto" :
366 (cp == PM_PROFILE_LOW) ? "low" :
367 (cp == PM_PROFILE_MID) ? "mid" :
368 (cp == PM_PROFILE_HIGH) ? "high" : "default");
369}
370
371static ssize_t radeon_set_pm_profile(struct device *dev,
372 struct device_attribute *attr,
373 const char *buf,
374 size_t count)
375{
376 struct drm_device *ddev = dev_get_drvdata(dev);
377 struct radeon_device *rdev = ddev->dev_private;
378
379
380 if ((rdev->flags & RADEON_IS_PX) &&
381 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
382 return -EINVAL;
383
384 mutex_lock(&rdev->pm.mutex);
385 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
386 if (strncmp("default", buf, strlen("default")) == 0)
387 rdev->pm.profile = PM_PROFILE_DEFAULT;
388 else if (strncmp("auto", buf, strlen("auto")) == 0)
389 rdev->pm.profile = PM_PROFILE_AUTO;
390 else if (strncmp("low", buf, strlen("low")) == 0)
391 rdev->pm.profile = PM_PROFILE_LOW;
392 else if (strncmp("mid", buf, strlen("mid")) == 0)
393 rdev->pm.profile = PM_PROFILE_MID;
394 else if (strncmp("high", buf, strlen("high")) == 0)
395 rdev->pm.profile = PM_PROFILE_HIGH;
396 else {
397 count = -EINVAL;
398 goto fail;
399 }
400 radeon_pm_update_profile(rdev);
401 radeon_pm_set_clocks(rdev);
402 } else
403 count = -EINVAL;
404
405fail:
406 mutex_unlock(&rdev->pm.mutex);
407
408 return count;
409}
410
411static ssize_t radeon_get_pm_method(struct device *dev,
412 struct device_attribute *attr,
413 char *buf)
414{
415 struct drm_device *ddev = dev_get_drvdata(dev);
416 struct radeon_device *rdev = ddev->dev_private;
417 int pm = rdev->pm.pm_method;
418
419 return snprintf(buf, PAGE_SIZE, "%s\n",
420 (pm == PM_METHOD_DYNPM) ? "dynpm" :
421 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
422}
423
424static ssize_t radeon_set_pm_method(struct device *dev,
425 struct device_attribute *attr,
426 const char *buf,
427 size_t count)
428{
429 struct drm_device *ddev = dev_get_drvdata(dev);
430 struct radeon_device *rdev = ddev->dev_private;
431
432
433 if ((rdev->flags & RADEON_IS_PX) &&
434 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
435 count = -EINVAL;
436 goto fail;
437 }
438
439
440 if (rdev->pm.pm_method == PM_METHOD_DPM) {
441 count = -EINVAL;
442 goto fail;
443 }
444
445 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
446 mutex_lock(&rdev->pm.mutex);
447 rdev->pm.pm_method = PM_METHOD_DYNPM;
448 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
449 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
450 mutex_unlock(&rdev->pm.mutex);
451 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
452 mutex_lock(&rdev->pm.mutex);
453
454 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
455 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
456 rdev->pm.pm_method = PM_METHOD_PROFILE;
457 mutex_unlock(&rdev->pm.mutex);
458 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
459 } else {
460 count = -EINVAL;
461 goto fail;
462 }
463 radeon_pm_compute_clocks(rdev);
464fail:
465 return count;
466}
467
468static ssize_t radeon_get_dpm_state(struct device *dev,
469 struct device_attribute *attr,
470 char *buf)
471{
472 struct drm_device *ddev = dev_get_drvdata(dev);
473 struct radeon_device *rdev = ddev->dev_private;
474 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
475
476 return snprintf(buf, PAGE_SIZE, "%s\n",
477 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
478 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
479}
480
481static ssize_t radeon_set_dpm_state(struct device *dev,
482 struct device_attribute *attr,
483 const char *buf,
484 size_t count)
485{
486 struct drm_device *ddev = dev_get_drvdata(dev);
487 struct radeon_device *rdev = ddev->dev_private;
488
489 mutex_lock(&rdev->pm.mutex);
490 if (strncmp("battery", buf, strlen("battery")) == 0)
491 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
492 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
493 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
494 else if (strncmp("performance", buf, strlen("performance")) == 0)
495 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
496 else {
497 mutex_unlock(&rdev->pm.mutex);
498 count = -EINVAL;
499 goto fail;
500 }
501 mutex_unlock(&rdev->pm.mutex);
502
503
504 if (!(rdev->flags & RADEON_IS_PX) ||
505 (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
506 radeon_pm_compute_clocks(rdev);
507
508fail:
509 return count;
510}
511
512static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
513 struct device_attribute *attr,
514 char *buf)
515{
516 struct drm_device *ddev = dev_get_drvdata(dev);
517 struct radeon_device *rdev = ddev->dev_private;
518 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
519
520 if ((rdev->flags & RADEON_IS_PX) &&
521 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
522 return snprintf(buf, PAGE_SIZE, "off\n");
523
524 return snprintf(buf, PAGE_SIZE, "%s\n",
525 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
526 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
527}
528
529static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
530 struct device_attribute *attr,
531 const char *buf,
532 size_t count)
533{
534 struct drm_device *ddev = dev_get_drvdata(dev);
535 struct radeon_device *rdev = ddev->dev_private;
536 enum radeon_dpm_forced_level level;
537 int ret = 0;
538
539
540 if ((rdev->flags & RADEON_IS_PX) &&
541 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
542 return -EINVAL;
543
544 mutex_lock(&rdev->pm.mutex);
545 if (strncmp("low", buf, strlen("low")) == 0) {
546 level = RADEON_DPM_FORCED_LEVEL_LOW;
547 } else if (strncmp("high", buf, strlen("high")) == 0) {
548 level = RADEON_DPM_FORCED_LEVEL_HIGH;
549 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
550 level = RADEON_DPM_FORCED_LEVEL_AUTO;
551 } else {
552 count = -EINVAL;
553 goto fail;
554 }
555 if (rdev->asic->dpm.force_performance_level) {
556 if (rdev->pm.dpm.thermal_active) {
557 count = -EINVAL;
558 goto fail;
559 }
560 ret = radeon_dpm_force_performance_level(rdev, level);
561 if (ret)
562 count = -EINVAL;
563 }
564fail:
565 mutex_unlock(&rdev->pm.mutex);
566
567 return count;
568}
569
570static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev,
571 struct device_attribute *attr,
572 char *buf)
573{
574 struct radeon_device *rdev = dev_get_drvdata(dev);
575 u32 pwm_mode = 0;
576
577 if (rdev->asic->dpm.fan_ctrl_get_mode)
578 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev);
579
580
581 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
582}
583
584static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev,
585 struct device_attribute *attr,
586 const char *buf,
587 size_t count)
588{
589 struct radeon_device *rdev = dev_get_drvdata(dev);
590 int err;
591 int value;
592
593 if(!rdev->asic->dpm.fan_ctrl_set_mode)
594 return -EINVAL;
595
596 err = kstrtoint(buf, 10, &value);
597 if (err)
598 return err;
599
600 switch (value) {
601 case 1:
602 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC);
603 break;
604 default:
605 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0);
606 break;
607 }
608
609 return count;
610}
611
612static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev,
613 struct device_attribute *attr,
614 char *buf)
615{
616 return sprintf(buf, "%i\n", 0);
617}
618
619static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev,
620 struct device_attribute *attr,
621 char *buf)
622{
623 return sprintf(buf, "%i\n", 255);
624}
625
626static ssize_t radeon_hwmon_set_pwm1(struct device *dev,
627 struct device_attribute *attr,
628 const char *buf, size_t count)
629{
630 struct radeon_device *rdev = dev_get_drvdata(dev);
631 int err;
632 u32 value;
633
634 err = kstrtou32(buf, 10, &value);
635 if (err)
636 return err;
637
638 value = (value * 100) / 255;
639
640 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value);
641 if (err)
642 return err;
643
644 return count;
645}
646
647static ssize_t radeon_hwmon_get_pwm1(struct device *dev,
648 struct device_attribute *attr,
649 char *buf)
650{
651 struct radeon_device *rdev = dev_get_drvdata(dev);
652 int err;
653 u32 speed;
654
655 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed);
656 if (err)
657 return err;
658
659 speed = (speed * 255) / 100;
660
661 return sprintf(buf, "%i\n", speed);
662}
663
664static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
665static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
666static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
667static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
668 radeon_get_dpm_forced_performance_level,
669 radeon_set_dpm_forced_performance_level);
670
671static ssize_t radeon_hwmon_show_temp(struct device *dev,
672 struct device_attribute *attr,
673 char *buf)
674{
675 struct radeon_device *rdev = dev_get_drvdata(dev);
676 struct drm_device *ddev = rdev->ddev;
677 int temp;
678
679
680 if ((rdev->flags & RADEON_IS_PX) &&
681 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
682 return -EINVAL;
683
684 if (rdev->asic->pm.get_temperature)
685 temp = radeon_get_temperature(rdev);
686 else
687 temp = 0;
688
689 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
690}
691
692static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
693 struct device_attribute *attr,
694 char *buf)
695{
696 struct radeon_device *rdev = dev_get_drvdata(dev);
697 int hyst = to_sensor_dev_attr(attr)->index;
698 int temp;
699
700 if (hyst)
701 temp = rdev->pm.dpm.thermal.min_temp;
702 else
703 temp = rdev->pm.dpm.thermal.max_temp;
704
705 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
706}
707
708static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
709static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
710static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
711static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0);
712static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0);
713static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0);
714static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0);
715
716static ssize_t radeon_hwmon_show_sclk(struct device *dev,
717 struct device_attribute *attr, char *buf)
718{
719 struct radeon_device *rdev = dev_get_drvdata(dev);
720 struct drm_device *ddev = rdev->ddev;
721 u32 sclk = 0;
722
723
724 if ((rdev->flags & RADEON_IS_PX) &&
725 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
726 return -EINVAL;
727
728 if (rdev->asic->dpm.get_current_sclk)
729 sclk = radeon_dpm_get_current_sclk(rdev);
730
731
732
733 sclk *= 10000;
734
735 return snprintf(buf, PAGE_SIZE, "%u\n", sclk);
736}
737
738static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, radeon_hwmon_show_sclk, NULL,
739 0);
740
741static ssize_t radeon_hwmon_show_vddc(struct device *dev,
742 struct device_attribute *attr, char *buf)
743{
744 struct radeon_device *rdev = dev_get_drvdata(dev);
745 struct drm_device *ddev = rdev->ddev;
746 u16 vddc = 0;
747
748
749 if ((rdev->flags & RADEON_IS_PX) &&
750 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
751 return -EINVAL;
752
753 if (rdev->asic->dpm.get_current_vddc)
754 vddc = rdev->asic->dpm.get_current_vddc(rdev);
755
756 return snprintf(buf, PAGE_SIZE, "%u\n", vddc);
757}
758
759static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, radeon_hwmon_show_vddc, NULL,
760 0);
761
762static struct attribute *hwmon_attributes[] = {
763 &sensor_dev_attr_temp1_input.dev_attr.attr,
764 &sensor_dev_attr_temp1_crit.dev_attr.attr,
765 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
766 &sensor_dev_attr_pwm1.dev_attr.attr,
767 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
768 &sensor_dev_attr_pwm1_min.dev_attr.attr,
769 &sensor_dev_attr_pwm1_max.dev_attr.attr,
770 &sensor_dev_attr_freq1_input.dev_attr.attr,
771 &sensor_dev_attr_in0_input.dev_attr.attr,
772 NULL
773};
774
775static umode_t hwmon_attributes_visible(struct kobject *kobj,
776 struct attribute *attr, int index)
777{
778 struct device *dev = kobj_to_dev(kobj);
779 struct radeon_device *rdev = dev_get_drvdata(dev);
780 umode_t effective_mode = attr->mode;
781
782
783 if (rdev->pm.pm_method != PM_METHOD_DPM &&
784 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
785 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
786 attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
787 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
788 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
789 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
790 attr == &sensor_dev_attr_freq1_input.dev_attr.attr ||
791 attr == &sensor_dev_attr_in0_input.dev_attr.attr))
792 return 0;
793
794
795 if(attr == &sensor_dev_attr_in0_input.dev_attr.attr &&
796 !rdev->asic->dpm.get_current_vddc)
797 return 0;
798
799
800 if (rdev->pm.no_fan &&
801 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
802 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
803 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
804 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
805 return 0;
806
807
808 if ((!rdev->asic->dpm.get_fan_speed_percent &&
809 attr == &sensor_dev_attr_pwm1.dev_attr.attr) ||
810 (!rdev->asic->dpm.fan_ctrl_get_mode &&
811 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr))
812 effective_mode &= ~S_IRUGO;
813
814 if ((!rdev->asic->dpm.set_fan_speed_percent &&
815 attr == &sensor_dev_attr_pwm1.dev_attr.attr) ||
816 (!rdev->asic->dpm.fan_ctrl_set_mode &&
817 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr))
818 effective_mode &= ~S_IWUSR;
819
820
821 if ((!rdev->asic->dpm.set_fan_speed_percent &&
822 !rdev->asic->dpm.get_fan_speed_percent) &&
823 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
824 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
825 return 0;
826
827 return effective_mode;
828}
829
830static const struct attribute_group hwmon_attrgroup = {
831 .attrs = hwmon_attributes,
832 .is_visible = hwmon_attributes_visible,
833};
834
835static const struct attribute_group *hwmon_groups[] = {
836 &hwmon_attrgroup,
837 NULL
838};
839
840static int radeon_hwmon_init(struct radeon_device *rdev)
841{
842 int err = 0;
843
844 switch (rdev->pm.int_thermal_type) {
845 case THERMAL_TYPE_RV6XX:
846 case THERMAL_TYPE_RV770:
847 case THERMAL_TYPE_EVERGREEN:
848 case THERMAL_TYPE_NI:
849 case THERMAL_TYPE_SUMO:
850 case THERMAL_TYPE_SI:
851 case THERMAL_TYPE_CI:
852 case THERMAL_TYPE_KV:
853 if (rdev->asic->pm.get_temperature == NULL)
854 return err;
855 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
856 "radeon", rdev,
857 hwmon_groups);
858 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
859 err = PTR_ERR(rdev->pm.int_hwmon_dev);
860 dev_err(rdev->dev,
861 "Unable to register hwmon device: %d\n", err);
862 }
863 break;
864 default:
865 break;
866 }
867
868 return err;
869}
870
871static void radeon_hwmon_fini(struct radeon_device *rdev)
872{
873 if (rdev->pm.int_hwmon_dev)
874 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
875}
876
877static void radeon_dpm_thermal_work_handler(struct work_struct *work)
878{
879 struct radeon_device *rdev =
880 container_of(work, struct radeon_device,
881 pm.dpm.thermal.work);
882
883 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
884
885 if (!rdev->pm.dpm_enabled)
886 return;
887
888 if (rdev->asic->pm.get_temperature) {
889 int temp = radeon_get_temperature(rdev);
890
891 if (temp < rdev->pm.dpm.thermal.min_temp)
892
893 dpm_state = rdev->pm.dpm.user_state;
894 } else {
895 if (rdev->pm.dpm.thermal.high_to_low)
896
897 dpm_state = rdev->pm.dpm.user_state;
898 }
899 mutex_lock(&rdev->pm.mutex);
900 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
901 rdev->pm.dpm.thermal_active = true;
902 else
903 rdev->pm.dpm.thermal_active = false;
904 rdev->pm.dpm.state = dpm_state;
905 mutex_unlock(&rdev->pm.mutex);
906
907 radeon_pm_compute_clocks(rdev);
908}
909
910static bool radeon_dpm_single_display(struct radeon_device *rdev)
911{
912 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
913 true : false;
914
915
916 if (single_display && rdev->asic->dpm.vblank_too_short) {
917 if (radeon_dpm_vblank_too_short(rdev))
918 single_display = false;
919 }
920
921
922
923
924 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
925 single_display = false;
926
927 return single_display;
928}
929
930static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
931 enum radeon_pm_state_type dpm_state)
932{
933 int i;
934 struct radeon_ps *ps;
935 u32 ui_class;
936 bool single_display = radeon_dpm_single_display(rdev);
937
938
939
940
941 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
942 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
943
944 if (dpm_state == POWER_STATE_TYPE_BALANCED)
945 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
946
947restart_search:
948
949 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
950 ps = &rdev->pm.dpm.ps[i];
951 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
952 switch (dpm_state) {
953
954 case POWER_STATE_TYPE_BATTERY:
955 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
956 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
957 if (single_display)
958 return ps;
959 } else
960 return ps;
961 }
962 break;
963 case POWER_STATE_TYPE_BALANCED:
964 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
965 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
966 if (single_display)
967 return ps;
968 } else
969 return ps;
970 }
971 break;
972 case POWER_STATE_TYPE_PERFORMANCE:
973 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
974 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
975 if (single_display)
976 return ps;
977 } else
978 return ps;
979 }
980 break;
981
982 case POWER_STATE_TYPE_INTERNAL_UVD:
983 if (rdev->pm.dpm.uvd_ps)
984 return rdev->pm.dpm.uvd_ps;
985 else
986 break;
987 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
988 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
989 return ps;
990 break;
991 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
992 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
993 return ps;
994 break;
995 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
996 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
997 return ps;
998 break;
999 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1000 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1001 return ps;
1002 break;
1003 case POWER_STATE_TYPE_INTERNAL_BOOT:
1004 return rdev->pm.dpm.boot_ps;
1005 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1006 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1007 return ps;
1008 break;
1009 case POWER_STATE_TYPE_INTERNAL_ACPI:
1010 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1011 return ps;
1012 break;
1013 case POWER_STATE_TYPE_INTERNAL_ULV:
1014 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1015 return ps;
1016 break;
1017 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1018 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1019 return ps;
1020 break;
1021 default:
1022 break;
1023 }
1024 }
1025
1026 switch (dpm_state) {
1027 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1028 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1029 goto restart_search;
1030 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1031 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1032 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1033 if (rdev->pm.dpm.uvd_ps) {
1034 return rdev->pm.dpm.uvd_ps;
1035 } else {
1036 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1037 goto restart_search;
1038 }
1039 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1040 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1041 goto restart_search;
1042 case POWER_STATE_TYPE_INTERNAL_ACPI:
1043 dpm_state = POWER_STATE_TYPE_BATTERY;
1044 goto restart_search;
1045 case POWER_STATE_TYPE_BATTERY:
1046 case POWER_STATE_TYPE_BALANCED:
1047 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1048 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1049 goto restart_search;
1050 default:
1051 break;
1052 }
1053
1054 return NULL;
1055}
1056
1057static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
1058{
1059 int i;
1060 struct radeon_ps *ps;
1061 enum radeon_pm_state_type dpm_state;
1062 int ret;
1063 bool single_display = radeon_dpm_single_display(rdev);
1064
1065
1066 if (!rdev->pm.dpm_enabled)
1067 return;
1068
1069 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
1070
1071 if ((!rdev->pm.dpm.thermal_active) &&
1072 (!rdev->pm.dpm.uvd_active))
1073 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
1074 }
1075 dpm_state = rdev->pm.dpm.state;
1076
1077 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
1078 if (ps)
1079 rdev->pm.dpm.requested_ps = ps;
1080 else
1081 return;
1082
1083
1084 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
1085
1086 if (ps->vce_active != rdev->pm.dpm.vce_active)
1087 goto force;
1088
1089 if (rdev->pm.dpm.single_display != single_display)
1090 goto force;
1091 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
1092
1093
1094
1095 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
1096
1097 radeon_bandwidth_update(rdev);
1098
1099 radeon_dpm_display_configuration_changed(rdev);
1100 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1101 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1102 }
1103 return;
1104 } else {
1105
1106
1107
1108
1109 if (rdev->pm.dpm.new_active_crtcs ==
1110 rdev->pm.dpm.current_active_crtcs) {
1111 return;
1112 } else {
1113 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
1114 (rdev->pm.dpm.new_active_crtc_count > 1)) {
1115
1116 radeon_bandwidth_update(rdev);
1117
1118 radeon_dpm_display_configuration_changed(rdev);
1119 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1120 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1121 return;
1122 }
1123 }
1124 }
1125 }
1126
1127force:
1128 if (radeon_dpm == 1) {
1129 printk("switching from power state:\n");
1130 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
1131 printk("switching to power state:\n");
1132 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
1133 }
1134
1135 down_write(&rdev->pm.mclk_lock);
1136 mutex_lock(&rdev->ring_lock);
1137
1138
1139 ps->vce_active = rdev->pm.dpm.vce_active;
1140
1141 ret = radeon_dpm_pre_set_power_state(rdev);
1142 if (ret)
1143 goto done;
1144
1145
1146 radeon_bandwidth_update(rdev);
1147
1148 radeon_dpm_display_configuration_changed(rdev);
1149
1150
1151 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1152 struct radeon_ring *ring = &rdev->ring[i];
1153 if (ring->ready)
1154 radeon_fence_wait_empty(rdev, i);
1155 }
1156
1157
1158 radeon_dpm_set_power_state(rdev);
1159
1160
1161 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
1162
1163 radeon_dpm_post_set_power_state(rdev);
1164
1165 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1166 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1167 rdev->pm.dpm.single_display = single_display;
1168
1169 if (rdev->asic->dpm.force_performance_level) {
1170 if (rdev->pm.dpm.thermal_active) {
1171 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1172
1173 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
1174
1175 rdev->pm.dpm.forced_level = level;
1176 } else {
1177
1178 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
1179 }
1180 }
1181
1182done:
1183 mutex_unlock(&rdev->ring_lock);
1184 up_write(&rdev->pm.mclk_lock);
1185}
1186
1187void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
1188{
1189 enum radeon_pm_state_type dpm_state;
1190
1191 if (rdev->asic->dpm.powergate_uvd) {
1192 mutex_lock(&rdev->pm.mutex);
1193
1194
1195 enable |= rdev->pm.dpm.sd > 0;
1196 enable |= rdev->pm.dpm.hd > 0;
1197
1198 radeon_dpm_powergate_uvd(rdev, !enable);
1199 mutex_unlock(&rdev->pm.mutex);
1200 } else {
1201 if (enable) {
1202 mutex_lock(&rdev->pm.mutex);
1203 rdev->pm.dpm.uvd_active = true;
1204
1205#if 0
1206 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
1207 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
1208 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
1209 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1210 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
1211 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1212 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
1213 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
1214 else
1215#endif
1216 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
1217 rdev->pm.dpm.state = dpm_state;
1218 mutex_unlock(&rdev->pm.mutex);
1219 } else {
1220 mutex_lock(&rdev->pm.mutex);
1221 rdev->pm.dpm.uvd_active = false;
1222 mutex_unlock(&rdev->pm.mutex);
1223 }
1224
1225 radeon_pm_compute_clocks(rdev);
1226 }
1227}
1228
1229void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1230{
1231 if (enable) {
1232 mutex_lock(&rdev->pm.mutex);
1233 rdev->pm.dpm.vce_active = true;
1234
1235 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1236 mutex_unlock(&rdev->pm.mutex);
1237 } else {
1238 mutex_lock(&rdev->pm.mutex);
1239 rdev->pm.dpm.vce_active = false;
1240 mutex_unlock(&rdev->pm.mutex);
1241 }
1242
1243 radeon_pm_compute_clocks(rdev);
1244}
1245
1246static void radeon_pm_suspend_old(struct radeon_device *rdev)
1247{
1248 mutex_lock(&rdev->pm.mutex);
1249 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1250 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1251 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1252 }
1253 mutex_unlock(&rdev->pm.mutex);
1254
1255 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1256}
1257
1258static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1259{
1260 mutex_lock(&rdev->pm.mutex);
1261
1262 radeon_dpm_disable(rdev);
1263
1264 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1265 rdev->pm.dpm_enabled = false;
1266 mutex_unlock(&rdev->pm.mutex);
1267}
1268
1269void radeon_pm_suspend(struct radeon_device *rdev)
1270{
1271 if (rdev->pm.pm_method == PM_METHOD_DPM)
1272 radeon_pm_suspend_dpm(rdev);
1273 else
1274 radeon_pm_suspend_old(rdev);
1275}
1276
1277static void radeon_pm_resume_old(struct radeon_device *rdev)
1278{
1279
1280 if ((rdev->family >= CHIP_BARTS) &&
1281 (rdev->family <= CHIP_CAYMAN) &&
1282 rdev->mc_fw) {
1283 if (rdev->pm.default_vddc)
1284 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1285 SET_VOLTAGE_TYPE_ASIC_VDDC);
1286 if (rdev->pm.default_vddci)
1287 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1288 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1289 if (rdev->pm.default_sclk)
1290 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1291 if (rdev->pm.default_mclk)
1292 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1293 }
1294
1295 mutex_lock(&rdev->pm.mutex);
1296 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1297 rdev->pm.current_clock_mode_index = 0;
1298 rdev->pm.current_sclk = rdev->pm.default_sclk;
1299 rdev->pm.current_mclk = rdev->pm.default_mclk;
1300 if (rdev->pm.power_state) {
1301 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1302 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1303 }
1304 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1305 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1306 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1307 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1308 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1309 }
1310 mutex_unlock(&rdev->pm.mutex);
1311 radeon_pm_compute_clocks(rdev);
1312}
1313
1314static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1315{
1316 int ret;
1317
1318
1319 mutex_lock(&rdev->pm.mutex);
1320 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1321 radeon_dpm_setup_asic(rdev);
1322 ret = radeon_dpm_enable(rdev);
1323 mutex_unlock(&rdev->pm.mutex);
1324 if (ret)
1325 goto dpm_resume_fail;
1326 rdev->pm.dpm_enabled = true;
1327 return;
1328
1329dpm_resume_fail:
1330 DRM_ERROR("radeon: dpm resume failed\n");
1331 if ((rdev->family >= CHIP_BARTS) &&
1332 (rdev->family <= CHIP_CAYMAN) &&
1333 rdev->mc_fw) {
1334 if (rdev->pm.default_vddc)
1335 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1336 SET_VOLTAGE_TYPE_ASIC_VDDC);
1337 if (rdev->pm.default_vddci)
1338 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1339 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1340 if (rdev->pm.default_sclk)
1341 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1342 if (rdev->pm.default_mclk)
1343 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1344 }
1345}
1346
1347void radeon_pm_resume(struct radeon_device *rdev)
1348{
1349 if (rdev->pm.pm_method == PM_METHOD_DPM)
1350 radeon_pm_resume_dpm(rdev);
1351 else
1352 radeon_pm_resume_old(rdev);
1353}
1354
1355static int radeon_pm_init_old(struct radeon_device *rdev)
1356{
1357 int ret;
1358
1359 rdev->pm.profile = PM_PROFILE_DEFAULT;
1360 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1361 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1362 rdev->pm.dynpm_can_upclock = true;
1363 rdev->pm.dynpm_can_downclock = true;
1364 rdev->pm.default_sclk = rdev->clock.default_sclk;
1365 rdev->pm.default_mclk = rdev->clock.default_mclk;
1366 rdev->pm.current_sclk = rdev->clock.default_sclk;
1367 rdev->pm.current_mclk = rdev->clock.default_mclk;
1368 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1369
1370 if (rdev->bios) {
1371 if (rdev->is_atom_bios)
1372 radeon_atombios_get_power_modes(rdev);
1373 else
1374 radeon_combios_get_power_modes(rdev);
1375 radeon_pm_print_states(rdev);
1376 radeon_pm_init_profile(rdev);
1377
1378 if ((rdev->family >= CHIP_BARTS) &&
1379 (rdev->family <= CHIP_CAYMAN) &&
1380 rdev->mc_fw) {
1381 if (rdev->pm.default_vddc)
1382 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1383 SET_VOLTAGE_TYPE_ASIC_VDDC);
1384 if (rdev->pm.default_vddci)
1385 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1386 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1387 if (rdev->pm.default_sclk)
1388 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1389 if (rdev->pm.default_mclk)
1390 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1391 }
1392 }
1393
1394
1395 ret = radeon_hwmon_init(rdev);
1396 if (ret)
1397 return ret;
1398
1399 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1400
1401 if (rdev->pm.num_power_states > 1) {
1402 if (radeon_debugfs_pm_init(rdev)) {
1403 DRM_ERROR("Failed to register debugfs file for PM!\n");
1404 }
1405
1406 DRM_INFO("radeon: power management initialized\n");
1407 }
1408
1409 return 0;
1410}
1411
1412static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1413{
1414 int i;
1415
1416 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1417 printk("== power state %d ==\n", i);
1418 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1419 }
1420}
1421
1422static int radeon_pm_init_dpm(struct radeon_device *rdev)
1423{
1424 int ret;
1425
1426
1427 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1428 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1429 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1430 rdev->pm.default_sclk = rdev->clock.default_sclk;
1431 rdev->pm.default_mclk = rdev->clock.default_mclk;
1432 rdev->pm.current_sclk = rdev->clock.default_sclk;
1433 rdev->pm.current_mclk = rdev->clock.default_mclk;
1434 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1435
1436 if (rdev->bios && rdev->is_atom_bios)
1437 radeon_atombios_get_power_modes(rdev);
1438 else
1439 return -EINVAL;
1440
1441
1442 ret = radeon_hwmon_init(rdev);
1443 if (ret)
1444 return ret;
1445
1446 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1447 mutex_lock(&rdev->pm.mutex);
1448 radeon_dpm_init(rdev);
1449 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1450 if (radeon_dpm == 1)
1451 radeon_dpm_print_power_states(rdev);
1452 radeon_dpm_setup_asic(rdev);
1453 ret = radeon_dpm_enable(rdev);
1454 mutex_unlock(&rdev->pm.mutex);
1455 if (ret)
1456 goto dpm_failed;
1457 rdev->pm.dpm_enabled = true;
1458
1459 if (radeon_debugfs_pm_init(rdev)) {
1460 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1461 }
1462
1463 DRM_INFO("radeon: dpm initialized\n");
1464
1465 return 0;
1466
1467dpm_failed:
1468 rdev->pm.dpm_enabled = false;
1469 if ((rdev->family >= CHIP_BARTS) &&
1470 (rdev->family <= CHIP_CAYMAN) &&
1471 rdev->mc_fw) {
1472 if (rdev->pm.default_vddc)
1473 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1474 SET_VOLTAGE_TYPE_ASIC_VDDC);
1475 if (rdev->pm.default_vddci)
1476 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1477 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1478 if (rdev->pm.default_sclk)
1479 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1480 if (rdev->pm.default_mclk)
1481 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1482 }
1483 DRM_ERROR("radeon: dpm initialization failed\n");
1484 return ret;
1485}
1486
1487struct radeon_dpm_quirk {
1488 u32 chip_vendor;
1489 u32 chip_device;
1490 u32 subsys_vendor;
1491 u32 subsys_device;
1492};
1493
1494
1495static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = {
1496
1497 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 },
1498
1499 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 },
1500 { 0, 0, 0, 0 },
1501};
1502
1503int radeon_pm_init(struct radeon_device *rdev)
1504{
1505 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list;
1506 bool disable_dpm = false;
1507
1508
1509 while (p && p->chip_device != 0) {
1510 if (rdev->pdev->vendor == p->chip_vendor &&
1511 rdev->pdev->device == p->chip_device &&
1512 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
1513 rdev->pdev->subsystem_device == p->subsys_device) {
1514 disable_dpm = true;
1515 break;
1516 }
1517 ++p;
1518 }
1519
1520
1521 switch (rdev->family) {
1522 case CHIP_RV610:
1523 case CHIP_RV630:
1524 case CHIP_RV620:
1525 case CHIP_RV635:
1526 case CHIP_RV670:
1527 case CHIP_RS780:
1528 case CHIP_RS880:
1529 case CHIP_RV770:
1530
1531 if (!rdev->rlc_fw)
1532 rdev->pm.pm_method = PM_METHOD_PROFILE;
1533 else if ((rdev->family >= CHIP_RV770) &&
1534 (!(rdev->flags & RADEON_IS_IGP)) &&
1535 (!rdev->smc_fw))
1536 rdev->pm.pm_method = PM_METHOD_PROFILE;
1537 else if (radeon_dpm == 1)
1538 rdev->pm.pm_method = PM_METHOD_DPM;
1539 else
1540 rdev->pm.pm_method = PM_METHOD_PROFILE;
1541 break;
1542 case CHIP_RV730:
1543 case CHIP_RV710:
1544 case CHIP_RV740:
1545 case CHIP_CEDAR:
1546 case CHIP_REDWOOD:
1547 case CHIP_JUNIPER:
1548 case CHIP_CYPRESS:
1549 case CHIP_HEMLOCK:
1550 case CHIP_PALM:
1551 case CHIP_SUMO:
1552 case CHIP_SUMO2:
1553 case CHIP_BARTS:
1554 case CHIP_TURKS:
1555 case CHIP_CAICOS:
1556 case CHIP_CAYMAN:
1557 case CHIP_ARUBA:
1558 case CHIP_TAHITI:
1559 case CHIP_PITCAIRN:
1560 case CHIP_VERDE:
1561 case CHIP_OLAND:
1562 case CHIP_HAINAN:
1563 case CHIP_BONAIRE:
1564 case CHIP_KABINI:
1565 case CHIP_KAVERI:
1566 case CHIP_HAWAII:
1567 case CHIP_MULLINS:
1568
1569 if (!rdev->rlc_fw)
1570 rdev->pm.pm_method = PM_METHOD_PROFILE;
1571 else if ((rdev->family >= CHIP_RV770) &&
1572 (!(rdev->flags & RADEON_IS_IGP)) &&
1573 (!rdev->smc_fw))
1574 rdev->pm.pm_method = PM_METHOD_PROFILE;
1575 else if (disable_dpm && (radeon_dpm == -1))
1576 rdev->pm.pm_method = PM_METHOD_PROFILE;
1577 else if (radeon_dpm == 0)
1578 rdev->pm.pm_method = PM_METHOD_PROFILE;
1579 else
1580 rdev->pm.pm_method = PM_METHOD_DPM;
1581 break;
1582 default:
1583
1584 rdev->pm.pm_method = PM_METHOD_PROFILE;
1585 break;
1586 }
1587
1588 if (rdev->pm.pm_method == PM_METHOD_DPM)
1589 return radeon_pm_init_dpm(rdev);
1590 else
1591 return radeon_pm_init_old(rdev);
1592}
1593
1594int radeon_pm_late_init(struct radeon_device *rdev)
1595{
1596 int ret = 0;
1597
1598 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1599 if (rdev->pm.dpm_enabled) {
1600 if (!rdev->pm.sysfs_initialized) {
1601 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1602 if (ret)
1603 DRM_ERROR("failed to create device file for dpm state\n");
1604 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1605 if (ret)
1606 DRM_ERROR("failed to create device file for dpm state\n");
1607
1608 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1609 if (ret)
1610 DRM_ERROR("failed to create device file for power profile\n");
1611 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1612 if (ret)
1613 DRM_ERROR("failed to create device file for power method\n");
1614 rdev->pm.sysfs_initialized = true;
1615 }
1616
1617 mutex_lock(&rdev->pm.mutex);
1618 ret = radeon_dpm_late_enable(rdev);
1619 mutex_unlock(&rdev->pm.mutex);
1620 if (ret) {
1621 rdev->pm.dpm_enabled = false;
1622 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1623 } else {
1624
1625
1626
1627 radeon_pm_compute_clocks(rdev);
1628 }
1629 }
1630 } else {
1631 if ((rdev->pm.num_power_states > 1) &&
1632 (!rdev->pm.sysfs_initialized)) {
1633
1634 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1635 if (ret)
1636 DRM_ERROR("failed to create device file for power profile\n");
1637 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1638 if (ret)
1639 DRM_ERROR("failed to create device file for power method\n");
1640 if (!ret)
1641 rdev->pm.sysfs_initialized = true;
1642 }
1643 }
1644 return ret;
1645}
1646
1647static void radeon_pm_fini_old(struct radeon_device *rdev)
1648{
1649 if (rdev->pm.num_power_states > 1) {
1650 mutex_lock(&rdev->pm.mutex);
1651 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1652 rdev->pm.profile = PM_PROFILE_DEFAULT;
1653 radeon_pm_update_profile(rdev);
1654 radeon_pm_set_clocks(rdev);
1655 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1656
1657 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1658 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1659 radeon_pm_set_clocks(rdev);
1660 }
1661 mutex_unlock(&rdev->pm.mutex);
1662
1663 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1664
1665 device_remove_file(rdev->dev, &dev_attr_power_profile);
1666 device_remove_file(rdev->dev, &dev_attr_power_method);
1667 }
1668
1669 radeon_hwmon_fini(rdev);
1670 kfree(rdev->pm.power_state);
1671}
1672
1673static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1674{
1675 if (rdev->pm.num_power_states > 1) {
1676 mutex_lock(&rdev->pm.mutex);
1677 radeon_dpm_disable(rdev);
1678 mutex_unlock(&rdev->pm.mutex);
1679
1680 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1681 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1682
1683 device_remove_file(rdev->dev, &dev_attr_power_profile);
1684 device_remove_file(rdev->dev, &dev_attr_power_method);
1685 }
1686 radeon_dpm_fini(rdev);
1687
1688 radeon_hwmon_fini(rdev);
1689 kfree(rdev->pm.power_state);
1690}
1691
1692void radeon_pm_fini(struct radeon_device *rdev)
1693{
1694 if (rdev->pm.pm_method == PM_METHOD_DPM)
1695 radeon_pm_fini_dpm(rdev);
1696 else
1697 radeon_pm_fini_old(rdev);
1698}
1699
1700static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1701{
1702 struct drm_device *ddev = rdev->ddev;
1703 struct drm_crtc *crtc;
1704 struct radeon_crtc *radeon_crtc;
1705
1706 if (rdev->pm.num_power_states < 2)
1707 return;
1708
1709 mutex_lock(&rdev->pm.mutex);
1710
1711 rdev->pm.active_crtcs = 0;
1712 rdev->pm.active_crtc_count = 0;
1713 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1714 list_for_each_entry(crtc,
1715 &ddev->mode_config.crtc_list, head) {
1716 radeon_crtc = to_radeon_crtc(crtc);
1717 if (radeon_crtc->enabled) {
1718 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1719 rdev->pm.active_crtc_count++;
1720 }
1721 }
1722 }
1723
1724 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1725 radeon_pm_update_profile(rdev);
1726 radeon_pm_set_clocks(rdev);
1727 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1728 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1729 if (rdev->pm.active_crtc_count > 1) {
1730 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1731 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1732
1733 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1734 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1735 radeon_pm_get_dynpm_state(rdev);
1736 radeon_pm_set_clocks(rdev);
1737
1738 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1739 }
1740 } else if (rdev->pm.active_crtc_count == 1) {
1741
1742
1743 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1744 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1745 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1746 radeon_pm_get_dynpm_state(rdev);
1747 radeon_pm_set_clocks(rdev);
1748
1749 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1750 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1751 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1752 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1753 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1754 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1755 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1756 }
1757 } else {
1758 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1759 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1760
1761 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1762 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1763 radeon_pm_get_dynpm_state(rdev);
1764 radeon_pm_set_clocks(rdev);
1765 }
1766 }
1767 }
1768 }
1769
1770 mutex_unlock(&rdev->pm.mutex);
1771}
1772
1773static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1774{
1775 struct drm_device *ddev = rdev->ddev;
1776 struct drm_crtc *crtc;
1777 struct radeon_crtc *radeon_crtc;
1778
1779 if (!rdev->pm.dpm_enabled)
1780 return;
1781
1782 mutex_lock(&rdev->pm.mutex);
1783
1784
1785 rdev->pm.dpm.new_active_crtcs = 0;
1786 rdev->pm.dpm.new_active_crtc_count = 0;
1787 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1788 list_for_each_entry(crtc,
1789 &ddev->mode_config.crtc_list, head) {
1790 radeon_crtc = to_radeon_crtc(crtc);
1791 if (crtc->enabled) {
1792 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1793 rdev->pm.dpm.new_active_crtc_count++;
1794 }
1795 }
1796 }
1797
1798
1799 if (power_supply_is_system_supplied() > 0)
1800 rdev->pm.dpm.ac_power = true;
1801 else
1802 rdev->pm.dpm.ac_power = false;
1803
1804 radeon_dpm_change_power_state_locked(rdev);
1805
1806 mutex_unlock(&rdev->pm.mutex);
1807
1808}
1809
1810void radeon_pm_compute_clocks(struct radeon_device *rdev)
1811{
1812 if (rdev->pm.pm_method == PM_METHOD_DPM)
1813 radeon_pm_compute_clocks_dpm(rdev);
1814 else
1815 radeon_pm_compute_clocks_old(rdev);
1816}
1817
1818static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1819{
1820 int crtc, vpos, hpos, vbl_status;
1821 bool in_vbl = true;
1822
1823
1824
1825
1826 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1827 if (rdev->pm.active_crtcs & (1 << crtc)) {
1828 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev,
1829 crtc,
1830 USE_REAL_VBLANKSTART,
1831 &vpos, &hpos, NULL, NULL,
1832 &rdev->mode_info.crtcs[crtc]->base.hwmode);
1833 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1834 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK))
1835 in_vbl = false;
1836 }
1837 }
1838
1839 return in_vbl;
1840}
1841
1842static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1843{
1844 u32 stat_crtc = 0;
1845 bool in_vbl = radeon_pm_in_vbl(rdev);
1846
1847 if (!in_vbl)
1848 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1849 finish ? "exit" : "entry");
1850 return in_vbl;
1851}
1852
1853static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1854{
1855 struct radeon_device *rdev;
1856 int resched;
1857 rdev = container_of(work, struct radeon_device,
1858 pm.dynpm_idle_work.work);
1859
1860 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1861 mutex_lock(&rdev->pm.mutex);
1862 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1863 int not_processed = 0;
1864 int i;
1865
1866 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1867 struct radeon_ring *ring = &rdev->ring[i];
1868
1869 if (ring->ready) {
1870 not_processed += radeon_fence_count_emitted(rdev, i);
1871 if (not_processed >= 3)
1872 break;
1873 }
1874 }
1875
1876 if (not_processed >= 3) {
1877 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1878 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1879 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1880 rdev->pm.dynpm_can_upclock) {
1881 rdev->pm.dynpm_planned_action =
1882 DYNPM_ACTION_UPCLOCK;
1883 rdev->pm.dynpm_action_timeout = jiffies +
1884 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1885 }
1886 } else if (not_processed == 0) {
1887 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1888 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1889 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1890 rdev->pm.dynpm_can_downclock) {
1891 rdev->pm.dynpm_planned_action =
1892 DYNPM_ACTION_DOWNCLOCK;
1893 rdev->pm.dynpm_action_timeout = jiffies +
1894 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1895 }
1896 }
1897
1898
1899
1900
1901 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1902 jiffies > rdev->pm.dynpm_action_timeout) {
1903 radeon_pm_get_dynpm_state(rdev);
1904 radeon_pm_set_clocks(rdev);
1905 }
1906
1907 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1908 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1909 }
1910 mutex_unlock(&rdev->pm.mutex);
1911 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1912}
1913
1914
1915
1916
1917#if defined(CONFIG_DEBUG_FS)
1918
1919static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1920{
1921 struct drm_info_node *node = (struct drm_info_node *) m->private;
1922 struct drm_device *dev = node->minor->dev;
1923 struct radeon_device *rdev = dev->dev_private;
1924 struct drm_device *ddev = rdev->ddev;
1925
1926 if ((rdev->flags & RADEON_IS_PX) &&
1927 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1928 seq_printf(m, "PX asic powered off\n");
1929 } else if (rdev->pm.dpm_enabled) {
1930 mutex_lock(&rdev->pm.mutex);
1931 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1932 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1933 else
1934 seq_printf(m, "Debugfs support not implemented for this asic\n");
1935 mutex_unlock(&rdev->pm.mutex);
1936 } else {
1937 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1938
1939 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1940 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1941 else
1942 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1943 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1944 if (rdev->asic->pm.get_memory_clock)
1945 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1946 if (rdev->pm.current_vddc)
1947 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1948 if (rdev->asic->pm.get_pcie_lanes)
1949 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1950 }
1951
1952 return 0;
1953}
1954
1955static struct drm_info_list radeon_pm_info_list[] = {
1956 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1957};
1958#endif
1959
1960static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1961{
1962#if defined(CONFIG_DEBUG_FS)
1963 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1964#else
1965 return 0;
1966#endif
1967}
1968
