linux/drivers/gpu/drm/udl/udl_modeset.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2012 Red Hat
   4 *
   5 * based in parts on udlfb.c:
   6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it>
   7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com>
   8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
   9
  10 */
  11
  12#include <linux/dma-buf.h>
  13
  14#include <drm/drm_atomic_helper.h>
  15#include <drm/drm_crtc_helper.h>
  16#include <drm/drm_damage_helper.h>
  17#include <drm/drm_fourcc.h>
  18#include <drm/drm_gem_framebuffer_helper.h>
  19#include <drm/drm_gem_shmem_helper.h>
  20#include <drm/drm_modeset_helper_vtables.h>
  21#include <drm/drm_vblank.h>
  22
  23#include "udl_drv.h"
  24
  25#define UDL_COLOR_DEPTH_16BPP   0
  26
  27/*
  28 * All DisplayLink bulk operations start with 0xAF, followed by specific code
  29 * All operations are written to buffers which then later get sent to device
  30 */
  31static char *udl_set_register(char *buf, u8 reg, u8 val)
  32{
  33        *buf++ = 0xAF;
  34        *buf++ = 0x20;
  35        *buf++ = reg;
  36        *buf++ = val;
  37        return buf;
  38}
  39
  40static char *udl_vidreg_lock(char *buf)
  41{
  42        return udl_set_register(buf, 0xFF, 0x00);
  43}
  44
  45static char *udl_vidreg_unlock(char *buf)
  46{
  47        return udl_set_register(buf, 0xFF, 0xFF);
  48}
  49
  50static char *udl_set_blank_mode(char *buf, u8 mode)
  51{
  52        return udl_set_register(buf, UDL_REG_BLANK_MODE, mode);
  53}
  54
  55static char *udl_set_color_depth(char *buf, u8 selection)
  56{
  57        return udl_set_register(buf, 0x00, selection);
  58}
  59
  60static char *udl_set_base16bpp(char *wrptr, u32 base)
  61{
  62        /* the base pointer is 16 bits wide, 0x20 is hi byte. */
  63        wrptr = udl_set_register(wrptr, 0x20, base >> 16);
  64        wrptr = udl_set_register(wrptr, 0x21, base >> 8);
  65        return udl_set_register(wrptr, 0x22, base);
  66}
  67
  68/*
  69 * DisplayLink HW has separate 16bpp and 8bpp framebuffers.
  70 * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer
  71 */
  72static char *udl_set_base8bpp(char *wrptr, u32 base)
  73{
  74        wrptr = udl_set_register(wrptr, 0x26, base >> 16);
  75        wrptr = udl_set_register(wrptr, 0x27, base >> 8);
  76        return udl_set_register(wrptr, 0x28, base);
  77}
  78
  79static char *udl_set_register_16(char *wrptr, u8 reg, u16 value)
  80{
  81        wrptr = udl_set_register(wrptr, reg, value >> 8);
  82        return udl_set_register(wrptr, reg+1, value);
  83}
  84
  85/*
  86 * This is kind of weird because the controller takes some
  87 * register values in a different byte order than other registers.
  88 */
  89static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value)
  90{
  91        wrptr = udl_set_register(wrptr, reg, value);
  92        return udl_set_register(wrptr, reg+1, value >> 8);
  93}
  94
  95/*
  96 * LFSR is linear feedback shift register. The reason we have this is
  97 * because the display controller needs to minimize the clock depth of
  98 * various counters used in the display path. So this code reverses the
  99 * provided value into the lfsr16 value by counting backwards to get
 100 * the value that needs to be set in the hardware comparator to get the
 101 * same actual count. This makes sense once you read above a couple of
 102 * times and think about it from a hardware perspective.
 103 */
 104static u16 udl_lfsr16(u16 actual_count)
 105{
 106        u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */
 107
 108        while (actual_count--) {
 109                lv =     ((lv << 1) |
 110                        (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1))
 111                        & 0xFFFF;
 112        }
 113
 114        return (u16) lv;
 115}
 116
 117/*
 118 * This does LFSR conversion on the value that is to be written.
 119 * See LFSR explanation above for more detail.
 120 */
 121static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value)
 122{
 123        return udl_set_register_16(wrptr, reg, udl_lfsr16(value));
 124}
 125
 126/*
 127 * This takes a standard fbdev screeninfo struct and all of its monitor mode
 128 * details and converts them into the DisplayLink equivalent register commands.
 129  ERR(vreg(dev,               0x00, (color_depth == 16) ? 0 : 1));
 130  ERR(vreg_lfsr16(dev,        0x01, xDisplayStart));
 131  ERR(vreg_lfsr16(dev,        0x03, xDisplayEnd));
 132  ERR(vreg_lfsr16(dev,        0x05, yDisplayStart));
 133  ERR(vreg_lfsr16(dev,        0x07, yDisplayEnd));
 134  ERR(vreg_lfsr16(dev,        0x09, xEndCount));
 135  ERR(vreg_lfsr16(dev,        0x0B, hSyncStart));
 136  ERR(vreg_lfsr16(dev,        0x0D, hSyncEnd));
 137  ERR(vreg_big_endian(dev,    0x0F, hPixels));
 138  ERR(vreg_lfsr16(dev,        0x11, yEndCount));
 139  ERR(vreg_lfsr16(dev,        0x13, vSyncStart));
 140  ERR(vreg_lfsr16(dev,        0x15, vSyncEnd));
 141  ERR(vreg_big_endian(dev,    0x17, vPixels));
 142  ERR(vreg_little_endian(dev, 0x1B, pixelClock5KHz));
 143
 144  ERR(vreg(dev,               0x1F, 0));
 145
 146  ERR(vbuf(dev, WRITE_VIDREG_UNLOCK, DSIZEOF(WRITE_VIDREG_UNLOCK)));
 147 */
 148static char *udl_set_vid_cmds(char *wrptr, struct drm_display_mode *mode)
 149{
 150        u16 xds, yds;
 151        u16 xde, yde;
 152        u16 yec;
 153
 154        /* x display start */
 155        xds = mode->crtc_htotal - mode->crtc_hsync_start;
 156        wrptr = udl_set_register_lfsr16(wrptr, 0x01, xds);
 157        /* x display end */
 158        xde = xds + mode->crtc_hdisplay;
 159        wrptr = udl_set_register_lfsr16(wrptr, 0x03, xde);
 160
 161        /* y display start */
 162        yds = mode->crtc_vtotal - mode->crtc_vsync_start;
 163        wrptr = udl_set_register_lfsr16(wrptr, 0x05, yds);
 164        /* y display end */
 165        yde = yds + mode->crtc_vdisplay;
 166        wrptr = udl_set_register_lfsr16(wrptr, 0x07, yde);
 167
 168        /* x end count is active + blanking - 1 */
 169        wrptr = udl_set_register_lfsr16(wrptr, 0x09,
 170                                        mode->crtc_htotal - 1);
 171
 172        /* libdlo hardcodes hsync start to 1 */
 173        wrptr = udl_set_register_lfsr16(wrptr, 0x0B, 1);
 174
 175        /* hsync end is width of sync pulse + 1 */
 176        wrptr = udl_set_register_lfsr16(wrptr, 0x0D,
 177                                        mode->crtc_hsync_end - mode->crtc_hsync_start + 1);
 178
 179        /* hpixels is active pixels */
 180        wrptr = udl_set_register_16(wrptr, 0x0F, mode->hdisplay);
 181
 182        /* yendcount is vertical active + vertical blanking */
 183        yec = mode->crtc_vtotal;
 184        wrptr = udl_set_register_lfsr16(wrptr, 0x11, yec);
 185
 186        /* libdlo hardcodes vsync start to 0 */
 187        wrptr = udl_set_register_lfsr16(wrptr, 0x13, 0);
 188
 189        /* vsync end is width of vsync pulse */
 190        wrptr = udl_set_register_lfsr16(wrptr, 0x15, mode->crtc_vsync_end - mode->crtc_vsync_start);
 191
 192        /* vpixels is active pixels */
 193        wrptr = udl_set_register_16(wrptr, 0x17, mode->crtc_vdisplay);
 194
 195        wrptr = udl_set_register_16be(wrptr, 0x1B,
 196                                      mode->clock / 5);
 197
 198        return wrptr;
 199}
 200
 201static char *udl_dummy_render(char *wrptr)
 202{
 203        *wrptr++ = 0xAF;
 204        *wrptr++ = 0x6A; /* copy */
 205        *wrptr++ = 0x00; /* from addr */
 206        *wrptr++ = 0x00;
 207        *wrptr++ = 0x00;
 208        *wrptr++ = 0x01; /* one pixel */
 209        *wrptr++ = 0x00; /* to address */
 210        *wrptr++ = 0x00;
 211        *wrptr++ = 0x00;
 212        return wrptr;
 213}
 214
 215static int udl_crtc_write_mode_to_hw(struct drm_crtc *crtc)
 216{
 217        struct drm_device *dev = crtc->dev;
 218        struct udl_device *udl = to_udl(dev);
 219        struct urb *urb;
 220        char *buf;
 221        int retval;
 222
 223        if (udl->mode_buf_len == 0) {
 224                DRM_ERROR("No mode set\n");
 225                return -EINVAL;
 226        }
 227
 228        urb = udl_get_urb(dev);
 229        if (!urb)
 230                return -ENOMEM;
 231
 232        buf = (char *)urb->transfer_buffer;
 233
 234        memcpy(buf, udl->mode_buf, udl->mode_buf_len);
 235        retval = udl_submit_urb(dev, urb, udl->mode_buf_len);
 236        DRM_DEBUG("write mode info %d\n", udl->mode_buf_len);
 237        return retval;
 238}
 239
 240static long udl_log_cpp(unsigned int cpp)
 241{
 242        if (WARN_ON(!is_power_of_2(cpp)))
 243                return -EINVAL;
 244        return __ffs(cpp);
 245}
 246
 247static int udl_aligned_damage_clip(struct drm_rect *clip, int x, int y,
 248                                   int width, int height)
 249{
 250        int x1, x2;
 251
 252        if (WARN_ON_ONCE(x < 0) ||
 253            WARN_ON_ONCE(y < 0) ||
 254            WARN_ON_ONCE(width < 0) ||
 255            WARN_ON_ONCE(height < 0))
 256                return -EINVAL;
 257
 258        x1 = ALIGN_DOWN(x, sizeof(unsigned long));
 259        x2 = ALIGN(width + (x - x1), sizeof(unsigned long)) + x1;
 260
 261        clip->x1 = x1;
 262        clip->y1 = y;
 263        clip->x2 = x2;
 264        clip->y2 = y + height;
 265
 266        return 0;
 267}
 268
 269static int udl_handle_damage(struct drm_framebuffer *fb, int x, int y,
 270                             int width, int height)
 271{
 272        struct drm_device *dev = fb->dev;
 273        struct dma_buf_attachment *import_attach = fb->obj[0]->import_attach;
 274        int i, ret, tmp_ret;
 275        char *cmd;
 276        struct urb *urb;
 277        struct drm_rect clip;
 278        int log_bpp;
 279        struct dma_buf_map map;
 280        void *vaddr;
 281
 282        ret = udl_log_cpp(fb->format->cpp[0]);
 283        if (ret < 0)
 284                return ret;
 285        log_bpp = ret;
 286
 287        ret = udl_aligned_damage_clip(&clip, x, y, width, height);
 288        if (ret)
 289                return ret;
 290        else if ((clip.x2 > fb->width) || (clip.y2 > fb->height))
 291                return -EINVAL;
 292
 293        if (import_attach) {
 294                ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
 295                                               DMA_FROM_DEVICE);
 296                if (ret)
 297                        return ret;
 298        }
 299
 300        ret = drm_gem_shmem_vmap(fb->obj[0], &map);
 301        if (ret) {
 302                DRM_ERROR("failed to vmap fb\n");
 303                goto out_dma_buf_end_cpu_access;
 304        }
 305        vaddr = map.vaddr; /* TODO: Use mapping abstraction properly */
 306
 307        urb = udl_get_urb(dev);
 308        if (!urb) {
 309                ret = -ENOMEM;
 310                goto out_drm_gem_shmem_vunmap;
 311        }
 312        cmd = urb->transfer_buffer;
 313
 314        for (i = clip.y1; i < clip.y2; i++) {
 315                const int line_offset = fb->pitches[0] * i;
 316                const int byte_offset = line_offset + (clip.x1 << log_bpp);
 317                const int dev_byte_offset = (fb->width * i + clip.x1) << log_bpp;
 318                const int byte_width = (clip.x2 - clip.x1) << log_bpp;
 319                ret = udl_render_hline(dev, log_bpp, &urb, (char *)vaddr,
 320                                       &cmd, byte_offset, dev_byte_offset,
 321                                       byte_width);
 322                if (ret)
 323                        goto out_drm_gem_shmem_vunmap;
 324        }
 325
 326        if (cmd > (char *)urb->transfer_buffer) {
 327                /* Send partial buffer remaining before exiting */
 328                int len;
 329                if (cmd < (char *)urb->transfer_buffer + urb->transfer_buffer_length)
 330                        *cmd++ = 0xAF;
 331                len = cmd - (char *)urb->transfer_buffer;
 332                ret = udl_submit_urb(dev, urb, len);
 333        } else {
 334                udl_urb_completion(urb);
 335        }
 336
 337        ret = 0;
 338
 339out_drm_gem_shmem_vunmap:
 340        drm_gem_shmem_vunmap(fb->obj[0], &map);
 341out_dma_buf_end_cpu_access:
 342        if (import_attach) {
 343                tmp_ret = dma_buf_end_cpu_access(import_attach->dmabuf,
 344                                                 DMA_FROM_DEVICE);
 345                if (tmp_ret && !ret)
 346                        ret = tmp_ret; /* only update ret if not set yet */
 347        }
 348
 349        return ret;
 350}
 351
 352/*
 353 * Simple display pipeline
 354 */
 355
 356static const uint32_t udl_simple_display_pipe_formats[] = {
 357        DRM_FORMAT_RGB565,
 358        DRM_FORMAT_XRGB8888,
 359};
 360
 361static enum drm_mode_status
 362udl_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
 363                                   const struct drm_display_mode *mode)
 364{
 365        return MODE_OK;
 366}
 367
 368static void
 369udl_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe,
 370                               struct drm_crtc_state *crtc_state,
 371                               struct drm_plane_state *plane_state)
 372{
 373        struct drm_crtc *crtc = &pipe->crtc;
 374        struct drm_device *dev = crtc->dev;
 375        struct drm_framebuffer *fb = plane_state->fb;
 376        struct udl_device *udl = to_udl(dev);
 377        struct drm_display_mode *mode = &crtc_state->mode;
 378        char *buf;
 379        char *wrptr;
 380        int color_depth = UDL_COLOR_DEPTH_16BPP;
 381
 382        buf = (char *)udl->mode_buf;
 383
 384        /* This first section has to do with setting the base address on the
 385         * controller associated with the display. There are 2 base
 386         * pointers, currently, we only use the 16 bpp segment.
 387         */
 388        wrptr = udl_vidreg_lock(buf);
 389        wrptr = udl_set_color_depth(wrptr, color_depth);
 390        /* set base for 16bpp segment to 0 */
 391        wrptr = udl_set_base16bpp(wrptr, 0);
 392        /* set base for 8bpp segment to end of fb */
 393        wrptr = udl_set_base8bpp(wrptr, 2 * mode->vdisplay * mode->hdisplay);
 394
 395        wrptr = udl_set_vid_cmds(wrptr, mode);
 396        wrptr = udl_set_blank_mode(wrptr, UDL_BLANK_MODE_ON);
 397        wrptr = udl_vidreg_unlock(wrptr);
 398
 399        wrptr = udl_dummy_render(wrptr);
 400
 401        udl->mode_buf_len = wrptr - buf;
 402
 403        udl_handle_damage(fb, 0, 0, fb->width, fb->height);
 404
 405        if (!crtc_state->mode_changed)
 406                return;
 407
 408        /* enable display */
 409        udl_crtc_write_mode_to_hw(crtc);
 410}
 411
 412static void
 413udl_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe)
 414{
 415        struct drm_crtc *crtc = &pipe->crtc;
 416        struct drm_device *dev = crtc->dev;
 417        struct urb *urb;
 418        char *buf;
 419
 420        urb = udl_get_urb(dev);
 421        if (!urb)
 422                return;
 423
 424        buf = (char *)urb->transfer_buffer;
 425        buf = udl_vidreg_lock(buf);
 426        buf = udl_set_blank_mode(buf, UDL_BLANK_MODE_POWERDOWN);
 427        buf = udl_vidreg_unlock(buf);
 428        buf = udl_dummy_render(buf);
 429
 430        udl_submit_urb(dev, urb, buf - (char *)urb->transfer_buffer);
 431}
 432
 433static void
 434udl_simple_display_pipe_update(struct drm_simple_display_pipe *pipe,
 435                               struct drm_plane_state *old_plane_state)
 436{
 437        struct drm_plane_state *state = pipe->plane.state;
 438        struct drm_framebuffer *fb = state->fb;
 439        struct drm_rect rect;
 440
 441        if (!fb)
 442                return;
 443
 444        if (drm_atomic_helper_damage_merged(old_plane_state, state, &rect))
 445                udl_handle_damage(fb, rect.x1, rect.y1, rect.x2 - rect.x1,
 446                                  rect.y2 - rect.y1);
 447}
 448
 449static const
 450struct drm_simple_display_pipe_funcs udl_simple_display_pipe_funcs = {
 451        .mode_valid = udl_simple_display_pipe_mode_valid,
 452        .enable = udl_simple_display_pipe_enable,
 453        .disable = udl_simple_display_pipe_disable,
 454        .update = udl_simple_display_pipe_update,
 455        .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
 456};
 457
 458/*
 459 * Modesetting
 460 */
 461
 462static const struct drm_mode_config_funcs udl_mode_funcs = {
 463        .fb_create = drm_gem_fb_create_with_dirty,
 464        .atomic_check  = drm_atomic_helper_check,
 465        .atomic_commit = drm_atomic_helper_commit,
 466};
 467
 468int udl_modeset_init(struct drm_device *dev)
 469{
 470        size_t format_count = ARRAY_SIZE(udl_simple_display_pipe_formats);
 471        struct udl_device *udl = to_udl(dev);
 472        struct drm_connector *connector;
 473        int ret;
 474
 475        ret = drmm_mode_config_init(dev);
 476        if (ret)
 477                return ret;
 478
 479        dev->mode_config.min_width = 640;
 480        dev->mode_config.min_height = 480;
 481
 482        dev->mode_config.max_width = 2048;
 483        dev->mode_config.max_height = 2048;
 484
 485        dev->mode_config.prefer_shadow = 0;
 486        dev->mode_config.preferred_depth = 16;
 487
 488        dev->mode_config.funcs = &udl_mode_funcs;
 489
 490        connector = udl_connector_init(dev);
 491        if (IS_ERR(connector))
 492                return PTR_ERR(connector);
 493
 494        format_count = ARRAY_SIZE(udl_simple_display_pipe_formats);
 495
 496        ret = drm_simple_display_pipe_init(dev, &udl->display_pipe,
 497                                           &udl_simple_display_pipe_funcs,
 498                                           udl_simple_display_pipe_formats,
 499                                           format_count, NULL, connector);
 500        if (ret)
 501                return ret;
 502
 503        drm_mode_config_reset(dev);
 504
 505        return 0;
 506}
 507