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15#include <linux/module.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
18#include <linux/delay.h>
19#include <linux/slab.h>
20#include <linux/acpi.h>
21#include <linux/pm.h>
22#include <linux/pm_runtime.h>
23#include <linux/iio/iio.h>
24#include <linux/iio/sysfs.h>
25#include <linux/iio/buffer.h>
26#include <linux/iio/events.h>
27#include <linux/iio/trigger.h>
28#include <linux/iio/trigger_consumer.h>
29#include <linux/iio/triggered_buffer.h>
30#include <linux/regmap.h>
31#include <linux/regulator/consumer.h>
32
33#include "bmc150-accel.h"
34
35#define BMC150_ACCEL_DRV_NAME "bmc150_accel"
36#define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event"
37
38#define BMC150_ACCEL_REG_CHIP_ID 0x00
39
40#define BMC150_ACCEL_REG_INT_STATUS_2 0x0B
41#define BMC150_ACCEL_ANY_MOTION_MASK 0x07
42#define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0)
43#define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1)
44#define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2)
45#define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3)
46
47#define BMC150_ACCEL_REG_PMU_LPW 0x11
48#define BMC150_ACCEL_PMU_MODE_MASK 0xE0
49#define BMC150_ACCEL_PMU_MODE_SHIFT 5
50#define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17
51#define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1
52
53#define BMC150_ACCEL_REG_PMU_RANGE 0x0F
54
55#define BMC150_ACCEL_DEF_RANGE_2G 0x03
56#define BMC150_ACCEL_DEF_RANGE_4G 0x05
57#define BMC150_ACCEL_DEF_RANGE_8G 0x08
58#define BMC150_ACCEL_DEF_RANGE_16G 0x0C
59
60
61#define BMC150_ACCEL_REG_PMU_BW 0x10
62#define BMC150_ACCEL_DEF_BW 125
63
64#define BMC150_ACCEL_REG_RESET 0x14
65#define BMC150_ACCEL_RESET_VAL 0xB6
66
67#define BMC150_ACCEL_REG_INT_MAP_0 0x19
68#define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2)
69
70#define BMC150_ACCEL_REG_INT_MAP_1 0x1A
71#define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0)
72#define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1)
73#define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2)
74
75#define BMC150_ACCEL_REG_INT_RST_LATCH 0x21
76#define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80
77#define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
78#define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00
79
80#define BMC150_ACCEL_REG_INT_EN_0 0x16
81#define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0)
82#define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1)
83#define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2)
84
85#define BMC150_ACCEL_REG_INT_EN_1 0x17
86#define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4)
87#define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5)
88#define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6)
89
90#define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20
91#define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0)
92
93#define BMC150_ACCEL_REG_INT_5 0x27
94#define BMC150_ACCEL_SLOPE_DUR_MASK 0x03
95
96#define BMC150_ACCEL_REG_INT_6 0x28
97#define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF
98
99
100#define BMC150_ACCEL_DEF_SLOPE_DURATION 1
101
102#define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1
103
104#define BMC150_ACCEL_REG_XOUT_L 0x02
105
106#define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100
107
108
109#define BMC150_ACCEL_SLEEP_500_MICRO 0x05
110#define BMC150_ACCEL_SLEEP_1_MS 0x06
111#define BMC150_ACCEL_SLEEP_2_MS 0x07
112#define BMC150_ACCEL_SLEEP_4_MS 0x08
113#define BMC150_ACCEL_SLEEP_6_MS 0x09
114#define BMC150_ACCEL_SLEEP_10_MS 0x0A
115#define BMC150_ACCEL_SLEEP_25_MS 0x0B
116#define BMC150_ACCEL_SLEEP_50_MS 0x0C
117#define BMC150_ACCEL_SLEEP_100_MS 0x0D
118#define BMC150_ACCEL_SLEEP_500_MS 0x0E
119#define BMC150_ACCEL_SLEEP_1_SEC 0x0F
120
121#define BMC150_ACCEL_REG_TEMP 0x08
122#define BMC150_ACCEL_TEMP_CENTER_VAL 23
123
124#define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
125#define BMC150_AUTO_SUSPEND_DELAY_MS 2000
126
127#define BMC150_ACCEL_REG_FIFO_STATUS 0x0E
128#define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30
129#define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E
130#define BMC150_ACCEL_REG_FIFO_DATA 0x3F
131#define BMC150_ACCEL_FIFO_LENGTH 32
132
133enum bmc150_accel_axis {
134 AXIS_X,
135 AXIS_Y,
136 AXIS_Z,
137 AXIS_MAX,
138};
139
140enum bmc150_power_modes {
141 BMC150_ACCEL_SLEEP_MODE_NORMAL,
142 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
143 BMC150_ACCEL_SLEEP_MODE_LPM,
144 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
145};
146
147struct bmc150_scale_info {
148 int scale;
149 u8 reg_range;
150};
151
152struct bmc150_accel_chip_info {
153 const char *name;
154 u8 chip_id;
155 const struct iio_chan_spec *channels;
156 int num_channels;
157 const struct bmc150_scale_info scale_table[4];
158};
159
160struct bmc150_accel_interrupt {
161 const struct bmc150_accel_interrupt_info *info;
162 atomic_t users;
163};
164
165struct bmc150_accel_trigger {
166 struct bmc150_accel_data *data;
167 struct iio_trigger *indio_trig;
168 int (*setup)(struct bmc150_accel_trigger *t, bool state);
169 int intr;
170 bool enabled;
171};
172
173enum bmc150_accel_interrupt_id {
174 BMC150_ACCEL_INT_DATA_READY,
175 BMC150_ACCEL_INT_ANY_MOTION,
176 BMC150_ACCEL_INT_WATERMARK,
177 BMC150_ACCEL_INTERRUPTS,
178};
179
180enum bmc150_accel_trigger_id {
181 BMC150_ACCEL_TRIGGER_DATA_READY,
182 BMC150_ACCEL_TRIGGER_ANY_MOTION,
183 BMC150_ACCEL_TRIGGERS,
184};
185
186struct bmc150_accel_data {
187 struct regmap *regmap;
188 struct regulator_bulk_data regulators[2];
189 struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
190 struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
191 struct mutex mutex;
192 u8 fifo_mode, watermark;
193 s16 buffer[8];
194
195
196
197
198 struct {
199 __le16 channels[3];
200 s64 ts __aligned(8);
201 } scan;
202 u8 bw_bits;
203 u32 slope_dur;
204 u32 slope_thres;
205 u32 range;
206 int ev_enable_state;
207 int64_t timestamp, old_timestamp;
208 const struct bmc150_accel_chip_info *chip_info;
209 struct i2c_client *second_device;
210 struct iio_mount_matrix orientation;
211};
212
213static const struct {
214 int val;
215 int val2;
216 u8 bw_bits;
217} bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
218 {31, 260000, 0x09},
219 {62, 500000, 0x0A},
220 {125, 0, 0x0B},
221 {250, 0, 0x0C},
222 {500, 0, 0x0D},
223 {1000, 0, 0x0E},
224 {2000, 0, 0x0F} };
225
226static const struct {
227 int bw_bits;
228 int msec;
229} bmc150_accel_sample_upd_time[] = { {0x08, 64},
230 {0x09, 32},
231 {0x0A, 16},
232 {0x0B, 8},
233 {0x0C, 4},
234 {0x0D, 2},
235 {0x0E, 1},
236 {0x0F, 1} };
237
238static const struct {
239 int sleep_dur;
240 u8 reg_value;
241} bmc150_accel_sleep_value_table[] = { {0, 0},
242 {500, BMC150_ACCEL_SLEEP_500_MICRO},
243 {1000, BMC150_ACCEL_SLEEP_1_MS},
244 {2000, BMC150_ACCEL_SLEEP_2_MS},
245 {4000, BMC150_ACCEL_SLEEP_4_MS},
246 {6000, BMC150_ACCEL_SLEEP_6_MS},
247 {10000, BMC150_ACCEL_SLEEP_10_MS},
248 {25000, BMC150_ACCEL_SLEEP_25_MS},
249 {50000, BMC150_ACCEL_SLEEP_50_MS},
250 {100000, BMC150_ACCEL_SLEEP_100_MS},
251 {500000, BMC150_ACCEL_SLEEP_500_MS},
252 {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
253
254const struct regmap_config bmc150_regmap_conf = {
255 .reg_bits = 8,
256 .val_bits = 8,
257 .max_register = 0x3f,
258};
259EXPORT_SYMBOL_GPL(bmc150_regmap_conf);
260
261static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
262 enum bmc150_power_modes mode,
263 int dur_us)
264{
265 struct device *dev = regmap_get_device(data->regmap);
266 int i;
267 int ret;
268 u8 lpw_bits;
269 int dur_val = -1;
270
271 if (dur_us > 0) {
272 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
273 ++i) {
274 if (bmc150_accel_sleep_value_table[i].sleep_dur ==
275 dur_us)
276 dur_val =
277 bmc150_accel_sleep_value_table[i].reg_value;
278 }
279 } else {
280 dur_val = 0;
281 }
282
283 if (dur_val < 0)
284 return -EINVAL;
285
286 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
287 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
288
289 dev_dbg(dev, "Set Mode bits %x\n", lpw_bits);
290
291 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
292 if (ret < 0) {
293 dev_err(dev, "Error writing reg_pmu_lpw\n");
294 return ret;
295 }
296
297 return 0;
298}
299
300static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
301 int val2)
302{
303 int i;
304 int ret;
305
306 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
307 if (bmc150_accel_samp_freq_table[i].val == val &&
308 bmc150_accel_samp_freq_table[i].val2 == val2) {
309 ret = regmap_write(data->regmap,
310 BMC150_ACCEL_REG_PMU_BW,
311 bmc150_accel_samp_freq_table[i].bw_bits);
312 if (ret < 0)
313 return ret;
314
315 data->bw_bits =
316 bmc150_accel_samp_freq_table[i].bw_bits;
317 return 0;
318 }
319 }
320
321 return -EINVAL;
322}
323
324static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
325{
326 struct device *dev = regmap_get_device(data->regmap);
327 int ret;
328
329 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
330 data->slope_thres);
331 if (ret < 0) {
332 dev_err(dev, "Error writing reg_int_6\n");
333 return ret;
334 }
335
336 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
337 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
338 if (ret < 0) {
339 dev_err(dev, "Error updating reg_int_5\n");
340 return ret;
341 }
342
343 dev_dbg(dev, "%x %x\n", data->slope_thres, data->slope_dur);
344
345 return ret;
346}
347
348static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
349 bool state)
350{
351 if (state)
352 return bmc150_accel_update_slope(t->data);
353
354 return 0;
355}
356
357static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
358 int *val2)
359{
360 int i;
361
362 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
363 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
364 *val = bmc150_accel_samp_freq_table[i].val;
365 *val2 = bmc150_accel_samp_freq_table[i].val2;
366 return IIO_VAL_INT_PLUS_MICRO;
367 }
368 }
369
370 return -EINVAL;
371}
372
373#ifdef CONFIG_PM
374static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
375{
376 int i;
377
378 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
379 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
380 return bmc150_accel_sample_upd_time[i].msec;
381 }
382
383 return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
384}
385
386static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
387{
388 struct device *dev = regmap_get_device(data->regmap);
389 int ret;
390
391 if (on) {
392 ret = pm_runtime_get_sync(dev);
393 } else {
394 pm_runtime_mark_last_busy(dev);
395 ret = pm_runtime_put_autosuspend(dev);
396 }
397
398 if (ret < 0) {
399 dev_err(dev,
400 "Failed: %s for %d\n", __func__, on);
401 if (on)
402 pm_runtime_put_noidle(dev);
403
404 return ret;
405 }
406
407 return 0;
408}
409#else
410static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
411{
412 return 0;
413}
414#endif
415
416#ifdef CONFIG_ACPI
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442static bool bmc150_apply_acpi_orientation(struct device *dev,
443 struct iio_mount_matrix *orientation)
444{
445 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
446 struct acpi_device *adev = ACPI_COMPANION(dev);
447 union acpi_object *obj, *elements;
448 char *name, *alt_name, *str;
449 acpi_status status;
450 int i, j, val[3];
451
452 if (!adev || !acpi_dev_hid_uid_match(adev, "BOSC0200", NULL))
453 return false;
454
455 if (strcmp(dev_name(dev), "i2c-BOSC0200:base") == 0)
456 alt_name = "ROMK";
457 else
458 alt_name = "ROMS";
459
460 if (acpi_has_method(adev->handle, "ROTM"))
461 name = "ROTM";
462 else if (acpi_has_method(adev->handle, alt_name))
463 name = alt_name;
464 else
465 return false;
466
467 status = acpi_evaluate_object(adev->handle, name, NULL, &buffer);
468 if (ACPI_FAILURE(status)) {
469 dev_warn(dev, "Failed to get ACPI mount matrix: %d\n", status);
470 return false;
471 }
472
473 obj = buffer.pointer;
474 if (obj->type != ACPI_TYPE_PACKAGE || obj->package.count != 3)
475 goto unknown_format;
476
477 elements = obj->package.elements;
478 for (i = 0; i < 3; i++) {
479 if (elements[i].type != ACPI_TYPE_STRING)
480 goto unknown_format;
481
482 str = elements[i].string.pointer;
483 if (sscanf(str, "%d %d %d", &val[0], &val[1], &val[2]) != 3)
484 goto unknown_format;
485
486 for (j = 0; j < 3; j++) {
487 switch (val[j]) {
488 case -1: str = "-1"; break;
489 case 0: str = "0"; break;
490 case 1: str = "1"; break;
491 default: goto unknown_format;
492 }
493 orientation->rotation[i * 3 + j] = str;
494 }
495 }
496
497 kfree(buffer.pointer);
498 return true;
499
500unknown_format:
501 dev_warn(dev, "Unknown ACPI mount matrix format, ignoring\n");
502 kfree(buffer.pointer);
503 return false;
504}
505#else
506static bool bmc150_apply_acpi_orientation(struct device *dev,
507 struct iio_mount_matrix *orientation)
508{
509 return false;
510}
511#endif
512
513static const struct bmc150_accel_interrupt_info {
514 u8 map_reg;
515 u8 map_bitmask;
516 u8 en_reg;
517 u8 en_bitmask;
518} bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
519 {
520 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
521 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
522 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
523 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
524 },
525 {
526 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
527 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
528 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
529 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X |
530 BMC150_ACCEL_INT_EN_BIT_SLP_Y |
531 BMC150_ACCEL_INT_EN_BIT_SLP_Z
532 },
533 {
534 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
535 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
536 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
537 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
538 },
539};
540
541static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
542 struct bmc150_accel_data *data)
543{
544 int i;
545
546 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
547 data->interrupts[i].info = &bmc150_accel_interrupts[i];
548}
549
550static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
551 bool state)
552{
553 struct device *dev = regmap_get_device(data->regmap);
554 struct bmc150_accel_interrupt *intr = &data->interrupts[i];
555 const struct bmc150_accel_interrupt_info *info = intr->info;
556 int ret;
557
558 if (state) {
559 if (atomic_inc_return(&intr->users) > 1)
560 return 0;
561 } else {
562 if (atomic_dec_return(&intr->users) > 0)
563 return 0;
564 }
565
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573
574
575 ret = bmc150_accel_set_power_state(data, state);
576 if (ret < 0)
577 return ret;
578
579
580 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
581 (state ? info->map_bitmask : 0));
582 if (ret < 0) {
583 dev_err(dev, "Error updating reg_int_map\n");
584 goto out_fix_power_state;
585 }
586
587
588 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
589 (state ? info->en_bitmask : 0));
590 if (ret < 0) {
591 dev_err(dev, "Error updating reg_int_en\n");
592 goto out_fix_power_state;
593 }
594
595 return 0;
596
597out_fix_power_state:
598 bmc150_accel_set_power_state(data, false);
599 return ret;
600}
601
602static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
603{
604 struct device *dev = regmap_get_device(data->regmap);
605 int ret, i;
606
607 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
608 if (data->chip_info->scale_table[i].scale == val) {
609 ret = regmap_write(data->regmap,
610 BMC150_ACCEL_REG_PMU_RANGE,
611 data->chip_info->scale_table[i].reg_range);
612 if (ret < 0) {
613 dev_err(dev, "Error writing pmu_range\n");
614 return ret;
615 }
616
617 data->range = data->chip_info->scale_table[i].reg_range;
618 return 0;
619 }
620 }
621
622 return -EINVAL;
623}
624
625static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
626{
627 struct device *dev = regmap_get_device(data->regmap);
628 int ret;
629 unsigned int value;
630
631 mutex_lock(&data->mutex);
632
633 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
634 if (ret < 0) {
635 dev_err(dev, "Error reading reg_temp\n");
636 mutex_unlock(&data->mutex);
637 return ret;
638 }
639 *val = sign_extend32(value, 7);
640
641 mutex_unlock(&data->mutex);
642
643 return IIO_VAL_INT;
644}
645
646static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
647 struct iio_chan_spec const *chan,
648 int *val)
649{
650 struct device *dev = regmap_get_device(data->regmap);
651 int ret;
652 int axis = chan->scan_index;
653 __le16 raw_val;
654
655 mutex_lock(&data->mutex);
656 ret = bmc150_accel_set_power_state(data, true);
657 if (ret < 0) {
658 mutex_unlock(&data->mutex);
659 return ret;
660 }
661
662 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
663 &raw_val, sizeof(raw_val));
664 if (ret < 0) {
665 dev_err(dev, "Error reading axis %d\n", axis);
666 bmc150_accel_set_power_state(data, false);
667 mutex_unlock(&data->mutex);
668 return ret;
669 }
670 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
671 chan->scan_type.realbits - 1);
672 ret = bmc150_accel_set_power_state(data, false);
673 mutex_unlock(&data->mutex);
674 if (ret < 0)
675 return ret;
676
677 return IIO_VAL_INT;
678}
679
680static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
681 struct iio_chan_spec const *chan,
682 int *val, int *val2, long mask)
683{
684 struct bmc150_accel_data *data = iio_priv(indio_dev);
685 int ret;
686
687 switch (mask) {
688 case IIO_CHAN_INFO_RAW:
689 switch (chan->type) {
690 case IIO_TEMP:
691 return bmc150_accel_get_temp(data, val);
692 case IIO_ACCEL:
693 if (iio_buffer_enabled(indio_dev))
694 return -EBUSY;
695 else
696 return bmc150_accel_get_axis(data, chan, val);
697 default:
698 return -EINVAL;
699 }
700 case IIO_CHAN_INFO_OFFSET:
701 if (chan->type == IIO_TEMP) {
702 *val = BMC150_ACCEL_TEMP_CENTER_VAL;
703 return IIO_VAL_INT;
704 } else {
705 return -EINVAL;
706 }
707 case IIO_CHAN_INFO_SCALE:
708 *val = 0;
709 switch (chan->type) {
710 case IIO_TEMP:
711 *val2 = 500000;
712 return IIO_VAL_INT_PLUS_MICRO;
713 case IIO_ACCEL:
714 {
715 int i;
716 const struct bmc150_scale_info *si;
717 int st_size = ARRAY_SIZE(data->chip_info->scale_table);
718
719 for (i = 0; i < st_size; ++i) {
720 si = &data->chip_info->scale_table[i];
721 if (si->reg_range == data->range) {
722 *val2 = si->scale;
723 return IIO_VAL_INT_PLUS_MICRO;
724 }
725 }
726 return -EINVAL;
727 }
728 default:
729 return -EINVAL;
730 }
731 case IIO_CHAN_INFO_SAMP_FREQ:
732 mutex_lock(&data->mutex);
733 ret = bmc150_accel_get_bw(data, val, val2);
734 mutex_unlock(&data->mutex);
735 return ret;
736 default:
737 return -EINVAL;
738 }
739}
740
741static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
742 struct iio_chan_spec const *chan,
743 int val, int val2, long mask)
744{
745 struct bmc150_accel_data *data = iio_priv(indio_dev);
746 int ret;
747
748 switch (mask) {
749 case IIO_CHAN_INFO_SAMP_FREQ:
750 mutex_lock(&data->mutex);
751 ret = bmc150_accel_set_bw(data, val, val2);
752 mutex_unlock(&data->mutex);
753 break;
754 case IIO_CHAN_INFO_SCALE:
755 if (val)
756 return -EINVAL;
757
758 mutex_lock(&data->mutex);
759 ret = bmc150_accel_set_scale(data, val2);
760 mutex_unlock(&data->mutex);
761 return ret;
762 default:
763 ret = -EINVAL;
764 }
765
766 return ret;
767}
768
769static int bmc150_accel_read_event(struct iio_dev *indio_dev,
770 const struct iio_chan_spec *chan,
771 enum iio_event_type type,
772 enum iio_event_direction dir,
773 enum iio_event_info info,
774 int *val, int *val2)
775{
776 struct bmc150_accel_data *data = iio_priv(indio_dev);
777
778 *val2 = 0;
779 switch (info) {
780 case IIO_EV_INFO_VALUE:
781 *val = data->slope_thres;
782 break;
783 case IIO_EV_INFO_PERIOD:
784 *val = data->slope_dur;
785 break;
786 default:
787 return -EINVAL;
788 }
789
790 return IIO_VAL_INT;
791}
792
793static int bmc150_accel_write_event(struct iio_dev *indio_dev,
794 const struct iio_chan_spec *chan,
795 enum iio_event_type type,
796 enum iio_event_direction dir,
797 enum iio_event_info info,
798 int val, int val2)
799{
800 struct bmc150_accel_data *data = iio_priv(indio_dev);
801
802 if (data->ev_enable_state)
803 return -EBUSY;
804
805 switch (info) {
806 case IIO_EV_INFO_VALUE:
807 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
808 break;
809 case IIO_EV_INFO_PERIOD:
810 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
811 break;
812 default:
813 return -EINVAL;
814 }
815
816 return 0;
817}
818
819static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
820 const struct iio_chan_spec *chan,
821 enum iio_event_type type,
822 enum iio_event_direction dir)
823{
824 struct bmc150_accel_data *data = iio_priv(indio_dev);
825
826 return data->ev_enable_state;
827}
828
829static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
830 const struct iio_chan_spec *chan,
831 enum iio_event_type type,
832 enum iio_event_direction dir,
833 int state)
834{
835 struct bmc150_accel_data *data = iio_priv(indio_dev);
836 int ret;
837
838 if (state == data->ev_enable_state)
839 return 0;
840
841 mutex_lock(&data->mutex);
842
843 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
844 state);
845 if (ret < 0) {
846 mutex_unlock(&data->mutex);
847 return ret;
848 }
849
850 data->ev_enable_state = state;
851 mutex_unlock(&data->mutex);
852
853 return 0;
854}
855
856static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
857 struct iio_trigger *trig)
858{
859 struct bmc150_accel_data *data = iio_priv(indio_dev);
860 int i;
861
862 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
863 if (data->triggers[i].indio_trig == trig)
864 return 0;
865 }
866
867 return -EINVAL;
868}
869
870static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
871 struct device_attribute *attr,
872 char *buf)
873{
874 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
875 struct bmc150_accel_data *data = iio_priv(indio_dev);
876 int wm;
877
878 mutex_lock(&data->mutex);
879 wm = data->watermark;
880 mutex_unlock(&data->mutex);
881
882 return sprintf(buf, "%d\n", wm);
883}
884
885static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
886 struct device_attribute *attr,
887 char *buf)
888{
889 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
890 struct bmc150_accel_data *data = iio_priv(indio_dev);
891 bool state;
892
893 mutex_lock(&data->mutex);
894 state = data->fifo_mode;
895 mutex_unlock(&data->mutex);
896
897 return sprintf(buf, "%d\n", state);
898}
899
900static const struct iio_mount_matrix *
901bmc150_accel_get_mount_matrix(const struct iio_dev *indio_dev,
902 const struct iio_chan_spec *chan)
903{
904 struct bmc150_accel_data *data = iio_priv(indio_dev);
905
906 return &data->orientation;
907}
908
909static const struct iio_chan_spec_ext_info bmc150_accel_ext_info[] = {
910 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmc150_accel_get_mount_matrix),
911 { }
912};
913
914static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
915static IIO_CONST_ATTR(hwfifo_watermark_max,
916 __stringify(BMC150_ACCEL_FIFO_LENGTH));
917static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
918 bmc150_accel_get_fifo_state, NULL, 0);
919static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
920 bmc150_accel_get_fifo_watermark, NULL, 0);
921
922static const struct attribute *bmc150_accel_fifo_attributes[] = {
923 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
924 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
925 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
926 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
927 NULL,
928};
929
930static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
931{
932 struct bmc150_accel_data *data = iio_priv(indio_dev);
933
934 if (val > BMC150_ACCEL_FIFO_LENGTH)
935 val = BMC150_ACCEL_FIFO_LENGTH;
936
937 mutex_lock(&data->mutex);
938 data->watermark = val;
939 mutex_unlock(&data->mutex);
940
941 return 0;
942}
943
944
945
946
947
948static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
949 char *buffer, int samples)
950{
951 struct device *dev = regmap_get_device(data->regmap);
952 int sample_length = 3 * 2;
953 int ret;
954 int total_length = samples * sample_length;
955
956 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
957 buffer, total_length);
958 if (ret)
959 dev_err(dev,
960 "Error transferring data from fifo: %d\n", ret);
961
962 return ret;
963}
964
965static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
966 unsigned samples, bool irq)
967{
968 struct bmc150_accel_data *data = iio_priv(indio_dev);
969 struct device *dev = regmap_get_device(data->regmap);
970 int ret, i;
971 u8 count;
972 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
973 int64_t tstamp;
974 uint64_t sample_period;
975 unsigned int val;
976
977 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
978 if (ret < 0) {
979 dev_err(dev, "Error reading reg_fifo_status\n");
980 return ret;
981 }
982
983 count = val & 0x7F;
984
985 if (!count)
986 return 0;
987
988
989
990
991
992
993
994
995
996 if (!irq) {
997 data->old_timestamp = data->timestamp;
998 data->timestamp = iio_get_time_ns(indio_dev);
999 }
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015 sample_period = (data->timestamp - data->old_timestamp);
1016 do_div(sample_period, count);
1017 tstamp = data->timestamp - (count - 1) * sample_period;
1018
1019 if (samples && count > samples)
1020 count = samples;
1021
1022 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
1023 if (ret)
1024 return ret;
1025
1026
1027
1028
1029
1030
1031
1032 for (i = 0; i < count; i++) {
1033 int j, bit;
1034
1035 j = 0;
1036 for_each_set_bit(bit, indio_dev->active_scan_mask,
1037 indio_dev->masklength)
1038 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit],
1039 sizeof(data->scan.channels[0]));
1040
1041 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
1042 tstamp);
1043
1044 tstamp += sample_period;
1045 }
1046
1047 return count;
1048}
1049
1050static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
1051{
1052 struct bmc150_accel_data *data = iio_priv(indio_dev);
1053 int ret;
1054
1055 mutex_lock(&data->mutex);
1056 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
1057 mutex_unlock(&data->mutex);
1058
1059 return ret;
1060}
1061
1062static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
1063 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
1064
1065static struct attribute *bmc150_accel_attributes[] = {
1066 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1067 NULL,
1068};
1069
1070static const struct attribute_group bmc150_accel_attrs_group = {
1071 .attrs = bmc150_accel_attributes,
1072};
1073
1074static const struct iio_event_spec bmc150_accel_event = {
1075 .type = IIO_EV_TYPE_ROC,
1076 .dir = IIO_EV_DIR_EITHER,
1077 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
1078 BIT(IIO_EV_INFO_ENABLE) |
1079 BIT(IIO_EV_INFO_PERIOD)
1080};
1081
1082#define BMC150_ACCEL_CHANNEL(_axis, bits) { \
1083 .type = IIO_ACCEL, \
1084 .modified = 1, \
1085 .channel2 = IIO_MOD_##_axis, \
1086 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
1087 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
1088 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1089 .scan_index = AXIS_##_axis, \
1090 .scan_type = { \
1091 .sign = 's', \
1092 .realbits = (bits), \
1093 .storagebits = 16, \
1094 .shift = 16 - (bits), \
1095 .endianness = IIO_LE, \
1096 }, \
1097 .ext_info = bmc150_accel_ext_info, \
1098 .event_spec = &bmc150_accel_event, \
1099 .num_event_specs = 1 \
1100}
1101
1102#define BMC150_ACCEL_CHANNELS(bits) { \
1103 { \
1104 .type = IIO_TEMP, \
1105 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1106 BIT(IIO_CHAN_INFO_SCALE) | \
1107 BIT(IIO_CHAN_INFO_OFFSET), \
1108 .scan_index = -1, \
1109 }, \
1110 BMC150_ACCEL_CHANNEL(X, bits), \
1111 BMC150_ACCEL_CHANNEL(Y, bits), \
1112 BMC150_ACCEL_CHANNEL(Z, bits), \
1113 IIO_CHAN_SOFT_TIMESTAMP(3), \
1114}
1115
1116static const struct iio_chan_spec bma222e_accel_channels[] =
1117 BMC150_ACCEL_CHANNELS(8);
1118static const struct iio_chan_spec bma250e_accel_channels[] =
1119 BMC150_ACCEL_CHANNELS(10);
1120static const struct iio_chan_spec bmc150_accel_channels[] =
1121 BMC150_ACCEL_CHANNELS(12);
1122static const struct iio_chan_spec bma280_accel_channels[] =
1123 BMC150_ACCEL_CHANNELS(14);
1124
1125static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1126 [bmc150] = {
1127 .name = "BMC150A",
1128 .chip_id = 0xFA,
1129 .channels = bmc150_accel_channels,
1130 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1131 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1132 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1133 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1134 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1135 },
1136 [bmi055] = {
1137 .name = "BMI055A",
1138 .chip_id = 0xFA,
1139 .channels = bmc150_accel_channels,
1140 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1141 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1142 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1143 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1144 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1145 },
1146 [bma255] = {
1147 .name = "BMA0255",
1148 .chip_id = 0xFA,
1149 .channels = bmc150_accel_channels,
1150 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1151 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1152 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1153 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1154 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1155 },
1156 [bma250e] = {
1157 .name = "BMA250E",
1158 .chip_id = 0xF9,
1159 .channels = bma250e_accel_channels,
1160 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1161 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1162 {76590, BMC150_ACCEL_DEF_RANGE_4G},
1163 {153277, BMC150_ACCEL_DEF_RANGE_8G},
1164 {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1165 },
1166 [bma222] = {
1167 .name = "BMA222",
1168 .chip_id = 0x03,
1169 .channels = bma222e_accel_channels,
1170 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1171
1172
1173
1174
1175 .scale_table = { {156000, BMC150_ACCEL_DEF_RANGE_2G},
1176 {313000, BMC150_ACCEL_DEF_RANGE_4G},
1177 {625000, BMC150_ACCEL_DEF_RANGE_8G},
1178 {1250000, BMC150_ACCEL_DEF_RANGE_16G} },
1179 },
1180 [bma222e] = {
1181 .name = "BMA222E",
1182 .chip_id = 0xF8,
1183 .channels = bma222e_accel_channels,
1184 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1185 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1186 {306457, BMC150_ACCEL_DEF_RANGE_4G},
1187 {612915, BMC150_ACCEL_DEF_RANGE_8G},
1188 {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1189 },
1190 [bma280] = {
1191 .name = "BMA0280",
1192 .chip_id = 0xFB,
1193 .channels = bma280_accel_channels,
1194 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1195 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1196 {4785, BMC150_ACCEL_DEF_RANGE_4G},
1197 {9581, BMC150_ACCEL_DEF_RANGE_8G},
1198 {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1199 },
1200};
1201
1202static const struct iio_info bmc150_accel_info = {
1203 .attrs = &bmc150_accel_attrs_group,
1204 .read_raw = bmc150_accel_read_raw,
1205 .write_raw = bmc150_accel_write_raw,
1206 .read_event_value = bmc150_accel_read_event,
1207 .write_event_value = bmc150_accel_write_event,
1208 .write_event_config = bmc150_accel_write_event_config,
1209 .read_event_config = bmc150_accel_read_event_config,
1210};
1211
1212static const struct iio_info bmc150_accel_info_fifo = {
1213 .attrs = &bmc150_accel_attrs_group,
1214 .read_raw = bmc150_accel_read_raw,
1215 .write_raw = bmc150_accel_write_raw,
1216 .read_event_value = bmc150_accel_read_event,
1217 .write_event_value = bmc150_accel_write_event,
1218 .write_event_config = bmc150_accel_write_event_config,
1219 .read_event_config = bmc150_accel_read_event_config,
1220 .validate_trigger = bmc150_accel_validate_trigger,
1221 .hwfifo_set_watermark = bmc150_accel_set_watermark,
1222 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1223};
1224
1225static const unsigned long bmc150_accel_scan_masks[] = {
1226 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
1227 0};
1228
1229static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1230{
1231 struct iio_poll_func *pf = p;
1232 struct iio_dev *indio_dev = pf->indio_dev;
1233 struct bmc150_accel_data *data = iio_priv(indio_dev);
1234 int ret;
1235
1236 mutex_lock(&data->mutex);
1237 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L,
1238 data->buffer, AXIS_MAX * 2);
1239 mutex_unlock(&data->mutex);
1240 if (ret < 0)
1241 goto err_read;
1242
1243 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1244 pf->timestamp);
1245err_read:
1246 iio_trigger_notify_done(indio_dev->trig);
1247
1248 return IRQ_HANDLED;
1249}
1250
1251static void bmc150_accel_trig_reen(struct iio_trigger *trig)
1252{
1253 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1254 struct bmc150_accel_data *data = t->data;
1255 struct device *dev = regmap_get_device(data->regmap);
1256 int ret;
1257
1258
1259 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1260 return;
1261
1262 mutex_lock(&data->mutex);
1263
1264 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1265 BMC150_ACCEL_INT_MODE_LATCH_INT |
1266 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1267 mutex_unlock(&data->mutex);
1268 if (ret < 0)
1269 dev_err(dev, "Error writing reg_int_rst_latch\n");
1270}
1271
1272static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1273 bool state)
1274{
1275 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1276 struct bmc150_accel_data *data = t->data;
1277 int ret;
1278
1279 mutex_lock(&data->mutex);
1280
1281 if (t->enabled == state) {
1282 mutex_unlock(&data->mutex);
1283 return 0;
1284 }
1285
1286 if (t->setup) {
1287 ret = t->setup(t, state);
1288 if (ret < 0) {
1289 mutex_unlock(&data->mutex);
1290 return ret;
1291 }
1292 }
1293
1294 ret = bmc150_accel_set_interrupt(data, t->intr, state);
1295 if (ret < 0) {
1296 mutex_unlock(&data->mutex);
1297 return ret;
1298 }
1299
1300 t->enabled = state;
1301
1302 mutex_unlock(&data->mutex);
1303
1304 return ret;
1305}
1306
1307static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1308 .set_trigger_state = bmc150_accel_trigger_set_state,
1309 .reenable = bmc150_accel_trig_reen,
1310};
1311
1312static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1313{
1314 struct bmc150_accel_data *data = iio_priv(indio_dev);
1315 struct device *dev = regmap_get_device(data->regmap);
1316 int dir;
1317 int ret;
1318 unsigned int val;
1319
1320 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1321 if (ret < 0) {
1322 dev_err(dev, "Error reading reg_int_status_2\n");
1323 return ret;
1324 }
1325
1326 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1327 dir = IIO_EV_DIR_FALLING;
1328 else
1329 dir = IIO_EV_DIR_RISING;
1330
1331 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1332 iio_push_event(indio_dev,
1333 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1334 0,
1335 IIO_MOD_X,
1336 IIO_EV_TYPE_ROC,
1337 dir),
1338 data->timestamp);
1339
1340 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1341 iio_push_event(indio_dev,
1342 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1343 0,
1344 IIO_MOD_Y,
1345 IIO_EV_TYPE_ROC,
1346 dir),
1347 data->timestamp);
1348
1349 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1350 iio_push_event(indio_dev,
1351 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1352 0,
1353 IIO_MOD_Z,
1354 IIO_EV_TYPE_ROC,
1355 dir),
1356 data->timestamp);
1357
1358 return ret;
1359}
1360
1361static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1362{
1363 struct iio_dev *indio_dev = private;
1364 struct bmc150_accel_data *data = iio_priv(indio_dev);
1365 struct device *dev = regmap_get_device(data->regmap);
1366 bool ack = false;
1367 int ret;
1368
1369 mutex_lock(&data->mutex);
1370
1371 if (data->fifo_mode) {
1372 ret = __bmc150_accel_fifo_flush(indio_dev,
1373 BMC150_ACCEL_FIFO_LENGTH, true);
1374 if (ret > 0)
1375 ack = true;
1376 }
1377
1378 if (data->ev_enable_state) {
1379 ret = bmc150_accel_handle_roc_event(indio_dev);
1380 if (ret > 0)
1381 ack = true;
1382 }
1383
1384 if (ack) {
1385 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1386 BMC150_ACCEL_INT_MODE_LATCH_INT |
1387 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1388 if (ret)
1389 dev_err(dev, "Error writing reg_int_rst_latch\n");
1390
1391 ret = IRQ_HANDLED;
1392 } else {
1393 ret = IRQ_NONE;
1394 }
1395
1396 mutex_unlock(&data->mutex);
1397
1398 return ret;
1399}
1400
1401static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1402{
1403 struct iio_dev *indio_dev = private;
1404 struct bmc150_accel_data *data = iio_priv(indio_dev);
1405 bool ack = false;
1406 int i;
1407
1408 data->old_timestamp = data->timestamp;
1409 data->timestamp = iio_get_time_ns(indio_dev);
1410
1411 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1412 if (data->triggers[i].enabled) {
1413 iio_trigger_poll(data->triggers[i].indio_trig);
1414 ack = true;
1415 break;
1416 }
1417 }
1418
1419 if (data->ev_enable_state || data->fifo_mode)
1420 return IRQ_WAKE_THREAD;
1421
1422 if (ack)
1423 return IRQ_HANDLED;
1424
1425 return IRQ_NONE;
1426}
1427
1428static const struct {
1429 int intr;
1430 const char *name;
1431 int (*setup)(struct bmc150_accel_trigger *t, bool state);
1432} bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1433 {
1434 .intr = 0,
1435 .name = "%s-dev%d",
1436 },
1437 {
1438 .intr = 1,
1439 .name = "%s-any-motion-dev%d",
1440 .setup = bmc150_accel_any_motion_setup,
1441 },
1442};
1443
1444static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1445 int from)
1446{
1447 int i;
1448
1449 for (i = from; i >= 0; i--) {
1450 if (data->triggers[i].indio_trig) {
1451 iio_trigger_unregister(data->triggers[i].indio_trig);
1452 data->triggers[i].indio_trig = NULL;
1453 }
1454 }
1455}
1456
1457static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1458 struct bmc150_accel_data *data)
1459{
1460 struct device *dev = regmap_get_device(data->regmap);
1461 int i, ret;
1462
1463 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1464 struct bmc150_accel_trigger *t = &data->triggers[i];
1465
1466 t->indio_trig = devm_iio_trigger_alloc(dev,
1467 bmc150_accel_triggers[i].name,
1468 indio_dev->name,
1469 indio_dev->id);
1470 if (!t->indio_trig) {
1471 ret = -ENOMEM;
1472 break;
1473 }
1474
1475 t->indio_trig->dev.parent = dev;
1476 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1477 t->intr = bmc150_accel_triggers[i].intr;
1478 t->data = data;
1479 t->setup = bmc150_accel_triggers[i].setup;
1480 iio_trigger_set_drvdata(t->indio_trig, t);
1481
1482 ret = iio_trigger_register(t->indio_trig);
1483 if (ret)
1484 break;
1485 }
1486
1487 if (ret)
1488 bmc150_accel_unregister_triggers(data, i - 1);
1489
1490 return ret;
1491}
1492
1493#define BMC150_ACCEL_FIFO_MODE_STREAM 0x80
1494#define BMC150_ACCEL_FIFO_MODE_FIFO 0x40
1495#define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00
1496
1497static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1498{
1499 struct device *dev = regmap_get_device(data->regmap);
1500 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1501 int ret;
1502
1503 ret = regmap_write(data->regmap, reg, data->fifo_mode);
1504 if (ret < 0) {
1505 dev_err(dev, "Error writing reg_fifo_config1\n");
1506 return ret;
1507 }
1508
1509 if (!data->fifo_mode)
1510 return 0;
1511
1512 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1513 data->watermark);
1514 if (ret < 0)
1515 dev_err(dev, "Error writing reg_fifo_config0\n");
1516
1517 return ret;
1518}
1519
1520static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1521{
1522 struct bmc150_accel_data *data = iio_priv(indio_dev);
1523
1524 return bmc150_accel_set_power_state(data, true);
1525}
1526
1527static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1528{
1529 struct bmc150_accel_data *data = iio_priv(indio_dev);
1530 int ret = 0;
1531
1532 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1533 return 0;
1534
1535 mutex_lock(&data->mutex);
1536
1537 if (!data->watermark)
1538 goto out;
1539
1540 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1541 true);
1542 if (ret)
1543 goto out;
1544
1545 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1546
1547 ret = bmc150_accel_fifo_set_mode(data);
1548 if (ret) {
1549 data->fifo_mode = 0;
1550 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1551 false);
1552 }
1553
1554out:
1555 mutex_unlock(&data->mutex);
1556
1557 return ret;
1558}
1559
1560static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1561{
1562 struct bmc150_accel_data *data = iio_priv(indio_dev);
1563
1564 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1565 return 0;
1566
1567 mutex_lock(&data->mutex);
1568
1569 if (!data->fifo_mode)
1570 goto out;
1571
1572 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1573 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1574 data->fifo_mode = 0;
1575 bmc150_accel_fifo_set_mode(data);
1576
1577out:
1578 mutex_unlock(&data->mutex);
1579
1580 return 0;
1581}
1582
1583static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1584{
1585 struct bmc150_accel_data *data = iio_priv(indio_dev);
1586
1587 return bmc150_accel_set_power_state(data, false);
1588}
1589
1590static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1591 .preenable = bmc150_accel_buffer_preenable,
1592 .postenable = bmc150_accel_buffer_postenable,
1593 .predisable = bmc150_accel_buffer_predisable,
1594 .postdisable = bmc150_accel_buffer_postdisable,
1595};
1596
1597static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1598{
1599 struct device *dev = regmap_get_device(data->regmap);
1600 int ret, i;
1601 unsigned int val;
1602
1603
1604
1605
1606
1607 regmap_write(data->regmap, BMC150_ACCEL_REG_RESET,
1608 BMC150_ACCEL_RESET_VAL);
1609 usleep_range(1800, 2500);
1610
1611 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1612 if (ret < 0) {
1613 dev_err(dev, "Error: Reading chip id\n");
1614 return ret;
1615 }
1616
1617 dev_dbg(dev, "Chip Id %x\n", val);
1618 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1619 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1620 data->chip_info = &bmc150_accel_chip_info_tbl[i];
1621 break;
1622 }
1623 }
1624
1625 if (!data->chip_info) {
1626 dev_err(dev, "Invalid chip %x\n", val);
1627 return -ENODEV;
1628 }
1629
1630 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1631 if (ret < 0)
1632 return ret;
1633
1634
1635 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1636 if (ret < 0)
1637 return ret;
1638
1639
1640 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1641 BMC150_ACCEL_DEF_RANGE_4G);
1642 if (ret < 0) {
1643 dev_err(dev, "Error writing reg_pmu_range\n");
1644 return ret;
1645 }
1646
1647 data->range = BMC150_ACCEL_DEF_RANGE_4G;
1648
1649
1650 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1651 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1652 ret = bmc150_accel_update_slope(data);
1653 if (ret < 0)
1654 return ret;
1655
1656
1657 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1658 BMC150_ACCEL_INT_MODE_LATCH_INT |
1659 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1660 if (ret < 0) {
1661 dev_err(dev, "Error writing reg_int_rst_latch\n");
1662 return ret;
1663 }
1664
1665 return 0;
1666}
1667
1668int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1669 const char *name, bool block_supported)
1670{
1671 const struct attribute **fifo_attrs;
1672 struct bmc150_accel_data *data;
1673 struct iio_dev *indio_dev;
1674 int ret;
1675
1676 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1677 if (!indio_dev)
1678 return -ENOMEM;
1679
1680 data = iio_priv(indio_dev);
1681 dev_set_drvdata(dev, indio_dev);
1682
1683 data->regmap = regmap;
1684
1685 if (!bmc150_apply_acpi_orientation(dev, &data->orientation)) {
1686 ret = iio_read_mount_matrix(dev, "mount-matrix",
1687 &data->orientation);
1688 if (ret)
1689 return ret;
1690 }
1691
1692
1693
1694
1695
1696 data->regulators[0].supply = "vdd";
1697 data->regulators[1].supply = "vddio";
1698 ret = devm_regulator_bulk_get(dev,
1699 ARRAY_SIZE(data->regulators),
1700 data->regulators);
1701 if (ret)
1702 return dev_err_probe(dev, ret, "failed to get regulators\n");
1703
1704 ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators),
1705 data->regulators);
1706 if (ret) {
1707 dev_err(dev, "failed to enable regulators: %d\n", ret);
1708 return ret;
1709 }
1710
1711
1712
1713
1714 msleep(5);
1715
1716 ret = bmc150_accel_chip_init(data);
1717 if (ret < 0)
1718 goto err_disable_regulators;
1719
1720 mutex_init(&data->mutex);
1721
1722 indio_dev->channels = data->chip_info->channels;
1723 indio_dev->num_channels = data->chip_info->num_channels;
1724 indio_dev->name = name ? name : data->chip_info->name;
1725 indio_dev->available_scan_masks = bmc150_accel_scan_masks;
1726 indio_dev->modes = INDIO_DIRECT_MODE;
1727 indio_dev->info = &bmc150_accel_info;
1728
1729 if (block_supported) {
1730 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1731 indio_dev->info = &bmc150_accel_info_fifo;
1732 fifo_attrs = bmc150_accel_fifo_attributes;
1733 } else {
1734 fifo_attrs = NULL;
1735 }
1736
1737 ret = iio_triggered_buffer_setup_ext(indio_dev,
1738 &iio_pollfunc_store_time,
1739 bmc150_accel_trigger_handler,
1740 &bmc150_accel_buffer_ops,
1741 fifo_attrs);
1742 if (ret < 0) {
1743 dev_err(dev, "Failed: iio triggered buffer setup\n");
1744 goto err_disable_regulators;
1745 }
1746
1747 if (irq > 0) {
1748 ret = devm_request_threaded_irq(dev, irq,
1749 bmc150_accel_irq_handler,
1750 bmc150_accel_irq_thread_handler,
1751 IRQF_TRIGGER_RISING,
1752 BMC150_ACCEL_IRQ_NAME,
1753 indio_dev);
1754 if (ret)
1755 goto err_buffer_cleanup;
1756
1757
1758
1759
1760
1761
1762
1763 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1764 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1765 if (ret < 0) {
1766 dev_err(dev, "Error writing reg_int_rst_latch\n");
1767 goto err_buffer_cleanup;
1768 }
1769
1770 bmc150_accel_interrupts_setup(indio_dev, data);
1771
1772 ret = bmc150_accel_triggers_setup(indio_dev, data);
1773 if (ret)
1774 goto err_buffer_cleanup;
1775 }
1776
1777 ret = pm_runtime_set_active(dev);
1778 if (ret)
1779 goto err_trigger_unregister;
1780
1781 pm_runtime_enable(dev);
1782 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1783 pm_runtime_use_autosuspend(dev);
1784
1785 ret = iio_device_register(indio_dev);
1786 if (ret < 0) {
1787 dev_err(dev, "Unable to register iio device\n");
1788 goto err_trigger_unregister;
1789 }
1790
1791 return 0;
1792
1793err_trigger_unregister:
1794 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1795err_buffer_cleanup:
1796 iio_triggered_buffer_cleanup(indio_dev);
1797err_disable_regulators:
1798 regulator_bulk_disable(ARRAY_SIZE(data->regulators),
1799 data->regulators);
1800
1801 return ret;
1802}
1803EXPORT_SYMBOL_GPL(bmc150_accel_core_probe);
1804
1805struct i2c_client *bmc150_get_second_device(struct i2c_client *client)
1806{
1807 struct bmc150_accel_data *data = i2c_get_clientdata(client);
1808
1809 if (!data)
1810 return NULL;
1811
1812 return data->second_device;
1813}
1814EXPORT_SYMBOL_GPL(bmc150_get_second_device);
1815
1816void bmc150_set_second_device(struct i2c_client *client)
1817{
1818 struct bmc150_accel_data *data = i2c_get_clientdata(client);
1819
1820 if (data)
1821 data->second_device = client;
1822}
1823EXPORT_SYMBOL_GPL(bmc150_set_second_device);
1824
1825int bmc150_accel_core_remove(struct device *dev)
1826{
1827 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1828 struct bmc150_accel_data *data = iio_priv(indio_dev);
1829
1830 iio_device_unregister(indio_dev);
1831
1832 pm_runtime_disable(dev);
1833 pm_runtime_set_suspended(dev);
1834 pm_runtime_put_noidle(dev);
1835
1836 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1837
1838 iio_triggered_buffer_cleanup(indio_dev);
1839
1840 mutex_lock(&data->mutex);
1841 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1842 mutex_unlock(&data->mutex);
1843
1844 regulator_bulk_disable(ARRAY_SIZE(data->regulators),
1845 data->regulators);
1846
1847 return 0;
1848}
1849EXPORT_SYMBOL_GPL(bmc150_accel_core_remove);
1850
1851#ifdef CONFIG_PM_SLEEP
1852static int bmc150_accel_suspend(struct device *dev)
1853{
1854 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1855 struct bmc150_accel_data *data = iio_priv(indio_dev);
1856
1857 mutex_lock(&data->mutex);
1858 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1859 mutex_unlock(&data->mutex);
1860
1861 return 0;
1862}
1863
1864static int bmc150_accel_resume(struct device *dev)
1865{
1866 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1867 struct bmc150_accel_data *data = iio_priv(indio_dev);
1868
1869 mutex_lock(&data->mutex);
1870 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1871 bmc150_accel_fifo_set_mode(data);
1872 mutex_unlock(&data->mutex);
1873
1874 return 0;
1875}
1876#endif
1877
1878#ifdef CONFIG_PM
1879static int bmc150_accel_runtime_suspend(struct device *dev)
1880{
1881 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1882 struct bmc150_accel_data *data = iio_priv(indio_dev);
1883 int ret;
1884
1885 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1886 if (ret < 0)
1887 return -EAGAIN;
1888
1889 return 0;
1890}
1891
1892static int bmc150_accel_runtime_resume(struct device *dev)
1893{
1894 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1895 struct bmc150_accel_data *data = iio_priv(indio_dev);
1896 int ret;
1897 int sleep_val;
1898
1899 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1900 if (ret < 0)
1901 return ret;
1902 ret = bmc150_accel_fifo_set_mode(data);
1903 if (ret < 0)
1904 return ret;
1905
1906 sleep_val = bmc150_accel_get_startup_times(data);
1907 if (sleep_val < 20)
1908 usleep_range(sleep_val * 1000, 20000);
1909 else
1910 msleep_interruptible(sleep_val);
1911
1912 return 0;
1913}
1914#endif
1915
1916const struct dev_pm_ops bmc150_accel_pm_ops = {
1917 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1918 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1919 bmc150_accel_runtime_resume, NULL)
1920};
1921EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops);
1922
1923MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1924MODULE_LICENSE("GPL v2");
1925MODULE_DESCRIPTION("BMC150 accelerometer driver");
1926
