1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21#include <linux/module.h>
22#include <linux/i2c.h>
23#include <linux/iio/iio.h>
24#include <linux/iio/sysfs.h>
25#include <linux/iio/buffer.h>
26#include <linux/iio/trigger.h>
27#include <linux/iio/trigger_consumer.h>
28#include <linux/iio/triggered_buffer.h>
29#include <linux/iio/events.h>
30#include <linux/delay.h>
31#include <linux/of_device.h>
32#include <linux/of_irq.h>
33#include <linux/pm_runtime.h>
34#include <linux/regulator/consumer.h>
35
36#define MMA8452_STATUS 0x00
37#define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
38#define MMA8452_OUT_X 0x01
39#define MMA8452_OUT_Y 0x03
40#define MMA8452_OUT_Z 0x05
41#define MMA8452_INT_SRC 0x0c
42#define MMA8452_WHO_AM_I 0x0d
43#define MMA8452_DATA_CFG 0x0e
44#define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
45#define MMA8452_DATA_CFG_FS_2G 0
46#define MMA8452_DATA_CFG_FS_4G 1
47#define MMA8452_DATA_CFG_FS_8G 2
48#define MMA8452_DATA_CFG_HPF_MASK BIT(4)
49#define MMA8452_HP_FILTER_CUTOFF 0x0f
50#define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
51#define MMA8452_FF_MT_CFG 0x15
52#define MMA8452_FF_MT_CFG_OAE BIT(6)
53#define MMA8452_FF_MT_CFG_ELE BIT(7)
54#define MMA8452_FF_MT_SRC 0x16
55#define MMA8452_FF_MT_SRC_XHE BIT(1)
56#define MMA8452_FF_MT_SRC_YHE BIT(3)
57#define MMA8452_FF_MT_SRC_ZHE BIT(5)
58#define MMA8452_FF_MT_THS 0x17
59#define MMA8452_FF_MT_THS_MASK 0x7f
60#define MMA8452_FF_MT_COUNT 0x18
61#define MMA8452_FF_MT_CHAN_SHIFT 3
62#define MMA8452_TRANSIENT_CFG 0x1d
63#define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
64#define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
65#define MMA8452_TRANSIENT_CFG_ELE BIT(4)
66#define MMA8452_TRANSIENT_SRC 0x1e
67#define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
68#define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
69#define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
70#define MMA8452_TRANSIENT_THS 0x1f
71#define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
72#define MMA8452_TRANSIENT_COUNT 0x20
73#define MMA8452_TRANSIENT_CHAN_SHIFT 1
74#define MMA8452_CTRL_REG1 0x2a
75#define MMA8452_CTRL_ACTIVE BIT(0)
76#define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
77#define MMA8452_CTRL_DR_SHIFT 3
78#define MMA8452_CTRL_DR_DEFAULT 0x4
79#define MMA8452_CTRL_REG2 0x2b
80#define MMA8452_CTRL_REG2_RST BIT(6)
81#define MMA8452_CTRL_REG2_MODS_SHIFT 3
82#define MMA8452_CTRL_REG2_MODS_MASK 0x1b
83#define MMA8452_CTRL_REG4 0x2d
84#define MMA8452_CTRL_REG5 0x2e
85#define MMA8452_OFF_X 0x2f
86#define MMA8452_OFF_Y 0x30
87#define MMA8452_OFF_Z 0x31
88
89#define MMA8452_MAX_REG 0x31
90
91#define MMA8452_INT_DRDY BIT(0)
92#define MMA8452_INT_FF_MT BIT(2)
93#define MMA8452_INT_TRANS BIT(5)
94
95#define MMA8451_DEVICE_ID 0x1a
96#define MMA8452_DEVICE_ID 0x2a
97#define MMA8453_DEVICE_ID 0x3a
98#define MMA8652_DEVICE_ID 0x4a
99#define MMA8653_DEVICE_ID 0x5a
100#define FXLS8471_DEVICE_ID 0x6a
101
102#define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
103
104struct mma8452_data {
105 struct i2c_client *client;
106 struct mutex lock;
107 u8 ctrl_reg1;
108 u8 data_cfg;
109 const struct mma_chip_info *chip_info;
110 int sleep_val;
111 struct regulator *vdd_reg;
112 struct regulator *vddio_reg;
113
114
115 struct {
116 __be16 channels[3];
117 s64 ts __aligned(8);
118 } buffer;
119};
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136struct mma8452_event_regs {
137 u8 ev_cfg;
138 u8 ev_cfg_ele;
139 u8 ev_cfg_chan_shift;
140 u8 ev_src;
141 u8 ev_ths;
142 u8 ev_ths_mask;
143 u8 ev_count;
144};
145
146static const struct mma8452_event_regs ff_mt_ev_regs = {
147 .ev_cfg = MMA8452_FF_MT_CFG,
148 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
149 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT,
150 .ev_src = MMA8452_FF_MT_SRC,
151 .ev_ths = MMA8452_FF_MT_THS,
152 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
153 .ev_count = MMA8452_FF_MT_COUNT
154};
155
156static const struct mma8452_event_regs trans_ev_regs = {
157 .ev_cfg = MMA8452_TRANSIENT_CFG,
158 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
159 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT,
160 .ev_src = MMA8452_TRANSIENT_SRC,
161 .ev_ths = MMA8452_TRANSIENT_THS,
162 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
163 .ev_count = MMA8452_TRANSIENT_COUNT,
164};
165
166
167
168
169
170
171
172
173
174
175
176
177
178struct mma_chip_info {
179 u8 chip_id;
180 const struct iio_chan_spec *channels;
181 int num_channels;
182 const int mma_scales[3][2];
183 int all_events;
184 int enabled_events;
185};
186
187enum {
188 idx_x,
189 idx_y,
190 idx_z,
191 idx_ts,
192};
193
194static int mma8452_drdy(struct mma8452_data *data)
195{
196 int tries = 150;
197
198 while (tries-- > 0) {
199 int ret = i2c_smbus_read_byte_data(data->client,
200 MMA8452_STATUS);
201 if (ret < 0)
202 return ret;
203 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
204 return 0;
205
206 if (data->sleep_val <= 20)
207 usleep_range(data->sleep_val * 250,
208 data->sleep_val * 500);
209 else
210 msleep(20);
211 }
212
213 dev_err(&data->client->dev, "data not ready\n");
214
215 return -EIO;
216}
217
218static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
219{
220#ifdef CONFIG_PM
221 int ret;
222
223 if (on) {
224 ret = pm_runtime_get_sync(&client->dev);
225 } else {
226 pm_runtime_mark_last_busy(&client->dev);
227 ret = pm_runtime_put_autosuspend(&client->dev);
228 }
229
230 if (ret < 0) {
231 dev_err(&client->dev,
232 "failed to change power state to %d\n", on);
233 if (on)
234 pm_runtime_put_noidle(&client->dev);
235
236 return ret;
237 }
238#endif
239
240 return 0;
241}
242
243static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
244{
245 int ret = mma8452_drdy(data);
246
247 if (ret < 0)
248 return ret;
249
250 ret = mma8452_set_runtime_pm_state(data->client, true);
251 if (ret)
252 return ret;
253
254 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
255 3 * sizeof(__be16), (u8 *)buf);
256
257 ret = mma8452_set_runtime_pm_state(data->client, false);
258
259 return ret;
260}
261
262static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
263 int n)
264{
265 size_t len = 0;
266
267 while (n-- > 0)
268 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
269 vals[n][0], vals[n][1]);
270
271
272 buf[len - 1] = '\n';
273
274 return len;
275}
276
277static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
278 int val, int val2)
279{
280 while (n-- > 0)
281 if (val == vals[n][0] && val2 == vals[n][1])
282 return n;
283
284 return -EINVAL;
285}
286
287static unsigned int mma8452_get_odr_index(struct mma8452_data *data)
288{
289 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
290 MMA8452_CTRL_DR_SHIFT;
291}
292
293static const int mma8452_samp_freq[8][2] = {
294 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
295 {6, 250000}, {1, 560000}
296};
297
298
299static const unsigned int mma8452_time_step_us[4][8] = {
300 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 },
301 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 },
302 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 },
303 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 }
304};
305
306
307static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
308 {
309 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
310 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
311 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
312 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
313 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
314 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
315 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
316 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }
317 },
318 {
319 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
320 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
321 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
322 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
323 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
324 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
325 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
326 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
327 },
328 {
329 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
330 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
331 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
332 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
333 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
334 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
335 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
336 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
337 },
338 {
339 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
340 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
341 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
342 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
343 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
344 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
345 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
346 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
347 }
348};
349
350
351static const u16 mma8452_os_ratio[4][8] = {
352
353 { 2, 4, 4, 4, 4, 16, 32, 128 },
354 { 2, 4, 4, 4, 4, 4, 8, 32 },
355 { 2, 4, 8, 16, 32, 128, 256, 1024 },
356 { 2, 2, 2, 2, 2, 2, 4, 16 }
357};
358
359static int mma8452_get_power_mode(struct mma8452_data *data)
360{
361 int reg;
362
363 reg = i2c_smbus_read_byte_data(data->client,
364 MMA8452_CTRL_REG2);
365 if (reg < 0)
366 return reg;
367
368 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
369 MMA8452_CTRL_REG2_MODS_SHIFT);
370}
371
372static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
373 struct device_attribute *attr,
374 char *buf)
375{
376 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
377 ARRAY_SIZE(mma8452_samp_freq));
378}
379
380static ssize_t mma8452_show_scale_avail(struct device *dev,
381 struct device_attribute *attr,
382 char *buf)
383{
384 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
385 to_i2c_client(dev)));
386
387 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
388 ARRAY_SIZE(data->chip_info->mma_scales));
389}
390
391static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
392 struct device_attribute *attr,
393 char *buf)
394{
395 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
396 struct mma8452_data *data = iio_priv(indio_dev);
397 int i, j;
398
399 i = mma8452_get_odr_index(data);
400 j = mma8452_get_power_mode(data);
401 if (j < 0)
402 return j;
403
404 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
405 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
406}
407
408static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
409 struct device_attribute *attr,
410 char *buf)
411{
412 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
413 struct mma8452_data *data = iio_priv(indio_dev);
414 int i = mma8452_get_odr_index(data);
415 int j;
416 u16 val = 0;
417 size_t len = 0;
418
419 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
420 if (val == mma8452_os_ratio[j][i])
421 continue;
422
423 val = mma8452_os_ratio[j][i];
424
425 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
426 }
427 buf[len - 1] = '\n';
428
429 return len;
430}
431
432static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
433static IIO_DEVICE_ATTR(in_accel_scale_available, 0444,
434 mma8452_show_scale_avail, NULL, 0);
435static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
436 0444, mma8452_show_hp_cutoff_avail, NULL, 0);
437static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444,
438 mma8452_show_os_ratio_avail, NULL, 0);
439
440static int mma8452_get_samp_freq_index(struct mma8452_data *data,
441 int val, int val2)
442{
443 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
444 ARRAY_SIZE(mma8452_samp_freq),
445 val, val2);
446}
447
448static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
449{
450 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
451 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
452}
453
454static int mma8452_get_hp_filter_index(struct mma8452_data *data,
455 int val, int val2)
456{
457 int i, j;
458
459 i = mma8452_get_odr_index(data);
460 j = mma8452_get_power_mode(data);
461 if (j < 0)
462 return j;
463
464 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
465 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
466}
467
468static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
469{
470 int j, i, ret;
471
472 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
473 if (ret < 0)
474 return ret;
475
476 i = mma8452_get_odr_index(data);
477 j = mma8452_get_power_mode(data);
478 if (j < 0)
479 return j;
480
481 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
482 *hz = mma8452_hp_filter_cutoff[j][i][ret][0];
483 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
484
485 return 0;
486}
487
488static int mma8452_read_raw(struct iio_dev *indio_dev,
489 struct iio_chan_spec const *chan,
490 int *val, int *val2, long mask)
491{
492 struct mma8452_data *data = iio_priv(indio_dev);
493 __be16 buffer[3];
494 int i, ret;
495
496 switch (mask) {
497 case IIO_CHAN_INFO_RAW:
498 ret = iio_device_claim_direct_mode(indio_dev);
499 if (ret)
500 return ret;
501
502 mutex_lock(&data->lock);
503 ret = mma8452_read(data, buffer);
504 mutex_unlock(&data->lock);
505 iio_device_release_direct_mode(indio_dev);
506 if (ret < 0)
507 return ret;
508
509 *val = sign_extend32(be16_to_cpu(
510 buffer[chan->scan_index]) >> chan->scan_type.shift,
511 chan->scan_type.realbits - 1);
512
513 return IIO_VAL_INT;
514 case IIO_CHAN_INFO_SCALE:
515 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
516 *val = data->chip_info->mma_scales[i][0];
517 *val2 = data->chip_info->mma_scales[i][1];
518
519 return IIO_VAL_INT_PLUS_MICRO;
520 case IIO_CHAN_INFO_SAMP_FREQ:
521 i = mma8452_get_odr_index(data);
522 *val = mma8452_samp_freq[i][0];
523 *val2 = mma8452_samp_freq[i][1];
524
525 return IIO_VAL_INT_PLUS_MICRO;
526 case IIO_CHAN_INFO_CALIBBIAS:
527 ret = i2c_smbus_read_byte_data(data->client,
528 MMA8452_OFF_X +
529 chan->scan_index);
530 if (ret < 0)
531 return ret;
532
533 *val = sign_extend32(ret, 7);
534
535 return IIO_VAL_INT;
536 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
537 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
538 ret = mma8452_read_hp_filter(data, val, val2);
539 if (ret < 0)
540 return ret;
541 } else {
542 *val = 0;
543 *val2 = 0;
544 }
545
546 return IIO_VAL_INT_PLUS_MICRO;
547 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
548 ret = mma8452_get_power_mode(data);
549 if (ret < 0)
550 return ret;
551
552 i = mma8452_get_odr_index(data);
553
554 *val = mma8452_os_ratio[ret][i];
555 return IIO_VAL_INT;
556 }
557
558 return -EINVAL;
559}
560
561static int mma8452_calculate_sleep(struct mma8452_data *data)
562{
563 int ret, i = mma8452_get_odr_index(data);
564
565 if (mma8452_samp_freq[i][0] > 0)
566 ret = 1000 / mma8452_samp_freq[i][0];
567 else
568 ret = 1000;
569
570 return ret == 0 ? 1 : ret;
571}
572
573static int mma8452_standby(struct mma8452_data *data)
574{
575 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
576 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
577}
578
579static int mma8452_active(struct mma8452_data *data)
580{
581 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
582 data->ctrl_reg1);
583}
584
585
586static int mma8452_is_active(struct mma8452_data *data)
587{
588 int reg;
589
590 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
591 if (reg < 0)
592 return reg;
593
594 return reg & MMA8452_CTRL_ACTIVE;
595}
596
597static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
598{
599 int ret;
600 int is_active;
601
602 mutex_lock(&data->lock);
603
604 is_active = mma8452_is_active(data);
605 if (is_active < 0) {
606 ret = is_active;
607 goto fail;
608 }
609
610
611 if (is_active > 0) {
612 ret = mma8452_standby(data);
613 if (ret < 0)
614 goto fail;
615 }
616
617 ret = i2c_smbus_write_byte_data(data->client, reg, val);
618 if (ret < 0)
619 goto fail;
620
621 if (is_active > 0) {
622 ret = mma8452_active(data);
623 if (ret < 0)
624 goto fail;
625 }
626
627 ret = 0;
628fail:
629 mutex_unlock(&data->lock);
630
631 return ret;
632}
633
634static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
635{
636 int reg;
637
638 reg = i2c_smbus_read_byte_data(data->client,
639 MMA8452_CTRL_REG2);
640 if (reg < 0)
641 return reg;
642
643 reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
644 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;
645
646 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
647}
648
649
650static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
651{
652 int val;
653
654 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
655 if (val < 0)
656 return val;
657
658 return !(val & MMA8452_FF_MT_CFG_OAE);
659}
660
661static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
662{
663 int val;
664
665 if ((state && mma8452_freefall_mode_enabled(data)) ||
666 (!state && !(mma8452_freefall_mode_enabled(data))))
667 return 0;
668
669 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
670 if (val < 0)
671 return val;
672
673 if (state) {
674 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
675 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
676 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
677 val &= ~MMA8452_FF_MT_CFG_OAE;
678 } else {
679 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
680 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
681 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
682 val |= MMA8452_FF_MT_CFG_OAE;
683 }
684
685 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val);
686}
687
688static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
689 int val, int val2)
690{
691 int i, reg;
692
693 i = mma8452_get_hp_filter_index(data, val, val2);
694 if (i < 0)
695 return i;
696
697 reg = i2c_smbus_read_byte_data(data->client,
698 MMA8452_HP_FILTER_CUTOFF);
699 if (reg < 0)
700 return reg;
701
702 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
703 reg |= i;
704
705 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
706}
707
708static int mma8452_write_raw(struct iio_dev *indio_dev,
709 struct iio_chan_spec const *chan,
710 int val, int val2, long mask)
711{
712 struct mma8452_data *data = iio_priv(indio_dev);
713 int i, ret;
714
715 ret = iio_device_claim_direct_mode(indio_dev);
716 if (ret)
717 return ret;
718
719 switch (mask) {
720 case IIO_CHAN_INFO_SAMP_FREQ:
721 i = mma8452_get_samp_freq_index(data, val, val2);
722 if (i < 0) {
723 ret = i;
724 break;
725 }
726 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
727 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
728
729 data->sleep_val = mma8452_calculate_sleep(data);
730
731 ret = mma8452_change_config(data, MMA8452_CTRL_REG1,
732 data->ctrl_reg1);
733 break;
734 case IIO_CHAN_INFO_SCALE:
735 i = mma8452_get_scale_index(data, val, val2);
736 if (i < 0) {
737 ret = i;
738 break;
739 }
740
741 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
742 data->data_cfg |= i;
743
744 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
745 data->data_cfg);
746 break;
747 case IIO_CHAN_INFO_CALIBBIAS:
748 if (val < -128 || val > 127) {
749 ret = -EINVAL;
750 break;
751 }
752
753 ret = mma8452_change_config(data,
754 MMA8452_OFF_X + chan->scan_index,
755 val);
756 break;
757
758 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
759 if (val == 0 && val2 == 0) {
760 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
761 } else {
762 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
763 ret = mma8452_set_hp_filter_frequency(data, val, val2);
764 if (ret < 0)
765 break;
766 }
767
768 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
769 data->data_cfg);
770 break;
771
772 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
773 ret = mma8452_get_odr_index(data);
774
775 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
776 if (mma8452_os_ratio[i][ret] == val) {
777 ret = mma8452_set_power_mode(data, i);
778 break;
779 }
780 }
781 break;
782 default:
783 ret = -EINVAL;
784 break;
785 }
786
787 iio_device_release_direct_mode(indio_dev);
788 return ret;
789}
790
791static int mma8452_get_event_regs(struct mma8452_data *data,
792 const struct iio_chan_spec *chan, enum iio_event_direction dir,
793 const struct mma8452_event_regs **ev_reg)
794{
795 if (!chan)
796 return -EINVAL;
797
798 switch (chan->type) {
799 case IIO_ACCEL:
800 switch (dir) {
801 case IIO_EV_DIR_RISING:
802 if ((data->chip_info->all_events
803 & MMA8452_INT_TRANS) &&
804 (data->chip_info->enabled_events
805 & MMA8452_INT_TRANS))
806 *ev_reg = &trans_ev_regs;
807 else
808 *ev_reg = &ff_mt_ev_regs;
809 return 0;
810 case IIO_EV_DIR_FALLING:
811 *ev_reg = &ff_mt_ev_regs;
812 return 0;
813 default:
814 return -EINVAL;
815 }
816 default:
817 return -EINVAL;
818 }
819}
820
821static int mma8452_read_event_value(struct iio_dev *indio_dev,
822 const struct iio_chan_spec *chan,
823 enum iio_event_type type,
824 enum iio_event_direction dir,
825 enum iio_event_info info,
826 int *val, int *val2)
827{
828 struct mma8452_data *data = iio_priv(indio_dev);
829 int ret, us, power_mode;
830 const struct mma8452_event_regs *ev_regs;
831
832 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
833 if (ret)
834 return ret;
835
836 switch (info) {
837 case IIO_EV_INFO_VALUE:
838 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths);
839 if (ret < 0)
840 return ret;
841
842 *val = ret & ev_regs->ev_ths_mask;
843
844 return IIO_VAL_INT;
845
846 case IIO_EV_INFO_PERIOD:
847 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count);
848 if (ret < 0)
849 return ret;
850
851 power_mode = mma8452_get_power_mode(data);
852 if (power_mode < 0)
853 return power_mode;
854
855 us = ret * mma8452_time_step_us[power_mode][
856 mma8452_get_odr_index(data)];
857 *val = us / USEC_PER_SEC;
858 *val2 = us % USEC_PER_SEC;
859
860 return IIO_VAL_INT_PLUS_MICRO;
861
862 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
863 ret = i2c_smbus_read_byte_data(data->client,
864 MMA8452_TRANSIENT_CFG);
865 if (ret < 0)
866 return ret;
867
868 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
869 *val = 0;
870 *val2 = 0;
871 } else {
872 ret = mma8452_read_hp_filter(data, val, val2);
873 if (ret < 0)
874 return ret;
875 }
876
877 return IIO_VAL_INT_PLUS_MICRO;
878
879 default:
880 return -EINVAL;
881 }
882}
883
884static int mma8452_write_event_value(struct iio_dev *indio_dev,
885 const struct iio_chan_spec *chan,
886 enum iio_event_type type,
887 enum iio_event_direction dir,
888 enum iio_event_info info,
889 int val, int val2)
890{
891 struct mma8452_data *data = iio_priv(indio_dev);
892 int ret, reg, steps;
893 const struct mma8452_event_regs *ev_regs;
894
895 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
896 if (ret)
897 return ret;
898
899 switch (info) {
900 case IIO_EV_INFO_VALUE:
901 if (val < 0 || val > ev_regs->ev_ths_mask)
902 return -EINVAL;
903
904 return mma8452_change_config(data, ev_regs->ev_ths, val);
905
906 case IIO_EV_INFO_PERIOD:
907 ret = mma8452_get_power_mode(data);
908 if (ret < 0)
909 return ret;
910
911 steps = (val * USEC_PER_SEC + val2) /
912 mma8452_time_step_us[ret][
913 mma8452_get_odr_index(data)];
914
915 if (steps < 0 || steps > 0xff)
916 return -EINVAL;
917
918 return mma8452_change_config(data, ev_regs->ev_count, steps);
919
920 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
921 reg = i2c_smbus_read_byte_data(data->client,
922 MMA8452_TRANSIENT_CFG);
923 if (reg < 0)
924 return reg;
925
926 if (val == 0 && val2 == 0) {
927 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
928 } else {
929 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
930 ret = mma8452_set_hp_filter_frequency(data, val, val2);
931 if (ret < 0)
932 return ret;
933 }
934
935 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
936
937 default:
938 return -EINVAL;
939 }
940}
941
942static int mma8452_read_event_config(struct iio_dev *indio_dev,
943 const struct iio_chan_spec *chan,
944 enum iio_event_type type,
945 enum iio_event_direction dir)
946{
947 struct mma8452_data *data = iio_priv(indio_dev);
948 int ret;
949 const struct mma8452_event_regs *ev_regs;
950
951 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
952 if (ret)
953 return ret;
954
955 switch (dir) {
956 case IIO_EV_DIR_FALLING:
957 return mma8452_freefall_mode_enabled(data);
958 case IIO_EV_DIR_RISING:
959 ret = i2c_smbus_read_byte_data(data->client,
960 ev_regs->ev_cfg);
961 if (ret < 0)
962 return ret;
963
964 return !!(ret & BIT(chan->scan_index +
965 ev_regs->ev_cfg_chan_shift));
966 default:
967 return -EINVAL;
968 }
969}
970
971static int mma8452_write_event_config(struct iio_dev *indio_dev,
972 const struct iio_chan_spec *chan,
973 enum iio_event_type type,
974 enum iio_event_direction dir,
975 int state)
976{
977 struct mma8452_data *data = iio_priv(indio_dev);
978 int val, ret;
979 const struct mma8452_event_regs *ev_regs;
980
981 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
982 if (ret)
983 return ret;
984
985 ret = mma8452_set_runtime_pm_state(data->client, state);
986 if (ret)
987 return ret;
988
989 switch (dir) {
990 case IIO_EV_DIR_FALLING:
991 return mma8452_set_freefall_mode(data, state);
992 case IIO_EV_DIR_RISING:
993 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg);
994 if (val < 0)
995 return val;
996
997 if (state) {
998 if (mma8452_freefall_mode_enabled(data)) {
999 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift);
1000 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift);
1001 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift);
1002 val |= MMA8452_FF_MT_CFG_OAE;
1003 }
1004 val |= BIT(chan->scan_index +
1005 ev_regs->ev_cfg_chan_shift);
1006 } else {
1007 if (mma8452_freefall_mode_enabled(data))
1008 return 0;
1009
1010 val &= ~BIT(chan->scan_index +
1011 ev_regs->ev_cfg_chan_shift);
1012 }
1013
1014 val |= ev_regs->ev_cfg_ele;
1015
1016 return mma8452_change_config(data, ev_regs->ev_cfg, val);
1017 default:
1018 return -EINVAL;
1019 }
1020}
1021
1022static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
1023{
1024 struct mma8452_data *data = iio_priv(indio_dev);
1025 s64 ts = iio_get_time_ns(indio_dev);
1026 int src;
1027
1028 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
1029 if (src < 0)
1030 return;
1031
1032 if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
1033 iio_push_event(indio_dev,
1034 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1035 IIO_EV_TYPE_MAG,
1036 IIO_EV_DIR_RISING),
1037 ts);
1038
1039 if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
1040 iio_push_event(indio_dev,
1041 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
1042 IIO_EV_TYPE_MAG,
1043 IIO_EV_DIR_RISING),
1044 ts);
1045
1046 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
1047 iio_push_event(indio_dev,
1048 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
1049 IIO_EV_TYPE_MAG,
1050 IIO_EV_DIR_RISING),
1051 ts);
1052}
1053
1054static irqreturn_t mma8452_interrupt(int irq, void *p)
1055{
1056 struct iio_dev *indio_dev = p;
1057 struct mma8452_data *data = iio_priv(indio_dev);
1058 int ret = IRQ_NONE;
1059 int src;
1060
1061 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
1062 if (src < 0)
1063 return IRQ_NONE;
1064
1065 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY)))
1066 return IRQ_NONE;
1067
1068 if (src & MMA8452_INT_DRDY) {
1069 iio_trigger_poll_chained(indio_dev->trig);
1070 ret = IRQ_HANDLED;
1071 }
1072
1073 if (src & MMA8452_INT_FF_MT) {
1074 if (mma8452_freefall_mode_enabled(data)) {
1075 s64 ts = iio_get_time_ns(indio_dev);
1076
1077 iio_push_event(indio_dev,
1078 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1079 IIO_MOD_X_AND_Y_AND_Z,
1080 IIO_EV_TYPE_MAG,
1081 IIO_EV_DIR_FALLING),
1082 ts);
1083 }
1084 ret = IRQ_HANDLED;
1085 }
1086
1087 if (src & MMA8452_INT_TRANS) {
1088 mma8452_transient_interrupt(indio_dev);
1089 ret = IRQ_HANDLED;
1090 }
1091
1092 return ret;
1093}
1094
1095static irqreturn_t mma8452_trigger_handler(int irq, void *p)
1096{
1097 struct iio_poll_func *pf = p;
1098 struct iio_dev *indio_dev = pf->indio_dev;
1099 struct mma8452_data *data = iio_priv(indio_dev);
1100 int ret;
1101
1102 ret = mma8452_read(data, data->buffer.channels);
1103 if (ret < 0)
1104 goto done;
1105
1106 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
1107 iio_get_time_ns(indio_dev));
1108
1109done:
1110 iio_trigger_notify_done(indio_dev->trig);
1111
1112 return IRQ_HANDLED;
1113}
1114
1115static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
1116 unsigned int reg, unsigned int writeval,
1117 unsigned int *readval)
1118{
1119 int ret;
1120 struct mma8452_data *data = iio_priv(indio_dev);
1121
1122 if (reg > MMA8452_MAX_REG)
1123 return -EINVAL;
1124
1125 if (!readval)
1126 return mma8452_change_config(data, reg, writeval);
1127
1128 ret = i2c_smbus_read_byte_data(data->client, reg);
1129 if (ret < 0)
1130 return ret;
1131
1132 *readval = ret;
1133
1134 return 0;
1135}
1136
1137static const struct iio_event_spec mma8452_freefall_event[] = {
1138 {
1139 .type = IIO_EV_TYPE_MAG,
1140 .dir = IIO_EV_DIR_FALLING,
1141 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1142 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1143 BIT(IIO_EV_INFO_PERIOD) |
1144 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1145 },
1146};
1147
1148static const struct iio_event_spec mma8652_freefall_event[] = {
1149 {
1150 .type = IIO_EV_TYPE_MAG,
1151 .dir = IIO_EV_DIR_FALLING,
1152 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1153 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1154 BIT(IIO_EV_INFO_PERIOD)
1155 },
1156};
1157
1158static const struct iio_event_spec mma8452_transient_event[] = {
1159 {
1160 .type = IIO_EV_TYPE_MAG,
1161 .dir = IIO_EV_DIR_RISING,
1162 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1163 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1164 BIT(IIO_EV_INFO_PERIOD) |
1165 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1166 },
1167};
1168
1169static const struct iio_event_spec mma8452_motion_event[] = {
1170 {
1171 .type = IIO_EV_TYPE_MAG,
1172 .dir = IIO_EV_DIR_RISING,
1173 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1174 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1175 BIT(IIO_EV_INFO_PERIOD)
1176 },
1177};
1178
1179
1180
1181
1182
1183static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
1184
1185static struct attribute *mma8452_event_attributes[] = {
1186 &iio_const_attr_accel_transient_scale.dev_attr.attr,
1187 NULL,
1188};
1189
1190static const struct attribute_group mma8452_event_attribute_group = {
1191 .attrs = mma8452_event_attributes,
1192};
1193
1194#define MMA8452_FREEFALL_CHANNEL(modifier) { \
1195 .type = IIO_ACCEL, \
1196 .modified = 1, \
1197 .channel2 = modifier, \
1198 .scan_index = -1, \
1199 .event_spec = mma8452_freefall_event, \
1200 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1201}
1202
1203#define MMA8652_FREEFALL_CHANNEL(modifier) { \
1204 .type = IIO_ACCEL, \
1205 .modified = 1, \
1206 .channel2 = modifier, \
1207 .scan_index = -1, \
1208 .event_spec = mma8652_freefall_event, \
1209 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1210}
1211
1212#define MMA8452_CHANNEL(axis, idx, bits) { \
1213 .type = IIO_ACCEL, \
1214 .modified = 1, \
1215 .channel2 = IIO_MOD_##axis, \
1216 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1217 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1218 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1219 BIT(IIO_CHAN_INFO_SCALE) | \
1220 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1221 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1222 .scan_index = idx, \
1223 .scan_type = { \
1224 .sign = 's', \
1225 .realbits = (bits), \
1226 .storagebits = 16, \
1227 .shift = 16 - (bits), \
1228 .endianness = IIO_BE, \
1229 }, \
1230 .event_spec = mma8452_transient_event, \
1231 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1232}
1233
1234#define MMA8652_CHANNEL(axis, idx, bits) { \
1235 .type = IIO_ACCEL, \
1236 .modified = 1, \
1237 .channel2 = IIO_MOD_##axis, \
1238 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1239 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1240 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1241 BIT(IIO_CHAN_INFO_SCALE) | \
1242 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1243 .scan_index = idx, \
1244 .scan_type = { \
1245 .sign = 's', \
1246 .realbits = (bits), \
1247 .storagebits = 16, \
1248 .shift = 16 - (bits), \
1249 .endianness = IIO_BE, \
1250 }, \
1251 .event_spec = mma8452_motion_event, \
1252 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1253}
1254
1255static const struct iio_chan_spec mma8451_channels[] = {
1256 MMA8452_CHANNEL(X, idx_x, 14),
1257 MMA8452_CHANNEL(Y, idx_y, 14),
1258 MMA8452_CHANNEL(Z, idx_z, 14),
1259 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1260 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1261};
1262
1263static const struct iio_chan_spec mma8452_channels[] = {
1264 MMA8452_CHANNEL(X, idx_x, 12),
1265 MMA8452_CHANNEL(Y, idx_y, 12),
1266 MMA8452_CHANNEL(Z, idx_z, 12),
1267 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1268 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1269};
1270
1271static const struct iio_chan_spec mma8453_channels[] = {
1272 MMA8452_CHANNEL(X, idx_x, 10),
1273 MMA8452_CHANNEL(Y, idx_y, 10),
1274 MMA8452_CHANNEL(Z, idx_z, 10),
1275 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1276 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1277};
1278
1279static const struct iio_chan_spec mma8652_channels[] = {
1280 MMA8652_CHANNEL(X, idx_x, 12),
1281 MMA8652_CHANNEL(Y, idx_y, 12),
1282 MMA8652_CHANNEL(Z, idx_z, 12),
1283 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1284 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1285};
1286
1287static const struct iio_chan_spec mma8653_channels[] = {
1288 MMA8652_CHANNEL(X, idx_x, 10),
1289 MMA8652_CHANNEL(Y, idx_y, 10),
1290 MMA8652_CHANNEL(Z, idx_z, 10),
1291 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1292 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1293};
1294
1295enum {
1296 mma8451,
1297 mma8452,
1298 mma8453,
1299 mma8652,
1300 mma8653,
1301 fxls8471,
1302};
1303
1304static const struct mma_chip_info mma_chip_info_table[] = {
1305 [mma8451] = {
1306 .chip_id = MMA8451_DEVICE_ID,
1307 .channels = mma8451_channels,
1308 .num_channels = ARRAY_SIZE(mma8451_channels),
1309
1310
1311
1312
1313
1314
1315
1316
1317 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1318
1319
1320
1321
1322
1323 .all_events = MMA8452_INT_DRDY |
1324 MMA8452_INT_TRANS |
1325 MMA8452_INT_FF_MT,
1326 .enabled_events = MMA8452_INT_TRANS |
1327 MMA8452_INT_FF_MT,
1328 },
1329 [mma8452] = {
1330 .chip_id = MMA8452_DEVICE_ID,
1331 .channels = mma8452_channels,
1332 .num_channels = ARRAY_SIZE(mma8452_channels),
1333 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1334
1335
1336
1337
1338
1339 .all_events = MMA8452_INT_DRDY |
1340 MMA8452_INT_TRANS |
1341 MMA8452_INT_FF_MT,
1342 .enabled_events = MMA8452_INT_TRANS |
1343 MMA8452_INT_FF_MT,
1344 },
1345 [mma8453] = {
1346 .chip_id = MMA8453_DEVICE_ID,
1347 .channels = mma8453_channels,
1348 .num_channels = ARRAY_SIZE(mma8453_channels),
1349 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1350
1351
1352
1353
1354
1355 .all_events = MMA8452_INT_DRDY |
1356 MMA8452_INT_TRANS |
1357 MMA8452_INT_FF_MT,
1358 .enabled_events = MMA8452_INT_TRANS |
1359 MMA8452_INT_FF_MT,
1360 },
1361 [mma8652] = {
1362 .chip_id = MMA8652_DEVICE_ID,
1363 .channels = mma8652_channels,
1364 .num_channels = ARRAY_SIZE(mma8652_channels),
1365 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1366 .all_events = MMA8452_INT_DRDY |
1367 MMA8452_INT_FF_MT,
1368 .enabled_events = MMA8452_INT_FF_MT,
1369 },
1370 [mma8653] = {
1371 .chip_id = MMA8653_DEVICE_ID,
1372 .channels = mma8653_channels,
1373 .num_channels = ARRAY_SIZE(mma8653_channels),
1374 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1375
1376
1377
1378
1379
1380 .all_events = MMA8452_INT_DRDY |
1381 MMA8452_INT_FF_MT,
1382 .enabled_events = MMA8452_INT_FF_MT,
1383 },
1384 [fxls8471] = {
1385 .chip_id = FXLS8471_DEVICE_ID,
1386 .channels = mma8451_channels,
1387 .num_channels = ARRAY_SIZE(mma8451_channels),
1388 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1389
1390
1391
1392
1393
1394 .all_events = MMA8452_INT_DRDY |
1395 MMA8452_INT_TRANS |
1396 MMA8452_INT_FF_MT,
1397 .enabled_events = MMA8452_INT_TRANS |
1398 MMA8452_INT_FF_MT,
1399 },
1400};
1401
1402static struct attribute *mma8452_attributes[] = {
1403 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1404 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1405 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1406 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr,
1407 NULL
1408};
1409
1410static const struct attribute_group mma8452_group = {
1411 .attrs = mma8452_attributes,
1412};
1413
1414static const struct iio_info mma8452_info = {
1415 .attrs = &mma8452_group,
1416 .read_raw = &mma8452_read_raw,
1417 .write_raw = &mma8452_write_raw,
1418 .event_attrs = &mma8452_event_attribute_group,
1419 .read_event_value = &mma8452_read_event_value,
1420 .write_event_value = &mma8452_write_event_value,
1421 .read_event_config = &mma8452_read_event_config,
1422 .write_event_config = &mma8452_write_event_config,
1423 .debugfs_reg_access = &mma8452_reg_access_dbg,
1424};
1425
1426static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1427
1428static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1429 bool state)
1430{
1431 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1432 struct mma8452_data *data = iio_priv(indio_dev);
1433 int reg, ret;
1434
1435 ret = mma8452_set_runtime_pm_state(data->client, state);
1436 if (ret)
1437 return ret;
1438
1439 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1440 if (reg < 0)
1441 return reg;
1442
1443 if (state)
1444 reg |= MMA8452_INT_DRDY;
1445 else
1446 reg &= ~MMA8452_INT_DRDY;
1447
1448 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1449}
1450
1451static const struct iio_trigger_ops mma8452_trigger_ops = {
1452 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1453 .validate_device = iio_trigger_validate_own_device,
1454};
1455
1456static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1457{
1458 struct mma8452_data *data = iio_priv(indio_dev);
1459 struct iio_trigger *trig;
1460 int ret;
1461
1462 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1463 indio_dev->name,
1464 indio_dev->id);
1465 if (!trig)
1466 return -ENOMEM;
1467
1468 trig->dev.parent = &data->client->dev;
1469 trig->ops = &mma8452_trigger_ops;
1470 iio_trigger_set_drvdata(trig, indio_dev);
1471
1472 ret = iio_trigger_register(trig);
1473 if (ret)
1474 return ret;
1475
1476 indio_dev->trig = trig;
1477
1478 return 0;
1479}
1480
1481static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1482{
1483 if (indio_dev->trig)
1484 iio_trigger_unregister(indio_dev->trig);
1485}
1486
1487static int mma8452_reset(struct i2c_client *client)
1488{
1489 int i;
1490 int ret;
1491
1492 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1493 MMA8452_CTRL_REG2_RST);
1494 if (ret < 0)
1495 return ret;
1496
1497 for (i = 0; i < 10; i++) {
1498 usleep_range(100, 200);
1499 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1500 if (ret == -EIO)
1501 continue;
1502 if (ret < 0)
1503 return ret;
1504 if (!(ret & MMA8452_CTRL_REG2_RST))
1505 return 0;
1506 }
1507
1508 return -ETIMEDOUT;
1509}
1510
1511static const struct of_device_id mma8452_dt_ids[] = {
1512 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1513 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1514 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1515 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1516 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1517 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1518 { }
1519};
1520MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1521
1522static int mma8452_probe(struct i2c_client *client,
1523 const struct i2c_device_id *id)
1524{
1525 struct mma8452_data *data;
1526 struct iio_dev *indio_dev;
1527 int ret;
1528 const struct of_device_id *match;
1529
1530 match = of_match_device(mma8452_dt_ids, &client->dev);
1531 if (!match) {
1532 dev_err(&client->dev, "unknown device model\n");
1533 return -ENODEV;
1534 }
1535
1536 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1537 if (!indio_dev)
1538 return -ENOMEM;
1539
1540 data = iio_priv(indio_dev);
1541 data->client = client;
1542 mutex_init(&data->lock);
1543 data->chip_info = match->data;
1544
1545 data->vdd_reg = devm_regulator_get(&client->dev, "vdd");
1546 if (IS_ERR(data->vdd_reg))
1547 return dev_err_probe(&client->dev, PTR_ERR(data->vdd_reg),
1548 "failed to get VDD regulator!\n");
1549
1550 data->vddio_reg = devm_regulator_get(&client->dev, "vddio");
1551 if (IS_ERR(data->vddio_reg))
1552 return dev_err_probe(&client->dev, PTR_ERR(data->vddio_reg),
1553 "failed to get VDDIO regulator!\n");
1554
1555 ret = regulator_enable(data->vdd_reg);
1556 if (ret) {
1557 dev_err(&client->dev, "failed to enable VDD regulator!\n");
1558 return ret;
1559 }
1560
1561 ret = regulator_enable(data->vddio_reg);
1562 if (ret) {
1563 dev_err(&client->dev, "failed to enable VDDIO regulator!\n");
1564 goto disable_regulator_vdd;
1565 }
1566
1567 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1568 if (ret < 0)
1569 goto disable_regulators;
1570
1571 switch (ret) {
1572 case MMA8451_DEVICE_ID:
1573 case MMA8452_DEVICE_ID:
1574 case MMA8453_DEVICE_ID:
1575 case MMA8652_DEVICE_ID:
1576 case MMA8653_DEVICE_ID:
1577 case FXLS8471_DEVICE_ID:
1578 if (ret == data->chip_info->chip_id)
1579 break;
1580 fallthrough;
1581 default:
1582 ret = -ENODEV;
1583 goto disable_regulators;
1584 }
1585
1586 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1587 match->compatible, data->chip_info->chip_id);
1588
1589 i2c_set_clientdata(client, indio_dev);
1590 indio_dev->info = &mma8452_info;
1591 indio_dev->name = id->name;
1592 indio_dev->modes = INDIO_DIRECT_MODE;
1593 indio_dev->channels = data->chip_info->channels;
1594 indio_dev->num_channels = data->chip_info->num_channels;
1595 indio_dev->available_scan_masks = mma8452_scan_masks;
1596
1597 ret = mma8452_reset(client);
1598 if (ret < 0)
1599 goto disable_regulators;
1600
1601 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1602 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1603 data->data_cfg);
1604 if (ret < 0)
1605 goto disable_regulators;
1606
1607
1608
1609
1610
1611 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1612 MMA8452_TRANSIENT_THS_MASK);
1613 if (ret < 0)
1614 goto disable_regulators;
1615
1616 if (client->irq) {
1617 int irq2;
1618
1619 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1620
1621 if (irq2 == client->irq) {
1622 dev_dbg(&client->dev, "using interrupt line INT2\n");
1623 } else {
1624 ret = i2c_smbus_write_byte_data(client,
1625 MMA8452_CTRL_REG5,
1626 data->chip_info->all_events);
1627 if (ret < 0)
1628 goto disable_regulators;
1629
1630 dev_dbg(&client->dev, "using interrupt line INT1\n");
1631 }
1632
1633 ret = i2c_smbus_write_byte_data(client,
1634 MMA8452_CTRL_REG4,
1635 data->chip_info->enabled_events);
1636 if (ret < 0)
1637 goto disable_regulators;
1638
1639 ret = mma8452_trigger_setup(indio_dev);
1640 if (ret < 0)
1641 goto disable_regulators;
1642 }
1643
1644 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1645 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1646
1647 data->sleep_val = mma8452_calculate_sleep(data);
1648
1649 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1650 data->ctrl_reg1);
1651 if (ret < 0)
1652 goto trigger_cleanup;
1653
1654 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1655 mma8452_trigger_handler, NULL);
1656 if (ret < 0)
1657 goto trigger_cleanup;
1658
1659 if (client->irq) {
1660 ret = devm_request_threaded_irq(&client->dev,
1661 client->irq,
1662 NULL, mma8452_interrupt,
1663 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1664 client->name, indio_dev);
1665 if (ret)
1666 goto buffer_cleanup;
1667 }
1668
1669 ret = pm_runtime_set_active(&client->dev);
1670 if (ret < 0)
1671 goto buffer_cleanup;
1672
1673 pm_runtime_enable(&client->dev);
1674 pm_runtime_set_autosuspend_delay(&client->dev,
1675 MMA8452_AUTO_SUSPEND_DELAY_MS);
1676 pm_runtime_use_autosuspend(&client->dev);
1677
1678 ret = iio_device_register(indio_dev);
1679 if (ret < 0)
1680 goto buffer_cleanup;
1681
1682 ret = mma8452_set_freefall_mode(data, false);
1683 if (ret < 0)
1684 goto unregister_device;
1685
1686 return 0;
1687
1688unregister_device:
1689 iio_device_unregister(indio_dev);
1690
1691buffer_cleanup:
1692 iio_triggered_buffer_cleanup(indio_dev);
1693
1694trigger_cleanup:
1695 mma8452_trigger_cleanup(indio_dev);
1696
1697disable_regulators:
1698 regulator_disable(data->vddio_reg);
1699
1700disable_regulator_vdd:
1701 regulator_disable(data->vdd_reg);
1702
1703 return ret;
1704}
1705
1706static int mma8452_remove(struct i2c_client *client)
1707{
1708 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1709 struct mma8452_data *data = iio_priv(indio_dev);
1710
1711 iio_device_unregister(indio_dev);
1712
1713 pm_runtime_disable(&client->dev);
1714 pm_runtime_set_suspended(&client->dev);
1715 pm_runtime_put_noidle(&client->dev);
1716
1717 iio_triggered_buffer_cleanup(indio_dev);
1718 mma8452_trigger_cleanup(indio_dev);
1719 mma8452_standby(iio_priv(indio_dev));
1720
1721 regulator_disable(data->vddio_reg);
1722 regulator_disable(data->vdd_reg);
1723
1724 return 0;
1725}
1726
1727#ifdef CONFIG_PM
1728static int mma8452_runtime_suspend(struct device *dev)
1729{
1730 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1731 struct mma8452_data *data = iio_priv(indio_dev);
1732 int ret;
1733
1734 mutex_lock(&data->lock);
1735 ret = mma8452_standby(data);
1736 mutex_unlock(&data->lock);
1737 if (ret < 0) {
1738 dev_err(&data->client->dev, "powering off device failed\n");
1739 return -EAGAIN;
1740 }
1741
1742 ret = regulator_disable(data->vddio_reg);
1743 if (ret) {
1744 dev_err(dev, "failed to disable VDDIO regulator\n");
1745 return ret;
1746 }
1747
1748 ret = regulator_disable(data->vdd_reg);
1749 if (ret) {
1750 dev_err(dev, "failed to disable VDD regulator\n");
1751 return ret;
1752 }
1753
1754 return 0;
1755}
1756
1757static int mma8452_runtime_resume(struct device *dev)
1758{
1759 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1760 struct mma8452_data *data = iio_priv(indio_dev);
1761 int ret, sleep_val;
1762
1763 ret = regulator_enable(data->vdd_reg);
1764 if (ret) {
1765 dev_err(dev, "failed to enable VDD regulator\n");
1766 return ret;
1767 }
1768
1769 ret = regulator_enable(data->vddio_reg);
1770 if (ret) {
1771 dev_err(dev, "failed to enable VDDIO regulator\n");
1772 regulator_disable(data->vdd_reg);
1773 return ret;
1774 }
1775
1776 ret = mma8452_active(data);
1777 if (ret < 0)
1778 goto runtime_resume_failed;
1779
1780 ret = mma8452_get_odr_index(data);
1781 sleep_val = 1000 / mma8452_samp_freq[ret][0];
1782 if (sleep_val < 20)
1783 usleep_range(sleep_val * 1000, 20000);
1784 else
1785 msleep_interruptible(sleep_val);
1786
1787 return 0;
1788
1789runtime_resume_failed:
1790 regulator_disable(data->vddio_reg);
1791 regulator_disable(data->vdd_reg);
1792
1793 return ret;
1794}
1795#endif
1796
1797static const struct dev_pm_ops mma8452_pm_ops = {
1798 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1799 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1800 mma8452_runtime_resume, NULL)
1801};
1802
1803static const struct i2c_device_id mma8452_id[] = {
1804 { "mma8451", mma8451 },
1805 { "mma8452", mma8452 },
1806 { "mma8453", mma8453 },
1807 { "mma8652", mma8652 },
1808 { "mma8653", mma8653 },
1809 { "fxls8471", fxls8471 },
1810 { }
1811};
1812MODULE_DEVICE_TABLE(i2c, mma8452_id);
1813
1814static struct i2c_driver mma8452_driver = {
1815 .driver = {
1816 .name = "mma8452",
1817 .of_match_table = of_match_ptr(mma8452_dt_ids),
1818 .pm = &mma8452_pm_ops,
1819 },
1820 .probe = mma8452_probe,
1821 .remove = mma8452_remove,
1822 .id_table = mma8452_id,
1823};
1824module_i2c_driver(mma8452_driver);
1825
1826MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1827MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver");
1828MODULE_LICENSE("GPL");
1829
