LXR linux/drivers/irqchip/irq-versatile-fpga.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 *  Support for Versatile FPGA-based IRQ controllers
   4 */
   5#include <linux/bitops.h>
   6#include <linux/irq.h>
   7#include <linux/io.h>
   8#include <linux/irqchip.h>
   9#include <linux/irqchip/chained_irq.h>
  10#include <linux/irqchip/versatile-fpga.h>
  11#include <linux/irqdomain.h>
  12#include <linux/module.h>
  13#include <linux/of.h>
  14#include <linux/of_address.h>
  15#include <linux/of_irq.h>
  16
  17#include <asm/exception.h>
  18#include <asm/mach/irq.h>
  19
  20#define IRQ_STATUS              0x00
  21#define IRQ_RAW_STATUS          0x04
  22#define IRQ_ENABLE_SET          0x08
  23#define IRQ_ENABLE_CLEAR        0x0c
  24#define INT_SOFT_SET            0x10
  25#define INT_SOFT_CLEAR          0x14
  26#define FIQ_STATUS              0x20
  27#define FIQ_RAW_STATUS          0x24
  28#define FIQ_ENABLE              0x28
  29#define FIQ_ENABLE_SET          0x28
  30#define FIQ_ENABLE_CLEAR        0x2C
  31
  32#define PIC_ENABLES             0x20    /* set interrupt pass through bits */
  33
  34/**
  35 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
  36 * @base: memory offset in virtual memory
  37 * @chip: chip container for this instance
  38 * @domain: IRQ domain for this instance
  39 * @valid: mask for valid IRQs on this controller
  40 * @used_irqs: number of active IRQs on this controller
  41 */
  42struct fpga_irq_data {
  43        void __iomem *base;
  44        struct irq_chip chip;
  45        u32 valid;
  46        struct irq_domain *domain;
  47        u8 used_irqs;
  48};
  49
  50/* we cannot allocate memory when the controllers are initially registered */
  51static struct fpga_irq_data fpga_irq_devices[CONFIG_VERSATILE_FPGA_IRQ_NR];
  52static int fpga_irq_id;
  53
  54static void fpga_irq_mask(struct irq_data *d)
  55{
  56        struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
  57        u32 mask = 1 << d->hwirq;
  58
  59        writel(mask, f->base + IRQ_ENABLE_CLEAR);
  60}
  61
  62static void fpga_irq_unmask(struct irq_data *d)
  63{
  64        struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
  65        u32 mask = 1 << d->hwirq;
  66
  67        writel(mask, f->base + IRQ_ENABLE_SET);
  68}
  69
  70static void fpga_irq_handle(struct irq_desc *desc)
  71{
  72        struct irq_chip *chip = irq_desc_get_chip(desc);
  73        struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
  74        u32 status;
  75
  76        chained_irq_enter(chip, desc);
  77
  78        status = readl(f->base + IRQ_STATUS);
  79        if (status == 0) {
  80                do_bad_IRQ(desc);
  81                goto out;
  82        }
  83
  84        do {
  85                unsigned int irq = ffs(status) - 1;
  86
  87                status &= ~(1 << irq);
  88                generic_handle_irq(irq_find_mapping(f->domain, irq));
  89        } while (status);
  90
  91out:
  92        chained_irq_exit(chip, desc);
  93}
  94
  95/*
  96 * Handle each interrupt in a single FPGA IRQ controller.  Returns non-zero
  97 * if we've handled at least one interrupt.  This does a single read of the
  98 * status register and handles all interrupts in order from LSB first.
  99 */
 100static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
 101{
 102        int handled = 0;
 103        int irq;
 104        u32 status;
 105
 106        while ((status  = readl(f->base + IRQ_STATUS))) {
 107                irq = ffs(status) - 1;
 108                handle_domain_irq(f->domain, irq, regs);
 109                handled = 1;
 110        }
 111
 112        return handled;
 113}
 114
 115/*
 116 * Keep iterating over all registered FPGA IRQ controllers until there are
 117 * no pending interrupts.
 118 */
 119asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
 120{
 121        int i, handled;
 122
 123        do {
 124                for (i = 0, handled = 0; i < fpga_irq_id; ++i)
 125                        handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
 126        } while (handled);
 127}
 128
 129static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
 130                irq_hw_number_t hwirq)
 131{
 132        struct fpga_irq_data *f = d->host_data;
 133
 134        /* Skip invalid IRQs, only register handlers for the real ones */
 135        if (!(f->valid & BIT(hwirq)))
 136                return -EPERM;
 137        irq_set_chip_data(irq, f);
 138        irq_set_chip_and_handler(irq, &f->chip,
 139                                handle_level_irq);
 140        irq_set_probe(irq);
 141        return 0;
 142}
 143
 144static const struct irq_domain_ops fpga_irqdomain_ops = {
 145        .map = fpga_irqdomain_map,
 146        .xlate = irq_domain_xlate_onetwocell,
 147};
 148
 149void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
 150                          int parent_irq, u32 valid, struct device_node *node)
 151{
 152        struct fpga_irq_data *f;
 153        int i;
 154
 155        if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
 156                pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_VERSATILE_FPGA_IRQ_NR\n", __func__);
 157                return;
 158        }
 159        f = &fpga_irq_devices[fpga_irq_id];
 160        f->base = base;
 161        f->chip.name = name;
 162        f->chip.irq_ack = fpga_irq_mask;
 163        f->chip.irq_mask = fpga_irq_mask;
 164        f->chip.irq_unmask = fpga_irq_unmask;
 165        f->valid = valid;
 166
 167        if (parent_irq != -1) {
 168                irq_set_chained_handler_and_data(parent_irq, fpga_irq_handle,
 169                                                 f);
 170        }
 171
 172        /* This will also allocate irq descriptors */
 173        f->domain = irq_domain_add_simple(node, fls(valid), irq_start,
 174                                          &fpga_irqdomain_ops, f);
 175
 176        /* This will allocate all valid descriptors in the linear case */
 177        for (i = 0; i < fls(valid); i++)
 178                if (valid & BIT(i)) {
 179                        if (!irq_start)
 180                                irq_create_mapping(f->domain, i);
 181                        f->used_irqs++;
 182                }
 183
 184        pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs",
 185                fpga_irq_id, name, base, f->used_irqs);
 186        if (parent_irq != -1)
 187                pr_cont(", parent IRQ: %d\n", parent_irq);
 188        else
 189                pr_cont("\n");
 190
 191        fpga_irq_id++;
 192}
 193
 194#ifdef CONFIG_OF
 195int __init fpga_irq_of_init(struct device_node *node,
 196                            struct device_node *parent)
 197{
 198        void __iomem *base;
 199        u32 clear_mask;
 200        u32 valid_mask;
 201        int parent_irq;
 202
 203        if (WARN_ON(!node))
 204                return -ENODEV;
 205
 206        base = of_iomap(node, 0);
 207        WARN(!base, "unable to map fpga irq registers\n");
 208
 209        if (of_property_read_u32(node, "clear-mask", &clear_mask))
 210                clear_mask = 0;
 211
 212        if (of_property_read_u32(node, "valid-mask", &valid_mask))
 213                valid_mask = 0;
 214
 215        writel(clear_mask, base + IRQ_ENABLE_CLEAR);
 216        writel(clear_mask, base + FIQ_ENABLE_CLEAR);
 217
 218        /* Some chips are cascaded from a parent IRQ */
 219        parent_irq = irq_of_parse_and_map(node, 0);
 220        if (!parent_irq) {
 221                set_handle_irq(fpga_handle_irq);
 222                parent_irq = -1;
 223        }
 224
 225        fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
 226
 227        /*
 228         * On Versatile AB/PB, some secondary interrupts have a direct
 229         * pass-thru to the primary controller for IRQs 20 and 22-31 which need
 230         * to be enabled. See section 3.10 of the Versatile AB user guide.
 231         */
 232        if (of_device_is_compatible(node, "arm,versatile-sic"))
 233                writel(0xffd00000, base + PIC_ENABLES);
 234
 235        return 0;
 236}
 237IRQCHIP_DECLARE(arm_fpga, "arm,versatile-fpga-irq", fpga_irq_of_init);
 238IRQCHIP_DECLARE(arm_fpga_sic, "arm,versatile-sic", fpga_irq_of_init);
 239IRQCHIP_DECLARE(ox810se_rps, "oxsemi,ox810se-rps-irq", fpga_irq_of_init);
 240#endif
 241