1
2
3
4#include <asm/unaligned.h>
5#include <linux/acpi.h>
6#include <linux/delay.h>
7#include <linux/i2c.h>
8#include <linux/module.h>
9#include <linux/pm_runtime.h>
10#include <linux/nvmem-provider.h>
11#include <linux/regmap.h>
12#include <media/v4l2-ctrls.h>
13#include <media/v4l2-device.h>
14#include <media/v4l2-fwnode.h>
15
16#define OV2740_LINK_FREQ_360MHZ 360000000ULL
17#define OV2740_SCLK 72000000LL
18#define OV2740_MCLK 19200000
19#define OV2740_DATA_LANES 2
20#define OV2740_RGB_DEPTH 10
21
22#define OV2740_REG_CHIP_ID 0x300a
23#define OV2740_CHIP_ID 0x2740
24
25#define OV2740_REG_MODE_SELECT 0x0100
26#define OV2740_MODE_STANDBY 0x00
27#define OV2740_MODE_STREAMING 0x01
28
29
30#define OV2740_REG_VTS 0x380e
31#define OV2740_VTS_DEF 0x088a
32#define OV2740_VTS_MIN 0x0460
33#define OV2740_VTS_MAX 0x7fff
34
35
36#define OV2740_REG_HTS 0x380c
37
38
39#define OV2740_REG_EXPOSURE 0x3500
40#define OV2740_EXPOSURE_MIN 4
41#define OV2740_EXPOSURE_MAX_MARGIN 8
42#define OV2740_EXPOSURE_STEP 1
43
44
45#define OV2740_REG_ANALOG_GAIN 0x3508
46#define OV2740_ANAL_GAIN_MIN 128
47#define OV2740_ANAL_GAIN_MAX 1983
48#define OV2740_ANAL_GAIN_STEP 1
49
50
51#define OV2740_REG_MWB_R_GAIN 0x500a
52#define OV2740_REG_MWB_G_GAIN 0x500c
53#define OV2740_REG_MWB_B_GAIN 0x500e
54#define OV2740_DGTL_GAIN_MIN 0
55#define OV2740_DGTL_GAIN_MAX 4095
56#define OV2740_DGTL_GAIN_STEP 1
57#define OV2740_DGTL_GAIN_DEFAULT 1024
58
59
60#define OV2740_REG_TEST_PATTERN 0x5040
61#define OV2740_TEST_PATTERN_ENABLE BIT(7)
62#define OV2740_TEST_PATTERN_BAR_SHIFT 2
63
64
65#define OV2740_REG_ISP_CTRL00 0x5000
66
67#define OV2740_REG_ISP_CTRL01 0x5001
68
69#define CUSTOMER_USE_OTP_SIZE 0x100
70
71#define OV2740_REG_OTP_CUSTOMER 0x7010
72
73struct nvm_data {
74 struct i2c_client *client;
75 struct nvmem_device *nvmem;
76 struct regmap *regmap;
77 char *nvm_buffer;
78};
79
80enum {
81 OV2740_LINK_FREQ_360MHZ_INDEX,
82};
83
84struct ov2740_reg {
85 u16 address;
86 u8 val;
87};
88
89struct ov2740_reg_list {
90 u32 num_of_regs;
91 const struct ov2740_reg *regs;
92};
93
94struct ov2740_link_freq_config {
95 const struct ov2740_reg_list reg_list;
96};
97
98struct ov2740_mode {
99
100 u32 width;
101
102
103 u32 height;
104
105
106 u32 hts;
107
108
109 u32 vts_def;
110
111
112 u32 vts_min;
113
114
115 u32 link_freq_index;
116
117
118 const struct ov2740_reg_list reg_list;
119};
120
121static const struct ov2740_reg mipi_data_rate_720mbps[] = {
122 {0x0103, 0x01},
123 {0x0302, 0x4b},
124 {0x030d, 0x4b},
125 {0x030e, 0x02},
126 {0x030a, 0x01},
127 {0x0312, 0x11},
128};
129
130static const struct ov2740_reg mode_1932x1092_regs[] = {
131 {0x3000, 0x00},
132 {0x3018, 0x32},
133 {0x3031, 0x0a},
134 {0x3080, 0x08},
135 {0x3083, 0xB4},
136 {0x3103, 0x00},
137 {0x3104, 0x01},
138 {0x3106, 0x01},
139 {0x3500, 0x00},
140 {0x3501, 0x44},
141 {0x3502, 0x40},
142 {0x3503, 0x88},
143 {0x3507, 0x00},
144 {0x3508, 0x00},
145 {0x3509, 0x80},
146 {0x350c, 0x00},
147 {0x350d, 0x80},
148 {0x3510, 0x00},
149 {0x3511, 0x00},
150 {0x3512, 0x20},
151 {0x3632, 0x00},
152 {0x3633, 0x10},
153 {0x3634, 0x10},
154 {0x3635, 0x10},
155 {0x3645, 0x13},
156 {0x3646, 0x81},
157 {0x3636, 0x10},
158 {0x3651, 0x0a},
159 {0x3656, 0x02},
160 {0x3659, 0x04},
161 {0x365a, 0xda},
162 {0x365b, 0xa2},
163 {0x365c, 0x04},
164 {0x365d, 0x1d},
165 {0x365e, 0x1a},
166 {0x3662, 0xd7},
167 {0x3667, 0x78},
168 {0x3669, 0x0a},
169 {0x366a, 0x92},
170 {0x3700, 0x54},
171 {0x3702, 0x10},
172 {0x3706, 0x42},
173 {0x3709, 0x30},
174 {0x370b, 0xc2},
175 {0x3714, 0x63},
176 {0x3715, 0x01},
177 {0x3716, 0x00},
178 {0x371a, 0x3e},
179 {0x3732, 0x0e},
180 {0x3733, 0x10},
181 {0x375f, 0x0e},
182 {0x3768, 0x30},
183 {0x3769, 0x44},
184 {0x376a, 0x22},
185 {0x377b, 0x20},
186 {0x377c, 0x00},
187 {0x377d, 0x0c},
188 {0x3798, 0x00},
189 {0x37a1, 0x55},
190 {0x37a8, 0x6d},
191 {0x37c2, 0x04},
192 {0x37c5, 0x00},
193 {0x37c8, 0x00},
194 {0x3800, 0x00},
195 {0x3801, 0x00},
196 {0x3802, 0x00},
197 {0x3803, 0x00},
198 {0x3804, 0x07},
199 {0x3805, 0x8f},
200 {0x3806, 0x04},
201 {0x3807, 0x47},
202 {0x3808, 0x07},
203 {0x3809, 0x88},
204 {0x380a, 0x04},
205 {0x380b, 0x40},
206 {0x380c, 0x04},
207 {0x380d, 0x38},
208 {0x380e, 0x04},
209 {0x380f, 0x60},
210 {0x3810, 0x00},
211 {0x3811, 0x04},
212 {0x3812, 0x00},
213 {0x3813, 0x04},
214 {0x3814, 0x01},
215 {0x3815, 0x01},
216 {0x3820, 0x80},
217 {0x3821, 0x46},
218 {0x3822, 0x84},
219 {0x3829, 0x00},
220 {0x382a, 0x01},
221 {0x382b, 0x01},
222 {0x3830, 0x04},
223 {0x3836, 0x01},
224 {0x3837, 0x08},
225 {0x3839, 0x01},
226 {0x383a, 0x00},
227 {0x383b, 0x08},
228 {0x383c, 0x00},
229 {0x3f0b, 0x00},
230 {0x4001, 0x20},
231 {0x4009, 0x07},
232 {0x4003, 0x10},
233 {0x4010, 0xe0},
234 {0x4016, 0x00},
235 {0x4017, 0x10},
236 {0x4044, 0x02},
237 {0x4304, 0x08},
238 {0x4307, 0x30},
239 {0x4320, 0x80},
240 {0x4322, 0x00},
241 {0x4323, 0x00},
242 {0x4324, 0x00},
243 {0x4325, 0x00},
244 {0x4326, 0x00},
245 {0x4327, 0x00},
246 {0x4328, 0x00},
247 {0x4329, 0x00},
248 {0x432c, 0x03},
249 {0x432d, 0x81},
250 {0x4501, 0x84},
251 {0x4502, 0x40},
252 {0x4503, 0x18},
253 {0x4504, 0x04},
254 {0x4508, 0x02},
255 {0x4601, 0x10},
256 {0x4800, 0x00},
257 {0x4816, 0x52},
258 {0x4837, 0x16},
259 {0x5000, 0x7f},
260 {0x5001, 0x00},
261 {0x5005, 0x38},
262 {0x501e, 0x0d},
263 {0x5040, 0x00},
264 {0x5901, 0x00},
265 {0x3800, 0x00},
266 {0x3801, 0x00},
267 {0x3802, 0x00},
268 {0x3803, 0x00},
269 {0x3804, 0x07},
270 {0x3805, 0x8f},
271 {0x3806, 0x04},
272 {0x3807, 0x47},
273 {0x3808, 0x07},
274 {0x3809, 0x8c},
275 {0x380a, 0x04},
276 {0x380b, 0x44},
277 {0x3810, 0x00},
278 {0x3811, 0x00},
279 {0x3812, 0x00},
280 {0x3813, 0x01},
281};
282
283static const char * const ov2740_test_pattern_menu[] = {
284 "Disabled",
285 "Color Bar",
286 "Top-Bottom Darker Color Bar",
287 "Right-Left Darker Color Bar",
288 "Bottom-Top Darker Color Bar",
289};
290
291static const s64 link_freq_menu_items[] = {
292 OV2740_LINK_FREQ_360MHZ,
293};
294
295static const struct ov2740_link_freq_config link_freq_configs[] = {
296 [OV2740_LINK_FREQ_360MHZ_INDEX] = {
297 .reg_list = {
298 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
299 .regs = mipi_data_rate_720mbps,
300 }
301 },
302};
303
304static const struct ov2740_mode supported_modes[] = {
305 {
306 .width = 1932,
307 .height = 1092,
308 .hts = 1080,
309 .vts_def = OV2740_VTS_DEF,
310 .vts_min = OV2740_VTS_MIN,
311 .reg_list = {
312 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs),
313 .regs = mode_1932x1092_regs,
314 },
315 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX,
316 },
317};
318
319struct ov2740 {
320 struct v4l2_subdev sd;
321 struct media_pad pad;
322 struct v4l2_ctrl_handler ctrl_handler;
323
324
325 struct v4l2_ctrl *link_freq;
326 struct v4l2_ctrl *pixel_rate;
327 struct v4l2_ctrl *vblank;
328 struct v4l2_ctrl *hblank;
329 struct v4l2_ctrl *exposure;
330
331
332 const struct ov2740_mode *cur_mode;
333
334
335 struct mutex mutex;
336
337
338 bool streaming;
339
340
341 struct nvm_data *nvm;
342};
343
344static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev)
345{
346 return container_of(subdev, struct ov2740, sd);
347}
348
349static u64 to_pixel_rate(u32 f_index)
350{
351 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES;
352
353 do_div(pixel_rate, OV2740_RGB_DEPTH);
354
355 return pixel_rate;
356}
357
358static u64 to_pixels_per_line(u32 hts, u32 f_index)
359{
360 u64 ppl = hts * to_pixel_rate(f_index);
361
362 do_div(ppl, OV2740_SCLK);
363
364 return ppl;
365}
366
367static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val)
368{
369 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
370 struct i2c_msg msgs[2];
371 u8 addr_buf[2];
372 u8 data_buf[4] = {0};
373 int ret = 0;
374
375 if (len > sizeof(data_buf))
376 return -EINVAL;
377
378 put_unaligned_be16(reg, addr_buf);
379 msgs[0].addr = client->addr;
380 msgs[0].flags = 0;
381 msgs[0].len = sizeof(addr_buf);
382 msgs[0].buf = addr_buf;
383 msgs[1].addr = client->addr;
384 msgs[1].flags = I2C_M_RD;
385 msgs[1].len = len;
386 msgs[1].buf = &data_buf[sizeof(data_buf) - len];
387
388 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
389 if (ret != ARRAY_SIZE(msgs))
390 return ret < 0 ? ret : -EIO;
391
392 *val = get_unaligned_be32(data_buf);
393
394 return 0;
395}
396
397static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val)
398{
399 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
400 u8 buf[6];
401 int ret = 0;
402
403 if (len > 4)
404 return -EINVAL;
405
406 put_unaligned_be16(reg, buf);
407 put_unaligned_be32(val << 8 * (4 - len), buf + 2);
408
409 ret = i2c_master_send(client, buf, len + 2);
410 if (ret != len + 2)
411 return ret < 0 ? ret : -EIO;
412
413 return 0;
414}
415
416static int ov2740_write_reg_list(struct ov2740 *ov2740,
417 const struct ov2740_reg_list *r_list)
418{
419 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
420 unsigned int i;
421 int ret = 0;
422
423 for (i = 0; i < r_list->num_of_regs; i++) {
424 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1,
425 r_list->regs[i].val);
426 if (ret) {
427 dev_err_ratelimited(&client->dev,
428 "write reg 0x%4.4x return err = %d",
429 r_list->regs[i].address, ret);
430 return ret;
431 }
432 }
433
434 return 0;
435}
436
437static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain)
438{
439 int ret = 0;
440
441 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain);
442 if (ret)
443 return ret;
444
445 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain);
446 if (ret)
447 return ret;
448
449 return ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain);
450}
451
452static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern)
453{
454 if (pattern)
455 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT |
456 OV2740_TEST_PATTERN_ENABLE;
457
458 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern);
459}
460
461static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl)
462{
463 struct ov2740 *ov2740 = container_of(ctrl->handler,
464 struct ov2740, ctrl_handler);
465 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
466 s64 exposure_max;
467 int ret = 0;
468
469
470 if (ctrl->id == V4L2_CID_VBLANK) {
471
472 exposure_max = ov2740->cur_mode->height + ctrl->val -
473 OV2740_EXPOSURE_MAX_MARGIN;
474 __v4l2_ctrl_modify_range(ov2740->exposure,
475 ov2740->exposure->minimum,
476 exposure_max, ov2740->exposure->step,
477 exposure_max);
478 }
479
480
481 if (!pm_runtime_get_if_in_use(&client->dev))
482 return 0;
483
484 switch (ctrl->id) {
485 case V4L2_CID_ANALOGUE_GAIN:
486 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2,
487 ctrl->val);
488 break;
489
490 case V4L2_CID_DIGITAL_GAIN:
491 ret = ov2740_update_digital_gain(ov2740, ctrl->val);
492 break;
493
494 case V4L2_CID_EXPOSURE:
495
496 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3,
497 ctrl->val << 4);
498 break;
499
500 case V4L2_CID_VBLANK:
501 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2,
502 ov2740->cur_mode->height + ctrl->val);
503 break;
504
505 case V4L2_CID_TEST_PATTERN:
506 ret = ov2740_test_pattern(ov2740, ctrl->val);
507 break;
508
509 default:
510 ret = -EINVAL;
511 break;
512 }
513
514 pm_runtime_put(&client->dev);
515
516 return ret;
517}
518
519static const struct v4l2_ctrl_ops ov2740_ctrl_ops = {
520 .s_ctrl = ov2740_set_ctrl,
521};
522
523static int ov2740_init_controls(struct ov2740 *ov2740)
524{
525 struct v4l2_ctrl_handler *ctrl_hdlr;
526 const struct ov2740_mode *cur_mode;
527 s64 exposure_max, h_blank, pixel_rate;
528 u32 vblank_min, vblank_max, vblank_default;
529 int size;
530 int ret = 0;
531
532 ctrl_hdlr = &ov2740->ctrl_handler;
533 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
534 if (ret)
535 return ret;
536
537 ctrl_hdlr->lock = &ov2740->mutex;
538 cur_mode = ov2740->cur_mode;
539 size = ARRAY_SIZE(link_freq_menu_items);
540
541 ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops,
542 V4L2_CID_LINK_FREQ,
543 size - 1, 0,
544 link_freq_menu_items);
545 if (ov2740->link_freq)
546 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
547
548 pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX);
549 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
550 V4L2_CID_PIXEL_RATE, 0,
551 pixel_rate, 1, pixel_rate);
552
553 vblank_min = cur_mode->vts_min - cur_mode->height;
554 vblank_max = OV2740_VTS_MAX - cur_mode->height;
555 vblank_default = cur_mode->vts_def - cur_mode->height;
556 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
557 V4L2_CID_VBLANK, vblank_min,
558 vblank_max, 1, vblank_default);
559
560 h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index);
561 h_blank -= cur_mode->width;
562 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
563 V4L2_CID_HBLANK, h_blank, h_blank, 1,
564 h_blank);
565 if (ov2740->hblank)
566 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
567
568 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
569 OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX,
570 OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN);
571 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
572 OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX,
573 OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT);
574 exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN;
575 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
576 V4L2_CID_EXPOSURE,
577 OV2740_EXPOSURE_MIN, exposure_max,
578 OV2740_EXPOSURE_STEP,
579 exposure_max);
580 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops,
581 V4L2_CID_TEST_PATTERN,
582 ARRAY_SIZE(ov2740_test_pattern_menu) - 1,
583 0, 0, ov2740_test_pattern_menu);
584 if (ctrl_hdlr->error)
585 return ctrl_hdlr->error;
586
587 ov2740->sd.ctrl_handler = ctrl_hdlr;
588
589 return 0;
590}
591
592static void ov2740_update_pad_format(const struct ov2740_mode *mode,
593 struct v4l2_mbus_framefmt *fmt)
594{
595 fmt->width = mode->width;
596 fmt->height = mode->height;
597 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
598 fmt->field = V4L2_FIELD_NONE;
599}
600
601static int ov2740_load_otp_data(struct nvm_data *nvm)
602{
603 struct i2c_client *client;
604 struct ov2740 *ov2740;
605 u32 isp_ctrl00 = 0;
606 u32 isp_ctrl01 = 0;
607 int ret;
608
609 if (!nvm)
610 return -EINVAL;
611
612 if (nvm->nvm_buffer)
613 return 0;
614
615 client = nvm->client;
616 ov2740 = to_ov2740(i2c_get_clientdata(client));
617
618 nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL);
619 if (!nvm->nvm_buffer)
620 return -ENOMEM;
621
622 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00);
623 if (ret) {
624 dev_err(&client->dev, "failed to read ISP CTRL00\n");
625 goto err;
626 }
627
628 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01);
629 if (ret) {
630 dev_err(&client->dev, "failed to read ISP CTRL01\n");
631 goto err;
632 }
633
634
635 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1,
636 isp_ctrl00 & ~BIT(5));
637 if (ret) {
638 dev_err(&client->dev, "failed to set ISP CTRL00\n");
639 goto err;
640 }
641
642
643 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1,
644 isp_ctrl01 & ~BIT(7));
645 if (ret) {
646 dev_err(&client->dev, "failed to set ISP CTRL01\n");
647 goto err;
648 }
649
650 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
651 OV2740_MODE_STREAMING);
652 if (ret) {
653 dev_err(&client->dev, "failed to set streaming mode\n");
654 goto err;
655 }
656
657
658
659
660
661 msleep(20);
662
663 ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER,
664 nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE);
665 if (ret) {
666 dev_err(&client->dev, "failed to read OTP data, ret %d\n", ret);
667 goto err;
668 }
669
670 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
671 OV2740_MODE_STANDBY);
672 if (ret) {
673 dev_err(&client->dev, "failed to set streaming mode\n");
674 goto err;
675 }
676
677 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01);
678 if (ret) {
679 dev_err(&client->dev, "failed to set ISP CTRL01\n");
680 goto err;
681 }
682
683 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00);
684 if (ret) {
685 dev_err(&client->dev, "failed to set ISP CTRL00\n");
686 goto err;
687 }
688
689 return 0;
690err:
691 kfree(nvm->nvm_buffer);
692 nvm->nvm_buffer = NULL;
693
694 return ret;
695}
696
697static int ov2740_start_streaming(struct ov2740 *ov2740)
698{
699 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
700 struct nvm_data *nvm = ov2740->nvm;
701 const struct ov2740_reg_list *reg_list;
702 int link_freq_index;
703 int ret = 0;
704
705 ov2740_load_otp_data(nvm);
706
707 link_freq_index = ov2740->cur_mode->link_freq_index;
708 reg_list = &link_freq_configs[link_freq_index].reg_list;
709 ret = ov2740_write_reg_list(ov2740, reg_list);
710 if (ret) {
711 dev_err(&client->dev, "failed to set plls");
712 return ret;
713 }
714
715 reg_list = &ov2740->cur_mode->reg_list;
716 ret = ov2740_write_reg_list(ov2740, reg_list);
717 if (ret) {
718 dev_err(&client->dev, "failed to set mode");
719 return ret;
720 }
721
722 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler);
723 if (ret)
724 return ret;
725
726 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
727 OV2740_MODE_STREAMING);
728 if (ret)
729 dev_err(&client->dev, "failed to start streaming");
730
731 return ret;
732}
733
734static void ov2740_stop_streaming(struct ov2740 *ov2740)
735{
736 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
737
738 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
739 OV2740_MODE_STANDBY))
740 dev_err(&client->dev, "failed to stop streaming");
741}
742
743static int ov2740_set_stream(struct v4l2_subdev *sd, int enable)
744{
745 struct ov2740 *ov2740 = to_ov2740(sd);
746 struct i2c_client *client = v4l2_get_subdevdata(sd);
747 int ret = 0;
748
749 if (ov2740->streaming == enable)
750 return 0;
751
752 mutex_lock(&ov2740->mutex);
753 if (enable) {
754 ret = pm_runtime_get_sync(&client->dev);
755 if (ret < 0) {
756 pm_runtime_put_noidle(&client->dev);
757 mutex_unlock(&ov2740->mutex);
758 return ret;
759 }
760
761 ret = ov2740_start_streaming(ov2740);
762 if (ret) {
763 enable = 0;
764 ov2740_stop_streaming(ov2740);
765 pm_runtime_put(&client->dev);
766 }
767 } else {
768 ov2740_stop_streaming(ov2740);
769 pm_runtime_put(&client->dev);
770 }
771
772 ov2740->streaming = enable;
773 mutex_unlock(&ov2740->mutex);
774
775 return ret;
776}
777
778static int __maybe_unused ov2740_suspend(struct device *dev)
779{
780 struct v4l2_subdev *sd = dev_get_drvdata(dev);
781 struct ov2740 *ov2740 = to_ov2740(sd);
782
783 mutex_lock(&ov2740->mutex);
784 if (ov2740->streaming)
785 ov2740_stop_streaming(ov2740);
786
787 mutex_unlock(&ov2740->mutex);
788
789 return 0;
790}
791
792static int __maybe_unused ov2740_resume(struct device *dev)
793{
794 struct v4l2_subdev *sd = dev_get_drvdata(dev);
795 struct ov2740 *ov2740 = to_ov2740(sd);
796 int ret = 0;
797
798 mutex_lock(&ov2740->mutex);
799 if (!ov2740->streaming)
800 goto exit;
801
802 ret = ov2740_start_streaming(ov2740);
803 if (ret) {
804 ov2740->streaming = false;
805 ov2740_stop_streaming(ov2740);
806 }
807
808exit:
809 mutex_unlock(&ov2740->mutex);
810 return ret;
811}
812
813static int ov2740_set_format(struct v4l2_subdev *sd,
814 struct v4l2_subdev_pad_config *cfg,
815 struct v4l2_subdev_format *fmt)
816{
817 struct ov2740 *ov2740 = to_ov2740(sd);
818 const struct ov2740_mode *mode;
819 s32 vblank_def, h_blank;
820
821 mode = v4l2_find_nearest_size(supported_modes,
822 ARRAY_SIZE(supported_modes), width,
823 height, fmt->format.width,
824 fmt->format.height);
825
826 mutex_lock(&ov2740->mutex);
827 ov2740_update_pad_format(mode, &fmt->format);
828 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
829 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
830 } else {
831 ov2740->cur_mode = mode;
832 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index);
833 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate,
834 to_pixel_rate(mode->link_freq_index));
835
836
837 vblank_def = mode->vts_def - mode->height;
838 __v4l2_ctrl_modify_range(ov2740->vblank,
839 mode->vts_min - mode->height,
840 OV2740_VTS_MAX - mode->height, 1,
841 vblank_def);
842 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def);
843 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
844 mode->width;
845 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1,
846 h_blank);
847 }
848 mutex_unlock(&ov2740->mutex);
849
850 return 0;
851}
852
853static int ov2740_get_format(struct v4l2_subdev *sd,
854 struct v4l2_subdev_pad_config *cfg,
855 struct v4l2_subdev_format *fmt)
856{
857 struct ov2740 *ov2740 = to_ov2740(sd);
858
859 mutex_lock(&ov2740->mutex);
860 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
861 fmt->format = *v4l2_subdev_get_try_format(&ov2740->sd, cfg,
862 fmt->pad);
863 else
864 ov2740_update_pad_format(ov2740->cur_mode, &fmt->format);
865
866 mutex_unlock(&ov2740->mutex);
867
868 return 0;
869}
870
871static int ov2740_enum_mbus_code(struct v4l2_subdev *sd,
872 struct v4l2_subdev_pad_config *cfg,
873 struct v4l2_subdev_mbus_code_enum *code)
874{
875 if (code->index > 0)
876 return -EINVAL;
877
878 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
879
880 return 0;
881}
882
883static int ov2740_enum_frame_size(struct v4l2_subdev *sd,
884 struct v4l2_subdev_pad_config *cfg,
885 struct v4l2_subdev_frame_size_enum *fse)
886{
887 if (fse->index >= ARRAY_SIZE(supported_modes))
888 return -EINVAL;
889
890 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
891 return -EINVAL;
892
893 fse->min_width = supported_modes[fse->index].width;
894 fse->max_width = fse->min_width;
895 fse->min_height = supported_modes[fse->index].height;
896 fse->max_height = fse->min_height;
897
898 return 0;
899}
900
901static int ov2740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
902{
903 struct ov2740 *ov2740 = to_ov2740(sd);
904
905 mutex_lock(&ov2740->mutex);
906 ov2740_update_pad_format(&supported_modes[0],
907 v4l2_subdev_get_try_format(sd, fh->pad, 0));
908 mutex_unlock(&ov2740->mutex);
909
910 return 0;
911}
912
913static const struct v4l2_subdev_video_ops ov2740_video_ops = {
914 .s_stream = ov2740_set_stream,
915};
916
917static const struct v4l2_subdev_pad_ops ov2740_pad_ops = {
918 .set_fmt = ov2740_set_format,
919 .get_fmt = ov2740_get_format,
920 .enum_mbus_code = ov2740_enum_mbus_code,
921 .enum_frame_size = ov2740_enum_frame_size,
922};
923
924static const struct v4l2_subdev_ops ov2740_subdev_ops = {
925 .video = &ov2740_video_ops,
926 .pad = &ov2740_pad_ops,
927};
928
929static const struct media_entity_operations ov2740_subdev_entity_ops = {
930 .link_validate = v4l2_subdev_link_validate,
931};
932
933static const struct v4l2_subdev_internal_ops ov2740_internal_ops = {
934 .open = ov2740_open,
935};
936
937static int ov2740_identify_module(struct ov2740 *ov2740)
938{
939 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
940 int ret;
941 u32 val;
942
943 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val);
944 if (ret)
945 return ret;
946
947 if (val != OV2740_CHIP_ID) {
948 dev_err(&client->dev, "chip id mismatch: %x!=%x",
949 OV2740_CHIP_ID, val);
950 return -ENXIO;
951 }
952
953 return 0;
954}
955
956static int ov2740_check_hwcfg(struct device *dev)
957{
958 struct fwnode_handle *ep;
959 struct fwnode_handle *fwnode = dev_fwnode(dev);
960 struct v4l2_fwnode_endpoint bus_cfg = {
961 .bus_type = V4L2_MBUS_CSI2_DPHY
962 };
963 u32 mclk;
964 int ret;
965 unsigned int i, j;
966
967 if (!fwnode)
968 return -ENXIO;
969
970 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
971 if (ret)
972 return ret;
973
974 if (mclk != OV2740_MCLK) {
975 dev_err(dev, "external clock %d is not supported", mclk);
976 return -EINVAL;
977 }
978
979 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
980 if (!ep)
981 return -ENXIO;
982
983 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
984 fwnode_handle_put(ep);
985 if (ret)
986 return ret;
987
988 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) {
989 dev_err(dev, "number of CSI2 data lanes %d is not supported",
990 bus_cfg.bus.mipi_csi2.num_data_lanes);
991 ret = -EINVAL;
992 goto check_hwcfg_error;
993 }
994
995 if (!bus_cfg.nr_of_link_frequencies) {
996 dev_err(dev, "no link frequencies defined");
997 ret = -EINVAL;
998 goto check_hwcfg_error;
999 }
1000
1001 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1002 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1003 if (link_freq_menu_items[i] ==
1004 bus_cfg.link_frequencies[j])
1005 break;
1006 }
1007
1008 if (j == bus_cfg.nr_of_link_frequencies) {
1009 dev_err(dev, "no link frequency %lld supported",
1010 link_freq_menu_items[i]);
1011 ret = -EINVAL;
1012 goto check_hwcfg_error;
1013 }
1014 }
1015
1016check_hwcfg_error:
1017 v4l2_fwnode_endpoint_free(&bus_cfg);
1018
1019 return ret;
1020}
1021
1022static int ov2740_remove(struct i2c_client *client)
1023{
1024 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1025 struct ov2740 *ov2740 = to_ov2740(sd);
1026
1027 v4l2_async_unregister_subdev(sd);
1028 media_entity_cleanup(&sd->entity);
1029 v4l2_ctrl_handler_free(sd->ctrl_handler);
1030 pm_runtime_disable(&client->dev);
1031 mutex_destroy(&ov2740->mutex);
1032
1033 return 0;
1034}
1035
1036static int ov2740_nvmem_read(void *priv, unsigned int off, void *val,
1037 size_t count)
1038{
1039 struct nvm_data *nvm = priv;
1040 struct v4l2_subdev *sd = i2c_get_clientdata(nvm->client);
1041 struct device *dev = &nvm->client->dev;
1042 struct ov2740 *ov2740 = to_ov2740(sd);
1043 int ret = 0;
1044
1045 mutex_lock(&ov2740->mutex);
1046
1047 if (nvm->nvm_buffer) {
1048 memcpy(val, nvm->nvm_buffer + off, count);
1049 goto exit;
1050 }
1051
1052 ret = pm_runtime_get_sync(dev);
1053 if (ret < 0) {
1054 pm_runtime_put_noidle(dev);
1055 goto exit;
1056 }
1057
1058 ret = ov2740_load_otp_data(nvm);
1059 if (!ret)
1060 memcpy(val, nvm->nvm_buffer + off, count);
1061
1062 pm_runtime_put(dev);
1063exit:
1064 mutex_unlock(&ov2740->mutex);
1065 return ret;
1066}
1067
1068static int ov2740_register_nvmem(struct i2c_client *client,
1069 struct ov2740 *ov2740)
1070{
1071 struct nvm_data *nvm;
1072 struct regmap_config regmap_config = { };
1073 struct nvmem_config nvmem_config = { };
1074 struct regmap *regmap;
1075 struct device *dev = &client->dev;
1076 int ret;
1077
1078 nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL);
1079 if (!nvm)
1080 return -ENOMEM;
1081
1082 regmap_config.val_bits = 8;
1083 regmap_config.reg_bits = 16;
1084 regmap_config.disable_locking = true;
1085 regmap = devm_regmap_init_i2c(client, ®map_config);
1086 if (IS_ERR(regmap))
1087 return PTR_ERR(regmap);
1088
1089 nvm->regmap = regmap;
1090 nvm->client = client;
1091
1092 nvmem_config.name = dev_name(dev);
1093 nvmem_config.dev = dev;
1094 nvmem_config.read_only = true;
1095 nvmem_config.root_only = true;
1096 nvmem_config.owner = THIS_MODULE;
1097 nvmem_config.compat = true;
1098 nvmem_config.base_dev = dev;
1099 nvmem_config.reg_read = ov2740_nvmem_read;
1100 nvmem_config.reg_write = NULL;
1101 nvmem_config.priv = nvm;
1102 nvmem_config.stride = 1;
1103 nvmem_config.word_size = 1;
1104 nvmem_config.size = CUSTOMER_USE_OTP_SIZE;
1105
1106 nvm->nvmem = devm_nvmem_register(dev, &nvmem_config);
1107
1108 ret = PTR_ERR_OR_ZERO(nvm->nvmem);
1109 if (!ret)
1110 ov2740->nvm = nvm;
1111
1112 return ret;
1113}
1114
1115static int ov2740_probe(struct i2c_client *client)
1116{
1117 struct ov2740 *ov2740;
1118 int ret = 0;
1119
1120 ret = ov2740_check_hwcfg(&client->dev);
1121 if (ret) {
1122 dev_err(&client->dev, "failed to check HW configuration: %d",
1123 ret);
1124 return ret;
1125 }
1126
1127 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL);
1128 if (!ov2740)
1129 return -ENOMEM;
1130
1131 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops);
1132 ret = ov2740_identify_module(ov2740);
1133 if (ret) {
1134 dev_err(&client->dev, "failed to find sensor: %d", ret);
1135 return ret;
1136 }
1137
1138 mutex_init(&ov2740->mutex);
1139 ov2740->cur_mode = &supported_modes[0];
1140 ret = ov2740_init_controls(ov2740);
1141 if (ret) {
1142 dev_err(&client->dev, "failed to init controls: %d", ret);
1143 goto probe_error_v4l2_ctrl_handler_free;
1144 }
1145
1146 ov2740->sd.internal_ops = &ov2740_internal_ops;
1147 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1148 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops;
1149 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1150 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE;
1151 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad);
1152 if (ret) {
1153 dev_err(&client->dev, "failed to init entity pads: %d", ret);
1154 goto probe_error_v4l2_ctrl_handler_free;
1155 }
1156
1157 ret = v4l2_async_register_subdev_sensor_common(&ov2740->sd);
1158 if (ret < 0) {
1159 dev_err(&client->dev, "failed to register V4L2 subdev: %d",
1160 ret);
1161 goto probe_error_media_entity_cleanup;
1162 }
1163
1164 ret = ov2740_register_nvmem(client, ov2740);
1165 if (ret)
1166 dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret);
1167
1168
1169
1170
1171
1172 pm_runtime_set_active(&client->dev);
1173 pm_runtime_enable(&client->dev);
1174 pm_runtime_idle(&client->dev);
1175
1176 return 0;
1177
1178probe_error_media_entity_cleanup:
1179 media_entity_cleanup(&ov2740->sd.entity);
1180
1181probe_error_v4l2_ctrl_handler_free:
1182 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler);
1183 mutex_destroy(&ov2740->mutex);
1184
1185 return ret;
1186}
1187
1188static const struct dev_pm_ops ov2740_pm_ops = {
1189 SET_SYSTEM_SLEEP_PM_OPS(ov2740_suspend, ov2740_resume)
1190};
1191
1192static const struct acpi_device_id ov2740_acpi_ids[] = {
1193 {"INT3474"},
1194 {}
1195};
1196
1197MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids);
1198
1199static struct i2c_driver ov2740_i2c_driver = {
1200 .driver = {
1201 .name = "ov2740",
1202 .pm = &ov2740_pm_ops,
1203 .acpi_match_table = ov2740_acpi_ids,
1204 },
1205 .probe_new = ov2740_probe,
1206 .remove = ov2740_remove,
1207};
1208
1209module_i2c_driver(ov2740_i2c_driver);
1210
1211MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
1212MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>");
1213MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
1214MODULE_DESCRIPTION("OmniVision OV2740 sensor driver");
1215MODULE_LICENSE("GPL v2");
1216
