1
2
3
4#include <asm/unaligned.h>
5#include <linux/acpi.h>
6#include <linux/delay.h>
7#include <linux/i2c.h>
8#include <linux/module.h>
9#include <linux/pm_runtime.h>
10#include <media/v4l2-ctrls.h>
11#include <media/v4l2-device.h>
12#include <media/v4l2-fwnode.h>
13
14#define OV5675_REG_VALUE_08BIT 1
15#define OV5675_REG_VALUE_16BIT 2
16#define OV5675_REG_VALUE_24BIT 3
17
18#define OV5675_LINK_FREQ_450MHZ 450000000ULL
19#define OV5675_SCLK 90000000LL
20#define OV5675_MCLK 19200000
21#define OV5675_DATA_LANES 2
22#define OV5675_RGB_DEPTH 10
23
24#define OV5675_REG_CHIP_ID 0x300a
25#define OV5675_CHIP_ID 0x5675
26
27#define OV5675_REG_MODE_SELECT 0x0100
28#define OV5675_MODE_STANDBY 0x00
29#define OV5675_MODE_STREAMING 0x01
30
31
32#define OV5675_REG_VTS 0x380e
33#define OV5675_VTS_30FPS 0x07e4
34#define OV5675_VTS_30FPS_MIN 0x07e4
35#define OV5675_VTS_MAX 0x7fff
36
37
38#define OV5675_REG_HTS 0x380c
39
40
41#define OV5675_REG_EXPOSURE 0x3500
42#define OV5675_EXPOSURE_MIN 4
43#define OV5675_EXPOSURE_MAX_MARGIN 4
44#define OV5675_EXPOSURE_STEP 1
45
46
47#define OV5675_REG_ANALOG_GAIN 0x3508
48#define OV5675_ANAL_GAIN_MIN 128
49#define OV5675_ANAL_GAIN_MAX 2047
50#define OV5675_ANAL_GAIN_STEP 1
51
52
53#define OV5675_REG_MWB_R_GAIN 0x5019
54#define OV5675_REG_MWB_G_GAIN 0x501b
55#define OV5675_REG_MWB_B_GAIN 0x501d
56#define OV5675_DGTL_GAIN_MIN 0
57#define OV5675_DGTL_GAIN_MAX 4095
58#define OV5675_DGTL_GAIN_STEP 1
59#define OV5675_DGTL_GAIN_DEFAULT 1024
60
61
62#define OV5675_REG_TEST_PATTERN 0x4503
63#define OV5675_TEST_PATTERN_ENABLE BIT(7)
64#define OV5675_TEST_PATTERN_BAR_SHIFT 2
65
66
67#define OV5675_REG_FORMAT1 0x3820
68#define OV5675_REG_FORMAT2 0x373d
69
70#define to_ov5675(_sd) container_of(_sd, struct ov5675, sd)
71
72enum {
73 OV5675_LINK_FREQ_900MBPS,
74};
75
76struct ov5675_reg {
77 u16 address;
78 u8 val;
79};
80
81struct ov5675_reg_list {
82 u32 num_of_regs;
83 const struct ov5675_reg *regs;
84};
85
86struct ov5675_link_freq_config {
87 const struct ov5675_reg_list reg_list;
88};
89
90struct ov5675_mode {
91
92 u32 width;
93
94
95 u32 height;
96
97
98 u32 hts;
99
100
101 u32 vts_def;
102
103
104 u32 vts_min;
105
106
107 u32 link_freq_index;
108
109
110 const struct ov5675_reg_list reg_list;
111};
112
113static const struct ov5675_reg mipi_data_rate_900mbps[] = {
114 {0x0103, 0x01},
115 {0x0100, 0x00},
116 {0x0300, 0x04},
117 {0x0302, 0x8d},
118 {0x0303, 0x00},
119 {0x030d, 0x26},
120};
121
122static const struct ov5675_reg mode_2592x1944_regs[] = {
123 {0x3002, 0x21},
124 {0x3107, 0x23},
125 {0x3501, 0x20},
126 {0x3503, 0x0c},
127 {0x3508, 0x03},
128 {0x3509, 0x00},
129 {0x3600, 0x66},
130 {0x3602, 0x30},
131 {0x3610, 0xa5},
132 {0x3612, 0x93},
133 {0x3620, 0x80},
134 {0x3642, 0x0e},
135 {0x3661, 0x00},
136 {0x3662, 0x10},
137 {0x3664, 0xf3},
138 {0x3665, 0x9e},
139 {0x3667, 0xa5},
140 {0x366e, 0x55},
141 {0x366f, 0x55},
142 {0x3670, 0x11},
143 {0x3671, 0x11},
144 {0x3672, 0x11},
145 {0x3673, 0x11},
146 {0x3714, 0x24},
147 {0x371a, 0x3e},
148 {0x3733, 0x10},
149 {0x3734, 0x00},
150 {0x373d, 0x24},
151 {0x3764, 0x20},
152 {0x3765, 0x20},
153 {0x3766, 0x12},
154 {0x37a1, 0x14},
155 {0x37a8, 0x1c},
156 {0x37ab, 0x0f},
157 {0x37c2, 0x04},
158 {0x37cb, 0x00},
159 {0x37cc, 0x00},
160 {0x37cd, 0x00},
161 {0x37ce, 0x00},
162 {0x37d8, 0x02},
163 {0x37d9, 0x08},
164 {0x37dc, 0x04},
165 {0x3800, 0x00},
166 {0x3801, 0x00},
167 {0x3802, 0x00},
168 {0x3803, 0x04},
169 {0x3804, 0x0a},
170 {0x3805, 0x3f},
171 {0x3806, 0x07},
172 {0x3807, 0xb3},
173 {0x3808, 0x0a},
174 {0x3809, 0x20},
175 {0x380a, 0x07},
176 {0x380b, 0x98},
177 {0x380c, 0x02},
178 {0x380d, 0xee},
179 {0x380e, 0x07},
180 {0x380f, 0xe4},
181 {0x3811, 0x10},
182 {0x3813, 0x0d},
183 {0x3814, 0x01},
184 {0x3815, 0x01},
185 {0x3816, 0x01},
186 {0x3817, 0x01},
187 {0x381e, 0x02},
188 {0x3820, 0x88},
189 {0x3821, 0x01},
190 {0x3832, 0x04},
191 {0x3c80, 0x01},
192 {0x3c82, 0x00},
193 {0x3c83, 0xc8},
194 {0x3c8c, 0x0f},
195 {0x3c8d, 0xa0},
196 {0x3c90, 0x07},
197 {0x3c91, 0x00},
198 {0x3c92, 0x00},
199 {0x3c93, 0x00},
200 {0x3c94, 0xd0},
201 {0x3c95, 0x50},
202 {0x3c96, 0x35},
203 {0x3c97, 0x00},
204 {0x4001, 0xe0},
205 {0x4008, 0x02},
206 {0x4009, 0x0d},
207 {0x400f, 0x80},
208 {0x4013, 0x02},
209 {0x4040, 0x00},
210 {0x4041, 0x07},
211 {0x404c, 0x50},
212 {0x404e, 0x20},
213 {0x4500, 0x06},
214 {0x4503, 0x00},
215 {0x450a, 0x04},
216 {0x4809, 0x04},
217 {0x480c, 0x12},
218 {0x4819, 0x70},
219 {0x4825, 0x32},
220 {0x4826, 0x32},
221 {0x482a, 0x06},
222 {0x4833, 0x08},
223 {0x4837, 0x0d},
224 {0x5000, 0x77},
225 {0x5b00, 0x01},
226 {0x5b01, 0x10},
227 {0x5b02, 0x01},
228 {0x5b03, 0xdb},
229 {0x5b05, 0x6c},
230 {0x5e10, 0xfc},
231 {0x3500, 0x00},
232 {0x3501, 0x3E},
233 {0x3502, 0x60},
234 {0x3503, 0x08},
235 {0x3508, 0x04},
236 {0x3509, 0x00},
237 {0x3832, 0x48},
238 {0x5780, 0x3e},
239 {0x5781, 0x0f},
240 {0x5782, 0x44},
241 {0x5783, 0x02},
242 {0x5784, 0x01},
243 {0x5785, 0x01},
244 {0x5786, 0x00},
245 {0x5787, 0x04},
246 {0x5788, 0x02},
247 {0x5789, 0x0f},
248 {0x578a, 0xfd},
249 {0x578b, 0xf5},
250 {0x578c, 0xf5},
251 {0x578d, 0x03},
252 {0x578e, 0x08},
253 {0x578f, 0x0c},
254 {0x5790, 0x08},
255 {0x5791, 0x06},
256 {0x5792, 0x00},
257 {0x5793, 0x52},
258 {0x5794, 0xa3},
259 {0x4003, 0x40},
260 {0x3107, 0x01},
261 {0x3c80, 0x08},
262 {0x3c83, 0xb1},
263 {0x3c8c, 0x10},
264 {0x3c8d, 0x00},
265 {0x3c90, 0x00},
266 {0x3c94, 0x00},
267 {0x3c95, 0x00},
268 {0x3c96, 0x00},
269 {0x37cb, 0x09},
270 {0x37cc, 0x15},
271 {0x37cd, 0x1f},
272 {0x37ce, 0x1f},
273};
274
275static const struct ov5675_reg mode_1296x972_regs[] = {
276 {0x3002, 0x21},
277 {0x3107, 0x23},
278 {0x3501, 0x20},
279 {0x3503, 0x0c},
280 {0x3508, 0x03},
281 {0x3509, 0x00},
282 {0x3600, 0x66},
283 {0x3602, 0x30},
284 {0x3610, 0xa5},
285 {0x3612, 0x93},
286 {0x3620, 0x80},
287 {0x3642, 0x0e},
288 {0x3661, 0x00},
289 {0x3662, 0x08},
290 {0x3664, 0xf3},
291 {0x3665, 0x9e},
292 {0x3667, 0xa5},
293 {0x366e, 0x55},
294 {0x366f, 0x55},
295 {0x3670, 0x11},
296 {0x3671, 0x11},
297 {0x3672, 0x11},
298 {0x3673, 0x11},
299 {0x3714, 0x28},
300 {0x371a, 0x3e},
301 {0x3733, 0x10},
302 {0x3734, 0x00},
303 {0x373d, 0x24},
304 {0x3764, 0x20},
305 {0x3765, 0x20},
306 {0x3766, 0x12},
307 {0x37a1, 0x14},
308 {0x37a8, 0x1c},
309 {0x37ab, 0x0f},
310 {0x37c2, 0x14},
311 {0x37cb, 0x00},
312 {0x37cc, 0x00},
313 {0x37cd, 0x00},
314 {0x37ce, 0x00},
315 {0x37d8, 0x02},
316 {0x37d9, 0x04},
317 {0x37dc, 0x04},
318 {0x3800, 0x00},
319 {0x3801, 0x00},
320 {0x3802, 0x00},
321 {0x3803, 0x00},
322 {0x3804, 0x0a},
323 {0x3805, 0x3f},
324 {0x3806, 0x07},
325 {0x3807, 0xb7},
326 {0x3808, 0x05},
327 {0x3809, 0x10},
328 {0x380a, 0x03},
329 {0x380b, 0xcc},
330 {0x380c, 0x02},
331 {0x380d, 0xee},
332 {0x380e, 0x07},
333 {0x380f, 0xd0},
334 {0x3811, 0x08},
335 {0x3813, 0x0d},
336 {0x3814, 0x03},
337 {0x3815, 0x01},
338 {0x3816, 0x03},
339 {0x3817, 0x01},
340 {0x381e, 0x02},
341 {0x3820, 0x8b},
342 {0x3821, 0x01},
343 {0x3832, 0x04},
344 {0x3c80, 0x01},
345 {0x3c82, 0x00},
346 {0x3c83, 0xc8},
347 {0x3c8c, 0x0f},
348 {0x3c8d, 0xa0},
349 {0x3c90, 0x07},
350 {0x3c91, 0x00},
351 {0x3c92, 0x00},
352 {0x3c93, 0x00},
353 {0x3c94, 0xd0},
354 {0x3c95, 0x50},
355 {0x3c96, 0x35},
356 {0x3c97, 0x00},
357 {0x4001, 0xe0},
358 {0x4008, 0x00},
359 {0x4009, 0x07},
360 {0x400f, 0x80},
361 {0x4013, 0x02},
362 {0x4040, 0x00},
363 {0x4041, 0x03},
364 {0x404c, 0x50},
365 {0x404e, 0x20},
366 {0x4500, 0x06},
367 {0x4503, 0x00},
368 {0x450a, 0x04},
369 {0x4809, 0x04},
370 {0x480c, 0x12},
371 {0x4819, 0x70},
372 {0x4825, 0x32},
373 {0x4826, 0x32},
374 {0x482a, 0x06},
375 {0x4833, 0x08},
376 {0x4837, 0x0d},
377 {0x5000, 0x77},
378 {0x5b00, 0x01},
379 {0x5b01, 0x10},
380 {0x5b02, 0x01},
381 {0x5b03, 0xdb},
382 {0x5b05, 0x6c},
383 {0x5e10, 0xfc},
384 {0x3500, 0x00},
385 {0x3501, 0x1F},
386 {0x3502, 0x20},
387 {0x3503, 0x08},
388 {0x3508, 0x04},
389 {0x3509, 0x00},
390 {0x3832, 0x48},
391 {0x5780, 0x3e},
392 {0x5781, 0x0f},
393 {0x5782, 0x44},
394 {0x5783, 0x02},
395 {0x5784, 0x01},
396 {0x5785, 0x01},
397 {0x5786, 0x00},
398 {0x5787, 0x04},
399 {0x5788, 0x02},
400 {0x5789, 0x0f},
401 {0x578a, 0xfd},
402 {0x578b, 0xf5},
403 {0x578c, 0xf5},
404 {0x578d, 0x03},
405 {0x578e, 0x08},
406 {0x578f, 0x0c},
407 {0x5790, 0x08},
408 {0x5791, 0x06},
409 {0x5792, 0x00},
410 {0x5793, 0x52},
411 {0x5794, 0xa3},
412 {0x4003, 0x40},
413 {0x3107, 0x01},
414 {0x3c80, 0x08},
415 {0x3c83, 0xb1},
416 {0x3c8c, 0x10},
417 {0x3c8d, 0x00},
418 {0x3c90, 0x00},
419 {0x3c94, 0x00},
420 {0x3c95, 0x00},
421 {0x3c96, 0x00},
422 {0x37cb, 0x09},
423 {0x37cc, 0x15},
424 {0x37cd, 0x1f},
425 {0x37ce, 0x1f},
426};
427
428static const char * const ov5675_test_pattern_menu[] = {
429 "Disabled",
430 "Standard Color Bar",
431 "Top-Bottom Darker Color Bar",
432 "Right-Left Darker Color Bar",
433 "Bottom-Top Darker Color Bar"
434};
435
436static const s64 link_freq_menu_items[] = {
437 OV5675_LINK_FREQ_450MHZ,
438};
439
440static const struct ov5675_link_freq_config link_freq_configs[] = {
441 [OV5675_LINK_FREQ_900MBPS] = {
442 .reg_list = {
443 .num_of_regs = ARRAY_SIZE(mipi_data_rate_900mbps),
444 .regs = mipi_data_rate_900mbps,
445 }
446 }
447};
448
449static const struct ov5675_mode supported_modes[] = {
450 {
451 .width = 2592,
452 .height = 1944,
453 .hts = 1500,
454 .vts_def = OV5675_VTS_30FPS,
455 .vts_min = OV5675_VTS_30FPS_MIN,
456 .reg_list = {
457 .num_of_regs = ARRAY_SIZE(mode_2592x1944_regs),
458 .regs = mode_2592x1944_regs,
459 },
460 .link_freq_index = OV5675_LINK_FREQ_900MBPS,
461 },
462 {
463 .width = 1296,
464 .height = 972,
465 .hts = 1500,
466 .vts_def = OV5675_VTS_30FPS,
467 .vts_min = OV5675_VTS_30FPS_MIN,
468 .reg_list = {
469 .num_of_regs = ARRAY_SIZE(mode_1296x972_regs),
470 .regs = mode_1296x972_regs,
471 },
472 .link_freq_index = OV5675_LINK_FREQ_900MBPS,
473 }
474};
475
476struct ov5675 {
477 struct v4l2_subdev sd;
478 struct media_pad pad;
479 struct v4l2_ctrl_handler ctrl_handler;
480
481
482 struct v4l2_ctrl *link_freq;
483 struct v4l2_ctrl *pixel_rate;
484 struct v4l2_ctrl *vblank;
485 struct v4l2_ctrl *hblank;
486 struct v4l2_ctrl *exposure;
487
488
489 const struct ov5675_mode *cur_mode;
490
491
492 struct mutex mutex;
493
494
495 bool streaming;
496};
497
498static u64 to_pixel_rate(u32 f_index)
499{
500 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV5675_DATA_LANES;
501
502 do_div(pixel_rate, OV5675_RGB_DEPTH);
503
504 return pixel_rate;
505}
506
507static u64 to_pixels_per_line(u32 hts, u32 f_index)
508{
509 u64 ppl = hts * to_pixel_rate(f_index);
510
511 do_div(ppl, OV5675_SCLK);
512
513 return ppl;
514}
515
516static int ov5675_read_reg(struct ov5675 *ov5675, u16 reg, u16 len, u32 *val)
517{
518 struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd);
519 struct i2c_msg msgs[2];
520 u8 addr_buf[2];
521 u8 data_buf[4] = {0};
522 int ret;
523
524 if (len > 4)
525 return -EINVAL;
526
527 put_unaligned_be16(reg, addr_buf);
528 msgs[0].addr = client->addr;
529 msgs[0].flags = 0;
530 msgs[0].len = sizeof(addr_buf);
531 msgs[0].buf = addr_buf;
532 msgs[1].addr = client->addr;
533 msgs[1].flags = I2C_M_RD;
534 msgs[1].len = len;
535 msgs[1].buf = &data_buf[4 - len];
536
537 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
538 if (ret != ARRAY_SIZE(msgs))
539 return -EIO;
540
541 *val = get_unaligned_be32(data_buf);
542
543 return 0;
544}
545
546static int ov5675_write_reg(struct ov5675 *ov5675, u16 reg, u16 len, u32 val)
547{
548 struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd);
549 u8 buf[6];
550
551 if (len > 4)
552 return -EINVAL;
553
554 put_unaligned_be16(reg, buf);
555 put_unaligned_be32(val << 8 * (4 - len), buf + 2);
556 if (i2c_master_send(client, buf, len + 2) != len + 2)
557 return -EIO;
558
559 return 0;
560}
561
562static int ov5675_write_reg_list(struct ov5675 *ov5675,
563 const struct ov5675_reg_list *r_list)
564{
565 struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd);
566 unsigned int i;
567 int ret;
568
569 for (i = 0; i < r_list->num_of_regs; i++) {
570 ret = ov5675_write_reg(ov5675, r_list->regs[i].address, 1,
571 r_list->regs[i].val);
572 if (ret) {
573 dev_err_ratelimited(&client->dev,
574 "failed to write reg 0x%4.4x. error = %d",
575 r_list->regs[i].address, ret);
576 return ret;
577 }
578 }
579
580 return 0;
581}
582
583static int ov5675_update_digital_gain(struct ov5675 *ov5675, u32 d_gain)
584{
585 int ret;
586
587 ret = ov5675_write_reg(ov5675, OV5675_REG_MWB_R_GAIN,
588 OV5675_REG_VALUE_16BIT, d_gain);
589 if (ret)
590 return ret;
591
592 ret = ov5675_write_reg(ov5675, OV5675_REG_MWB_G_GAIN,
593 OV5675_REG_VALUE_16BIT, d_gain);
594 if (ret)
595 return ret;
596
597 return ov5675_write_reg(ov5675, OV5675_REG_MWB_B_GAIN,
598 OV5675_REG_VALUE_16BIT, d_gain);
599}
600
601static int ov5675_test_pattern(struct ov5675 *ov5675, u32 pattern)
602{
603 if (pattern)
604 pattern = (pattern - 1) << OV5675_TEST_PATTERN_BAR_SHIFT |
605 OV5675_TEST_PATTERN_ENABLE;
606
607 return ov5675_write_reg(ov5675, OV5675_REG_TEST_PATTERN,
608 OV5675_REG_VALUE_08BIT, pattern);
609}
610
611
612
613
614
615static int ov5675_set_ctrl_hflip(struct ov5675 *ov5675, u32 ctrl_val)
616{
617 int ret;
618 u32 val;
619
620 ret = ov5675_read_reg(ov5675, OV5675_REG_FORMAT1,
621 OV5675_REG_VALUE_08BIT, &val);
622 if (ret)
623 return ret;
624
625 return ov5675_write_reg(ov5675, OV5675_REG_FORMAT1,
626 OV5675_REG_VALUE_08BIT,
627 ctrl_val ? val & ~BIT(3) : val);
628}
629
630static int ov5675_set_ctrl_vflip(struct ov5675 *ov5675, u8 ctrl_val)
631{
632 int ret;
633 u32 val;
634
635 ret = ov5675_read_reg(ov5675, OV5675_REG_FORMAT1,
636 OV5675_REG_VALUE_08BIT, &val);
637 if (ret)
638 return ret;
639
640 ret = ov5675_write_reg(ov5675, OV5675_REG_FORMAT1,
641 OV5675_REG_VALUE_08BIT,
642 ctrl_val ? val | BIT(4) | BIT(5) : val);
643
644 if (ret)
645 return ret;
646
647 ret = ov5675_read_reg(ov5675, OV5675_REG_FORMAT2,
648 OV5675_REG_VALUE_08BIT, &val);
649
650 if (ret)
651 return ret;
652
653 return ov5675_write_reg(ov5675, OV5675_REG_FORMAT2,
654 OV5675_REG_VALUE_08BIT,
655 ctrl_val ? val | BIT(1) : val);
656}
657
658static int ov5675_set_ctrl(struct v4l2_ctrl *ctrl)
659{
660 struct ov5675 *ov5675 = container_of(ctrl->handler,
661 struct ov5675, ctrl_handler);
662 struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd);
663 s64 exposure_max;
664 int ret = 0;
665
666
667 if (ctrl->id == V4L2_CID_VBLANK) {
668
669 exposure_max = ov5675->cur_mode->height + ctrl->val -
670 OV5675_EXPOSURE_MAX_MARGIN;
671 __v4l2_ctrl_modify_range(ov5675->exposure,
672 ov5675->exposure->minimum,
673 exposure_max, ov5675->exposure->step,
674 exposure_max);
675 }
676
677
678 if (!pm_runtime_get_if_in_use(&client->dev))
679 return 0;
680
681 switch (ctrl->id) {
682 case V4L2_CID_ANALOGUE_GAIN:
683 ret = ov5675_write_reg(ov5675, OV5675_REG_ANALOG_GAIN,
684 OV5675_REG_VALUE_16BIT, ctrl->val);
685 break;
686
687 case V4L2_CID_DIGITAL_GAIN:
688 ret = ov5675_update_digital_gain(ov5675, ctrl->val);
689 break;
690
691 case V4L2_CID_EXPOSURE:
692
693
694
695
696
697
698
699 ret = ov5675_write_reg(ov5675, OV5675_REG_EXPOSURE,
700 OV5675_REG_VALUE_24BIT, ctrl->val << 3);
701 break;
702
703 case V4L2_CID_VBLANK:
704 ret = ov5675_write_reg(ov5675, OV5675_REG_VTS,
705 OV5675_REG_VALUE_16BIT,
706 ov5675->cur_mode->height + ctrl->val +
707 10);
708 break;
709
710 case V4L2_CID_TEST_PATTERN:
711 ret = ov5675_test_pattern(ov5675, ctrl->val);
712 break;
713
714 case V4L2_CID_HFLIP:
715 ov5675_set_ctrl_hflip(ov5675, ctrl->val);
716 break;
717
718 case V4L2_CID_VFLIP:
719 ov5675_set_ctrl_vflip(ov5675, ctrl->val);
720 break;
721
722 default:
723 ret = -EINVAL;
724 break;
725 }
726
727 pm_runtime_put(&client->dev);
728
729 return ret;
730}
731
732static const struct v4l2_ctrl_ops ov5675_ctrl_ops = {
733 .s_ctrl = ov5675_set_ctrl,
734};
735
736static int ov5675_init_controls(struct ov5675 *ov5675)
737{
738 struct v4l2_ctrl_handler *ctrl_hdlr;
739 s64 exposure_max, h_blank;
740 int ret;
741
742 ctrl_hdlr = &ov5675->ctrl_handler;
743 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
744 if (ret)
745 return ret;
746
747 ctrl_hdlr->lock = &ov5675->mutex;
748 ov5675->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov5675_ctrl_ops,
749 V4L2_CID_LINK_FREQ,
750 ARRAY_SIZE(link_freq_menu_items) - 1,
751 0, link_freq_menu_items);
752 if (ov5675->link_freq)
753 ov5675->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
754
755 ov5675->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
756 V4L2_CID_PIXEL_RATE, 0,
757 to_pixel_rate(OV5675_LINK_FREQ_900MBPS),
758 1,
759 to_pixel_rate(OV5675_LINK_FREQ_900MBPS));
760 ov5675->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
761 V4L2_CID_VBLANK,
762 ov5675->cur_mode->vts_min - ov5675->cur_mode->height,
763 OV5675_VTS_MAX - ov5675->cur_mode->height, 1,
764 ov5675->cur_mode->vts_def - ov5675->cur_mode->height);
765 h_blank = to_pixels_per_line(ov5675->cur_mode->hts,
766 ov5675->cur_mode->link_freq_index) - ov5675->cur_mode->width;
767 ov5675->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
768 V4L2_CID_HBLANK, h_blank, h_blank, 1,
769 h_blank);
770 if (ov5675->hblank)
771 ov5675->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
772
773 v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
774 OV5675_ANAL_GAIN_MIN, OV5675_ANAL_GAIN_MAX,
775 OV5675_ANAL_GAIN_STEP, OV5675_ANAL_GAIN_MIN);
776 v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
777 OV5675_DGTL_GAIN_MIN, OV5675_DGTL_GAIN_MAX,
778 OV5675_DGTL_GAIN_STEP, OV5675_DGTL_GAIN_DEFAULT);
779 exposure_max = (ov5675->cur_mode->vts_def - OV5675_EXPOSURE_MAX_MARGIN);
780 ov5675->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
781 V4L2_CID_EXPOSURE,
782 OV5675_EXPOSURE_MIN, exposure_max,
783 OV5675_EXPOSURE_STEP,
784 exposure_max);
785 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov5675_ctrl_ops,
786 V4L2_CID_TEST_PATTERN,
787 ARRAY_SIZE(ov5675_test_pattern_menu) - 1,
788 0, 0, ov5675_test_pattern_menu);
789 v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
790 V4L2_CID_HFLIP, 0, 1, 1, 0);
791 v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
792 V4L2_CID_VFLIP, 0, 1, 1, 0);
793
794 if (ctrl_hdlr->error)
795 return ctrl_hdlr->error;
796
797 ov5675->sd.ctrl_handler = ctrl_hdlr;
798
799 return 0;
800}
801
802static void ov5675_update_pad_format(const struct ov5675_mode *mode,
803 struct v4l2_mbus_framefmt *fmt)
804{
805 fmt->width = mode->width;
806 fmt->height = mode->height;
807 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
808 fmt->field = V4L2_FIELD_NONE;
809}
810
811static int ov5675_start_streaming(struct ov5675 *ov5675)
812{
813 struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd);
814 const struct ov5675_reg_list *reg_list;
815 int link_freq_index, ret;
816
817 link_freq_index = ov5675->cur_mode->link_freq_index;
818 reg_list = &link_freq_configs[link_freq_index].reg_list;
819 ret = ov5675_write_reg_list(ov5675, reg_list);
820 if (ret) {
821 dev_err(&client->dev, "failed to set plls");
822 return ret;
823 }
824
825 reg_list = &ov5675->cur_mode->reg_list;
826 ret = ov5675_write_reg_list(ov5675, reg_list);
827 if (ret) {
828 dev_err(&client->dev, "failed to set mode");
829 return ret;
830 }
831
832 ret = __v4l2_ctrl_handler_setup(ov5675->sd.ctrl_handler);
833 if (ret)
834 return ret;
835
836 ret = ov5675_write_reg(ov5675, OV5675_REG_MODE_SELECT,
837 OV5675_REG_VALUE_08BIT, OV5675_MODE_STREAMING);
838 if (ret) {
839 dev_err(&client->dev, "failed to set stream");
840 return ret;
841 }
842
843 return 0;
844}
845
846static void ov5675_stop_streaming(struct ov5675 *ov5675)
847{
848 struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd);
849
850 if (ov5675_write_reg(ov5675, OV5675_REG_MODE_SELECT,
851 OV5675_REG_VALUE_08BIT, OV5675_MODE_STANDBY))
852 dev_err(&client->dev, "failed to set stream");
853}
854
855static int ov5675_set_stream(struct v4l2_subdev *sd, int enable)
856{
857 struct ov5675 *ov5675 = to_ov5675(sd);
858 struct i2c_client *client = v4l2_get_subdevdata(sd);
859 int ret = 0;
860
861 if (ov5675->streaming == enable)
862 return 0;
863
864 mutex_lock(&ov5675->mutex);
865 if (enable) {
866 ret = pm_runtime_get_sync(&client->dev);
867 if (ret < 0) {
868 pm_runtime_put_noidle(&client->dev);
869 mutex_unlock(&ov5675->mutex);
870 return ret;
871 }
872
873 ret = ov5675_start_streaming(ov5675);
874 if (ret) {
875 enable = 0;
876 ov5675_stop_streaming(ov5675);
877 pm_runtime_put(&client->dev);
878 }
879 } else {
880 ov5675_stop_streaming(ov5675);
881 pm_runtime_put(&client->dev);
882 }
883
884 ov5675->streaming = enable;
885 mutex_unlock(&ov5675->mutex);
886
887 return ret;
888}
889
890static int __maybe_unused ov5675_suspend(struct device *dev)
891{
892 struct v4l2_subdev *sd = dev_get_drvdata(dev);
893 struct ov5675 *ov5675 = to_ov5675(sd);
894
895 mutex_lock(&ov5675->mutex);
896 if (ov5675->streaming)
897 ov5675_stop_streaming(ov5675);
898
899 mutex_unlock(&ov5675->mutex);
900
901 return 0;
902}
903
904static int __maybe_unused ov5675_resume(struct device *dev)
905{
906 struct v4l2_subdev *sd = dev_get_drvdata(dev);
907 struct ov5675 *ov5675 = to_ov5675(sd);
908 int ret;
909
910 mutex_lock(&ov5675->mutex);
911 if (ov5675->streaming) {
912 ret = ov5675_start_streaming(ov5675);
913 if (ret) {
914 ov5675->streaming = false;
915 ov5675_stop_streaming(ov5675);
916 mutex_unlock(&ov5675->mutex);
917 return ret;
918 }
919 }
920
921 mutex_unlock(&ov5675->mutex);
922
923 return 0;
924}
925
926static int ov5675_set_format(struct v4l2_subdev *sd,
927 struct v4l2_subdev_pad_config *cfg,
928 struct v4l2_subdev_format *fmt)
929{
930 struct ov5675 *ov5675 = to_ov5675(sd);
931 const struct ov5675_mode *mode;
932 s32 vblank_def, h_blank;
933
934 mode = v4l2_find_nearest_size(supported_modes,
935 ARRAY_SIZE(supported_modes), width,
936 height, fmt->format.width,
937 fmt->format.height);
938
939 mutex_lock(&ov5675->mutex);
940 ov5675_update_pad_format(mode, &fmt->format);
941 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
942 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
943 } else {
944 ov5675->cur_mode = mode;
945 __v4l2_ctrl_s_ctrl(ov5675->link_freq, mode->link_freq_index);
946 __v4l2_ctrl_s_ctrl_int64(ov5675->pixel_rate,
947 to_pixel_rate(mode->link_freq_index));
948
949
950 vblank_def = mode->vts_def - mode->height;
951 __v4l2_ctrl_modify_range(ov5675->vblank,
952 mode->vts_min - mode->height,
953 OV5675_VTS_MAX - mode->height, 1,
954 vblank_def);
955 __v4l2_ctrl_s_ctrl(ov5675->vblank, vblank_def);
956 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
957 mode->width;
958 __v4l2_ctrl_modify_range(ov5675->hblank, h_blank, h_blank, 1,
959 h_blank);
960 }
961
962 mutex_unlock(&ov5675->mutex);
963
964 return 0;
965}
966
967static int ov5675_get_format(struct v4l2_subdev *sd,
968 struct v4l2_subdev_pad_config *cfg,
969 struct v4l2_subdev_format *fmt)
970{
971 struct ov5675 *ov5675 = to_ov5675(sd);
972
973 mutex_lock(&ov5675->mutex);
974 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
975 fmt->format = *v4l2_subdev_get_try_format(&ov5675->sd, cfg,
976 fmt->pad);
977 else
978 ov5675_update_pad_format(ov5675->cur_mode, &fmt->format);
979
980 mutex_unlock(&ov5675->mutex);
981
982 return 0;
983}
984
985static int ov5675_enum_mbus_code(struct v4l2_subdev *sd,
986 struct v4l2_subdev_pad_config *cfg,
987 struct v4l2_subdev_mbus_code_enum *code)
988{
989 if (code->index > 0)
990 return -EINVAL;
991
992 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
993
994 return 0;
995}
996
997static int ov5675_enum_frame_size(struct v4l2_subdev *sd,
998 struct v4l2_subdev_pad_config *cfg,
999 struct v4l2_subdev_frame_size_enum *fse)
1000{
1001 if (fse->index >= ARRAY_SIZE(supported_modes))
1002 return -EINVAL;
1003
1004 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1005 return -EINVAL;
1006
1007 fse->min_width = supported_modes[fse->index].width;
1008 fse->max_width = fse->min_width;
1009 fse->min_height = supported_modes[fse->index].height;
1010 fse->max_height = fse->min_height;
1011
1012 return 0;
1013}
1014
1015static int ov5675_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1016{
1017 struct ov5675 *ov5675 = to_ov5675(sd);
1018
1019 mutex_lock(&ov5675->mutex);
1020 ov5675_update_pad_format(&supported_modes[0],
1021 v4l2_subdev_get_try_format(sd, fh->pad, 0));
1022 mutex_unlock(&ov5675->mutex);
1023
1024 return 0;
1025}
1026
1027static const struct v4l2_subdev_video_ops ov5675_video_ops = {
1028 .s_stream = ov5675_set_stream,
1029};
1030
1031static const struct v4l2_subdev_pad_ops ov5675_pad_ops = {
1032 .set_fmt = ov5675_set_format,
1033 .get_fmt = ov5675_get_format,
1034 .enum_mbus_code = ov5675_enum_mbus_code,
1035 .enum_frame_size = ov5675_enum_frame_size,
1036};
1037
1038static const struct v4l2_subdev_ops ov5675_subdev_ops = {
1039 .video = &ov5675_video_ops,
1040 .pad = &ov5675_pad_ops,
1041};
1042
1043static const struct media_entity_operations ov5675_subdev_entity_ops = {
1044 .link_validate = v4l2_subdev_link_validate,
1045};
1046
1047static const struct v4l2_subdev_internal_ops ov5675_internal_ops = {
1048 .open = ov5675_open,
1049};
1050
1051static int ov5675_identify_module(struct ov5675 *ov5675)
1052{
1053 struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd);
1054 int ret;
1055 u32 val;
1056
1057 ret = ov5675_read_reg(ov5675, OV5675_REG_CHIP_ID,
1058 OV5675_REG_VALUE_24BIT, &val);
1059 if (ret)
1060 return ret;
1061
1062 if (val != OV5675_CHIP_ID) {
1063 dev_err(&client->dev, "chip id mismatch: %x!=%x",
1064 OV5675_CHIP_ID, val);
1065 return -ENXIO;
1066 }
1067
1068 return 0;
1069}
1070
1071static int ov5675_check_hwcfg(struct device *dev)
1072{
1073 struct fwnode_handle *ep;
1074 struct fwnode_handle *fwnode = dev_fwnode(dev);
1075 struct v4l2_fwnode_endpoint bus_cfg = {
1076 .bus_type = V4L2_MBUS_CSI2_DPHY
1077 };
1078 u32 mclk;
1079 int ret;
1080 unsigned int i, j;
1081
1082 if (!fwnode)
1083 return -ENXIO;
1084
1085 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
1086
1087 if (ret) {
1088 dev_err(dev, "can't get clock frequency");
1089 return ret;
1090 }
1091
1092 if (mclk != OV5675_MCLK) {
1093 dev_err(dev, "external clock %d is not supported", mclk);
1094 return -EINVAL;
1095 }
1096
1097 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1098 if (!ep)
1099 return -ENXIO;
1100
1101 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1102 fwnode_handle_put(ep);
1103 if (ret)
1104 return ret;
1105
1106 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV5675_DATA_LANES) {
1107 dev_err(dev, "number of CSI2 data lanes %d is not supported",
1108 bus_cfg.bus.mipi_csi2.num_data_lanes);
1109 ret = -EINVAL;
1110 goto check_hwcfg_error;
1111 }
1112
1113 if (!bus_cfg.nr_of_link_frequencies) {
1114 dev_err(dev, "no link frequencies defined");
1115 ret = -EINVAL;
1116 goto check_hwcfg_error;
1117 }
1118
1119 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1120 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1121 if (link_freq_menu_items[i] ==
1122 bus_cfg.link_frequencies[j])
1123 break;
1124 }
1125
1126 if (j == bus_cfg.nr_of_link_frequencies) {
1127 dev_err(dev, "no link frequency %lld supported",
1128 link_freq_menu_items[i]);
1129 ret = -EINVAL;
1130 goto check_hwcfg_error;
1131 }
1132 }
1133
1134check_hwcfg_error:
1135 v4l2_fwnode_endpoint_free(&bus_cfg);
1136
1137 return ret;
1138}
1139
1140static int ov5675_remove(struct i2c_client *client)
1141{
1142 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1143 struct ov5675 *ov5675 = to_ov5675(sd);
1144
1145 v4l2_async_unregister_subdev(sd);
1146 media_entity_cleanup(&sd->entity);
1147 v4l2_ctrl_handler_free(sd->ctrl_handler);
1148 pm_runtime_disable(&client->dev);
1149 mutex_destroy(&ov5675->mutex);
1150
1151 return 0;
1152}
1153
1154static int ov5675_probe(struct i2c_client *client)
1155{
1156 struct ov5675 *ov5675;
1157 int ret;
1158
1159 ret = ov5675_check_hwcfg(&client->dev);
1160 if (ret) {
1161 dev_err(&client->dev, "failed to check HW configuration: %d",
1162 ret);
1163 return ret;
1164 }
1165
1166 ov5675 = devm_kzalloc(&client->dev, sizeof(*ov5675), GFP_KERNEL);
1167 if (!ov5675)
1168 return -ENOMEM;
1169
1170 v4l2_i2c_subdev_init(&ov5675->sd, client, &ov5675_subdev_ops);
1171 ret = ov5675_identify_module(ov5675);
1172 if (ret) {
1173 dev_err(&client->dev, "failed to find sensor: %d", ret);
1174 return ret;
1175 }
1176
1177 mutex_init(&ov5675->mutex);
1178 ov5675->cur_mode = &supported_modes[0];
1179 ret = ov5675_init_controls(ov5675);
1180 if (ret) {
1181 dev_err(&client->dev, "failed to init controls: %d", ret);
1182 goto probe_error_v4l2_ctrl_handler_free;
1183 }
1184
1185 ov5675->sd.internal_ops = &ov5675_internal_ops;
1186 ov5675->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1187 ov5675->sd.entity.ops = &ov5675_subdev_entity_ops;
1188 ov5675->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1189 ov5675->pad.flags = MEDIA_PAD_FL_SOURCE;
1190 ret = media_entity_pads_init(&ov5675->sd.entity, 1, &ov5675->pad);
1191 if (ret) {
1192 dev_err(&client->dev, "failed to init entity pads: %d", ret);
1193 goto probe_error_v4l2_ctrl_handler_free;
1194 }
1195
1196 ret = v4l2_async_register_subdev_sensor_common(&ov5675->sd);
1197 if (ret < 0) {
1198 dev_err(&client->dev, "failed to register V4L2 subdev: %d",
1199 ret);
1200 goto probe_error_media_entity_cleanup;
1201 }
1202
1203
1204
1205
1206
1207 pm_runtime_set_active(&client->dev);
1208 pm_runtime_enable(&client->dev);
1209 pm_runtime_idle(&client->dev);
1210
1211 return 0;
1212
1213probe_error_media_entity_cleanup:
1214 media_entity_cleanup(&ov5675->sd.entity);
1215
1216probe_error_v4l2_ctrl_handler_free:
1217 v4l2_ctrl_handler_free(ov5675->sd.ctrl_handler);
1218 mutex_destroy(&ov5675->mutex);
1219
1220 return ret;
1221}
1222
1223static const struct dev_pm_ops ov5675_pm_ops = {
1224 SET_SYSTEM_SLEEP_PM_OPS(ov5675_suspend, ov5675_resume)
1225};
1226
1227#ifdef CONFIG_ACPI
1228static const struct acpi_device_id ov5675_acpi_ids[] = {
1229 {"OVTI5675"},
1230 {}
1231};
1232
1233MODULE_DEVICE_TABLE(acpi, ov5675_acpi_ids);
1234#endif
1235
1236static struct i2c_driver ov5675_i2c_driver = {
1237 .driver = {
1238 .name = "ov5675",
1239 .pm = &ov5675_pm_ops,
1240 .acpi_match_table = ACPI_PTR(ov5675_acpi_ids),
1241 },
1242 .probe_new = ov5675_probe,
1243 .remove = ov5675_remove,
1244};
1245
1246module_i2c_driver(ov5675_i2c_driver);
1247
1248MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>");
1249MODULE_DESCRIPTION("OmniVision OV5675 sensor driver");
1250MODULE_LICENSE("GPL v2");
1251
