linux/drivers/memory/tegra/tegra20-emc.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Tegra20 External Memory Controller driver
   4 *
   5 * Author: Dmitry Osipenko <digetx@gmail.com>
   6 */
   7
   8#include <linux/clk.h>
   9#include <linux/clk/tegra.h>
  10#include <linux/debugfs.h>
  11#include <linux/devfreq.h>
  12#include <linux/err.h>
  13#include <linux/interconnect-provider.h>
  14#include <linux/interrupt.h>
  15#include <linux/io.h>
  16#include <linux/iopoll.h>
  17#include <linux/kernel.h>
  18#include <linux/module.h>
  19#include <linux/mutex.h>
  20#include <linux/of.h>
  21#include <linux/platform_device.h>
  22#include <linux/pm_opp.h>
  23#include <linux/slab.h>
  24#include <linux/sort.h>
  25#include <linux/types.h>
  26
  27#include <soc/tegra/common.h>
  28#include <soc/tegra/fuse.h>
  29
  30#include "mc.h"
  31
  32#define EMC_INTSTATUS                           0x000
  33#define EMC_INTMASK                             0x004
  34#define EMC_DBG                                 0x008
  35#define EMC_TIMING_CONTROL                      0x028
  36#define EMC_RC                                  0x02c
  37#define EMC_RFC                                 0x030
  38#define EMC_RAS                                 0x034
  39#define EMC_RP                                  0x038
  40#define EMC_R2W                                 0x03c
  41#define EMC_W2R                                 0x040
  42#define EMC_R2P                                 0x044
  43#define EMC_W2P                                 0x048
  44#define EMC_RD_RCD                              0x04c
  45#define EMC_WR_RCD                              0x050
  46#define EMC_RRD                                 0x054
  47#define EMC_REXT                                0x058
  48#define EMC_WDV                                 0x05c
  49#define EMC_QUSE                                0x060
  50#define EMC_QRST                                0x064
  51#define EMC_QSAFE                               0x068
  52#define EMC_RDV                                 0x06c
  53#define EMC_REFRESH                             0x070
  54#define EMC_BURST_REFRESH_NUM                   0x074
  55#define EMC_PDEX2WR                             0x078
  56#define EMC_PDEX2RD                             0x07c
  57#define EMC_PCHG2PDEN                           0x080
  58#define EMC_ACT2PDEN                            0x084
  59#define EMC_AR2PDEN                             0x088
  60#define EMC_RW2PDEN                             0x08c
  61#define EMC_TXSR                                0x090
  62#define EMC_TCKE                                0x094
  63#define EMC_TFAW                                0x098
  64#define EMC_TRPAB                               0x09c
  65#define EMC_TCLKSTABLE                          0x0a0
  66#define EMC_TCLKSTOP                            0x0a4
  67#define EMC_TREFBW                              0x0a8
  68#define EMC_QUSE_EXTRA                          0x0ac
  69#define EMC_ODT_WRITE                           0x0b0
  70#define EMC_ODT_READ                            0x0b4
  71#define EMC_FBIO_CFG5                           0x104
  72#define EMC_FBIO_CFG6                           0x114
  73#define EMC_STAT_CONTROL                        0x160
  74#define EMC_STAT_LLMC_CONTROL                   0x178
  75#define EMC_STAT_PWR_CLOCK_LIMIT                0x198
  76#define EMC_STAT_PWR_CLOCKS                     0x19c
  77#define EMC_STAT_PWR_COUNT                      0x1a0
  78#define EMC_AUTO_CAL_INTERVAL                   0x2a8
  79#define EMC_CFG_2                               0x2b8
  80#define EMC_CFG_DIG_DLL                         0x2bc
  81#define EMC_DLL_XFORM_DQS                       0x2c0
  82#define EMC_DLL_XFORM_QUSE                      0x2c4
  83#define EMC_ZCAL_REF_CNT                        0x2e0
  84#define EMC_ZCAL_WAIT_CNT                       0x2e4
  85#define EMC_CFG_CLKTRIM_0                       0x2d0
  86#define EMC_CFG_CLKTRIM_1                       0x2d4
  87#define EMC_CFG_CLKTRIM_2                       0x2d8
  88
  89#define EMC_CLKCHANGE_REQ_ENABLE                BIT(0)
  90#define EMC_CLKCHANGE_PD_ENABLE                 BIT(1)
  91#define EMC_CLKCHANGE_SR_ENABLE                 BIT(2)
  92
  93#define EMC_TIMING_UPDATE                       BIT(0)
  94
  95#define EMC_REFRESH_OVERFLOW_INT                BIT(3)
  96#define EMC_CLKCHANGE_COMPLETE_INT              BIT(4)
  97
  98#define EMC_DBG_READ_MUX_ASSEMBLY               BIT(0)
  99#define EMC_DBG_WRITE_MUX_ACTIVE                BIT(1)
 100#define EMC_DBG_FORCE_UPDATE                    BIT(2)
 101#define EMC_DBG_READ_DQM_CTRL                   BIT(9)
 102#define EMC_DBG_CFG_PRIORITY                    BIT(24)
 103
 104#define EMC_FBIO_CFG5_DRAM_WIDTH_X16            BIT(4)
 105
 106#define EMC_PWR_GATHER_CLEAR                    (1 << 8)
 107#define EMC_PWR_GATHER_DISABLE                  (2 << 8)
 108#define EMC_PWR_GATHER_ENABLE                   (3 << 8)
 109
 110static const u16 emc_timing_registers[] = {
 111        EMC_RC,
 112        EMC_RFC,
 113        EMC_RAS,
 114        EMC_RP,
 115        EMC_R2W,
 116        EMC_W2R,
 117        EMC_R2P,
 118        EMC_W2P,
 119        EMC_RD_RCD,
 120        EMC_WR_RCD,
 121        EMC_RRD,
 122        EMC_REXT,
 123        EMC_WDV,
 124        EMC_QUSE,
 125        EMC_QRST,
 126        EMC_QSAFE,
 127        EMC_RDV,
 128        EMC_REFRESH,
 129        EMC_BURST_REFRESH_NUM,
 130        EMC_PDEX2WR,
 131        EMC_PDEX2RD,
 132        EMC_PCHG2PDEN,
 133        EMC_ACT2PDEN,
 134        EMC_AR2PDEN,
 135        EMC_RW2PDEN,
 136        EMC_TXSR,
 137        EMC_TCKE,
 138        EMC_TFAW,
 139        EMC_TRPAB,
 140        EMC_TCLKSTABLE,
 141        EMC_TCLKSTOP,
 142        EMC_TREFBW,
 143        EMC_QUSE_EXTRA,
 144        EMC_FBIO_CFG6,
 145        EMC_ODT_WRITE,
 146        EMC_ODT_READ,
 147        EMC_FBIO_CFG5,
 148        EMC_CFG_DIG_DLL,
 149        EMC_DLL_XFORM_DQS,
 150        EMC_DLL_XFORM_QUSE,
 151        EMC_ZCAL_REF_CNT,
 152        EMC_ZCAL_WAIT_CNT,
 153        EMC_AUTO_CAL_INTERVAL,
 154        EMC_CFG_CLKTRIM_0,
 155        EMC_CFG_CLKTRIM_1,
 156        EMC_CFG_CLKTRIM_2,
 157};
 158
 159struct emc_timing {
 160        unsigned long rate;
 161        u32 data[ARRAY_SIZE(emc_timing_registers)];
 162};
 163
 164enum emc_rate_request_type {
 165        EMC_RATE_DEVFREQ,
 166        EMC_RATE_DEBUG,
 167        EMC_RATE_ICC,
 168        EMC_RATE_TYPE_MAX,
 169};
 170
 171struct emc_rate_request {
 172        unsigned long min_rate;
 173        unsigned long max_rate;
 174};
 175
 176struct tegra_emc {
 177        struct device *dev;
 178        struct tegra_mc *mc;
 179        struct icc_provider provider;
 180        struct notifier_block clk_nb;
 181        struct clk *clk;
 182        void __iomem *regs;
 183        unsigned int dram_bus_width;
 184
 185        struct emc_timing *timings;
 186        unsigned int num_timings;
 187
 188        struct {
 189                struct dentry *root;
 190                unsigned long min_rate;
 191                unsigned long max_rate;
 192        } debugfs;
 193
 194        /*
 195         * There are multiple sources in the EMC driver which could request
 196         * a min/max clock rate, these rates are contained in this array.
 197         */
 198        struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX];
 199
 200        /* protect shared rate-change code path */
 201        struct mutex rate_lock;
 202
 203        struct devfreq_simple_ondemand_data ondemand_data;
 204};
 205
 206static irqreturn_t tegra_emc_isr(int irq, void *data)
 207{
 208        struct tegra_emc *emc = data;
 209        u32 intmask = EMC_REFRESH_OVERFLOW_INT;
 210        u32 status;
 211
 212        status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
 213        if (!status)
 214                return IRQ_NONE;
 215
 216        /* notify about HW problem */
 217        if (status & EMC_REFRESH_OVERFLOW_INT)
 218                dev_err_ratelimited(emc->dev,
 219                                    "refresh request overflow timeout\n");
 220
 221        /* clear interrupts */
 222        writel_relaxed(status, emc->regs + EMC_INTSTATUS);
 223
 224        return IRQ_HANDLED;
 225}
 226
 227static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
 228                                                unsigned long rate)
 229{
 230        struct emc_timing *timing = NULL;
 231        unsigned int i;
 232
 233        for (i = 0; i < emc->num_timings; i++) {
 234                if (emc->timings[i].rate >= rate) {
 235                        timing = &emc->timings[i];
 236                        break;
 237                }
 238        }
 239
 240        if (!timing) {
 241                dev_err(emc->dev, "no timing for rate %lu\n", rate);
 242                return NULL;
 243        }
 244
 245        return timing;
 246}
 247
 248static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
 249{
 250        struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
 251        unsigned int i;
 252
 253        if (!timing)
 254                return -EINVAL;
 255
 256        dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
 257                __func__, timing->rate, rate);
 258
 259        /* program shadow registers */
 260        for (i = 0; i < ARRAY_SIZE(timing->data); i++)
 261                writel_relaxed(timing->data[i],
 262                               emc->regs + emc_timing_registers[i]);
 263
 264        /* wait until programming has settled */
 265        readl_relaxed(emc->regs + emc_timing_registers[i - 1]);
 266
 267        return 0;
 268}
 269
 270static int emc_complete_timing_change(struct tegra_emc *emc, bool flush)
 271{
 272        int err;
 273        u32 v;
 274
 275        dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush);
 276
 277        if (flush) {
 278                /* manually initiate memory timing update */
 279                writel_relaxed(EMC_TIMING_UPDATE,
 280                               emc->regs + EMC_TIMING_CONTROL);
 281                return 0;
 282        }
 283
 284        err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
 285                                                v & EMC_CLKCHANGE_COMPLETE_INT,
 286                                                1, 100);
 287        if (err) {
 288                dev_err(emc->dev, "emc-car handshake timeout: %d\n", err);
 289                return err;
 290        }
 291
 292        return 0;
 293}
 294
 295static int tegra_emc_clk_change_notify(struct notifier_block *nb,
 296                                       unsigned long msg, void *data)
 297{
 298        struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
 299        struct clk_notifier_data *cnd = data;
 300        int err;
 301
 302        switch (msg) {
 303        case PRE_RATE_CHANGE:
 304                err = emc_prepare_timing_change(emc, cnd->new_rate);
 305                break;
 306
 307        case ABORT_RATE_CHANGE:
 308                err = emc_prepare_timing_change(emc, cnd->old_rate);
 309                if (err)
 310                        break;
 311
 312                err = emc_complete_timing_change(emc, true);
 313                break;
 314
 315        case POST_RATE_CHANGE:
 316                err = emc_complete_timing_change(emc, false);
 317                break;
 318
 319        default:
 320                return NOTIFY_DONE;
 321        }
 322
 323        return notifier_from_errno(err);
 324}
 325
 326static int load_one_timing_from_dt(struct tegra_emc *emc,
 327                                   struct emc_timing *timing,
 328                                   struct device_node *node)
 329{
 330        u32 rate;
 331        int err;
 332
 333        if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) {
 334                dev_err(emc->dev, "incompatible DT node: %pOF\n", node);
 335                return -EINVAL;
 336        }
 337
 338        err = of_property_read_u32(node, "clock-frequency", &rate);
 339        if (err) {
 340                dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
 341                        node, err);
 342                return err;
 343        }
 344
 345        err = of_property_read_u32_array(node, "nvidia,emc-registers",
 346                                         timing->data,
 347                                         ARRAY_SIZE(emc_timing_registers));
 348        if (err) {
 349                dev_err(emc->dev,
 350                        "timing %pOF: failed to read emc timing data: %d\n",
 351                        node, err);
 352                return err;
 353        }
 354
 355        /*
 356         * The EMC clock rate is twice the bus rate, and the bus rate is
 357         * measured in kHz.
 358         */
 359        timing->rate = rate * 2 * 1000;
 360
 361        dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n",
 362                __func__, node, timing->rate);
 363
 364        return 0;
 365}
 366
 367static int cmp_timings(const void *_a, const void *_b)
 368{
 369        const struct emc_timing *a = _a;
 370        const struct emc_timing *b = _b;
 371
 372        if (a->rate < b->rate)
 373                return -1;
 374
 375        if (a->rate > b->rate)
 376                return 1;
 377
 378        return 0;
 379}
 380
 381static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
 382                                          struct device_node *node)
 383{
 384        struct device_node *child;
 385        struct emc_timing *timing;
 386        int child_count;
 387        int err;
 388
 389        child_count = of_get_child_count(node);
 390        if (!child_count) {
 391                dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node);
 392                return -EINVAL;
 393        }
 394
 395        emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
 396                                    GFP_KERNEL);
 397        if (!emc->timings)
 398                return -ENOMEM;
 399
 400        emc->num_timings = child_count;
 401        timing = emc->timings;
 402
 403        for_each_child_of_node(node, child) {
 404                err = load_one_timing_from_dt(emc, timing++, child);
 405                if (err) {
 406                        of_node_put(child);
 407                        return err;
 408                }
 409        }
 410
 411        sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
 412             NULL);
 413
 414        dev_info(emc->dev,
 415                 "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
 416                 emc->num_timings,
 417                 tegra_read_ram_code(),
 418                 emc->timings[0].rate / 1000000,
 419                 emc->timings[emc->num_timings - 1].rate / 1000000);
 420
 421        return 0;
 422}
 423
 424static struct device_node *
 425tegra_emc_find_node_by_ram_code(struct device *dev)
 426{
 427        struct device_node *np;
 428        u32 value, ram_code;
 429        int err;
 430
 431        if (of_get_child_count(dev->of_node) == 0) {
 432                dev_info(dev, "device-tree doesn't have memory timings\n");
 433                return NULL;
 434        }
 435
 436        if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code"))
 437                return of_node_get(dev->of_node);
 438
 439        ram_code = tegra_read_ram_code();
 440
 441        for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np;
 442             np = of_find_node_by_name(np, "emc-tables")) {
 443                err = of_property_read_u32(np, "nvidia,ram-code", &value);
 444                if (err || value != ram_code) {
 445                        of_node_put(np);
 446                        continue;
 447                }
 448
 449                return np;
 450        }
 451
 452        dev_err(dev, "no memory timings for RAM code %u found in device tree\n",
 453                ram_code);
 454
 455        return NULL;
 456}
 457
 458static int emc_setup_hw(struct tegra_emc *emc)
 459{
 460        u32 intmask = EMC_REFRESH_OVERFLOW_INT;
 461        u32 emc_cfg, emc_dbg, emc_fbio;
 462
 463        emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
 464
 465        /*
 466         * Depending on a memory type, DRAM should enter either self-refresh
 467         * or power-down state on EMC clock change.
 468         */
 469        if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) &&
 470            !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) {
 471                dev_err(emc->dev,
 472                        "bootloader didn't specify DRAM auto-suspend mode\n");
 473                return -EINVAL;
 474        }
 475
 476        /* enable EMC and CAR to handshake on PLL divider/source changes */
 477        emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE;
 478        writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
 479
 480        /* initialize interrupt */
 481        writel_relaxed(intmask, emc->regs + EMC_INTMASK);
 482        writel_relaxed(intmask, emc->regs + EMC_INTSTATUS);
 483
 484        /* ensure that unwanted debug features are disabled */
 485        emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
 486        emc_dbg |= EMC_DBG_CFG_PRIORITY;
 487        emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
 488        emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
 489        emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
 490        writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
 491
 492        emc_fbio = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
 493
 494        if (emc_fbio & EMC_FBIO_CFG5_DRAM_WIDTH_X16)
 495                emc->dram_bus_width = 16;
 496        else
 497                emc->dram_bus_width = 32;
 498
 499        dev_info(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
 500
 501        return 0;
 502}
 503
 504static long emc_round_rate(unsigned long rate,
 505                           unsigned long min_rate,
 506                           unsigned long max_rate,
 507                           void *arg)
 508{
 509        struct emc_timing *timing = NULL;
 510        struct tegra_emc *emc = arg;
 511        unsigned int i;
 512
 513        if (!emc->num_timings)
 514                return clk_get_rate(emc->clk);
 515
 516        min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
 517
 518        for (i = 0; i < emc->num_timings; i++) {
 519                if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
 520                        continue;
 521
 522                if (emc->timings[i].rate > max_rate) {
 523                        i = max(i, 1u) - 1;
 524
 525                        if (emc->timings[i].rate < min_rate)
 526                                break;
 527                }
 528
 529                if (emc->timings[i].rate < min_rate)
 530                        continue;
 531
 532                timing = &emc->timings[i];
 533                break;
 534        }
 535
 536        if (!timing) {
 537                dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
 538                        rate, min_rate, max_rate);
 539                return -EINVAL;
 540        }
 541
 542        return timing->rate;
 543}
 544
 545static void tegra_emc_rate_requests_init(struct tegra_emc *emc)
 546{
 547        unsigned int i;
 548
 549        for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {
 550                emc->requested_rate[i].min_rate = 0;
 551                emc->requested_rate[i].max_rate = ULONG_MAX;
 552        }
 553}
 554
 555static int emc_request_rate(struct tegra_emc *emc,
 556                            unsigned long new_min_rate,
 557                            unsigned long new_max_rate,
 558                            enum emc_rate_request_type type)
 559{
 560        struct emc_rate_request *req = emc->requested_rate;
 561        unsigned long min_rate = 0, max_rate = ULONG_MAX;
 562        unsigned int i;
 563        int err;
 564
 565        /* select minimum and maximum rates among the requested rates */
 566        for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {
 567                if (i == type) {
 568                        min_rate = max(new_min_rate, min_rate);
 569                        max_rate = min(new_max_rate, max_rate);
 570                } else {
 571                        min_rate = max(req->min_rate, min_rate);
 572                        max_rate = min(req->max_rate, max_rate);
 573                }
 574        }
 575
 576        if (min_rate > max_rate) {
 577                dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
 578                                    __func__, type, min_rate, max_rate);
 579                return -ERANGE;
 580        }
 581
 582        /*
 583         * EMC rate-changes should go via OPP API because it manages voltage
 584         * changes.
 585         */
 586        err = dev_pm_opp_set_rate(emc->dev, min_rate);
 587        if (err)
 588                return err;
 589
 590        emc->requested_rate[type].min_rate = new_min_rate;
 591        emc->requested_rate[type].max_rate = new_max_rate;
 592
 593        return 0;
 594}
 595
 596static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
 597                            enum emc_rate_request_type type)
 598{
 599        struct emc_rate_request *req = &emc->requested_rate[type];
 600        int ret;
 601
 602        mutex_lock(&emc->rate_lock);
 603        ret = emc_request_rate(emc, rate, req->max_rate, type);
 604        mutex_unlock(&emc->rate_lock);
 605
 606        return ret;
 607}
 608
 609static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
 610                            enum emc_rate_request_type type)
 611{
 612        struct emc_rate_request *req = &emc->requested_rate[type];
 613        int ret;
 614
 615        mutex_lock(&emc->rate_lock);
 616        ret = emc_request_rate(emc, req->min_rate, rate, type);
 617        mutex_unlock(&emc->rate_lock);
 618
 619        return ret;
 620}
 621
 622/*
 623 * debugfs interface
 624 *
 625 * The memory controller driver exposes some files in debugfs that can be used
 626 * to control the EMC frequency. The top-level directory can be found here:
 627 *
 628 *   /sys/kernel/debug/emc
 629 *
 630 * It contains the following files:
 631 *
 632 *   - available_rates: This file contains a list of valid, space-separated
 633 *     EMC frequencies.
 634 *
 635 *   - min_rate: Writing a value to this file sets the given frequency as the
 636 *       floor of the permitted range. If this is higher than the currently
 637 *       configured EMC frequency, this will cause the frequency to be
 638 *       increased so that it stays within the valid range.
 639 *
 640 *   - max_rate: Similarily to the min_rate file, writing a value to this file
 641 *       sets the given frequency as the ceiling of the permitted range. If
 642 *       the value is lower than the currently configured EMC frequency, this
 643 *       will cause the frequency to be decreased so that it stays within the
 644 *       valid range.
 645 */
 646
 647static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
 648{
 649        unsigned int i;
 650
 651        for (i = 0; i < emc->num_timings; i++)
 652                if (rate == emc->timings[i].rate)
 653                        return true;
 654
 655        return false;
 656}
 657
 658static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data)
 659{
 660        struct tegra_emc *emc = s->private;
 661        const char *prefix = "";
 662        unsigned int i;
 663
 664        for (i = 0; i < emc->num_timings; i++) {
 665                seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
 666                prefix = " ";
 667        }
 668
 669        seq_puts(s, "\n");
 670
 671        return 0;
 672}
 673
 674static int tegra_emc_debug_available_rates_open(struct inode *inode,
 675                                                struct file *file)
 676{
 677        return single_open(file, tegra_emc_debug_available_rates_show,
 678                           inode->i_private);
 679}
 680
 681static const struct file_operations tegra_emc_debug_available_rates_fops = {
 682        .open = tegra_emc_debug_available_rates_open,
 683        .read = seq_read,
 684        .llseek = seq_lseek,
 685        .release = single_release,
 686};
 687
 688static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
 689{
 690        struct tegra_emc *emc = data;
 691
 692        *rate = emc->debugfs.min_rate;
 693
 694        return 0;
 695}
 696
 697static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
 698{
 699        struct tegra_emc *emc = data;
 700        int err;
 701
 702        if (!tegra_emc_validate_rate(emc, rate))
 703                return -EINVAL;
 704
 705        err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
 706        if (err < 0)
 707                return err;
 708
 709        emc->debugfs.min_rate = rate;
 710
 711        return 0;
 712}
 713
 714DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
 715                        tegra_emc_debug_min_rate_get,
 716                        tegra_emc_debug_min_rate_set, "%llu\n");
 717
 718static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
 719{
 720        struct tegra_emc *emc = data;
 721
 722        *rate = emc->debugfs.max_rate;
 723
 724        return 0;
 725}
 726
 727static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
 728{
 729        struct tegra_emc *emc = data;
 730        int err;
 731
 732        if (!tegra_emc_validate_rate(emc, rate))
 733                return -EINVAL;
 734
 735        err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
 736        if (err < 0)
 737                return err;
 738
 739        emc->debugfs.max_rate = rate;
 740
 741        return 0;
 742}
 743
 744DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
 745                        tegra_emc_debug_max_rate_get,
 746                        tegra_emc_debug_max_rate_set, "%llu\n");
 747
 748static void tegra_emc_debugfs_init(struct tegra_emc *emc)
 749{
 750        struct device *dev = emc->dev;
 751        unsigned int i;
 752        int err;
 753
 754        emc->debugfs.min_rate = ULONG_MAX;
 755        emc->debugfs.max_rate = 0;
 756
 757        for (i = 0; i < emc->num_timings; i++) {
 758                if (emc->timings[i].rate < emc->debugfs.min_rate)
 759                        emc->debugfs.min_rate = emc->timings[i].rate;
 760
 761                if (emc->timings[i].rate > emc->debugfs.max_rate)
 762                        emc->debugfs.max_rate = emc->timings[i].rate;
 763        }
 764
 765        if (!emc->num_timings) {
 766                emc->debugfs.min_rate = clk_get_rate(emc->clk);
 767                emc->debugfs.max_rate = emc->debugfs.min_rate;
 768        }
 769
 770        err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
 771                                 emc->debugfs.max_rate);
 772        if (err < 0) {
 773                dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
 774                        emc->debugfs.min_rate, emc->debugfs.max_rate,
 775                        emc->clk);
 776        }
 777
 778        emc->debugfs.root = debugfs_create_dir("emc", NULL);
 779        if (!emc->debugfs.root) {
 780                dev_err(emc->dev, "failed to create debugfs directory\n");
 781                return;
 782        }
 783
 784        debugfs_create_file("available_rates", 0444, emc->debugfs.root,
 785                            emc, &tegra_emc_debug_available_rates_fops);
 786        debugfs_create_file("min_rate", 0644, emc->debugfs.root,
 787                            emc, &tegra_emc_debug_min_rate_fops);
 788        debugfs_create_file("max_rate", 0644, emc->debugfs.root,
 789                            emc, &tegra_emc_debug_max_rate_fops);
 790}
 791
 792static inline struct tegra_emc *
 793to_tegra_emc_provider(struct icc_provider *provider)
 794{
 795        return container_of(provider, struct tegra_emc, provider);
 796}
 797
 798static struct icc_node_data *
 799emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
 800{
 801        struct icc_provider *provider = data;
 802        struct icc_node_data *ndata;
 803        struct icc_node *node;
 804
 805        /* External Memory is the only possible ICC route */
 806        list_for_each_entry(node, &provider->nodes, node_list) {
 807                if (node->id != TEGRA_ICC_EMEM)
 808                        continue;
 809
 810                ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
 811                if (!ndata)
 812                        return ERR_PTR(-ENOMEM);
 813
 814                /*
 815                 * SRC and DST nodes should have matching TAG in order to have
 816                 * it set by default for a requested path.
 817                 */
 818                ndata->tag = TEGRA_MC_ICC_TAG_ISO;
 819                ndata->node = node;
 820
 821                return ndata;
 822        }
 823
 824        return ERR_PTR(-EPROBE_DEFER);
 825}
 826
 827static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
 828{
 829        struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
 830        unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);
 831        unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);
 832        unsigned long long rate = max(avg_bw, peak_bw);
 833        unsigned int dram_data_bus_width_bytes;
 834        int err;
 835
 836        /*
 837         * Tegra20 EMC runs on x2 clock rate of SDRAM bus because DDR data
 838         * is sampled on both clock edges.  This means that EMC clock rate
 839         * equals to the peak data-rate.
 840         */
 841        dram_data_bus_width_bytes = emc->dram_bus_width / 8;
 842        do_div(rate, dram_data_bus_width_bytes);
 843        rate = min_t(u64, rate, U32_MAX);
 844
 845        err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
 846        if (err)
 847                return err;
 848
 849        return 0;
 850}
 851
 852static int tegra_emc_interconnect_init(struct tegra_emc *emc)
 853{
 854        const struct tegra_mc_soc *soc;
 855        struct icc_node *node;
 856        int err;
 857
 858        emc->mc = devm_tegra_memory_controller_get(emc->dev);
 859        if (IS_ERR(emc->mc))
 860                return PTR_ERR(emc->mc);
 861
 862        soc = emc->mc->soc;
 863
 864        emc->provider.dev = emc->dev;
 865        emc->provider.set = emc_icc_set;
 866        emc->provider.data = &emc->provider;
 867        emc->provider.aggregate = soc->icc_ops->aggregate;
 868        emc->provider.xlate_extended = emc_of_icc_xlate_extended;
 869
 870        err = icc_provider_add(&emc->provider);
 871        if (err)
 872                goto err_msg;
 873
 874        /* create External Memory Controller node */
 875        node = icc_node_create(TEGRA_ICC_EMC);
 876        if (IS_ERR(node)) {
 877                err = PTR_ERR(node);
 878                goto del_provider;
 879        }
 880
 881        node->name = "External Memory Controller";
 882        icc_node_add(node, &emc->provider);
 883
 884        /* link External Memory Controller to External Memory (DRAM) */
 885        err = icc_link_create(node, TEGRA_ICC_EMEM);
 886        if (err)
 887                goto remove_nodes;
 888
 889        /* create External Memory node */
 890        node = icc_node_create(TEGRA_ICC_EMEM);
 891        if (IS_ERR(node)) {
 892                err = PTR_ERR(node);
 893                goto remove_nodes;
 894        }
 895
 896        node->name = "External Memory (DRAM)";
 897        icc_node_add(node, &emc->provider);
 898
 899        return 0;
 900
 901remove_nodes:
 902        icc_nodes_remove(&emc->provider);
 903del_provider:
 904        icc_provider_del(&emc->provider);
 905err_msg:
 906        dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
 907
 908        return err;
 909}
 910
 911static int tegra_emc_opp_table_init(struct tegra_emc *emc)
 912{
 913        u32 hw_version = BIT(tegra_sku_info.soc_process_id);
 914        struct opp_table *clk_opp_table, *hw_opp_table;
 915        int err;
 916
 917        clk_opp_table = dev_pm_opp_set_clkname(emc->dev, NULL);
 918        err = PTR_ERR_OR_ZERO(clk_opp_table);
 919        if (err) {
 920                dev_err(emc->dev, "failed to set OPP clk: %d\n", err);
 921                return err;
 922        }
 923
 924        hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1);
 925        err = PTR_ERR_OR_ZERO(hw_opp_table);
 926        if (err) {
 927                dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err);
 928                goto put_clk_table;
 929        }
 930
 931        err = dev_pm_opp_of_add_table(emc->dev);
 932        if (err) {
 933                if (err == -ENODEV)
 934                        dev_err(emc->dev, "OPP table not found, please update your device tree\n");
 935                else
 936                        dev_err(emc->dev, "failed to add OPP table: %d\n", err);
 937
 938                goto put_hw_table;
 939        }
 940
 941        dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
 942                 hw_version, clk_get_rate(emc->clk) / 1000000);
 943
 944        /* first dummy rate-set initializes voltage state */
 945        err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));
 946        if (err) {
 947                dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err);
 948                goto remove_table;
 949        }
 950
 951        return 0;
 952
 953remove_table:
 954        dev_pm_opp_of_remove_table(emc->dev);
 955put_hw_table:
 956        dev_pm_opp_put_supported_hw(hw_opp_table);
 957put_clk_table:
 958        dev_pm_opp_put_clkname(clk_opp_table);
 959
 960        return err;
 961}
 962
 963static void devm_tegra_emc_unset_callback(void *data)
 964{
 965        tegra20_clk_set_emc_round_callback(NULL, NULL);
 966}
 967
 968static void devm_tegra_emc_unreg_clk_notifier(void *data)
 969{
 970        struct tegra_emc *emc = data;
 971
 972        clk_notifier_unregister(emc->clk, &emc->clk_nb);
 973}
 974
 975static int tegra_emc_init_clk(struct tegra_emc *emc)
 976{
 977        int err;
 978
 979        tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
 980
 981        err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback,
 982                                       NULL);
 983        if (err)
 984                return err;
 985
 986        emc->clk = devm_clk_get(emc->dev, NULL);
 987        if (IS_ERR(emc->clk)) {
 988                dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk);
 989                return PTR_ERR(emc->clk);
 990        }
 991
 992        err = clk_notifier_register(emc->clk, &emc->clk_nb);
 993        if (err) {
 994                dev_err(emc->dev, "failed to register clk notifier: %d\n", err);
 995                return err;
 996        }
 997
 998        err = devm_add_action_or_reset(emc->dev,
 999                                       devm_tegra_emc_unreg_clk_notifier, emc);
1000        if (err)
1001                return err;
1002
1003        return 0;
1004}
1005
1006static int tegra_emc_devfreq_target(struct device *dev, unsigned long *freq,
1007                                    u32 flags)
1008{
1009        struct tegra_emc *emc = dev_get_drvdata(dev);
1010        struct dev_pm_opp *opp;
1011        unsigned long rate;
1012
1013        opp = devfreq_recommended_opp(dev, freq, flags);
1014        if (IS_ERR(opp)) {
1015                dev_err(dev, "failed to find opp for %lu Hz\n", *freq);
1016                return PTR_ERR(opp);
1017        }
1018
1019        rate = dev_pm_opp_get_freq(opp);
1020        dev_pm_opp_put(opp);
1021
1022        return emc_set_min_rate(emc, rate, EMC_RATE_DEVFREQ);
1023}
1024
1025static int tegra_emc_devfreq_get_dev_status(struct device *dev,
1026                                            struct devfreq_dev_status *stat)
1027{
1028        struct tegra_emc *emc = dev_get_drvdata(dev);
1029
1030        /* freeze counters */
1031        writel_relaxed(EMC_PWR_GATHER_DISABLE, emc->regs + EMC_STAT_CONTROL);
1032
1033        /*
1034         *  busy_time: number of clocks EMC request was accepted
1035         * total_time: number of clocks PWR_GATHER control was set to ENABLE
1036         */
1037        stat->busy_time = readl_relaxed(emc->regs + EMC_STAT_PWR_COUNT);
1038        stat->total_time = readl_relaxed(emc->regs + EMC_STAT_PWR_CLOCKS);
1039        stat->current_frequency = clk_get_rate(emc->clk);
1040
1041        /* clear counters and restart */
1042        writel_relaxed(EMC_PWR_GATHER_CLEAR, emc->regs + EMC_STAT_CONTROL);
1043        writel_relaxed(EMC_PWR_GATHER_ENABLE, emc->regs + EMC_STAT_CONTROL);
1044
1045        return 0;
1046}
1047
1048static struct devfreq_dev_profile tegra_emc_devfreq_profile = {
1049        .polling_ms = 30,
1050        .target = tegra_emc_devfreq_target,
1051        .get_dev_status = tegra_emc_devfreq_get_dev_status,
1052};
1053
1054static int tegra_emc_devfreq_init(struct tegra_emc *emc)
1055{
1056        struct devfreq *devfreq;
1057
1058        /*
1059         * PWR_COUNT is 1/2 of PWR_CLOCKS at max, and thus, the up-threshold
1060         * should be less than 50.  Secondly, multiple active memory clients
1061         * may cause over 20% of lost clock cycles due to stalls caused by
1062         * competing memory accesses.  This means that threshold should be
1063         * set to a less than 30 in order to have a properly working governor.
1064         */
1065        emc->ondemand_data.upthreshold = 20;
1066
1067        /*
1068         * Reset statistic gathers state, select global bandwidth for the
1069         * statistics collection mode and set clocks counter saturation
1070         * limit to maximum.
1071         */
1072        writel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL);
1073        writel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL);
1074        writel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT);
1075
1076        devfreq = devm_devfreq_add_device(emc->dev, &tegra_emc_devfreq_profile,
1077                                          DEVFREQ_GOV_SIMPLE_ONDEMAND,
1078                                          &emc->ondemand_data);
1079        if (IS_ERR(devfreq)) {
1080                dev_err(emc->dev, "failed to initialize devfreq: %pe", devfreq);
1081                return PTR_ERR(devfreq);
1082        }
1083
1084        return 0;
1085}
1086
1087static int tegra_emc_probe(struct platform_device *pdev)
1088{
1089        struct device_node *np;
1090        struct tegra_emc *emc;
1091        int irq, err;
1092
1093        irq = platform_get_irq(pdev, 0);
1094        if (irq < 0) {
1095                dev_err(&pdev->dev, "please update your device tree\n");
1096                return irq;
1097        }
1098
1099        emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1100        if (!emc)
1101                return -ENOMEM;
1102
1103        mutex_init(&emc->rate_lock);
1104        emc->clk_nb.notifier_call = tegra_emc_clk_change_notify;
1105        emc->dev = &pdev->dev;
1106
1107        np = tegra_emc_find_node_by_ram_code(&pdev->dev);
1108        if (np) {
1109                err = tegra_emc_load_timings_from_dt(emc, np);
1110                of_node_put(np);
1111                if (err)
1112                        return err;
1113        }
1114
1115        emc->regs = devm_platform_ioremap_resource(pdev, 0);
1116        if (IS_ERR(emc->regs))
1117                return PTR_ERR(emc->regs);
1118
1119        err = emc_setup_hw(emc);
1120        if (err)
1121                return err;
1122
1123        err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0,
1124                               dev_name(&pdev->dev), emc);
1125        if (err) {
1126                dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1127                return err;
1128        }
1129
1130        err = tegra_emc_init_clk(emc);
1131        if (err)
1132                return err;
1133
1134        err = tegra_emc_opp_table_init(emc);
1135        if (err)
1136                return err;
1137
1138        platform_set_drvdata(pdev, emc);
1139        tegra_emc_rate_requests_init(emc);
1140        tegra_emc_debugfs_init(emc);
1141        tegra_emc_interconnect_init(emc);
1142        tegra_emc_devfreq_init(emc);
1143
1144        /*
1145         * Don't allow the kernel module to be unloaded. Unloading adds some
1146         * extra complexity which doesn't really worth the effort in a case of
1147         * this driver.
1148         */
1149        try_module_get(THIS_MODULE);
1150
1151        return 0;
1152}
1153
1154static const struct of_device_id tegra_emc_of_match[] = {
1155        { .compatible = "nvidia,tegra20-emc", },
1156        {},
1157};
1158MODULE_DEVICE_TABLE(of, tegra_emc_of_match);
1159
1160static struct platform_driver tegra_emc_driver = {
1161        .probe = tegra_emc_probe,
1162        .driver = {
1163                .name = "tegra20-emc",
1164                .of_match_table = tegra_emc_of_match,
1165                .suppress_bind_attrs = true,
1166                .sync_state = icc_sync_state,
1167        },
1168};
1169module_platform_driver(tegra_emc_driver);
1170
1171MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>");
1172MODULE_DESCRIPTION("NVIDIA Tegra20 EMC driver");
1173MODULE_LICENSE("GPL v2");
1174