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4#ifndef __HNAE3_H
5#define __HNAE3_H
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24#include <linux/acpi.h>
25#include <linux/dcbnl.h>
26#include <linux/delay.h>
27#include <linux/device.h>
28#include <linux/ethtool.h>
29#include <linux/module.h>
30#include <linux/netdevice.h>
31#include <linux/pci.h>
32#include <linux/pkt_sched.h>
33#include <linux/types.h>
34#include <net/pkt_cls.h>
35
36#define HNAE3_MOD_VERSION "1.0"
37
38#define HNAE3_MIN_VECTOR_NUM 2
39
40
41#define HNAE3_DEVICE_VERSION_V1 0x00020
42#define HNAE3_DEVICE_VERSION_V2 0x00021
43#define HNAE3_DEVICE_VERSION_V3 0x00030
44
45#define HNAE3_PCI_REVISION_BIT_SIZE 8
46
47
48#define HNAE3_DEV_ID_GE 0xA220
49#define HNAE3_DEV_ID_25GE 0xA221
50#define HNAE3_DEV_ID_25GE_RDMA 0xA222
51#define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA223
52#define HNAE3_DEV_ID_50GE_RDMA 0xA224
53#define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA225
54#define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA226
55#define HNAE3_DEV_ID_200G_RDMA 0xA228
56#define HNAE3_DEV_ID_VF 0xA22E
57#define HNAE3_DEV_ID_RDMA_DCB_PFC_VF 0xA22F
58
59#define HNAE3_CLASS_NAME_SIZE 16
60
61#define HNAE3_DEV_INITED_B 0x0
62#define HNAE3_DEV_SUPPORT_ROCE_B 0x1
63#define HNAE3_DEV_SUPPORT_DCB_B 0x2
64#define HNAE3_KNIC_CLIENT_INITED_B 0x3
65#define HNAE3_UNIC_CLIENT_INITED_B 0x4
66#define HNAE3_ROCE_CLIENT_INITED_B 0x5
67
68#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\
69 BIT(HNAE3_DEV_SUPPORT_ROCE_B))
70
71#define hnae3_dev_roce_supported(hdev) \
72 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)
73
74#define hnae3_dev_dcb_supported(hdev) \
75 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)
76
77enum HNAE3_DEV_CAP_BITS {
78 HNAE3_DEV_SUPPORT_FD_B,
79 HNAE3_DEV_SUPPORT_GRO_B,
80 HNAE3_DEV_SUPPORT_FEC_B,
81 HNAE3_DEV_SUPPORT_UDP_GSO_B,
82 HNAE3_DEV_SUPPORT_QB_B,
83 HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B,
84 HNAE3_DEV_SUPPORT_PTP_B,
85 HNAE3_DEV_SUPPORT_INT_QL_B,
86 HNAE3_DEV_SUPPORT_HW_TX_CSUM_B,
87 HNAE3_DEV_SUPPORT_TX_PUSH_B,
88 HNAE3_DEV_SUPPORT_PHY_IMP_B,
89 HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B,
90 HNAE3_DEV_SUPPORT_HW_PAD_B,
91 HNAE3_DEV_SUPPORT_STASH_B,
92 HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,
93};
94
95#define hnae3_dev_fd_supported(hdev) \
96 test_bit(HNAE3_DEV_SUPPORT_FD_B, (hdev)->ae_dev->caps)
97
98#define hnae3_dev_gro_supported(hdev) \
99 test_bit(HNAE3_DEV_SUPPORT_GRO_B, (hdev)->ae_dev->caps)
100
101#define hnae3_dev_fec_supported(hdev) \
102 test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps)
103
104#define hnae3_dev_udp_gso_supported(hdev) \
105 test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps)
106
107#define hnae3_dev_qb_supported(hdev) \
108 test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps)
109
110#define hnae3_dev_fd_forward_tc_supported(hdev) \
111 test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps)
112
113#define hnae3_dev_ptp_supported(hdev) \
114 test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps)
115
116#define hnae3_dev_int_ql_supported(hdev) \
117 test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps)
118
119#define hnae3_dev_hw_csum_supported(hdev) \
120 test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps)
121
122#define hnae3_dev_tx_push_supported(hdev) \
123 test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps)
124
125#define hnae3_dev_phy_imp_supported(hdev) \
126 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps)
127
128#define hnae3_dev_tqp_txrx_indep_supported(hdev) \
129 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps)
130
131#define hnae3_dev_hw_pad_supported(hdev) \
132 test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps)
133
134#define hnae3_dev_stash_supported(hdev) \
135 test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps)
136
137#define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \
138 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps)
139
140#define ring_ptr_move_fw(ring, p) \
141 ((ring)->p = ((ring)->p + 1) % (ring)->desc_num)
142#define ring_ptr_move_bw(ring, p) \
143 ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num)
144
145enum hns_desc_type {
146 DESC_TYPE_UNKNOWN,
147 DESC_TYPE_SKB,
148 DESC_TYPE_FRAGLIST_SKB,
149 DESC_TYPE_PAGE,
150};
151
152struct hnae3_handle;
153
154struct hnae3_queue {
155 void __iomem *io_base;
156 struct hnae3_ae_algo *ae_algo;
157 struct hnae3_handle *handle;
158 int tqp_index;
159 u32 buf_size;
160 u16 tx_desc_num;
161 u16 rx_desc_num;
162};
163
164struct hns3_mac_stats {
165 u64 tx_pause_cnt;
166 u64 rx_pause_cnt;
167};
168
169
170enum hnae3_loop {
171 HNAE3_LOOP_APP,
172 HNAE3_LOOP_SERIAL_SERDES,
173 HNAE3_LOOP_PARALLEL_SERDES,
174 HNAE3_LOOP_PHY,
175 HNAE3_LOOP_NONE,
176};
177
178enum hnae3_client_type {
179 HNAE3_CLIENT_KNIC,
180 HNAE3_CLIENT_ROCE,
181};
182
183
184enum hnae3_media_type {
185 HNAE3_MEDIA_TYPE_UNKNOWN,
186 HNAE3_MEDIA_TYPE_FIBER,
187 HNAE3_MEDIA_TYPE_COPPER,
188 HNAE3_MEDIA_TYPE_BACKPLANE,
189 HNAE3_MEDIA_TYPE_NONE,
190};
191
192
193enum hnae3_module_type {
194 HNAE3_MODULE_TYPE_UNKNOWN = 0x00,
195 HNAE3_MODULE_TYPE_FIBRE_LR = 0x01,
196 HNAE3_MODULE_TYPE_FIBRE_SR = 0x02,
197 HNAE3_MODULE_TYPE_AOC = 0x03,
198 HNAE3_MODULE_TYPE_CR = 0x04,
199 HNAE3_MODULE_TYPE_KR = 0x05,
200 HNAE3_MODULE_TYPE_TP = 0x06,
201};
202
203enum hnae3_fec_mode {
204 HNAE3_FEC_AUTO = 0,
205 HNAE3_FEC_BASER,
206 HNAE3_FEC_RS,
207 HNAE3_FEC_USER_DEF,
208};
209
210enum hnae3_reset_notify_type {
211 HNAE3_UP_CLIENT,
212 HNAE3_DOWN_CLIENT,
213 HNAE3_INIT_CLIENT,
214 HNAE3_UNINIT_CLIENT,
215};
216
217enum hnae3_hw_error_type {
218 HNAE3_PPU_POISON_ERROR,
219 HNAE3_CMDQ_ECC_ERROR,
220 HNAE3_IMP_RD_POISON_ERROR,
221 HNAE3_ROCEE_AXI_RESP_ERROR,
222};
223
224enum hnae3_reset_type {
225 HNAE3_VF_RESET,
226 HNAE3_VF_FUNC_RESET,
227 HNAE3_VF_PF_FUNC_RESET,
228 HNAE3_VF_FULL_RESET,
229 HNAE3_FLR_RESET,
230 HNAE3_FUNC_RESET,
231 HNAE3_GLOBAL_RESET,
232 HNAE3_IMP_RESET,
233 HNAE3_UNKNOWN_RESET,
234 HNAE3_NONE_RESET,
235 HNAE3_MAX_RESET,
236};
237
238enum hnae3_port_base_vlan_state {
239 HNAE3_PORT_BASE_VLAN_DISABLE,
240 HNAE3_PORT_BASE_VLAN_ENABLE,
241 HNAE3_PORT_BASE_VLAN_MODIFY,
242 HNAE3_PORT_BASE_VLAN_NOCHANGE,
243};
244
245struct hnae3_vector_info {
246 u8 __iomem *io_addr;
247 int vector;
248};
249
250#define HNAE3_RING_TYPE_B 0
251#define HNAE3_RING_TYPE_TX 0
252#define HNAE3_RING_TYPE_RX 1
253#define HNAE3_RING_GL_IDX_S 0
254#define HNAE3_RING_GL_IDX_M GENMASK(1, 0)
255#define HNAE3_RING_GL_RX 0
256#define HNAE3_RING_GL_TX 1
257
258#define HNAE3_FW_VERSION_BYTE3_SHIFT 24
259#define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24)
260#define HNAE3_FW_VERSION_BYTE2_SHIFT 16
261#define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16)
262#define HNAE3_FW_VERSION_BYTE1_SHIFT 8
263#define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8)
264#define HNAE3_FW_VERSION_BYTE0_SHIFT 0
265#define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0)
266
267struct hnae3_ring_chain_node {
268 struct hnae3_ring_chain_node *next;
269 u32 tqp_index;
270 u32 flag;
271 u32 int_gl_idx;
272};
273
274#define HNAE3_IS_TX_RING(node) \
275 (((node)->flag & (1 << HNAE3_RING_TYPE_B)) == HNAE3_RING_TYPE_TX)
276
277
278struct hnae3_dev_specs {
279 u32 mac_entry_num;
280 u32 mng_entry_num;
281 u32 max_tm_rate;
282 u16 rss_ind_tbl_size;
283 u16 rss_key_size;
284 u16 int_ql_max;
285 u16 max_int_gl;
286 u8 max_non_tso_bd_num;
287};
288
289struct hnae3_client_ops {
290 int (*init_instance)(struct hnae3_handle *handle);
291 void (*uninit_instance)(struct hnae3_handle *handle, bool reset);
292 void (*link_status_change)(struct hnae3_handle *handle, bool state);
293 int (*setup_tc)(struct hnae3_handle *handle, u8 tc);
294 int (*reset_notify)(struct hnae3_handle *handle,
295 enum hnae3_reset_notify_type type);
296 void (*process_hw_error)(struct hnae3_handle *handle,
297 enum hnae3_hw_error_type);
298};
299
300#define HNAE3_CLIENT_NAME_LENGTH 16
301struct hnae3_client {
302 char name[HNAE3_CLIENT_NAME_LENGTH];
303 unsigned long state;
304 enum hnae3_client_type type;
305 const struct hnae3_client_ops *ops;
306 struct list_head node;
307};
308
309#define HNAE3_DEV_CAPS_MAX_NUM 96
310struct hnae3_ae_dev {
311 struct pci_dev *pdev;
312 const struct hnae3_ae_ops *ops;
313 struct list_head node;
314 u32 flag;
315 unsigned long hw_err_reset_req;
316 struct hnae3_dev_specs dev_specs;
317 u32 dev_version;
318 unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)];
319 void *priv;
320};
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469struct hnae3_ae_ops {
470 int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev);
471 void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev);
472 void (*flr_prepare)(struct hnae3_ae_dev *ae_dev);
473 void (*flr_done)(struct hnae3_ae_dev *ae_dev);
474 int (*init_client_instance)(struct hnae3_client *client,
475 struct hnae3_ae_dev *ae_dev);
476 void (*uninit_client_instance)(struct hnae3_client *client,
477 struct hnae3_ae_dev *ae_dev);
478 int (*start)(struct hnae3_handle *handle);
479 void (*stop)(struct hnae3_handle *handle);
480 int (*client_start)(struct hnae3_handle *handle);
481 void (*client_stop)(struct hnae3_handle *handle);
482 int (*get_status)(struct hnae3_handle *handle);
483 void (*get_ksettings_an_result)(struct hnae3_handle *handle,
484 u8 *auto_neg, u32 *speed, u8 *duplex);
485
486 int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed,
487 u8 duplex);
488
489 void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type,
490 u8 *module_type);
491 int (*check_port_speed)(struct hnae3_handle *handle, u32 speed);
492 void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability,
493 u8 *fec_mode);
494 int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode);
495 void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex);
496 int (*set_loopback)(struct hnae3_handle *handle,
497 enum hnae3_loop loop_mode, bool en);
498
499 int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc,
500 bool en_mc_pmc);
501 void (*request_update_promisc_mode)(struct hnae3_handle *handle);
502 int (*set_mtu)(struct hnae3_handle *handle, int new_mtu);
503
504 void (*get_pauseparam)(struct hnae3_handle *handle,
505 u32 *auto_neg, u32 *rx_en, u32 *tx_en);
506 int (*set_pauseparam)(struct hnae3_handle *handle,
507 u32 auto_neg, u32 rx_en, u32 tx_en);
508
509 int (*set_autoneg)(struct hnae3_handle *handle, bool enable);
510 int (*get_autoneg)(struct hnae3_handle *handle);
511 int (*restart_autoneg)(struct hnae3_handle *handle);
512 int (*halt_autoneg)(struct hnae3_handle *handle, bool halt);
513
514 void (*get_coalesce_usecs)(struct hnae3_handle *handle,
515 u32 *tx_usecs, u32 *rx_usecs);
516 void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle,
517 u32 *tx_frames, u32 *rx_frames);
518 int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout);
519 int (*set_coalesce_frames)(struct hnae3_handle *handle,
520 u32 coalesce_frames);
521 void (*get_coalesce_range)(struct hnae3_handle *handle,
522 u32 *tx_frames_low, u32 *rx_frames_low,
523 u32 *tx_frames_high, u32 *rx_frames_high,
524 u32 *tx_usecs_low, u32 *rx_usecs_low,
525 u32 *tx_usecs_high, u32 *rx_usecs_high);
526
527 void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p);
528 int (*set_mac_addr)(struct hnae3_handle *handle, void *p,
529 bool is_first);
530 int (*do_ioctl)(struct hnae3_handle *handle,
531 struct ifreq *ifr, int cmd);
532 int (*add_uc_addr)(struct hnae3_handle *handle,
533 const unsigned char *addr);
534 int (*rm_uc_addr)(struct hnae3_handle *handle,
535 const unsigned char *addr);
536 int (*set_mc_addr)(struct hnae3_handle *handle, void *addr);
537 int (*add_mc_addr)(struct hnae3_handle *handle,
538 const unsigned char *addr);
539 int (*rm_mc_addr)(struct hnae3_handle *handle,
540 const unsigned char *addr);
541 void (*set_tso_stats)(struct hnae3_handle *handle, int enable);
542 void (*update_stats)(struct hnae3_handle *handle,
543 struct net_device_stats *net_stats);
544 void (*get_stats)(struct hnae3_handle *handle, u64 *data);
545 void (*get_mac_stats)(struct hnae3_handle *handle,
546 struct hns3_mac_stats *mac_stats);
547 void (*get_strings)(struct hnae3_handle *handle,
548 u32 stringset, u8 *data);
549 int (*get_sset_count)(struct hnae3_handle *handle, int stringset);
550
551 void (*get_regs)(struct hnae3_handle *handle, u32 *version,
552 void *data);
553 int (*get_regs_len)(struct hnae3_handle *handle);
554
555 u32 (*get_rss_key_size)(struct hnae3_handle *handle);
556 u32 (*get_rss_indir_size)(struct hnae3_handle *handle);
557 int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key,
558 u8 *hfunc);
559 int (*set_rss)(struct hnae3_handle *handle, const u32 *indir,
560 const u8 *key, const u8 hfunc);
561 int (*set_rss_tuple)(struct hnae3_handle *handle,
562 struct ethtool_rxnfc *cmd);
563 int (*get_rss_tuple)(struct hnae3_handle *handle,
564 struct ethtool_rxnfc *cmd);
565
566 int (*get_tc_size)(struct hnae3_handle *handle);
567
568 int (*get_vector)(struct hnae3_handle *handle, u16 vector_num,
569 struct hnae3_vector_info *vector_info);
570 int (*put_vector)(struct hnae3_handle *handle, int vector_num);
571 int (*map_ring_to_vector)(struct hnae3_handle *handle,
572 int vector_num,
573 struct hnae3_ring_chain_node *vr_chain);
574 int (*unmap_ring_from_vector)(struct hnae3_handle *handle,
575 int vector_num,
576 struct hnae3_ring_chain_node *vr_chain);
577
578 int (*reset_queue)(struct hnae3_handle *handle, u16 queue_id);
579 u32 (*get_fw_version)(struct hnae3_handle *handle);
580 void (*get_mdix_mode)(struct hnae3_handle *handle,
581 u8 *tp_mdix_ctrl, u8 *tp_mdix);
582
583 void (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable);
584 int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto,
585 u16 vlan_id, bool is_kill);
586 int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid,
587 u16 vlan, u8 qos, __be16 proto);
588 int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable);
589 void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle);
590 enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev,
591 unsigned long *addr);
592 void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev,
593 enum hnae3_reset_type rst_type);
594 void (*get_channels)(struct hnae3_handle *handle,
595 struct ethtool_channels *ch);
596 void (*get_tqps_and_rss_info)(struct hnae3_handle *h,
597 u16 *alloc_tqps, u16 *max_rss_size);
598 int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num,
599 bool rxfh_configured);
600 void (*get_flowctrl_adv)(struct hnae3_handle *handle,
601 u32 *flowctrl_adv);
602 int (*set_led_id)(struct hnae3_handle *handle,
603 enum ethtool_phys_id_state status);
604 void (*get_link_mode)(struct hnae3_handle *handle,
605 unsigned long *supported,
606 unsigned long *advertising);
607 int (*add_fd_entry)(struct hnae3_handle *handle,
608 struct ethtool_rxnfc *cmd);
609 int (*del_fd_entry)(struct hnae3_handle *handle,
610 struct ethtool_rxnfc *cmd);
611 void (*del_all_fd_entries)(struct hnae3_handle *handle,
612 bool clear_list);
613 int (*get_fd_rule_cnt)(struct hnae3_handle *handle,
614 struct ethtool_rxnfc *cmd);
615 int (*get_fd_rule_info)(struct hnae3_handle *handle,
616 struct ethtool_rxnfc *cmd);
617 int (*get_fd_all_rules)(struct hnae3_handle *handle,
618 struct ethtool_rxnfc *cmd, u32 *rule_locs);
619 void (*enable_fd)(struct hnae3_handle *handle, bool enable);
620 int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id,
621 u16 flow_id, struct flow_keys *fkeys);
622 int (*dbg_run_cmd)(struct hnae3_handle *handle, const char *cmd_buf);
623 pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev);
624 bool (*get_hw_reset_stat)(struct hnae3_handle *handle);
625 bool (*ae_dev_resetting)(struct hnae3_handle *handle);
626 unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle);
627 int (*set_gro_en)(struct hnae3_handle *handle, bool enable);
628 u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id);
629 void (*set_timer_task)(struct hnae3_handle *handle, bool enable);
630 int (*mac_connect_phy)(struct hnae3_handle *handle);
631 void (*mac_disconnect_phy)(struct hnae3_handle *handle);
632 int (*get_vf_config)(struct hnae3_handle *handle, int vf,
633 struct ifla_vf_info *ivf);
634 int (*set_vf_link_state)(struct hnae3_handle *handle, int vf,
635 int link_state);
636 int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf,
637 bool enable);
638 int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable);
639 int (*set_vf_rate)(struct hnae3_handle *handle, int vf,
640 int min_tx_rate, int max_tx_rate, bool force);
641 int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p);
642 int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset,
643 u32 len, u8 *data);
644 bool (*get_cmdq_stat)(struct hnae3_handle *handle);
645 int (*add_cls_flower)(struct hnae3_handle *handle,
646 struct flow_cls_offload *cls_flower, int tc);
647 int (*del_cls_flower)(struct hnae3_handle *handle,
648 struct flow_cls_offload *cls_flower);
649 bool (*cls_flower_active)(struct hnae3_handle *handle);
650};
651
652struct hnae3_dcb_ops {
653
654 int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *);
655 int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *);
656 int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *);
657 int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *);
658
659
660 u8 (*getdcbx)(struct hnae3_handle *);
661 u8 (*setdcbx)(struct hnae3_handle *, u8);
662
663 int (*setup_tc)(struct hnae3_handle *handle,
664 struct tc_mqprio_qopt_offload *mqprio_qopt);
665};
666
667struct hnae3_ae_algo {
668 const struct hnae3_ae_ops *ops;
669 struct list_head node;
670 const struct pci_device_id *pdev_id_table;
671};
672
673#define HNAE3_INT_NAME_LEN 32
674#define HNAE3_ITR_COUNTDOWN_START 100
675
676#define HNAE3_MAX_TC 8
677#define HNAE3_MAX_USER_PRIO 8
678struct hnae3_tc_info {
679 u8 prio_tc[HNAE3_MAX_USER_PRIO];
680 u16 tqp_count[HNAE3_MAX_TC];
681 u16 tqp_offset[HNAE3_MAX_TC];
682 unsigned long tc_en;
683 u8 num_tc;
684 bool mqprio_active;
685};
686
687struct hnae3_knic_private_info {
688 struct net_device *netdev;
689 u16 rss_size;
690 u16 req_rss_size;
691 u16 rx_buf_len;
692 u16 num_tx_desc;
693 u16 num_rx_desc;
694
695 struct hnae3_tc_info tc_info;
696
697 u16 num_tqps;
698 struct hnae3_queue **tqp;
699 const struct hnae3_dcb_ops *dcb_ops;
700
701 u16 int_rl_setting;
702 enum pkt_hash_types rss_type;
703};
704
705struct hnae3_roce_private_info {
706 struct net_device *netdev;
707 void __iomem *roce_io_base;
708 void __iomem *roce_mem_base;
709 int base_vector;
710 int num_vectors;
711
712
713
714
715
716 unsigned long reset_state;
717 unsigned long instance_state;
718 unsigned long state;
719};
720
721#define HNAE3_SUPPORT_APP_LOOPBACK BIT(0)
722#define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1)
723#define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2)
724#define HNAE3_SUPPORT_VF BIT(3)
725#define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4)
726
727#define HNAE3_USER_UPE BIT(0)
728#define HNAE3_USER_MPE BIT(1)
729#define HNAE3_BPE BIT(2)
730#define HNAE3_OVERFLOW_UPE BIT(3)
731#define HNAE3_OVERFLOW_MPE BIT(4)
732#define HNAE3_VLAN_FLTR BIT(5)
733#define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE)
734#define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE)
735
736enum hnae3_pflag {
737 HNAE3_PFLAG_LIMIT_PROMISC,
738 HNAE3_PFLAG_MAX
739};
740
741struct hnae3_handle {
742 struct hnae3_client *client;
743 struct pci_dev *pdev;
744 void *priv;
745 struct hnae3_ae_algo *ae_algo;
746 u64 flags;
747
748 union {
749 struct net_device *netdev;
750 struct hnae3_knic_private_info kinfo;
751 struct hnae3_roce_private_info rinfo;
752 };
753
754 u32 numa_node_mask;
755
756 enum hnae3_port_base_vlan_state port_base_vlan_state;
757
758 u8 netdev_flags;
759 struct dentry *hnae3_dbgfs;
760
761
762 u32 msg_enable;
763
764 unsigned long supported_pflags;
765 unsigned long priv_flags;
766};
767
768#define hnae3_set_field(origin, mask, shift, val) \
769 do { \
770 (origin) &= (~(mask)); \
771 (origin) |= ((val) << (shift)) & (mask); \
772 } while (0)
773#define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift))
774
775#define hnae3_set_bit(origin, shift, val) \
776 hnae3_set_field((origin), (0x1 << (shift)), (shift), (val))
777#define hnae3_get_bit(origin, shift) \
778 hnae3_get_field((origin), (0x1 << (shift)), (shift))
779
780int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev);
781void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev);
782
783void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo);
784void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo);
785
786void hnae3_unregister_client(struct hnae3_client *client);
787int hnae3_register_client(struct hnae3_client *client);
788
789void hnae3_set_client_init_flag(struct hnae3_client *client,
790 struct hnae3_ae_dev *ae_dev,
791 unsigned int inited);
792#endif
793