LXR linux/drivers/net/ethernet/intel/e1000e/e1000.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4/* Linux PRO/1000 Ethernet Driver main header file */
   5
   6#ifndef _E1000_H_
   7#define _E1000_H_
   8
   9#include <linux/bitops.h>
  10#include <linux/types.h>
  11#include <linux/timer.h>
  12#include <linux/workqueue.h>
  13#include <linux/io.h>
  14#include <linux/netdevice.h>
  15#include <linux/pci.h>
  16#include <linux/crc32.h>
  17#include <linux/if_vlan.h>
  18#include <linux/timecounter.h>
  19#include <linux/net_tstamp.h>
  20#include <linux/ptp_clock_kernel.h>
  21#include <linux/ptp_classify.h>
  22#include <linux/mii.h>
  23#include <linux/mdio.h>
  24#include <linux/pm_qos.h>
  25#include "hw.h"
  26
  27struct e1000_info;
  28
  29#define e_dbg(format, arg...) \
  30        netdev_dbg(hw->adapter->netdev, format, ## arg)
  31#define e_err(format, arg...) \
  32        netdev_err(adapter->netdev, format, ## arg)
  33#define e_info(format, arg...) \
  34        netdev_info(adapter->netdev, format, ## arg)
  35#define e_warn(format, arg...) \
  36        netdev_warn(adapter->netdev, format, ## arg)
  37#define e_notice(format, arg...) \
  38        netdev_notice(adapter->netdev, format, ## arg)
  39
  40/* Interrupt modes, as used by the IntMode parameter */
  41#define E1000E_INT_MODE_LEGACY          0
  42#define E1000E_INT_MODE_MSI             1
  43#define E1000E_INT_MODE_MSIX            2
  44
  45/* Tx/Rx descriptor defines */
  46#define E1000_DEFAULT_TXD               256
  47#define E1000_MAX_TXD                   4096
  48#define E1000_MIN_TXD                   64
  49
  50#define E1000_DEFAULT_RXD               256
  51#define E1000_MAX_RXD                   4096
  52#define E1000_MIN_RXD                   64
  53
  54#define E1000_MIN_ITR_USECS             10 /* 100000 irq/sec */
  55#define E1000_MAX_ITR_USECS             10000 /* 100    irq/sec */
  56
  57#define E1000_FC_PAUSE_TIME             0x0680 /* 858 usec */
  58
  59/* How many Tx Descriptors do we need to call netif_wake_queue ? */
  60/* How many Rx Buffers do we bundle into one write to the hardware ? */
  61#define E1000_RX_BUFFER_WRITE           16 /* Must be power of 2 */
  62
  63#define AUTO_ALL_MODES                  0
  64#define E1000_EEPROM_APME               0x0400
  65
  66#define E1000_MNG_VLAN_NONE             (-1)
  67
  68#define DEFAULT_JUMBO                   9234
  69
  70/* Time to wait before putting the device into D3 if there's no link (in ms). */
  71#define LINK_TIMEOUT            100
  72
  73/* Count for polling __E1000_RESET condition every 10-20msec.
  74 * Experimentation has shown the reset can take approximately 210msec.
  75 */
  76#define E1000_CHECK_RESET_COUNT         25
  77
  78#define PCICFG_DESC_RING_STATUS         0xe4
  79#define FLUSH_DESC_REQUIRED             0x100
  80
  81/* in the case of WTHRESH, it appears at least the 82571/2 hardware
  82 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
  83 * WTHRESH=4, so a setting of 5 gives the most efficient bus
  84 * utilization but to avoid possible Tx stalls, set it to 1
  85 */
  86#define E1000_TXDCTL_DMA_BURST_ENABLE                          \
  87        (E1000_TXDCTL_GRAN | /* set descriptor granularity */  \
  88         E1000_TXDCTL_COUNT_DESC |                             \
  89         (1u << 16) | /* wthresh must be +1 more than desired */\
  90         (1u << 8)  | /* hthresh */                             \
  91         0x1f)        /* pthresh */
  92
  93#define E1000_RXDCTL_DMA_BURST_ENABLE                          \
  94        (0x01000000 | /* set descriptor granularity */         \
  95         (4u << 16) | /* set writeback threshold    */         \
  96         (4u << 8)  | /* set prefetch threshold     */         \
  97         0x20)        /* set hthresh                */
  98
  99#define E1000_TIDV_FPD BIT(31)
 100#define E1000_RDTR_FPD BIT(31)
 101
 102enum e1000_boards {
 103        board_82571,
 104        board_82572,
 105        board_82573,
 106        board_82574,
 107        board_82583,
 108        board_80003es2lan,
 109        board_ich8lan,
 110        board_ich9lan,
 111        board_ich10lan,
 112        board_pchlan,
 113        board_pch2lan,
 114        board_pch_lpt,
 115        board_pch_spt,
 116        board_pch_cnp
 117};
 118
 119struct e1000_ps_page {
 120        struct page *page;
 121        u64 dma; /* must be u64 - written to hw */
 122};
 123
 124/* wrappers around a pointer to a socket buffer,
 125 * so a DMA handle can be stored along with the buffer
 126 */
 127struct e1000_buffer {
 128        dma_addr_t dma;
 129        struct sk_buff *skb;
 130        union {
 131                /* Tx */
 132                struct {
 133                        unsigned long time_stamp;
 134                        u16 length;
 135                        u16 next_to_watch;
 136                        unsigned int segs;
 137                        unsigned int bytecount;
 138                        u16 mapped_as_page;
 139                };
 140                /* Rx */
 141                struct {
 142                        /* arrays of page information for packet split */
 143                        struct e1000_ps_page *ps_pages;
 144                        struct page *page;
 145                };
 146        };
 147};
 148
 149struct e1000_ring {
 150        struct e1000_adapter *adapter;  /* back pointer to adapter */
 151        void *desc;                     /* pointer to ring memory  */
 152        dma_addr_t dma;                 /* phys address of ring    */
 153        unsigned int size;              /* length of ring in bytes */
 154        unsigned int count;             /* number of desc. in ring */
 155
 156        u16 next_to_use;
 157        u16 next_to_clean;
 158
 159        void __iomem *head;
 160        void __iomem *tail;
 161
 162        /* array of buffer information structs */
 163        struct e1000_buffer *buffer_info;
 164
 165        char name[IFNAMSIZ + 5];
 166        u32 ims_val;
 167        u32 itr_val;
 168        void __iomem *itr_register;
 169        int set_itr;
 170
 171        struct sk_buff *rx_skb_top;
 172};
 173
 174/* PHY register snapshot values */
 175struct e1000_phy_regs {
 176        u16 bmcr;               /* basic mode control register    */
 177        u16 bmsr;               /* basic mode status register     */
 178        u16 advertise;          /* auto-negotiation advertisement */
 179        u16 lpa;                /* link partner ability register  */
 180        u16 expansion;          /* auto-negotiation expansion reg */
 181        u16 ctrl1000;           /* 1000BASE-T control register    */
 182        u16 stat1000;           /* 1000BASE-T status register     */
 183        u16 estatus;            /* extended status register       */
 184};
 185
 186/* board specific private data structure */
 187struct e1000_adapter {
 188        struct timer_list watchdog_timer;
 189        struct timer_list phy_info_timer;
 190        struct timer_list blink_timer;
 191
 192        struct work_struct reset_task;
 193        struct work_struct watchdog_task;
 194
 195        const struct e1000_info *ei;
 196
 197        unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 198        u32 bd_number;
 199        u32 rx_buffer_len;
 200        u16 mng_vlan_id;
 201        u16 link_speed;
 202        u16 link_duplex;
 203        u16 eeprom_vers;
 204
 205        /* track device up/down/testing state */
 206        unsigned long state;
 207
 208        /* Interrupt Throttle Rate */
 209        u32 itr;
 210        u32 itr_setting;
 211        u16 tx_itr;
 212        u16 rx_itr;
 213
 214        /* Tx - one ring per active queue */
 215        struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;
 216        u32 tx_fifo_limit;
 217
 218        struct napi_struct napi;
 219
 220        unsigned int uncorr_errors;     /* uncorrectable ECC errors */
 221        unsigned int corr_errors;       /* correctable ECC errors */
 222        unsigned int restart_queue;
 223        u32 txd_cmd;
 224
 225        bool detect_tx_hung;
 226        bool tx_hang_recheck;
 227        u8 tx_timeout_factor;
 228
 229        u32 tx_int_delay;
 230        u32 tx_abs_int_delay;
 231
 232        unsigned int total_tx_bytes;
 233        unsigned int total_tx_packets;
 234        unsigned int total_rx_bytes;
 235        unsigned int total_rx_packets;
 236
 237        /* Tx stats */
 238        u64 tpt_old;
 239        u64 colc_old;
 240        u32 gotc;
 241        u64 gotc_old;
 242        u32 tx_timeout_count;
 243        u32 tx_fifo_head;
 244        u32 tx_head_addr;
 245        u32 tx_fifo_size;
 246        u32 tx_dma_failed;
 247        u32 tx_hwtstamp_timeouts;
 248        u32 tx_hwtstamp_skipped;
 249
 250        /* Rx */
 251        bool (*clean_rx)(struct e1000_ring *ring, int *work_done,
 252                         int work_to_do) ____cacheline_aligned_in_smp;
 253        void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count,
 254                             gfp_t gfp);
 255        struct e1000_ring *rx_ring;
 256
 257        u32 rx_int_delay;
 258        u32 rx_abs_int_delay;
 259
 260        /* Rx stats */
 261        u64 hw_csum_err;
 262        u64 hw_csum_good;
 263        u64 rx_hdr_split;
 264        u32 gorc;
 265        u64 gorc_old;
 266        u32 alloc_rx_buff_failed;
 267        u32 rx_dma_failed;
 268        u32 rx_hwtstamp_cleared;
 269
 270        unsigned int rx_ps_pages;
 271        u16 rx_ps_bsize0;
 272        u32 max_frame_size;
 273        u32 min_frame_size;
 274
 275        /* OS defined structs */
 276        struct net_device *netdev;
 277        struct pci_dev *pdev;
 278
 279        /* structs defined in e1000_hw.h */
 280        struct e1000_hw hw;
 281
 282        spinlock_t stats64_lock;        /* protects statistics counters */
 283        struct e1000_hw_stats stats;
 284        struct e1000_phy_info phy_info;
 285        struct e1000_phy_stats phy_stats;
 286
 287        /* Snapshot of PHY registers */
 288        struct e1000_phy_regs phy_regs;
 289
 290        struct e1000_ring test_tx_ring;
 291        struct e1000_ring test_rx_ring;
 292        u32 test_icr;
 293
 294        u32 msg_enable;
 295        unsigned int num_vectors;
 296        struct msix_entry *msix_entries;
 297        int int_mode;
 298        u32 eiac_mask;
 299
 300        u32 eeprom_wol;
 301        u32 wol;
 302        u32 pba;
 303        u32 max_hw_frame_size;
 304
 305        bool fc_autoneg;
 306
 307        unsigned int flags;
 308        unsigned int flags2;
 309        struct work_struct downshift_task;
 310        struct work_struct update_phy_task;
 311        struct work_struct print_hang_task;
 312
 313        int phy_hang_count;
 314
 315        u16 tx_ring_count;
 316        u16 rx_ring_count;
 317
 318        struct hwtstamp_config hwtstamp_config;
 319        struct delayed_work systim_overflow_work;
 320        struct sk_buff *tx_hwtstamp_skb;
 321        unsigned long tx_hwtstamp_start;
 322        struct work_struct tx_hwtstamp_work;
 323        spinlock_t systim_lock; /* protects SYSTIML/H regsters */
 324        struct cyclecounter cc;
 325        struct timecounter tc;
 326        struct ptp_clock *ptp_clock;
 327        struct ptp_clock_info ptp_clock_info;
 328        struct pm_qos_request pm_qos_req;
 329        s32 ptp_delta;
 330
 331        u16 eee_advert;
 332};
 333
 334struct e1000_info {
 335        enum e1000_mac_type     mac;
 336        unsigned int            flags;
 337        unsigned int            flags2;
 338        u32                     pba;
 339        u32                     max_hw_frame_size;
 340        s32                     (*get_variants)(struct e1000_adapter *);
 341        const struct e1000_mac_operations *mac_ops;
 342        const struct e1000_phy_operations *phy_ops;
 343        const struct e1000_nvm_operations *nvm_ops;
 344};
 345
 346s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
 347
 348/* The system time is maintained by a 64-bit counter comprised of the 32-bit
 349 * SYSTIMH and SYSTIML registers.  How the counter increments (and therefore
 350 * its resolution) is based on the contents of the TIMINCA register - it
 351 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
 352 * For the best accuracy, the incperiod should be as small as possible.  The
 353 * incvalue is scaled by a factor as large as possible (while still fitting
 354 * in bits 23:0) so that relatively small clock corrections can be made.
 355 *
 356 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
 357 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
 358 * bits to count nanoseconds leaving the rest for fractional nonseconds.
 359 */
 360#define INCVALUE_96MHZ          125
 361#define INCVALUE_SHIFT_96MHZ    17
 362#define INCPERIOD_SHIFT_96MHZ   2
 363#define INCPERIOD_96MHZ         (12 >> INCPERIOD_SHIFT_96MHZ)
 364
 365#define INCVALUE_25MHZ          40
 366#define INCVALUE_SHIFT_25MHZ    18
 367#define INCPERIOD_25MHZ         1
 368
 369#define INCVALUE_24MHZ          125
 370#define INCVALUE_SHIFT_24MHZ    14
 371#define INCPERIOD_24MHZ         3
 372
 373#define INCVALUE_38400KHZ       26
 374#define INCVALUE_SHIFT_38400KHZ 19
 375#define INCPERIOD_38400KHZ      1
 376
 377/* Another drawback of scaling the incvalue by a large factor is the
 378 * 64-bit SYSTIM register overflows more quickly.  This is dealt with
 379 * by simply reading the clock before it overflows.
 380 *
 381 * Clock        ns bits Overflows after
 382 * ~~~~~~       ~~~~~~~ ~~~~~~~~~~~~~~~
 383 * 96MHz        47-bit  2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
 384 * 25MHz        46-bit  2^46 / 10^9 / 3600 = 19.55 hours
 385 */
 386#define E1000_SYSTIM_OVERFLOW_PERIOD    (HZ * 60 * 60 * 4)
 387#define E1000_MAX_82574_SYSTIM_REREADS  50
 388#define E1000_82574_SYSTIM_EPSILON      (1ULL << 35ULL)
 389
 390/* hardware capability, feature, and workaround flags */
 391#define FLAG_HAS_AMT                      BIT(0)
 392#define FLAG_HAS_FLASH                    BIT(1)
 393#define FLAG_HAS_HW_VLAN_FILTER           BIT(2)
 394#define FLAG_HAS_WOL                      BIT(3)
 395/* reserved BIT(4) */
 396#define FLAG_HAS_CTRLEXT_ON_LOAD          BIT(5)
 397#define FLAG_HAS_SWSM_ON_LOAD             BIT(6)
 398#define FLAG_HAS_JUMBO_FRAMES             BIT(7)
 399#define FLAG_READ_ONLY_NVM                BIT(8)
 400#define FLAG_IS_ICH                       BIT(9)
 401#define FLAG_HAS_MSIX                     BIT(10)
 402#define FLAG_HAS_SMART_POWER_DOWN         BIT(11)
 403#define FLAG_IS_QUAD_PORT_A               BIT(12)
 404#define FLAG_IS_QUAD_PORT                 BIT(13)
 405#define FLAG_HAS_HW_TIMESTAMP             BIT(14)
 406#define FLAG_APME_IN_WUC                  BIT(15)
 407#define FLAG_APME_IN_CTRL3                BIT(16)
 408#define FLAG_APME_CHECK_PORT_B            BIT(17)
 409#define FLAG_DISABLE_FC_PAUSE_TIME        BIT(18)
 410#define FLAG_NO_WAKE_UCAST                BIT(19)
 411#define FLAG_MNG_PT_ENABLED               BIT(20)
 412#define FLAG_RESET_OVERWRITES_LAA         BIT(21)
 413#define FLAG_TARC_SPEED_MODE_BIT          BIT(22)
 414#define FLAG_TARC_SET_BIT_ZERO            BIT(23)
 415#define FLAG_RX_NEEDS_RESTART             BIT(24)
 416#define FLAG_LSC_GIG_SPEED_DROP           BIT(25)
 417#define FLAG_SMART_POWER_DOWN             BIT(26)
 418#define FLAG_MSI_ENABLED                  BIT(27)
 419/* reserved BIT(28) */
 420#define FLAG_TSO_FORCE                    BIT(29)
 421#define FLAG_RESTART_NOW                  BIT(30)
 422#define FLAG_MSI_TEST_FAILED              BIT(31)
 423
 424#define FLAG2_CRC_STRIPPING               BIT(0)
 425#define FLAG2_HAS_PHY_WAKEUP              BIT(1)
 426#define FLAG2_IS_DISCARDING               BIT(2)
 427#define FLAG2_DISABLE_ASPM_L1             BIT(3)
 428#define FLAG2_HAS_PHY_STATS               BIT(4)
 429#define FLAG2_HAS_EEE                     BIT(5)
 430#define FLAG2_DMA_BURST                   BIT(6)
 431#define FLAG2_DISABLE_ASPM_L0S            BIT(7)
 432#define FLAG2_DISABLE_AIM                 BIT(8)
 433#define FLAG2_CHECK_PHY_HANG              BIT(9)
 434#define FLAG2_NO_DISABLE_RX               BIT(10)
 435#define FLAG2_PCIM2PCI_ARBITER_WA         BIT(11)
 436#define FLAG2_DFLT_CRC_STRIPPING          BIT(12)
 437#define FLAG2_CHECK_RX_HWTSTAMP           BIT(13)
 438#define FLAG2_CHECK_SYSTIM_OVERFLOW       BIT(14)
 439#define FLAG2_ENABLE_S0IX_FLOWS           BIT(15)
 440
 441#define E1000_RX_DESC_PS(R, i)      \
 442        (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
 443#define E1000_RX_DESC_EXT(R, i)     \
 444        (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
 445#define E1000_GET_DESC(R, i, type)      (&(((struct type *)((R).desc))[i]))
 446#define E1000_TX_DESC(R, i)             E1000_GET_DESC(R, i, e1000_tx_desc)
 447#define E1000_CONTEXT_DESC(R, i)        E1000_GET_DESC(R, i, e1000_context_desc)
 448
 449enum e1000_state_t {
 450        __E1000_TESTING,
 451        __E1000_RESETTING,
 452        __E1000_ACCESS_SHARED_RESOURCE,
 453        __E1000_DOWN
 454};
 455
 456enum latency_range {
 457        lowest_latency = 0,
 458        low_latency = 1,
 459        bulk_latency = 2,
 460        latency_invalid = 255
 461};
 462
 463extern char e1000e_driver_name[];
 464
 465void e1000e_check_options(struct e1000_adapter *adapter);
 466void e1000e_set_ethtool_ops(struct net_device *netdev);
 467
 468int e1000e_open(struct net_device *netdev);
 469int e1000e_close(struct net_device *netdev);
 470void e1000e_up(struct e1000_adapter *adapter);
 471void e1000e_down(struct e1000_adapter *adapter, bool reset);
 472void e1000e_reinit_locked(struct e1000_adapter *adapter);
 473void e1000e_reset(struct e1000_adapter *adapter);
 474void e1000e_power_up_phy(struct e1000_adapter *adapter);
 475int e1000e_setup_rx_resources(struct e1000_ring *ring);
 476int e1000e_setup_tx_resources(struct e1000_ring *ring);
 477void e1000e_free_rx_resources(struct e1000_ring *ring);
 478void e1000e_free_tx_resources(struct e1000_ring *ring);
 479void e1000e_get_stats64(struct net_device *netdev,
 480                        struct rtnl_link_stats64 *stats);
 481void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
 482void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
 483void e1000e_get_hw_control(struct e1000_adapter *adapter);
 484void e1000e_release_hw_control(struct e1000_adapter *adapter);
 485void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
 486
 487extern unsigned int copybreak;
 488
 489extern const struct e1000_info e1000_82571_info;
 490extern const struct e1000_info e1000_82572_info;
 491extern const struct e1000_info e1000_82573_info;
 492extern const struct e1000_info e1000_82574_info;
 493extern const struct e1000_info e1000_82583_info;
 494extern const struct e1000_info e1000_ich8_info;
 495extern const struct e1000_info e1000_ich9_info;
 496extern const struct e1000_info e1000_ich10_info;
 497extern const struct e1000_info e1000_pch_info;
 498extern const struct e1000_info e1000_pch2_info;
 499extern const struct e1000_info e1000_pch_lpt_info;
 500extern const struct e1000_info e1000_pch_spt_info;
 501extern const struct e1000_info e1000_pch_cnp_info;
 502extern const struct e1000_info e1000_es2_info;
 503
 504void e1000e_ptp_init(struct e1000_adapter *adapter);
 505void e1000e_ptp_remove(struct e1000_adapter *adapter);
 506
 507u64 e1000e_read_systim(struct e1000_adapter *adapter,
 508                       struct ptp_system_timestamp *sts);
 509
 510static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
 511{
 512        return hw->phy.ops.reset(hw);
 513}
 514
 515static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
 516{
 517        return hw->phy.ops.read_reg(hw, offset, data);
 518}
 519
 520static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
 521{
 522        return hw->phy.ops.read_reg_locked(hw, offset, data);
 523}
 524
 525static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
 526{
 527        return hw->phy.ops.write_reg(hw, offset, data);
 528}
 529
 530static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
 531{
 532        return hw->phy.ops.write_reg_locked(hw, offset, data);
 533}
 534
 535void e1000e_reload_nvm_generic(struct e1000_hw *hw);
 536
 537static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
 538{
 539        if (hw->mac.ops.read_mac_addr)
 540                return hw->mac.ops.read_mac_addr(hw);
 541
 542        return e1000_read_mac_addr_generic(hw);
 543}
 544
 545static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
 546{
 547        return hw->nvm.ops.validate(hw);
 548}
 549
 550static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
 551{
 552        return hw->nvm.ops.update(hw);
 553}
 554
 555static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words,
 556                                 u16 *data)
 557{
 558        return hw->nvm.ops.read(hw, offset, words, data);
 559}
 560
 561static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
 562                                  u16 *data)
 563{
 564        return hw->nvm.ops.write(hw, offset, words, data);
 565}
 566
 567static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
 568{
 569        return hw->phy.ops.get_info(hw);
 570}
 571
 572static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
 573{
 574        return readl(hw->hw_addr + reg);
 575}
 576
 577#define er32(reg)       __er32(hw, E1000_##reg)
 578
 579void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val);
 580
 581#define ew32(reg, val)  __ew32(hw, E1000_##reg, (val))
 582
 583#define e1e_flush()     er32(STATUS)
 584
 585#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
 586        (__ew32((a), (reg + ((offset) << 2)), (value)))
 587
 588#define E1000_READ_REG_ARRAY(a, reg, offset) \
 589        (readl((a)->hw_addr + reg + ((offset) << 2)))
 590
 591#endif /* _E1000_H_ */
 592