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11#ifndef MBOX_H
12#define MBOX_H
13
14#include <linux/etherdevice.h>
15#include <linux/sizes.h>
16
17#include "rvu_struct.h"
18#include "common.h"
19
20#define MBOX_SIZE SZ_64K
21
22
23#define MBOX_DOWN_RX_START 0
24#define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
25#define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
26#define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
27
28#define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
29#define MBOX_UP_RX_SIZE SZ_1K
30#define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
31#define MBOX_UP_TX_SIZE SZ_1K
32
33#if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
34# error "incorrect mailbox area sizes"
35#endif
36
37#define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
38
39#define MBOX_RSP_TIMEOUT 2000
40
41#define MBOX_MSG_ALIGN 16
42
43
44#define MBOX_DIR_AFPF 0
45#define MBOX_DIR_PFAF 1
46#define MBOX_DIR_PFVF 2
47#define MBOX_DIR_VFPF 3
48#define MBOX_DIR_AFPF_UP 4
49#define MBOX_DIR_PFAF_UP 5
50#define MBOX_DIR_PFVF_UP 6
51#define MBOX_DIR_VFPF_UP 7
52
53struct otx2_mbox_dev {
54 void *mbase;
55 spinlock_t mbox_lock;
56 u16 msg_size;
57 u16 rsp_size;
58 u16 num_msgs;
59 u16 msgs_acked;
60};
61
62struct otx2_mbox {
63 struct pci_dev *pdev;
64 void *hwbase;
65 void *reg_base;
66 u64 trigger;
67 u16 tr_shift;
68 u64 rx_start;
69 u64 tx_start;
70 u16 rx_size;
71 u16 tx_size;
72 u16 ndevs;
73 struct otx2_mbox_dev *dev;
74};
75
76
77struct mbox_hdr {
78 u64 msg_size;
79 u16 num_msgs;
80};
81
82
83struct mbox_msghdr {
84 u16 pcifunc;
85 u16 id;
86#define OTX2_MBOX_REQ_SIG (0xdead)
87#define OTX2_MBOX_RSP_SIG (0xbeef)
88 u16 sig;
89#define OTX2_MBOX_VERSION (0x0007)
90 u16 ver;
91 u16 next_msgoff;
92 int rc;
93};
94
95void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
96void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
97void otx2_mbox_destroy(struct otx2_mbox *mbox);
98int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
99 struct pci_dev *pdev, void __force *reg_base,
100 int direction, int ndevs);
101void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
102int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
103int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
104struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
105 int size, int size_rsp);
106struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
107 struct mbox_msghdr *msg);
108int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
109int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
110 u16 pcifunc, u16 id);
111bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
112const char *otx2_mbox_id2name(u16 id);
113static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
114 int devid, int size)
115{
116 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
117}
118
119
120#define MBOX_MSG_MASK 0xFFFF
121#define MBOX_MSG_INVALID 0xFFFE
122#define MBOX_MSG_MAX 0xFFFF
123
124#define MBOX_MESSAGES \
125 \
126M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
127M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
128M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
129M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
130M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
131M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
132M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
133 \
134M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
135M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
136M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
137M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
138 cgx_mac_addr_set_or_get) \
139M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
140 cgx_mac_addr_set_or_get) \
141M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
142M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
143M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
144M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
145M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
146M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
147M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
148M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
149M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
150M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
151 cgx_pause_frm_cfg) \
152 \
153M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \
154 npa_lf_alloc_req, npa_lf_alloc_rsp) \
155M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
156M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
157M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
158 \
159 \
160 \
161M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
162 msg_rsp) \
163M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
164M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
165 cpt_rd_wr_reg_msg) \
166 \
167M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
168 npc_mcam_alloc_entry_rsp) \
169M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
170 npc_mcam_free_entry_req, msg_rsp) \
171M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
172 npc_mcam_write_entry_req, msg_rsp) \
173M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
174 npc_mcam_ena_dis_entry_req, msg_rsp) \
175M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
176 npc_mcam_ena_dis_entry_req, msg_rsp) \
177M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
178 npc_mcam_shift_entry_rsp) \
179M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
180 npc_mcam_alloc_counter_req, \
181 npc_mcam_alloc_counter_rsp) \
182M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
183 npc_mcam_oper_counter_req, msg_rsp) \
184M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
185 npc_mcam_unmap_counter_req, msg_rsp) \
186M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
187 npc_mcam_oper_counter_req, msg_rsp) \
188M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
189 npc_mcam_oper_counter_req, \
190 npc_mcam_oper_counter_rsp) \
191M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
192 npc_mcam_alloc_and_write_entry_req, \
193 npc_mcam_alloc_and_write_entry_rsp) \
194M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
195 msg_req, npc_get_kex_cfg_rsp) \
196M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
197 npc_install_flow_req, npc_install_flow_rsp) \
198M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
199 npc_delete_flow_req, msg_rsp) \
200M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
201 npc_mcam_read_entry_req, \
202 npc_mcam_read_entry_rsp) \
203M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \
204 msg_req, npc_mcam_read_base_rule_rsp) \
205 \
206M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
207 nix_lf_alloc_req, nix_lf_alloc_rsp) \
208M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
209M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
210M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
211 hwctx_disable_req, msg_rsp) \
212M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
213 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
214M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
215M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \
216M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
217M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \
218 nix_vtag_config_rsp) \
219M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
220 nix_rss_flowkey_cfg, \
221 nix_rss_flowkey_cfg_rsp) \
222M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
223M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
224M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
225M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
226M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
227M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
228 nix_mark_format_cfg, \
229 nix_mark_format_cfg_rsp) \
230M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
231M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
232 nix_lso_format_cfg, \
233 nix_lso_format_cfg_rsp) \
234M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
235M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
236M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
237 nix_bp_cfg_rsp) \
238M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
239M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
240
241
242#define MBOX_UP_CGX_MESSAGES \
243M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
244
245enum {
246#define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
247MBOX_MESSAGES
248MBOX_UP_CGX_MESSAGES
249#undef M
250};
251
252
253
254#define RVU_DEFAULT_PF_FUNC 0xFFFF
255
256
257
258
259struct msg_req {
260 struct mbox_msghdr hdr;
261};
262
263
264
265
266struct msg_rsp {
267 struct mbox_msghdr hdr;
268};
269
270
271
272
273enum rvu_af_status {
274 RVU_INVALID_VF_ID = -256,
275};
276
277struct ready_msg_rsp {
278 struct mbox_msghdr hdr;
279 u16 sclk_freq;
280 u16 rclk_freq;
281};
282
283
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298
299
300struct rsrc_attach {
301 struct mbox_msghdr hdr;
302 u8 modify:1;
303 u8 npalf:1;
304 u8 nixlf:1;
305 u16 sso;
306 u16 ssow;
307 u16 timlfs;
308 u16 cptlfs;
309 int cpt_blkaddr;
310};
311
312
313
314
315
316
317struct rsrc_detach {
318 struct mbox_msghdr hdr;
319 u8 partial:1;
320 u8 npalf:1;
321 u8 nixlf:1;
322 u8 sso:1;
323 u8 ssow:1;
324 u8 timlfs:1;
325 u8 cptlfs:1;
326};
327
328#define MSIX_VECTOR_INVALID 0xFFFF
329#define MAX_RVU_BLKLF_CNT 256
330
331struct msix_offset_rsp {
332 struct mbox_msghdr hdr;
333 u16 npa_msixoff;
334 u16 nix_msixoff;
335 u8 sso;
336 u8 ssow;
337 u8 timlfs;
338 u8 cptlfs;
339 u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
340 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
341 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
342 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
343 u8 cpt1_lfs;
344 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
345};
346
347struct get_hw_cap_rsp {
348 struct mbox_msghdr hdr;
349 u8 nix_fixed_txschq_mapping;
350 u8 nix_shaping;
351};
352
353
354
355struct cgx_stats_rsp {
356 struct mbox_msghdr hdr;
357#define CGX_RX_STATS_COUNT 13
358#define CGX_TX_STATS_COUNT 18
359 u64 rx_stats[CGX_RX_STATS_COUNT];
360 u64 tx_stats[CGX_TX_STATS_COUNT];
361};
362
363
364
365
366struct cgx_mac_addr_set_or_get {
367 struct mbox_msghdr hdr;
368 u8 mac_addr[ETH_ALEN];
369};
370
371struct cgx_link_user_info {
372 uint64_t link_up:1;
373 uint64_t full_duplex:1;
374 uint64_t lmac_type_id:4;
375 uint64_t speed:20;
376#define LMACTYPE_STR_LEN 16
377 char lmac_type[LMACTYPE_STR_LEN];
378};
379
380struct cgx_link_info_msg {
381 struct mbox_msghdr hdr;
382 struct cgx_link_user_info link_info;
383};
384
385struct cgx_pause_frm_cfg {
386 struct mbox_msghdr hdr;
387 u8 set;
388
389
390 u8 rx_pause;
391 u8 tx_pause;
392};
393
394
395
396
397
398
399enum npa_af_status {
400 NPA_AF_ERR_PARAM = -301,
401 NPA_AF_ERR_AQ_FULL = -302,
402 NPA_AF_ERR_AQ_ENQUEUE = -303,
403 NPA_AF_ERR_AF_LF_INVALID = -304,
404 NPA_AF_ERR_AF_LF_ALLOC = -305,
405 NPA_AF_ERR_LF_RESET = -306,
406};
407
408
409struct npa_lf_alloc_req {
410 struct mbox_msghdr hdr;
411 int node;
412 int aura_sz;
413 u32 nr_pools;
414 u64 way_mask;
415};
416
417struct npa_lf_alloc_rsp {
418 struct mbox_msghdr hdr;
419 u32 stack_pg_ptrs;
420 u32 stack_pg_bytes;
421 u16 qints;
422};
423
424
425struct npa_aq_enq_req {
426 struct mbox_msghdr hdr;
427 u32 aura_id;
428 u8 ctype;
429 u8 op;
430 union {
431
432
433
434
435 struct npa_aura_s aura;
436
437 struct npa_pool_s pool;
438 };
439
440 union {
441
442 struct npa_aura_s aura_mask;
443
444 struct npa_pool_s pool_mask;
445 };
446};
447
448struct npa_aq_enq_rsp {
449 struct mbox_msghdr hdr;
450 union {
451
452 struct npa_aura_s aura;
453
454 struct npa_pool_s pool;
455 };
456};
457
458
459struct hwctx_disable_req {
460 struct mbox_msghdr hdr;
461 u8 ctype;
462};
463
464
465
466
467
468
469enum nix_af_status {
470 NIX_AF_ERR_PARAM = -401,
471 NIX_AF_ERR_AQ_FULL = -402,
472 NIX_AF_ERR_AQ_ENQUEUE = -403,
473 NIX_AF_ERR_AF_LF_INVALID = -404,
474 NIX_AF_ERR_AF_LF_ALLOC = -405,
475 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
476 NIX_AF_ERR_TLX_INVALID = -407,
477 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
478 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
479 NIX_AF_ERR_FRS_INVALID = -410,
480 NIX_AF_ERR_RX_LINK_INVALID = -411,
481 NIX_AF_INVAL_TXSCHQ_CFG = -412,
482 NIX_AF_SMQ_FLUSH_FAILED = -413,
483 NIX_AF_ERR_LF_RESET = -414,
484 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
485 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
486 NIX_AF_ERR_MARK_CFG_FAIL = -417,
487 NIX_AF_ERR_LSO_CFG_FAIL = -418,
488 NIX_AF_INVAL_NPA_PF_FUNC = -419,
489 NIX_AF_INVAL_SSO_PF_FUNC = -420,
490 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
491 NIX_AF_ERR_RX_VTAG_INUSE = -422,
492};
493
494
495enum nix_rx_vtag0_type {
496 NIX_AF_LFX_RX_VTAG_TYPE0,
497 NIX_AF_LFX_RX_VTAG_TYPE1,
498 NIX_AF_LFX_RX_VTAG_TYPE2,
499 NIX_AF_LFX_RX_VTAG_TYPE3,
500 NIX_AF_LFX_RX_VTAG_TYPE4,
501 NIX_AF_LFX_RX_VTAG_TYPE5,
502 NIX_AF_LFX_RX_VTAG_TYPE6,
503 NIX_AF_LFX_RX_VTAG_TYPE7,
504};
505
506
507struct nix_lf_alloc_req {
508 struct mbox_msghdr hdr;
509 int node;
510 u32 rq_cnt;
511 u32 sq_cnt;
512 u32 cq_cnt;
513 u8 xqe_sz;
514 u16 rss_sz;
515 u8 rss_grps;
516 u16 npa_func;
517 u16 sso_func;
518 u64 rx_cfg;
519 u64 way_mask;
520};
521
522struct nix_lf_alloc_rsp {
523 struct mbox_msghdr hdr;
524 u16 sqb_size;
525 u16 rx_chan_base;
526 u16 tx_chan_base;
527 u8 rx_chan_cnt;
528 u8 tx_chan_cnt;
529 u8 lso_tsov4_idx;
530 u8 lso_tsov6_idx;
531 u8 mac_addr[ETH_ALEN];
532 u8 lf_rx_stats;
533 u8 lf_tx_stats;
534 u16 cints;
535 u16 qints;
536 u8 cgx_links;
537 u8 lbk_links;
538 u8 sdp_links;
539};
540
541struct nix_lf_free_req {
542 struct mbox_msghdr hdr;
543#define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
544#define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
545 u64 flags;
546};
547
548
549struct nix_aq_enq_req {
550 struct mbox_msghdr hdr;
551 u32 qidx;
552 u8 ctype;
553 u8 op;
554 union {
555 struct nix_rq_ctx_s rq;
556 struct nix_sq_ctx_s sq;
557 struct nix_cq_ctx_s cq;
558 struct nix_rsse_s rss;
559 struct nix_rx_mce_s mce;
560 };
561 union {
562 struct nix_rq_ctx_s rq_mask;
563 struct nix_sq_ctx_s sq_mask;
564 struct nix_cq_ctx_s cq_mask;
565 struct nix_rsse_s rss_mask;
566 struct nix_rx_mce_s mce_mask;
567 };
568};
569
570struct nix_aq_enq_rsp {
571 struct mbox_msghdr hdr;
572 union {
573 struct nix_rq_ctx_s rq;
574 struct nix_sq_ctx_s sq;
575 struct nix_cq_ctx_s cq;
576 struct nix_rsse_s rss;
577 struct nix_rx_mce_s mce;
578 };
579};
580
581
582
583#define MAX_TXSCHQ_PER_FUNC 128
584
585struct nix_txsch_alloc_req {
586 struct mbox_msghdr hdr;
587
588 u16 schq_contig[NIX_TXSCH_LVL_CNT];
589 u16 schq[NIX_TXSCH_LVL_CNT];
590};
591
592struct nix_txsch_alloc_rsp {
593 struct mbox_msghdr hdr;
594
595 u16 schq_contig[NIX_TXSCH_LVL_CNT];
596 u16 schq[NIX_TXSCH_LVL_CNT];
597
598 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
599 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
600 u8 aggr_level;
601 u8 aggr_lvl_rr_prio;
602 u8 link_cfg_lvl;
603};
604
605struct nix_txsch_free_req {
606 struct mbox_msghdr hdr;
607#define TXSCHQ_FREE_ALL BIT_ULL(0)
608 u16 flags;
609
610 u16 schq_lvl;
611
612 u16 schq;
613};
614
615struct nix_txschq_config {
616 struct mbox_msghdr hdr;
617 u8 lvl;
618#define TXSCHQ_IDX_SHIFT 16
619#define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
620#define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
621 u8 num_regs;
622#define MAX_REGS_PER_MBOX_MSG 20
623 u64 reg[MAX_REGS_PER_MBOX_MSG];
624 u64 regval[MAX_REGS_PER_MBOX_MSG];
625};
626
627struct nix_vtag_config {
628 struct mbox_msghdr hdr;
629
630 u8 vtag_size;
631
632
633
634 u8 cfg_type;
635 union {
636
637 struct {
638 u64 vtag0;
639 u64 vtag1;
640
641
642
643
644
645 u8 cfg_vtag0 :1;
646
647 u8 cfg_vtag1 :1;
648
649
650
651
652
653
654
655
656
657
658 int vtag0_idx;
659 int vtag1_idx;
660
661
662
663
664
665
666
667 u8 free_vtag0 :1;
668
669
670
671 u8 free_vtag1 :1;
672 } tx;
673
674
675 struct {
676
677 u8 vtag_type;
678
679 u8 strip_vtag :1;
680
681 u8 capture_vtag :1;
682 } rx;
683 };
684};
685
686struct nix_vtag_config_rsp {
687 struct mbox_msghdr hdr;
688 int vtag0_idx;
689 int vtag1_idx;
690
691
692
693
694
695};
696
697struct nix_rss_flowkey_cfg {
698 struct mbox_msghdr hdr;
699 int mcam_index;
700#define NIX_FLOW_KEY_TYPE_PORT BIT(0)
701#define NIX_FLOW_KEY_TYPE_IPV4 BIT(1)
702#define NIX_FLOW_KEY_TYPE_IPV6 BIT(2)
703#define NIX_FLOW_KEY_TYPE_TCP BIT(3)
704#define NIX_FLOW_KEY_TYPE_UDP BIT(4)
705#define NIX_FLOW_KEY_TYPE_SCTP BIT(5)
706#define NIX_FLOW_KEY_TYPE_NVGRE BIT(6)
707#define NIX_FLOW_KEY_TYPE_VXLAN BIT(7)
708#define NIX_FLOW_KEY_TYPE_GENEVE BIT(8)
709#define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
710#define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
711#define NIX_FLOW_KEY_TYPE_GTPU BIT(11)
712#define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
713#define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
714#define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14)
715#define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15)
716#define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16)
717#define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
718#define NIX_FLOW_KEY_TYPE_VLAN BIT(20)
719#define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21)
720 u32 flowkey_cfg;
721 u8 group;
722};
723
724struct nix_rss_flowkey_cfg_rsp {
725 struct mbox_msghdr hdr;
726 u8 alg_idx;
727};
728
729struct nix_set_mac_addr {
730 struct mbox_msghdr hdr;
731 u8 mac_addr[ETH_ALEN];
732};
733
734struct nix_get_mac_addr_rsp {
735 struct mbox_msghdr hdr;
736 u8 mac_addr[ETH_ALEN];
737};
738
739struct nix_mark_format_cfg {
740 struct mbox_msghdr hdr;
741 u8 offset;
742 u8 y_mask;
743 u8 y_val;
744 u8 r_mask;
745 u8 r_val;
746};
747
748struct nix_mark_format_cfg_rsp {
749 struct mbox_msghdr hdr;
750 u8 mark_format_idx;
751};
752
753struct nix_rx_mode {
754 struct mbox_msghdr hdr;
755#define NIX_RX_MODE_UCAST BIT(0)
756#define NIX_RX_MODE_PROMISC BIT(1)
757#define NIX_RX_MODE_ALLMULTI BIT(2)
758 u16 mode;
759};
760
761struct nix_rx_cfg {
762 struct mbox_msghdr hdr;
763#define NIX_RX_OL3_VERIFY BIT(0)
764#define NIX_RX_OL4_VERIFY BIT(1)
765 u8 len_verify;
766#define NIX_RX_CSUM_OL4_VERIFY BIT(0)
767 u8 csum_verify;
768};
769
770struct nix_frs_cfg {
771 struct mbox_msghdr hdr;
772 u8 update_smq;
773 u8 update_minlen;
774 u8 sdp_link;
775 u16 maxlen;
776 u16 minlen;
777};
778
779struct nix_lso_format_cfg {
780 struct mbox_msghdr hdr;
781 u64 field_mask;
782#define NIX_LSO_FIELD_MAX 8
783 u64 fields[NIX_LSO_FIELD_MAX];
784};
785
786struct nix_lso_format_cfg_rsp {
787 struct mbox_msghdr hdr;
788 u8 lso_format_idx;
789};
790
791struct nix_bp_cfg_req {
792 struct mbox_msghdr hdr;
793 u16 chan_base;
794 u8 chan_cnt;
795 u8 bpid_per_chan;
796
797
798};
799
800
801
802
803#define NIX_MAX_BPID_CHAN 64
804struct nix_bp_cfg_rsp {
805 struct mbox_msghdr hdr;
806 u16 chan_bpid[NIX_MAX_BPID_CHAN];
807 u8 chan_cnt;
808};
809
810
811
812#define NPC_MCAM_ENTRY_INVALID 0xFFFF
813#define NPC_MCAM_INVALID_MAP 0xFFFF
814
815
816
817
818enum npc_af_status {
819 NPC_MCAM_INVALID_REQ = -701,
820 NPC_MCAM_ALLOC_DENIED = -702,
821 NPC_MCAM_ALLOC_FAILED = -703,
822 NPC_MCAM_PERM_DENIED = -704,
823};
824
825struct npc_mcam_alloc_entry_req {
826 struct mbox_msghdr hdr;
827#define NPC_MAX_NONCONTIG_ENTRIES 256
828 u8 contig;
829#define NPC_MCAM_ANY_PRIO 0
830#define NPC_MCAM_LOWER_PRIO 1
831#define NPC_MCAM_HIGHER_PRIO 2
832 u8 priority;
833 u16 ref_entry;
834 u16 count;
835};
836
837struct npc_mcam_alloc_entry_rsp {
838 struct mbox_msghdr hdr;
839 u16 entry;
840
841
842 u16 count;
843 u16 free_count;
844 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
845};
846
847struct npc_mcam_free_entry_req {
848 struct mbox_msghdr hdr;
849 u16 entry;
850 u8 all;
851};
852
853struct mcam_entry {
854#define NPC_MAX_KWS_IN_KEY 7
855 u64 kw[NPC_MAX_KWS_IN_KEY];
856 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
857 u64 action;
858 u64 vtag_action;
859};
860
861struct npc_mcam_write_entry_req {
862 struct mbox_msghdr hdr;
863 struct mcam_entry entry_data;
864 u16 entry;
865 u16 cntr;
866 u8 intf;
867 u8 enable_entry;
868 u8 set_cntr;
869};
870
871
872struct npc_mcam_ena_dis_entry_req {
873 struct mbox_msghdr hdr;
874 u16 entry;
875};
876
877struct npc_mcam_shift_entry_req {
878 struct mbox_msghdr hdr;
879#define NPC_MCAM_MAX_SHIFTS 64
880 u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
881 u16 new_entry[NPC_MCAM_MAX_SHIFTS];
882 u16 shift_count;
883};
884
885struct npc_mcam_shift_entry_rsp {
886 struct mbox_msghdr hdr;
887 u16 failed_entry_idx;
888};
889
890struct npc_mcam_alloc_counter_req {
891 struct mbox_msghdr hdr;
892 u8 contig;
893#define NPC_MAX_NONCONTIG_COUNTERS 64
894 u16 count;
895};
896
897struct npc_mcam_alloc_counter_rsp {
898 struct mbox_msghdr hdr;
899 u16 cntr;
900
901
902 u16 count;
903 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
904};
905
906struct npc_mcam_oper_counter_req {
907 struct mbox_msghdr hdr;
908 u16 cntr;
909};
910
911struct npc_mcam_oper_counter_rsp {
912 struct mbox_msghdr hdr;
913 u64 stat;
914};
915
916struct npc_mcam_unmap_counter_req {
917 struct mbox_msghdr hdr;
918 u16 cntr;
919 u16 entry;
920 u8 all;
921};
922
923struct npc_mcam_alloc_and_write_entry_req {
924 struct mbox_msghdr hdr;
925 struct mcam_entry entry_data;
926 u16 ref_entry;
927 u8 priority;
928 u8 intf;
929 u8 enable_entry;
930 u8 alloc_cntr;
931};
932
933struct npc_mcam_alloc_and_write_entry_rsp {
934 struct mbox_msghdr hdr;
935 u16 entry;
936 u16 cntr;
937};
938
939struct npc_get_kex_cfg_rsp {
940 struct mbox_msghdr hdr;
941 u64 rx_keyx_cfg;
942 u64 tx_keyx_cfg;
943#define NPC_MAX_INTF 2
944#define NPC_MAX_LID 8
945#define NPC_MAX_LT 16
946#define NPC_MAX_LD 2
947#define NPC_MAX_LFL 16
948
949 u64 kex_ld_flags[NPC_MAX_LD];
950
951 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
952
953 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
954#define MKEX_NAME_LEN 128
955 u8 mkex_pfl_name[MKEX_NAME_LEN];
956};
957
958struct flow_msg {
959 unsigned char dmac[6];
960 unsigned char smac[6];
961 __be16 etype;
962 __be16 vlan_etype;
963 __be16 vlan_tci;
964 union {
965 __be32 ip4src;
966 __be32 ip6src[4];
967 };
968 union {
969 __be32 ip4dst;
970 __be32 ip6dst[4];
971 };
972 u8 tos;
973 u8 ip_ver;
974 u8 ip_proto;
975 u8 tc;
976 __be16 sport;
977 __be16 dport;
978};
979
980struct npc_install_flow_req {
981 struct mbox_msghdr hdr;
982 struct flow_msg packet;
983 struct flow_msg mask;
984 u64 features;
985 u16 entry;
986 u16 channel;
987 u8 intf;
988 u8 set_cntr;
989 u8 default_rule;
990 u8 append;
991 u16 vf;
992
993 u32 index;
994 u16 match_id;
995 u8 flow_key_alg;
996 u8 op;
997
998 u8 vtag0_type;
999 u8 vtag0_valid;
1000 u8 vtag1_type;
1001 u8 vtag1_valid;
1002
1003 u16 vtag0_def;
1004 u8 vtag0_op;
1005 u16 vtag1_def;
1006 u8 vtag1_op;
1007};
1008
1009struct npc_install_flow_rsp {
1010 struct mbox_msghdr hdr;
1011 int counter;
1012};
1013
1014struct npc_delete_flow_req {
1015 struct mbox_msghdr hdr;
1016 u16 entry;
1017 u16 start;
1018 u16 end;
1019 u8 all;
1020};
1021
1022struct npc_mcam_read_entry_req {
1023 struct mbox_msghdr hdr;
1024 u16 entry;
1025};
1026
1027struct npc_mcam_read_entry_rsp {
1028 struct mbox_msghdr hdr;
1029 struct mcam_entry entry_data;
1030 u8 intf;
1031 u8 enable;
1032};
1033
1034struct npc_mcam_read_base_rule_rsp {
1035 struct mbox_msghdr hdr;
1036 struct mcam_entry entry;
1037};
1038
1039enum ptp_op {
1040 PTP_OP_ADJFINE = 0,
1041 PTP_OP_GET_CLOCK = 1,
1042};
1043
1044struct ptp_req {
1045 struct mbox_msghdr hdr;
1046 u8 op;
1047 s64 scaled_ppm;
1048};
1049
1050struct ptp_rsp {
1051 struct mbox_msghdr hdr;
1052 u64 clk;
1053};
1054
1055
1056
1057
1058enum cpt_af_status {
1059 CPT_AF_ERR_PARAM = -901,
1060 CPT_AF_ERR_GRP_INVALID = -902,
1061 CPT_AF_ERR_LF_INVALID = -903,
1062 CPT_AF_ERR_ACCESS_DENIED = -904,
1063 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1064 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906
1065};
1066
1067
1068struct cpt_rd_wr_reg_msg {
1069 struct mbox_msghdr hdr;
1070 u64 reg_offset;
1071 u64 *ret_val;
1072 u64 val;
1073 u8 is_write;
1074};
1075
1076struct cpt_lf_alloc_req_msg {
1077 struct mbox_msghdr hdr;
1078 u16 nix_pf_func;
1079 u16 sso_pf_func;
1080 u16 eng_grpmsk;
1081};
1082
1083#endif
1084