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11#ifndef RVU_REG_H
12#define RVU_REG_H
13
14
15#define RVU_AF_MSIXTR_BASE (0x10)
16#define RVU_AF_ECO (0x20)
17#define RVU_AF_BLK_RST (0x30)
18#define RVU_AF_PF_BAR4_ADDR (0x40)
19#define RVU_AF_RAS (0x100)
20#define RVU_AF_RAS_W1S (0x108)
21#define RVU_AF_RAS_ENA_W1S (0x110)
22#define RVU_AF_RAS_ENA_W1C (0x118)
23#define RVU_AF_GEN_INT (0x120)
24#define RVU_AF_GEN_INT_W1S (0x128)
25#define RVU_AF_GEN_INT_ENA_W1S (0x130)
26#define RVU_AF_GEN_INT_ENA_W1C (0x138)
27#define RVU_AF_AFPF_MBOX0 (0x02000)
28#define RVU_AF_AFPF_MBOX1 (0x02008)
29#define RVU_AF_AFPFX_MBOXX(a, b) (0x2000 | (a) << 4 | (b) << 3)
30#define RVU_AF_PFME_STATUS (0x2800)
31#define RVU_AF_PFTRPEND (0x2810)
32#define RVU_AF_PFTRPEND_W1S (0x2820)
33#define RVU_AF_PF_RST (0x2840)
34#define RVU_AF_HWVF_RST (0x2850)
35#define RVU_AF_PFAF_MBOX_INT (0x2880)
36#define RVU_AF_PFAF_MBOX_INT_W1S (0x2888)
37#define RVU_AF_PFAF_MBOX_INT_ENA_W1S (0x2890)
38#define RVU_AF_PFAF_MBOX_INT_ENA_W1C (0x2898)
39#define RVU_AF_PFFLR_INT (0x28a0)
40#define RVU_AF_PFFLR_INT_W1S (0x28a8)
41#define RVU_AF_PFFLR_INT_ENA_W1S (0x28b0)
42#define RVU_AF_PFFLR_INT_ENA_W1C (0x28b8)
43#define RVU_AF_PFME_INT (0x28c0)
44#define RVU_AF_PFME_INT_W1S (0x28c8)
45#define RVU_AF_PFME_INT_ENA_W1S (0x28d0)
46#define RVU_AF_PFME_INT_ENA_W1C (0x28d8)
47
48
49#define RVU_PRIV_CONST (0x8000000)
50#define RVU_PRIV_GEN_CFG (0x8000010)
51#define RVU_PRIV_CLK_CFG (0x8000020)
52#define RVU_PRIV_ACTIVE_PC (0x8000030)
53#define RVU_PRIV_PFX_CFG(a) (0x8000100 | (a) << 16)
54#define RVU_PRIV_PFX_MSIX_CFG(a) (0x8000110 | (a) << 16)
55#define RVU_PRIV_PFX_ID_CFG(a) (0x8000120 | (a) << 16)
56#define RVU_PRIV_PFX_INT_CFG(a) (0x8000200 | (a) << 16)
57#define RVU_PRIV_PFX_NIXX_CFG(a) (0x8000300 | (a) << 3)
58#define RVU_PRIV_PFX_NPA_CFG (0x8000310)
59#define RVU_PRIV_PFX_SSO_CFG (0x8000320)
60#define RVU_PRIV_PFX_SSOW_CFG (0x8000330)
61#define RVU_PRIV_PFX_TIM_CFG (0x8000340)
62#define RVU_PRIV_PFX_CPTX_CFG(a) (0x8000350 | (a) << 3)
63#define RVU_PRIV_BLOCK_TYPEX_REV(a) (0x8000400 | (a) << 3)
64#define RVU_PRIV_HWVFX_INT_CFG(a) (0x8001280 | (a) << 16)
65#define RVU_PRIV_HWVFX_NIXX_CFG(a) (0x8001300 | (a) << 3)
66#define RVU_PRIV_HWVFX_NPA_CFG (0x8001310)
67#define RVU_PRIV_HWVFX_SSO_CFG (0x8001320)
68#define RVU_PRIV_HWVFX_SSOW_CFG (0x8001330)
69#define RVU_PRIV_HWVFX_TIM_CFG (0x8001340)
70#define RVU_PRIV_HWVFX_CPTX_CFG(a) (0x8001350 | (a) << 3)
71
72
73#define RVU_PF_VFX_PFVF_MBOX0 (0x00000)
74#define RVU_PF_VFX_PFVF_MBOX1 (0x00008)
75#define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3)
76#define RVU_PF_VF_BAR4_ADDR (0x10)
77#define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
78#define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3)
79#define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3)
80#define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3)
81#define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3)
82#define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3)
83#define RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) (0x8C0 | (a) << 3)
84#define RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) (0x8E0 | (a) << 3)
85#define RVU_PF_VFFLR_INTX(a) (0x900 | (a) << 3)
86#define RVU_PF_VFFLR_INT_W1SX(a) (0x920 | (a) << 3)
87#define RVU_PF_VFFLR_INT_ENA_W1SX(a) (0x940 | (a) << 3)
88#define RVU_PF_VFFLR_INT_ENA_W1CX(a) (0x960 | (a) << 3)
89#define RVU_PF_VFME_INTX(a) (0x980 | (a) << 3)
90#define RVU_PF_VFME_INT_W1SX(a) (0x9A0 | (a) << 3)
91#define RVU_PF_VFME_INT_ENA_W1SX(a) (0x9C0 | (a) << 3)
92#define RVU_PF_VFME_INT_ENA_W1CX(a) (0x9E0 | (a) << 3)
93#define RVU_PF_PFAF_MBOX0 (0xC00)
94#define RVU_PF_PFAF_MBOX1 (0xC08)
95#define RVU_PF_PFAF_MBOXX(a) (0xC00 | (a) << 3)
96#define RVU_PF_INT (0xc20)
97#define RVU_PF_INT_W1S (0xc28)
98#define RVU_PF_INT_ENA_W1S (0xc30)
99#define RVU_PF_INT_ENA_W1C (0xc38)
100#define RVU_PF_MSIX_VECX_ADDR(a) (0x000 | (a) << 4)
101#define RVU_PF_MSIX_VECX_CTL(a) (0x008 | (a) << 4)
102#define RVU_PF_MSIX_PBAX(a) (0xF0000 | (a) << 3)
103
104
105#define RVU_VF_VFPF_MBOX0 (0x00000)
106#define RVU_VF_VFPF_MBOX1 (0x00008)
107
108
109#define NPA_AF_BLK_RST (0x0000)
110#define NPA_AF_CONST (0x0010)
111#define NPA_AF_CONST1 (0x0018)
112#define NPA_AF_LF_RST (0x0020)
113#define NPA_AF_GEN_CFG (0x0030)
114#define NPA_AF_NDC_CFG (0x0040)
115#define NPA_AF_INP_CTL (0x00D0)
116#define NPA_AF_ACTIVE_CYCLES_PC (0x00F0)
117#define NPA_AF_AVG_DELAY (0x0100)
118#define NPA_AF_GEN_INT (0x0140)
119#define NPA_AF_GEN_INT_W1S (0x0148)
120#define NPA_AF_GEN_INT_ENA_W1S (0x0150)
121#define NPA_AF_GEN_INT_ENA_W1C (0x0158)
122#define NPA_AF_RVU_INT (0x0160)
123#define NPA_AF_RVU_INT_W1S (0x0168)
124#define NPA_AF_RVU_INT_ENA_W1S (0x0170)
125#define NPA_AF_RVU_INT_ENA_W1C (0x0178)
126#define NPA_AF_ERR_INT (0x0180)
127#define NPA_AF_ERR_INT_W1S (0x0188)
128#define NPA_AF_ERR_INT_ENA_W1S (0x0190)
129#define NPA_AF_ERR_INT_ENA_W1C (0x0198)
130#define NPA_AF_RAS (0x01A0)
131#define NPA_AF_RAS_W1S (0x01A8)
132#define NPA_AF_RAS_ENA_W1S (0x01B0)
133#define NPA_AF_RAS_ENA_W1C (0x01B8)
134#define NPA_AF_BP_TEST (0x0200)
135#define NPA_AF_ECO (0x0300)
136#define NPA_AF_AQ_CFG (0x0600)
137#define NPA_AF_AQ_BASE (0x0610)
138#define NPA_AF_AQ_STATUS (0x0620)
139#define NPA_AF_AQ_DOOR (0x0630)
140#define NPA_AF_AQ_DONE_WAIT (0x0640)
141#define NPA_AF_AQ_DONE (0x0650)
142#define NPA_AF_AQ_DONE_ACK (0x0660)
143#define NPA_AF_AQ_DONE_INT (0x0680)
144#define NPA_AF_AQ_DONE_INT_W1S (0x0688)
145#define NPA_AF_AQ_DONE_ENA_W1S (0x0690)
146#define NPA_AF_AQ_DONE_ENA_W1C (0x0698)
147#define NPA_AF_LFX_AURAS_CFG(a) (0x4000 | (a) << 18)
148#define NPA_AF_LFX_LOC_AURAS_BASE(a) (0x4010 | (a) << 18)
149#define NPA_AF_LFX_QINTS_CFG(a) (0x4100 | (a) << 18)
150#define NPA_AF_LFX_QINTS_BASE(a) (0x4110 | (a) << 18)
151#define NPA_PRIV_AF_INT_CFG (0x10000)
152#define NPA_PRIV_LFX_CFG (0x10010)
153#define NPA_PRIV_LFX_INT_CFG (0x10020)
154#define NPA_AF_RVU_LF_CFG_DEBUG (0x10030)
155
156
157#define NIX_AF_CFG (0x0000)
158#define NIX_AF_STATUS (0x0010)
159#define NIX_AF_NDC_CFG (0x0018)
160#define NIX_AF_CONST (0x0020)
161#define NIX_AF_CONST1 (0x0028)
162#define NIX_AF_CONST2 (0x0030)
163#define NIX_AF_CONST3 (0x0038)
164#define NIX_AF_SQ_CONST (0x0040)
165#define NIX_AF_CQ_CONST (0x0048)
166#define NIX_AF_RQ_CONST (0x0050)
167#define NIX_AF_PSE_CONST (0x0060)
168#define NIX_AF_TL1_CONST (0x0070)
169#define NIX_AF_TL2_CONST (0x0078)
170#define NIX_AF_TL3_CONST (0x0080)
171#define NIX_AF_TL4_CONST (0x0088)
172#define NIX_AF_MDQ_CONST (0x0090)
173#define NIX_AF_MC_MIRROR_CONST (0x0098)
174#define NIX_AF_LSO_CFG (0x00A8)
175#define NIX_AF_BLK_RST (0x00B0)
176#define NIX_AF_TX_TSTMP_CFG (0x00C0)
177#define NIX_AF_RX_CFG (0x00D0)
178#define NIX_AF_AVG_DELAY (0x00E0)
179#define NIX_AF_CINT_DELAY (0x00F0)
180#define NIX_AF_RX_MCAST_BASE (0x0100)
181#define NIX_AF_RX_MCAST_CFG (0x0110)
182#define NIX_AF_RX_MCAST_BUF_BASE (0x0120)
183#define NIX_AF_RX_MCAST_BUF_CFG (0x0130)
184#define NIX_AF_RX_MIRROR_BUF_BASE (0x0140)
185#define NIX_AF_RX_MIRROR_BUF_CFG (0x0148)
186#define NIX_AF_LF_RST (0x0150)
187#define NIX_AF_GEN_INT (0x0160)
188#define NIX_AF_GEN_INT_W1S (0x0168)
189#define NIX_AF_GEN_INT_ENA_W1S (0x0170)
190#define NIX_AF_GEN_INT_ENA_W1C (0x0178)
191#define NIX_AF_ERR_INT (0x0180)
192#define NIX_AF_ERR_INT_W1S (0x0188)
193#define NIX_AF_ERR_INT_ENA_W1S (0x0190)
194#define NIX_AF_ERR_INT_ENA_W1C (0x0198)
195#define NIX_AF_RAS (0x01A0)
196#define NIX_AF_RAS_W1S (0x01A8)
197#define NIX_AF_RAS_ENA_W1S (0x01B0)
198#define NIX_AF_RAS_ENA_W1C (0x01B8)
199#define NIX_AF_RVU_INT (0x01C0)
200#define NIX_AF_RVU_INT_W1S (0x01C8)
201#define NIX_AF_RVU_INT_ENA_W1S (0x01D0)
202#define NIX_AF_RVU_INT_ENA_W1C (0x01D8)
203#define NIX_AF_TCP_TIMER (0x01E0)
204#define NIX_AF_RX_WQE_TAG_CTL (0x01F0)
205#define NIX_AF_RX_DEF_OL2 (0x0200)
206#define NIX_AF_RX_DEF_OIP4 (0x0210)
207#define NIX_AF_RX_DEF_IIP4 (0x0220)
208#define NIX_AF_RX_DEF_OIP6 (0x0230)
209#define NIX_AF_RX_DEF_IIP6 (0x0240)
210#define NIX_AF_RX_DEF_OTCP (0x0250)
211#define NIX_AF_RX_DEF_ITCP (0x0260)
212#define NIX_AF_RX_DEF_OUDP (0x0270)
213#define NIX_AF_RX_DEF_IUDP (0x0280)
214#define NIX_AF_RX_DEF_OSCTP (0x0290)
215#define NIX_AF_RX_DEF_ISCTP (0x02A0)
216#define NIX_AF_RX_DEF_IPSECX (0x02B0)
217#define NIX_AF_RX_IPSEC_GEN_CFG (0x0300)
218#define NIX_AF_RX_CPTX_INST_ADDR (0x0310)
219#define NIX_AF_NDC_TX_SYNC (0x03F0)
220#define NIX_AF_AQ_CFG (0x0400)
221#define NIX_AF_AQ_BASE (0x0410)
222#define NIX_AF_AQ_STATUS (0x0420)
223#define NIX_AF_AQ_DOOR (0x0430)
224#define NIX_AF_AQ_DONE_WAIT (0x0440)
225#define NIX_AF_AQ_DONE (0x0450)
226#define NIX_AF_AQ_DONE_ACK (0x0460)
227#define NIX_AF_AQ_DONE_TIMER (0x0470)
228#define NIX_AF_AQ_DONE_INT (0x0480)
229#define NIX_AF_AQ_DONE_INT_W1S (0x0488)
230#define NIX_AF_AQ_DONE_ENA_W1S (0x0490)
231#define NIX_AF_AQ_DONE_ENA_W1C (0x0498)
232#define NIX_AF_RX_LINKX_SLX_SPKT_CNT (0x0500)
233#define NIX_AF_RX_LINKX_SLX_SXQE_CNT (0x0510)
234#define NIX_AF_RX_MCAST_JOBSX_SW_CNT (0x0520)
235#define NIX_AF_RX_MIRROR_JOBSX_SW_CNT (0x0530)
236#define NIX_AF_RX_LINKX_CFG(a) (0x0540 | (a) << 16)
237#define NIX_AF_RX_SW_SYNC (0x0550)
238#define NIX_AF_RX_SW_SYNC_DONE (0x0560)
239#define NIX_AF_SEB_ECO (0x0600)
240#define NIX_AF_SEB_TEST_BP (0x0610)
241#define NIX_AF_NORM_TX_FIFO_STATUS (0x0620)
242#define NIX_AF_EXPR_TX_FIFO_STATUS (0x0630)
243#define NIX_AF_SDP_TX_FIFO_STATUS (0x0640)
244#define NIX_AF_TX_NPC_CAPTURE_CONFIG (0x0660)
245#define NIX_AF_TX_NPC_CAPTURE_INFO (0x0670)
246
247#define NIX_AF_DEBUG_NPC_RESP_DATAX(a) (0x680 | (a) << 3)
248#define NIX_AF_SMQX_CFG(a) (0x700 | (a) << 16)
249#define NIX_AF_SQM_DBG_CTL_STATUS (0x750)
250#define NIX_AF_PSE_CHANNEL_LEVEL (0x800)
251#define NIX_AF_PSE_SHAPER_CFG (0x810)
252#define NIX_AF_TX_EXPR_CREDIT (0x830)
253#define NIX_AF_MARK_FORMATX_CTL(a) (0x900 | (a) << 18)
254#define NIX_AF_TX_LINKX_NORM_CREDIT(a) (0xA00 | (a) << 16)
255#define NIX_AF_TX_LINKX_EXPR_CREDIT(a) (0xA10 | (a) << 16)
256#define NIX_AF_TX_LINKX_SW_XOFF(a) (0xA20 | (a) << 16)
257#define NIX_AF_TX_LINKX_HW_XOFF(a) (0xA30 | (a) << 16)
258#define NIX_AF_SDP_LINK_CREDIT (0xa40)
259#define NIX_AF_SDP_SW_XOFFX(a) (0xA60 | (a) << 3)
260#define NIX_AF_SDP_HW_XOFFX(a) (0xAC0 | (a) << 3)
261#define NIX_AF_TL4X_BP_STATUS(a) (0xB00 | (a) << 16)
262#define NIX_AF_TL4X_SDP_LINK_CFG(a) (0xB10 | (a) << 16)
263#define NIX_AF_TL1X_SCHEDULE(a) (0xC00 | (a) << 16)
264#define NIX_AF_TL1X_SHAPE(a) (0xC10 | (a) << 16)
265#define NIX_AF_TL1X_CIR(a) (0xC20 | (a) << 16)
266#define NIX_AF_TL1X_SHAPE_STATE(a) (0xC50 | (a) << 16)
267#define NIX_AF_TL1X_SW_XOFF(a) (0xC70 | (a) << 16)
268#define NIX_AF_TL1X_TOPOLOGY(a) (0xC80 | (a) << 16)
269#define NIX_AF_TL1X_GREEN(a) (0xC90 | (a) << 16)
270#define NIX_AF_TL1X_YELLOW(a) (0xCA0 | (a) << 16)
271#define NIX_AF_TL1X_RED(a) (0xCB0 | (a) << 16)
272#define NIX_AF_TL1X_MD_DEBUG0(a) (0xCC0 | (a) << 16)
273#define NIX_AF_TL1X_MD_DEBUG1(a) (0xCC8 | (a) << 16)
274#define NIX_AF_TL1X_MD_DEBUG2(a) (0xCD0 | (a) << 16)
275#define NIX_AF_TL1X_MD_DEBUG3(a) (0xCD8 | (a) << 16)
276#define NIX_AF_TL1A_DEBUG (0xce0)
277#define NIX_AF_TL1B_DEBUG (0xcf0)
278#define NIX_AF_TL1_DEBUG_GREEN (0xd00)
279#define NIX_AF_TL1_DEBUG_NODE (0xd10)
280#define NIX_AF_TL1X_DROPPED_PACKETS(a) (0xD20 | (a) << 16)
281#define NIX_AF_TL1X_DROPPED_BYTES(a) (0xD30 | (a) << 16)
282#define NIX_AF_TL1X_RED_PACKETS(a) (0xD40 | (a) << 16)
283#define NIX_AF_TL1X_RED_BYTES(a) (0xD50 | (a) << 16)
284#define NIX_AF_TL1X_YELLOW_PACKETS(a) (0xD60 | (a) << 16)
285#define NIX_AF_TL1X_YELLOW_BYTES(a) (0xD70 | (a) << 16)
286#define NIX_AF_TL1X_GREEN_PACKETS(a) (0xD80 | (a) << 16)
287#define NIX_AF_TL1X_GREEN_BYTES(a) (0xD90 | (a) << 16)
288#define NIX_AF_TL2X_SCHEDULE(a) (0xE00 | (a) << 16)
289#define NIX_AF_TL2X_SHAPE(a) (0xE10 | (a) << 16)
290#define NIX_AF_TL2X_CIR(a) (0xE20 | (a) << 16)
291#define NIX_AF_TL2X_PIR(a) (0xE30 | (a) << 16)
292#define NIX_AF_TL2X_SCHED_STATE(a) (0xE40 | (a) << 16)
293#define NIX_AF_TL2X_SHAPE_STATE(a) (0xE50 | (a) << 16)
294#define NIX_AF_TL2X_POINTERS(a) (0xE60 | (a) << 16)
295#define NIX_AF_TL2X_SW_XOFF(a) (0xE70 | (a) << 16)
296#define NIX_AF_TL2X_TOPOLOGY(a) (0xE80 | (a) << 16)
297#define NIX_AF_TL2X_PARENT(a) (0xE88 | (a) << 16)
298#define NIX_AF_TL2X_GREEN(a) (0xE90 | (a) << 16)
299#define NIX_AF_TL2X_YELLOW(a) (0xEA0 | (a) << 16)
300#define NIX_AF_TL2X_RED(a) (0xEB0 | (a) << 16)
301#define NIX_AF_TL2X_MD_DEBUG0(a) (0xEC0 | (a) << 16)
302#define NIX_AF_TL2X_MD_DEBUG1(a) (0xEC8 | (a) << 16)
303#define NIX_AF_TL2X_MD_DEBUG2(a) (0xED0 | (a) << 16)
304#define NIX_AF_TL2X_MD_DEBUG3(a) (0xED8 | (a) << 16)
305#define NIX_AF_TL2A_DEBUG (0xee0)
306#define NIX_AF_TL2B_DEBUG (0xef0)
307#define NIX_AF_TL3X_SCHEDULE(a) (0x1000 | (a) << 16)
308#define NIX_AF_TL3X_SHAPE(a) (0x1010 | (a) << 16)
309#define NIX_AF_TL3X_CIR(a) (0x1020 | (a) << 16)
310#define NIX_AF_TL3X_PIR(a) (0x1030 | (a) << 16)
311#define NIX_AF_TL3X_SCHED_STATE(a) (0x1040 | (a) << 16)
312#define NIX_AF_TL3X_SHAPE_STATE(a) (0x1050 | (a) << 16)
313#define NIX_AF_TL3X_POINTERS(a) (0x1060 | (a) << 16)
314#define NIX_AF_TL3X_SW_XOFF(a) (0x1070 | (a) << 16)
315#define NIX_AF_TL3X_TOPOLOGY(a) (0x1080 | (a) << 16)
316#define NIX_AF_TL3X_PARENT(a) (0x1088 | (a) << 16)
317#define NIX_AF_TL3X_GREEN(a) (0x1090 | (a) << 16)
318#define NIX_AF_TL3X_YELLOW(a) (0x10A0 | (a) << 16)
319#define NIX_AF_TL3X_RED(a) (0x10B0 | (a) << 16)
320#define NIX_AF_TL3X_MD_DEBUG0(a) (0x10C0 | (a) << 16)
321#define NIX_AF_TL3X_MD_DEBUG1(a) (0x10C8 | (a) << 16)
322#define NIX_AF_TL3X_MD_DEBUG2(a) (0x10D0 | (a) << 16)
323#define NIX_AF_TL3X_MD_DEBUG3(a) (0x10D8 | (a) << 16)
324#define NIX_AF_TL3A_DEBUG (0x10e0)
325#define NIX_AF_TL3B_DEBUG (0x10f0)
326#define NIX_AF_TL4X_SCHEDULE(a) (0x1200 | (a) << 16)
327#define NIX_AF_TL4X_SHAPE(a) (0x1210 | (a) << 16)
328#define NIX_AF_TL4X_CIR(a) (0x1220 | (a) << 16)
329#define NIX_AF_TL4X_PIR(a) (0x1230 | (a) << 16)
330#define NIX_AF_TL4X_SCHED_STATE(a) (0x1240 | (a) << 16)
331#define NIX_AF_TL4X_SHAPE_STATE(a) (0x1250 | (a) << 16)
332#define NIX_AF_TL4X_POINTERS(a) (0x1260 | (a) << 16)
333#define NIX_AF_TL4X_SW_XOFF(a) (0x1270 | (a) << 16)
334#define NIX_AF_TL4X_TOPOLOGY(a) (0x1280 | (a) << 16)
335#define NIX_AF_TL4X_PARENT(a) (0x1288 | (a) << 16)
336#define NIX_AF_TL4X_GREEN(a) (0x1290 | (a) << 16)
337#define NIX_AF_TL4X_YELLOW(a) (0x12A0 | (a) << 16)
338#define NIX_AF_TL4X_RED(a) (0x12B0 | (a) << 16)
339#define NIX_AF_TL4X_MD_DEBUG0(a) (0x12C0 | (a) << 16)
340#define NIX_AF_TL4X_MD_DEBUG1(a) (0x12C8 | (a) << 16)
341#define NIX_AF_TL4X_MD_DEBUG2(a) (0x12D0 | (a) << 16)
342#define NIX_AF_TL4X_MD_DEBUG3(a) (0x12D8 | (a) << 16)
343#define NIX_AF_TL4A_DEBUG (0x12e0)
344#define NIX_AF_TL4B_DEBUG (0x12f0)
345#define NIX_AF_MDQX_SCHEDULE(a) (0x1400 | (a) << 16)
346#define NIX_AF_MDQX_SHAPE(a) (0x1410 | (a) << 16)
347#define NIX_AF_MDQX_CIR(a) (0x1420 | (a) << 16)
348#define NIX_AF_MDQX_PIR(a) (0x1430 | (a) << 16)
349#define NIX_AF_MDQX_SCHED_STATE(a) (0x1440 | (a) << 16)
350#define NIX_AF_MDQX_SHAPE_STATE(a) (0x1450 | (a) << 16)
351#define NIX_AF_MDQX_POINTERS(a) (0x1460 | (a) << 16)
352#define NIX_AF_MDQX_SW_XOFF(a) (0x1470 | (a) << 16)
353#define NIX_AF_MDQX_PARENT(a) (0x1480 | (a) << 16)
354#define NIX_AF_MDQX_MD_DEBUG(a) (0x14C0 | (a) << 16)
355#define NIX_AF_MDQX_PTR_FIFO(a) (0x14D0 | (a) << 16)
356#define NIX_AF_MDQA_DEBUG (0x14e0)
357#define NIX_AF_MDQB_DEBUG (0x14f0)
358#define NIX_AF_TL3_TL2X_CFG(a) (0x1600 | (a) << 18)
359#define NIX_AF_TL3_TL2X_BP_STATUS(a) (0x1610 | (a) << 16)
360#define NIX_AF_TL3_TL2X_LINKX_CFG(a, b) (0x1700 | (a) << 16 | (b) << 3)
361#define NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(a, b) (0x1800 | (a) << 18 | (b) << 3)
362#define NIX_AF_TX_MCASTX(a) (0x1900 | (a) << 15)
363#define NIX_AF_TX_VTAG_DEFX_CTL(a) (0x1A00 | (a) << 16)
364#define NIX_AF_TX_VTAG_DEFX_DATA(a) (0x1A10 | (a) << 16)
365#define NIX_AF_RX_BPIDX_STATUS(a) (0x1A20 | (a) << 17)
366#define NIX_AF_RX_CHANX_CFG(a) (0x1A30 | (a) << 15)
367#define NIX_AF_CINT_TIMERX(a) (0x1A40 | (a) << 18)
368#define NIX_AF_LSO_FORMATX_FIELDX(a, b) (0x1B00 | (a) << 16 | (b) << 3)
369#define NIX_AF_LFX_CFG(a) (0x4000 | (a) << 17)
370#define NIX_AF_LFX_SQS_CFG(a) (0x4020 | (a) << 17)
371#define NIX_AF_LFX_TX_CFG2(a) (0x4028 | (a) << 17)
372#define NIX_AF_LFX_SQS_BASE(a) (0x4030 | (a) << 17)
373#define NIX_AF_LFX_RQS_CFG(a) (0x4040 | (a) << 17)
374#define NIX_AF_LFX_RQS_BASE(a) (0x4050 | (a) << 17)
375#define NIX_AF_LFX_CQS_CFG(a) (0x4060 | (a) << 17)
376#define NIX_AF_LFX_CQS_BASE(a) (0x4070 | (a) << 17)
377#define NIX_AF_LFX_TX_CFG(a) (0x4080 | (a) << 17)
378#define NIX_AF_LFX_TX_PARSE_CFG(a) (0x4090 | (a) << 17)
379#define NIX_AF_LFX_RX_CFG(a) (0x40A0 | (a) << 17)
380#define NIX_AF_LFX_RSS_CFG(a) (0x40C0 | (a) << 17)
381#define NIX_AF_LFX_RSS_BASE(a) (0x40D0 | (a) << 17)
382#define NIX_AF_LFX_QINTS_CFG(a) (0x4100 | (a) << 17)
383#define NIX_AF_LFX_QINTS_BASE(a) (0x4110 | (a) << 17)
384#define NIX_AF_LFX_CINTS_CFG(a) (0x4120 | (a) << 17)
385#define NIX_AF_LFX_CINTS_BASE(a) (0x4130 | (a) << 17)
386#define NIX_AF_LFX_RX_IPSEC_CFG0(a) (0x4140 | (a) << 17)
387#define NIX_AF_LFX_RX_IPSEC_CFG1(a) (0x4148 | (a) << 17)
388#define NIX_AF_LFX_RX_IPSEC_DYNO_CFG(a) (0x4150 | (a) << 17)
389#define NIX_AF_LFX_RX_IPSEC_DYNO_BASE(a) (0x4158 | (a) << 17)
390#define NIX_AF_LFX_RX_IPSEC_SA_BASE(a) (0x4170 | (a) << 17)
391#define NIX_AF_LFX_TX_STATUS(a) (0x4180 | (a) << 17)
392#define NIX_AF_LFX_RX_VTAG_TYPEX(a, b) (0x4200 | (a) << 17 | (b) << 3)
393#define NIX_AF_LFX_LOCKX(a, b) (0x4300 | (a) << 17 | (b) << 3)
394#define NIX_AF_LFX_TX_STATX(a, b) (0x4400 | (a) << 17 | (b) << 3)
395#define NIX_AF_LFX_RX_STATX(a, b) (0x4500 | (a) << 17 | (b) << 3)
396#define NIX_AF_LFX_RSS_GRPX(a, b) (0x4600 | (a) << 17 | (b) << 3)
397#define NIX_AF_RX_NPC_MC_RCV (0x4700)
398#define NIX_AF_RX_NPC_MC_DROP (0x4710)
399#define NIX_AF_RX_NPC_MIRROR_RCV (0x4720)
400#define NIX_AF_RX_NPC_MIRROR_DROP (0x4730)
401#define NIX_AF_RX_ACTIVE_CYCLES_PCX(a) (0x4800 | (a) << 16)
402
403#define NIX_PRIV_AF_INT_CFG (0x8000000)
404#define NIX_PRIV_LFX_CFG (0x8000010)
405#define NIX_PRIV_LFX_INT_CFG (0x8000020)
406#define NIX_AF_RVU_LF_CFG_DEBUG (0x8000030)
407
408
409#define SSO_AF_CONST (0x1000)
410#define SSO_AF_CONST1 (0x1008)
411#define SSO_AF_BLK_RST (0x10f8)
412#define SSO_AF_LF_HWGRP_RST (0x10e0)
413#define SSO_AF_RVU_LF_CFG_DEBUG (0x3800)
414#define SSO_PRIV_LFX_HWGRP_CFG (0x10000)
415#define SSO_PRIV_LFX_HWGRP_INT_CFG (0x20000)
416
417
418#define SSOW_AF_RVU_LF_HWS_CFG_DEBUG (0x0010)
419#define SSOW_AF_LF_HWS_RST (0x0030)
420#define SSOW_PRIV_LFX_HWS_CFG (0x1000)
421#define SSOW_PRIV_LFX_HWS_INT_CFG (0x2000)
422
423
424#define TIM_AF_CONST (0x90)
425#define TIM_PRIV_LFX_CFG (0x20000)
426#define TIM_PRIV_LFX_INT_CFG (0x24000)
427#define TIM_AF_RVU_LF_CFG_DEBUG (0x30000)
428#define TIM_AF_BLK_RST (0x10)
429#define TIM_AF_LF_RST (0x20)
430
431
432#define CPT_AF_CONSTANTS0 (0x0000)
433#define CPT_AF_CONSTANTS1 (0x1000)
434#define CPT_AF_DIAG (0x3000)
435#define CPT_AF_ECO (0x4000)
436#define CPT_AF_FLTX_INT(a) (0xa000ull | (u64)(a) << 3)
437#define CPT_AF_FLTX_INT_W1S(a) (0xb000ull | (u64)(a) << 3)
438#define CPT_AF_FLTX_INT_ENA_W1C(a) (0xc000ull | (u64)(a) << 3)
439#define CPT_AF_FLTX_INT_ENA_W1S(a) (0xd000ull | (u64)(a) << 3)
440#define CPT_AF_PSNX_EXE(a) (0xe000ull | (u64)(a) << 3)
441#define CPT_AF_PSNX_EXE_W1S(a) (0xf000ull | (u64)(a) << 3)
442#define CPT_AF_PSNX_LF(a) (0x10000ull | (u64)(a) << 3)
443#define CPT_AF_PSNX_LF_W1S(a) (0x11000ull | (u64)(a) << 3)
444#define CPT_AF_EXEX_CTL2(a) (0x12000ull | (u64)(a) << 3)
445#define CPT_AF_EXEX_STS(a) (0x13000ull | (u64)(a) << 3)
446#define CPT_AF_EXE_ERR_INFO (0x14000)
447#define CPT_AF_EXEX_ACTIVE(a) (0x16000ull | (u64)(a) << 3)
448#define CPT_AF_INST_REQ_PC (0x17000)
449#define CPT_AF_INST_LATENCY_PC (0x18000)
450#define CPT_AF_RD_REQ_PC (0x19000)
451#define CPT_AF_RD_LATENCY_PC (0x1a000)
452#define CPT_AF_RD_UC_PC (0x1b000)
453#define CPT_AF_ACTIVE_CYCLES_PC (0x1c000)
454#define CPT_AF_EXE_DBG_CTL (0x1d000)
455#define CPT_AF_EXE_DBG_DATA (0x1e000)
456#define CPT_AF_EXE_REQ_TIMER (0x1f000)
457#define CPT_AF_EXEX_CTL(a) (0x20000ull | (u64)(a) << 3)
458#define CPT_AF_EXE_PERF_CTL (0x21000)
459#define CPT_AF_EXE_DBG_CNTX(a) (0x22000ull | (u64)(a) << 3)
460#define CPT_AF_EXE_PERF_EVENT_CNT (0x23000)
461#define CPT_AF_EXE_EPCI_INBX_CNT(a) (0x24000ull | (u64)(a) << 3)
462#define CPT_AF_EXE_EPCI_OUTBX_CNT(a) (0x25000ull | (u64)(a) << 3)
463#define CPT_AF_EXEX_UCODE_BASE(a) (0x26000ull | (u64)(a) << 3)
464#define CPT_AF_LFX_CTL(a) (0x27000ull | (u64)(a) << 3)
465#define CPT_AF_LFX_CTL2(a) (0x29000ull | (u64)(a) << 3)
466#define CPT_AF_CPTCLK_CNT (0x2a000)
467#define CPT_AF_PF_FUNC (0x2b000)
468#define CPT_AF_LFX_PTR_CTL(a) (0x2c000ull | (u64)(a) << 3)
469#define CPT_AF_GRPX_THR(a) (0x2d000ull | (u64)(a) << 3)
470#define CPT_AF_CTL (0x2e000ull)
471#define CPT_AF_XEX_THR(a) (0x2f000ull | (u64)(a) << 3)
472#define CPT_PRIV_LFX_CFG (0x41000)
473#define CPT_PRIV_AF_INT_CFG (0x42000)
474#define CPT_PRIV_LFX_INT_CFG (0x43000)
475#define CPT_AF_LF_RST (0x44000)
476#define CPT_AF_RVU_LF_CFG_DEBUG (0x45000)
477#define CPT_AF_BLK_RST (0x46000)
478#define CPT_AF_RVU_INT (0x47000)
479#define CPT_AF_RVU_INT_W1S (0x47008)
480#define CPT_AF_RVU_INT_ENA_W1S (0x47010)
481#define CPT_AF_RVU_INT_ENA_W1C (0x47018)
482#define CPT_AF_RAS_INT (0x47020)
483#define CPT_AF_RAS_INT_W1S (0x47028)
484#define CPT_AF_RAS_INT_ENA_W1S (0x47030)
485#define CPT_AF_RAS_INT_ENA_W1C (0x47038)
486
487#define CPT_AF_LF_CTL2_SHIFT 3
488#define CPT_AF_LF_SSO_PF_FUNC_SHIFT 32
489
490#define NPC_AF_BLK_RST (0x00040)
491
492
493#define NPC_AF_CFG (0x00000)
494#define NPC_AF_ACTIVE_PC (0x00010)
495#define NPC_AF_CONST (0x00020)
496#define NPC_AF_CONST1 (0x00030)
497#define NPC_AF_BLK_RST (0x00040)
498#define NPC_AF_MCAM_SCRUB_CTL (0x000a0)
499#define NPC_AF_KCAM_SCRUB_CTL (0x000b0)
500#define NPC_AF_CONST2 (0x00100)
501#define NPC_AF_CONST3 (0x00110)
502#define NPC_AF_KPUX_CFG(a) (0x00500 | (a) << 3)
503#define NPC_AF_PCK_CFG (0x00600)
504#define NPC_AF_PCK_DEF_OL2 (0x00610)
505#define NPC_AF_PCK_DEF_OIP4 (0x00620)
506#define NPC_AF_PCK_DEF_OIP6 (0x00630)
507#define NPC_AF_PCK_DEF_IIP4 (0x00640)
508#define NPC_AF_KEX_LDATAX_FLAGS_CFG(a) (0x00800 | (a) << 3)
509#define NPC_AF_INTFX_KEX_CFG(a) (0x01010 | (a) << 8)
510#define NPC_AF_PKINDX_ACTION0(a) (0x80000ull | (a) << 6)
511#define NPC_AF_PKINDX_ACTION1(a) (0x80008ull | (a) << 6)
512#define NPC_AF_PKINDX_CPI_DEFX(a, b) (0x80020ull | (a) << 6 | (b) << 3)
513#define NPC_AF_KPUX_ENTRYX_CAMX(a, b, c) \
514 (0x100000 | (a) << 14 | (b) << 6 | (c) << 3)
515#define NPC_AF_KPUX_ENTRYX_ACTION0(a, b) \
516 (0x100020 | (a) << 14 | (b) << 6)
517#define NPC_AF_KPUX_ENTRYX_ACTION1(a, b) \
518 (0x100028 | (a) << 14 | (b) << 6)
519#define NPC_AF_KPUX_ENTRY_DISX(a, b) (0x180000 | (a) << 6 | (b) << 3)
520#define NPC_AF_CPIX_CFG(a) (0x200000 | (a) << 3)
521#define NPC_AF_INTFX_LIDX_LTX_LDX_CFG(a, b, c, d) \
522 (0x900000 | (a) << 16 | (b) << 12 | (c) << 5 | (d) << 3)
523#define NPC_AF_INTFX_LDATAX_FLAGSX_CFG(a, b, c) \
524 (0x980000 | (a) << 16 | (b) << 12 | (c) << 3)
525#define NPC_AF_INTFX_MISS_STAT_ACT(a) (0x1880040 + (a) * 0x8)
526#define NPC_AF_INTFX_MISS_ACT(a) (0x1a00000 | (a) << 4)
527#define NPC_AF_INTFX_MISS_TAG_ACT(a) (0x1b00008 | (a) << 4)
528#define NPC_AF_MCAM_BANKX_HITX(a, b) (0x1c80000 | (a) << 8 | (b) << 4)
529#define NPC_AF_LKUP_CTL (0x2000000)
530#define NPC_AF_LKUP_DATAX(a) (0x2000200 | (a) << 4)
531#define NPC_AF_LKUP_RESULTX(a) (0x2000400 | (a) << 4)
532#define NPC_AF_INTFX_STAT(a) (0x2000800 | (a) << 4)
533#define NPC_AF_DBG_CTL (0x3000000)
534#define NPC_AF_DBG_STATUS (0x3000010)
535#define NPC_AF_KPUX_DBG(a) (0x3000020 | (a) << 8)
536#define NPC_AF_IKPU_ERR_CTL (0x3000080)
537#define NPC_AF_KPUX_ERR_CTL(a) (0x30000a0 | (a) << 8)
538#define NPC_AF_MCAM_DBG (0x3001000)
539#define NPC_AF_DBG_DATAX(a) (0x3001400 | (a) << 4)
540#define NPC_AF_DBG_RESULTX(a) (0x3001800 | (a) << 4)
541
542#define NPC_AF_MCAMEX_BANKX_CAMX_INTF(a, b, c) ({ \
543 u64 offset; \
544 \
545 offset = (0x1000000ull | (a) << 10 | (b) << 6 | (c) << 3); \
546 if (rvu->hw->npc_ext_set) \
547 offset = (0x8000000ull | (a) << 8 | (b) << 22 | (c) << 3); \
548 offset; })
549
550#define NPC_AF_MCAMEX_BANKX_CAMX_W0(a, b, c) ({ \
551 u64 offset; \
552 \
553 offset = (0x1000010ull | (a) << 10 | (b) << 6 | (c) << 3); \
554 if (rvu->hw->npc_ext_set) \
555 offset = (0x8000010ull | (a) << 8 | (b) << 22 | (c) << 3); \
556 offset; })
557
558#define NPC_AF_MCAMEX_BANKX_CAMX_W1(a, b, c) ({ \
559 u64 offset; \
560 \
561 offset = (0x1000020ull | (a) << 10 | (b) << 6 | (c) << 3); \
562 if (rvu->hw->npc_ext_set) \
563 offset = (0x8000020ull | (a) << 8 | (b) << 22 | (c) << 3); \
564 offset; })
565
566#define NPC_AF_MCAMEX_BANKX_CFG(a, b) ({ \
567 u64 offset; \
568 \
569 offset = (0x1800000ull | (a) << 8 | (b) << 4); \
570 if (rvu->hw->npc_ext_set) \
571 offset = (0x8000038ull | (a) << 8 | (b) << 22); \
572 offset; })
573
574#define NPC_AF_MCAMEX_BANKX_ACTION(a, b) ({ \
575 u64 offset; \
576 \
577 offset = (0x1900000ull | (a) << 8 | (b) << 4); \
578 if (rvu->hw->npc_ext_set) \
579 offset = (0x8000040ull | (a) << 8 | (b) << 22); \
580 offset; }) \
581
582#define NPC_AF_MCAMEX_BANKX_TAG_ACT(a, b) ({ \
583 u64 offset; \
584 \
585 offset = (0x1900008ull | (a) << 8 | (b) << 4); \
586 if (rvu->hw->npc_ext_set) \
587 offset = (0x8000048ull | (a) << 8 | (b) << 22); \
588 offset; }) \
589
590#define NPC_AF_MCAMEX_BANKX_STAT_ACT(a, b) ({ \
591 u64 offset; \
592 \
593 offset = (0x1880000ull | (a) << 8 | (b) << 4); \
594 if (rvu->hw->npc_ext_set) \
595 offset = (0x8000050ull | (a) << 8 | (b) << 22); \
596 offset; }) \
597
598#define NPC_AF_MATCH_STATX(a) ({ \
599 u64 offset; \
600 \
601 offset = (0x1880008ull | (a) << 8); \
602 if (rvu->hw->npc_ext_set) \
603 offset = (0x8000078ull | (a) << 8); \
604 offset; }) \
605
606
607#define NDC_AF_CONST (0x00000)
608#define NDC_AF_CLK_EN (0x00020)
609#define NDC_AF_CTL (0x00030)
610#define NDC_AF_BANK_CTL (0x00040)
611#define NDC_AF_BANK_CTL_DONE (0x00048)
612#define NDC_AF_INTR (0x00058)
613#define NDC_AF_INTR_W1S (0x00060)
614#define NDC_AF_INTR_ENA_W1S (0x00068)
615#define NDC_AF_INTR_ENA_W1C (0x00070)
616#define NDC_AF_ACTIVE_PC (0x00078)
617#define NDC_AF_BP_TEST_ENABLE (0x001F8)
618#define NDC_AF_BP_TEST(a) (0x00200 | (a) << 3)
619#define NDC_AF_BLK_RST (0x002F0)
620#define NDC_PRIV_AF_INT_CFG (0x002F8)
621#define NDC_AF_HASHX(a) (0x00300 | (a) << 3)
622#define NDC_AF_PORTX_RTX_RWX_REQ_PC(a, b, c) \
623 (0x00C00 | (a) << 5 | (b) << 4 | (c) << 3)
624#define NDC_AF_PORTX_RTX_RWX_OSTDN_PC(a, b, c) \
625 (0x00D00 | (a) << 5 | (b) << 4 | (c) << 3)
626#define NDC_AF_PORTX_RTX_RWX_LAT_PC(a, b, c) \
627 (0x00E00 | (a) << 5 | (b) << 4 | (c) << 3)
628#define NDC_AF_PORTX_RTX_CANT_ALLOC_PC(a, b) \
629 (0x00F00 | (a) << 5 | (b) << 4)
630#define NDC_AF_BANKX_HIT_PC(a) (0x01000 | (a) << 3)
631#define NDC_AF_BANKX_MISS_PC(a) (0x01100 | (a) << 3)
632#endif
633
