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9#ifndef _SUNHME_H
10#define _SUNHME_H
11
12#include <linux/pci.h>
13
14
15#define GREG_SWRESET 0x000UL
16#define GREG_CFG 0x004UL
17#define GREG_STAT 0x100UL
18#define GREG_IMASK 0x104UL
19#define GREG_REG_SIZE 0x108UL
20
21
22#define GREG_RESET_ETX 0x01
23#define GREG_RESET_ERX 0x02
24#define GREG_RESET_ALL 0x03
25
26
27#define GREG_CFG_BURSTMSK 0x03
28#define GREG_CFG_BURST16 0x00
29#define GREG_CFG_BURST32 0x01
30#define GREG_CFG_BURST64 0x02
31#define GREG_CFG_64BIT 0x04
32#define GREG_CFG_PARITY 0x08
33#define GREG_CFG_RESV 0x10
34
35
36#define GREG_STAT_GOTFRAME 0x00000001
37#define GREG_STAT_RCNTEXP 0x00000002
38#define GREG_STAT_ACNTEXP 0x00000004
39#define GREG_STAT_CCNTEXP 0x00000008
40#define GREG_STAT_LCNTEXP 0x00000010
41#define GREG_STAT_RFIFOVF 0x00000020
42#define GREG_STAT_CVCNTEXP 0x00000040
43#define GREG_STAT_STSTERR 0x00000080
44#define GREG_STAT_SENTFRAME 0x00000100
45#define GREG_STAT_TFIFO_UND 0x00000200
46#define GREG_STAT_MAXPKTERR 0x00000400
47#define GREG_STAT_NCNTEXP 0x00000800
48#define GREG_STAT_ECNTEXP 0x00001000
49#define GREG_STAT_LCCNTEXP 0x00002000
50#define GREG_STAT_FCNTEXP 0x00004000
51#define GREG_STAT_DTIMEXP 0x00008000
52#define GREG_STAT_RXTOHOST 0x00010000
53#define GREG_STAT_NORXD 0x00020000
54#define GREG_STAT_RXERR 0x00040000
55#define GREG_STAT_RXLATERR 0x00080000
56#define GREG_STAT_RXPERR 0x00100000
57#define GREG_STAT_RXTERR 0x00200000
58#define GREG_STAT_EOPERR 0x00400000
59#define GREG_STAT_MIFIRQ 0x00800000
60#define GREG_STAT_HOSTTOTX 0x01000000
61#define GREG_STAT_TXALL 0x02000000
62#define GREG_STAT_TXEACK 0x04000000
63#define GREG_STAT_TXLERR 0x08000000
64#define GREG_STAT_TXPERR 0x10000000
65#define GREG_STAT_TXTERR 0x20000000
66#define GREG_STAT_SLVERR 0x40000000
67#define GREG_STAT_SLVPERR 0x80000000
68
69
70#define GREG_STAT_ERRORS 0xfc7efefc
71
72
73#define GREG_IMASK_GOTFRAME 0x00000001
74#define GREG_IMASK_RCNTEXP 0x00000002
75#define GREG_IMASK_ACNTEXP 0x00000004
76#define GREG_IMASK_CCNTEXP 0x00000008
77#define GREG_IMASK_LCNTEXP 0x00000010
78#define GREG_IMASK_RFIFOVF 0x00000020
79#define GREG_IMASK_CVCNTEXP 0x00000040
80#define GREG_IMASK_STSTERR 0x00000080
81#define GREG_IMASK_SENTFRAME 0x00000100
82#define GREG_IMASK_TFIFO_UND 0x00000200
83#define GREG_IMASK_MAXPKTERR 0x00000400
84#define GREG_IMASK_NCNTEXP 0x00000800
85#define GREG_IMASK_ECNTEXP 0x00001000
86#define GREG_IMASK_LCCNTEXP 0x00002000
87#define GREG_IMASK_FCNTEXP 0x00004000
88#define GREG_IMASK_DTIMEXP 0x00008000
89#define GREG_IMASK_RXTOHOST 0x00010000
90#define GREG_IMASK_NORXD 0x00020000
91#define GREG_IMASK_RXERR 0x00040000
92#define GREG_IMASK_RXLATERR 0x00080000
93#define GREG_IMASK_RXPERR 0x00100000
94#define GREG_IMASK_RXTERR 0x00200000
95#define GREG_IMASK_EOPERR 0x00400000
96#define GREG_IMASK_MIFIRQ 0x00800000
97#define GREG_IMASK_HOSTTOTX 0x01000000
98#define GREG_IMASK_TXALL 0x02000000
99#define GREG_IMASK_TXEACK 0x04000000
100#define GREG_IMASK_TXLERR 0x08000000
101#define GREG_IMASK_TXPERR 0x10000000
102#define GREG_IMASK_TXTERR 0x20000000
103#define GREG_IMASK_SLVERR 0x40000000
104#define GREG_IMASK_SLVPERR 0x80000000
105
106
107#define ETX_PENDING 0x00UL
108#define ETX_CFG 0x04UL
109#define ETX_RING 0x08UL
110#define ETX_BBASE 0x0cUL
111#define ETX_BDISP 0x10UL
112#define ETX_FIFOWPTR 0x14UL
113#define ETX_FIFOSWPTR 0x18UL
114#define ETX_FIFORPTR 0x1cUL
115#define ETX_FIFOSRPTR 0x20UL
116#define ETX_FIFOPCNT 0x24UL
117#define ETX_SMACHINE 0x28UL
118#define ETX_RSIZE 0x2cUL
119#define ETX_BPTR 0x30UL
120#define ETX_REG_SIZE 0x34UL
121
122
123#define ETX_TP_DMAWAKEUP 0x00000001
124
125
126#define ETX_CFG_DMAENABLE 0x00000001
127#define ETX_CFG_FIFOTHRESH 0x000003fe
128#define ETX_CFG_IRQDAFTER 0x00000400
129#define ETX_CFG_IRQDBEFORE 0x00000000
130
131#define ETX_RSIZE_SHIFT 4
132
133
134#define ERX_CFG 0x00UL
135#define ERX_RING 0x04UL
136#define ERX_BPTR 0x08UL
137#define ERX_FIFOWPTR 0x0cUL
138#define ERX_FIFOSWPTR 0x10UL
139#define ERX_FIFORPTR 0x14UL
140#define ERX_FIFOSRPTR 0x18UL
141#define ERX_SMACHINE 0x1cUL
142#define ERX_REG_SIZE 0x20UL
143
144
145#define ERX_CFG_DMAENABLE 0x00000001
146#define ERX_CFG_RESV1 0x00000006
147#define ERX_CFG_BYTEOFFSET 0x00000038
148#define ERX_CFG_RESV2 0x000001c0
149#define ERX_CFG_SIZE32 0x00000000
150#define ERX_CFG_SIZE64 0x00000200
151#define ERX_CFG_SIZE128 0x00000400
152#define ERX_CFG_SIZE256 0x00000600
153#define ERX_CFG_RESV3 0x0000f800
154#define ERX_CFG_CSUMSTART 0x007f0000
155
156
157
158#define BMAC_XIFCFG 0x0000UL
159
160#define BMAC_TXSWRESET 0x208UL
161#define BMAC_TXCFG 0x20cUL
162#define BMAC_IGAP1 0x210UL
163#define BMAC_IGAP2 0x214UL
164#define BMAC_ALIMIT 0x218UL
165#define BMAC_STIME 0x21cUL
166#define BMAC_PLEN 0x220UL
167#define BMAC_PPAT 0x224UL
168#define BMAC_TXSDELIM 0x228UL
169#define BMAC_JSIZE 0x22cUL
170#define BMAC_TXMAX 0x230UL
171#define BMAC_TXMIN 0x234UL
172#define BMAC_PATTEMPT 0x238UL
173#define BMAC_DTCTR 0x23cUL
174#define BMAC_NCCTR 0x240UL
175#define BMAC_FCCTR 0x244UL
176#define BMAC_EXCTR 0x248UL
177#define BMAC_LTCTR 0x24cUL
178#define BMAC_RSEED 0x250UL
179#define BMAC_TXSMACHINE 0x254UL
180
181#define BMAC_RXSWRESET 0x308UL
182#define BMAC_RXCFG 0x30cUL
183#define BMAC_RXMAX 0x310UL
184#define BMAC_RXMIN 0x314UL
185#define BMAC_MACADDR2 0x318UL
186#define BMAC_MACADDR1 0x31cUL
187#define BMAC_MACADDR0 0x320UL
188#define BMAC_FRCTR 0x324UL
189#define BMAC_GLECTR 0x328UL
190#define BMAC_UNALECTR 0x32cUL
191#define BMAC_RCRCECTR 0x330UL
192#define BMAC_RXSMACHINE 0x334UL
193#define BMAC_RXCVALID 0x338UL
194
195#define BMAC_HTABLE3 0x340UL
196#define BMAC_HTABLE2 0x344UL
197#define BMAC_HTABLE1 0x348UL
198#define BMAC_HTABLE0 0x34cUL
199#define BMAC_AFILTER2 0x350UL
200#define BMAC_AFILTER1 0x354UL
201#define BMAC_AFILTER0 0x358UL
202#define BMAC_AFMASK 0x35cUL
203#define BMAC_REG_SIZE 0x360UL
204
205
206#define BIGMAC_XCFG_ODENABLE 0x00000001
207#define BIGMAC_XCFG_XLBACK 0x00000002
208#define BIGMAC_XCFG_MLBACK 0x00000004
209#define BIGMAC_XCFG_MIIDISAB 0x00000008
210#define BIGMAC_XCFG_SQENABLE 0x00000010
211#define BIGMAC_XCFG_SQETWIN 0x000003e0
212#define BIGMAC_XCFG_LANCE 0x00000010
213#define BIGMAC_XCFG_LIPG0 0x000003e0
214
215
216#define BIGMAC_TXCFG_ENABLE 0x00000001
217#define BIGMAC_TXCFG_SMODE 0x00000020
218#define BIGMAC_TXCFG_CIGN 0x00000040
219#define BIGMAC_TXCFG_FCSOFF 0x00000080
220#define BIGMAC_TXCFG_DBACKOFF 0x00000100
221#define BIGMAC_TXCFG_FULLDPLX 0x00000200
222#define BIGMAC_TXCFG_DGIVEUP 0x00000400
223
224
225#define BIGMAC_RXCFG_ENABLE 0x00000001
226#define BIGMAC_RXCFG_PSTRIP 0x00000020
227#define BIGMAC_RXCFG_PMISC 0x00000040
228#define BIGMAC_RXCFG_DERR 0x00000080
229#define BIGMAC_RXCFG_DCRCS 0x00000100
230#define BIGMAC_RXCFG_REJME 0x00000200
231#define BIGMAC_RXCFG_PGRP 0x00000400
232#define BIGMAC_RXCFG_HENABLE 0x00000800
233#define BIGMAC_RXCFG_AENABLE 0x00001000
234
235
236#define TCVR_BBCLOCK 0x00UL
237#define TCVR_BBDATA 0x04UL
238#define TCVR_BBOENAB 0x08UL
239#define TCVR_FRAME 0x0cUL
240#define TCVR_CFG 0x10UL
241#define TCVR_IMASK 0x14UL
242#define TCVR_STATUS 0x18UL
243#define TCVR_SMACHINE 0x1cUL
244#define TCVR_REG_SIZE 0x20UL
245
246
247#define FRAME_WRITE 0x50020000
248#define FRAME_READ 0x60020000
249
250
251#define TCV_CFG_PSELECT 0x00000001
252#define TCV_CFG_PENABLE 0x00000002
253#define TCV_CFG_BENABLE 0x00000004
254#define TCV_CFG_PREGADDR 0x000000f8
255#define TCV_CFG_MDIO0 0x00000100
256#define TCV_CFG_MDIO1 0x00000200
257#define TCV_CFG_PDADDR 0x00007c00
258
259
260#define TCV_PADDR_ETX 0
261#define TCV_PADDR_ITX 1
262
263
264#define TCV_STAT_BASIC 0xffff0000
265#define TCV_STAT_NORMAL 0x0000ffff
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281
282#define DP83840_CSCONFIG 0x17
283
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285#define CSCONFIG_RESV1 0x0001
286#define CSCONFIG_LED4 0x0002
287#define CSCONFIG_LED1 0x0004
288#define CSCONFIG_RESV2 0x0008
289#define CSCONFIG_TCVDISAB 0x0010
290#define CSCONFIG_DFBYPASS 0x0020
291#define CSCONFIG_GLFORCE 0x0040
292#define CSCONFIG_CLKTRISTATE 0x0080
293#define CSCONFIG_RESV3 0x0700
294#define CSCONFIG_ENCODE 0x0800
295#define CSCONFIG_RENABLE 0x1000
296#define CSCONFIG_TCDISABLE 0x2000
297#define CSCONFIG_RESV4 0x4000
298#define CSCONFIG_NDISABLE 0x8000
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305
306typedef u32 __bitwise hme32;
307
308struct happy_meal_rxd {
309 hme32 rx_flags;
310 hme32 rx_addr;
311};
312
313#define RXFLAG_OWN 0x80000000
314#define RXFLAG_OVERFLOW 0x40000000
315#define RXFLAG_SIZE 0x3fff0000
316#define RXFLAG_CSUM 0x0000ffff
317
318struct happy_meal_txd {
319 hme32 tx_flags;
320 hme32 tx_addr;
321};
322
323#define TXFLAG_OWN 0x80000000
324#define TXFLAG_SOP 0x40000000
325#define TXFLAG_EOP 0x20000000
326#define TXFLAG_CSENABLE 0x10000000
327#define TXFLAG_CSLOCATION 0x0ff00000
328#define TXFLAG_CSBUFBEGIN 0x000fc000
329#define TXFLAG_SIZE 0x00003fff
330
331#define TX_RING_SIZE 32
332#define RX_RING_SIZE 32
333
334#if (TX_RING_SIZE < 16 || TX_RING_SIZE > 256 || (TX_RING_SIZE % 16) != 0)
335#error TX_RING_SIZE holds illegal value
336#endif
337
338#define TX_RING_MAXSIZE 256
339#define RX_RING_MAXSIZE 256
340
341
342#if (RX_RING_SIZE == 32)
343#define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE32|((14/2)<<16))
344#else
345#if (RX_RING_SIZE == 64)
346#define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE64|((14/2)<<16))
347#else
348#if (RX_RING_SIZE == 128)
349#define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE128|((14/2)<<16))
350#else
351#if (RX_RING_SIZE == 256)
352#define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE256|((14/2)<<16))
353#else
354#error RX_RING_SIZE holds illegal value
355#endif
356#endif
357#endif
358#endif
359
360#define NEXT_RX(num) (((num) + 1) & (RX_RING_SIZE - 1))
361#define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1))
362#define PREV_RX(num) (((num) - 1) & (RX_RING_SIZE - 1))
363#define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1))
364
365#define TX_BUFFS_AVAIL(hp) \
366 (((hp)->tx_old <= (hp)->tx_new) ? \
367 (hp)->tx_old + (TX_RING_SIZE - 1) - (hp)->tx_new : \
368 (hp)->tx_old - (hp)->tx_new - 1)
369
370#define RX_OFFSET 2
371#define RX_BUF_ALLOC_SIZE (1546 + RX_OFFSET + 64)
372
373#define RX_COPY_THRESHOLD 256
374
375struct hmeal_init_block {
376 struct happy_meal_rxd happy_meal_rxd[RX_RING_MAXSIZE];
377 struct happy_meal_txd happy_meal_txd[TX_RING_MAXSIZE];
378};
379
380#define hblock_offset(mem, elem) \
381((__u32)((unsigned long)(&(((struct hmeal_init_block *)0)->mem[elem]))))
382
383
384enum happy_transceiver {
385 external = 0,
386 internal = 1,
387 none = 2,
388};
389
390
391enum happy_timer_state {
392 arbwait = 0,
393 lupwait = 1,
394 ltrywait = 2,
395 asleep = 3,
396};
397
398struct quattro;
399
400
401struct happy_meal {
402 void __iomem *gregs;
403 struct hmeal_init_block *happy_block;
404
405#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
406 u32 (*read_desc32)(hme32 *);
407 void (*write_txd)(struct happy_meal_txd *, u32, u32);
408 void (*write_rxd)(struct happy_meal_rxd *, u32, u32);
409#endif
410
411
412 void *happy_dev;
413 struct device *dma_dev;
414
415 spinlock_t happy_lock;
416
417 struct sk_buff *rx_skbs[RX_RING_SIZE];
418 struct sk_buff *tx_skbs[TX_RING_SIZE];
419
420 int rx_new, tx_new, rx_old, tx_old;
421
422#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
423 u32 (*read32)(void __iomem *);
424 void (*write32)(void __iomem *, u32);
425#endif
426
427 void __iomem *etxregs;
428 void __iomem *erxregs;
429 void __iomem *bigmacregs;
430 void __iomem *tcvregs;
431
432 dma_addr_t hblock_dvma;
433 unsigned int happy_flags;
434 int irq;
435 enum happy_transceiver tcvr_type;
436 unsigned int happy_bursts;
437 unsigned int paddr;
438 unsigned short hm_revision;
439 unsigned short sw_bmcr;
440 unsigned short sw_bmsr;
441 unsigned short sw_physid1;
442 unsigned short sw_physid2;
443 unsigned short sw_advertise;
444 unsigned short sw_lpa;
445 unsigned short sw_expansion;
446 unsigned short sw_csconfig;
447 unsigned int auto_speed;
448 unsigned int forced_speed;
449 unsigned int poll_data;
450 unsigned int poll_flag;
451 unsigned int linkcheck;
452 unsigned int lnkup;
453 unsigned int lnkdown;
454 unsigned int lnkcnt;
455 struct timer_list happy_timer;
456 enum happy_timer_state timer_state;
457 unsigned int timer_ticks;
458
459 struct net_device *dev;
460 struct quattro *qfe_parent;
461 int qfe_ent;
462};
463
464
465#define HFLAG_POLL 0x00000001
466#define HFLAG_FENABLE 0x00000002
467#define HFLAG_LANCE 0x00000004
468#define HFLAG_RXENABLE 0x00000008
469#define HFLAG_AUTO 0x00000010
470#define HFLAG_FULL 0x00000020
471#define HFLAG_MACFULL 0x00000040
472#define HFLAG_POLLENABLE 0x00000080
473#define HFLAG_RXCV 0x00000100
474#define HFLAG_INIT 0x00000200
475#define HFLAG_LINKUP 0x00000400
476#define HFLAG_PCI 0x00000800
477#define HFLAG_QUATTRO 0x00001000
478
479#define HFLAG_20_21 (HFLAG_POLLENABLE | HFLAG_FENABLE)
480#define HFLAG_NOT_A0 (HFLAG_POLLENABLE | HFLAG_FENABLE | HFLAG_LANCE | HFLAG_RXCV)
481
482
483struct quattro {
484 struct net_device *happy_meals[4];
485
486
487 void *quattro_dev;
488
489 struct quattro *next;
490
491
492#ifdef CONFIG_SBUS
493 struct linux_prom_ranges ranges[8];
494#endif
495 int nranges;
496};
497
498
499#define ALIGNED_RX_SKB_ADDR(addr) \
500 ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
501#define happy_meal_alloc_skb(__length, __gfp_flags) \
502({ struct sk_buff *__skb; \
503 __skb = alloc_skb((__length) + 64, (__gfp_flags)); \
504 if(__skb) { \
505 int __offset = (int) ALIGNED_RX_SKB_ADDR(__skb->data); \
506 if(__offset) \
507 skb_reserve(__skb, __offset); \
508 } \
509 __skb; \
510})
511
512#endif
513