1
2
3
4
5#include "main.h"
6#include "regd.h"
7#include "fw.h"
8#include "ps.h"
9#include "sec.h"
10#include "mac.h"
11#include "coex.h"
12#include "phy.h"
13#include "reg.h"
14#include "efuse.h"
15#include "tx.h"
16#include "debug.h"
17#include "bf.h"
18
19bool rtw_disable_lps_deep_mode;
20EXPORT_SYMBOL(rtw_disable_lps_deep_mode);
21bool rtw_bf_support = true;
22unsigned int rtw_debug_mask;
23EXPORT_SYMBOL(rtw_debug_mask);
24
25module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644);
26module_param_named(support_bf, rtw_bf_support, bool, 0644);
27module_param_named(debug_mask, rtw_debug_mask, uint, 0644);
28
29MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS");
30MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support");
31MODULE_PARM_DESC(debug_mask, "Debugging mask");
32
33static struct ieee80211_channel rtw_channeltable_2g[] = {
34 {.center_freq = 2412, .hw_value = 1,},
35 {.center_freq = 2417, .hw_value = 2,},
36 {.center_freq = 2422, .hw_value = 3,},
37 {.center_freq = 2427, .hw_value = 4,},
38 {.center_freq = 2432, .hw_value = 5,},
39 {.center_freq = 2437, .hw_value = 6,},
40 {.center_freq = 2442, .hw_value = 7,},
41 {.center_freq = 2447, .hw_value = 8,},
42 {.center_freq = 2452, .hw_value = 9,},
43 {.center_freq = 2457, .hw_value = 10,},
44 {.center_freq = 2462, .hw_value = 11,},
45 {.center_freq = 2467, .hw_value = 12,},
46 {.center_freq = 2472, .hw_value = 13,},
47 {.center_freq = 2484, .hw_value = 14,},
48};
49
50static struct ieee80211_channel rtw_channeltable_5g[] = {
51 {.center_freq = 5180, .hw_value = 36,},
52 {.center_freq = 5200, .hw_value = 40,},
53 {.center_freq = 5220, .hw_value = 44,},
54 {.center_freq = 5240, .hw_value = 48,},
55 {.center_freq = 5260, .hw_value = 52,},
56 {.center_freq = 5280, .hw_value = 56,},
57 {.center_freq = 5300, .hw_value = 60,},
58 {.center_freq = 5320, .hw_value = 64,},
59 {.center_freq = 5500, .hw_value = 100,},
60 {.center_freq = 5520, .hw_value = 104,},
61 {.center_freq = 5540, .hw_value = 108,},
62 {.center_freq = 5560, .hw_value = 112,},
63 {.center_freq = 5580, .hw_value = 116,},
64 {.center_freq = 5600, .hw_value = 120,},
65 {.center_freq = 5620, .hw_value = 124,},
66 {.center_freq = 5640, .hw_value = 128,},
67 {.center_freq = 5660, .hw_value = 132,},
68 {.center_freq = 5680, .hw_value = 136,},
69 {.center_freq = 5700, .hw_value = 140,},
70 {.center_freq = 5720, .hw_value = 144,},
71 {.center_freq = 5745, .hw_value = 149,},
72 {.center_freq = 5765, .hw_value = 153,},
73 {.center_freq = 5785, .hw_value = 157,},
74 {.center_freq = 5805, .hw_value = 161,},
75 {.center_freq = 5825, .hw_value = 165,
76 .flags = IEEE80211_CHAN_NO_HT40MINUS},
77};
78
79static struct ieee80211_rate rtw_ratetable[] = {
80 {.bitrate = 10, .hw_value = 0x00,},
81 {.bitrate = 20, .hw_value = 0x01,},
82 {.bitrate = 55, .hw_value = 0x02,},
83 {.bitrate = 110, .hw_value = 0x03,},
84 {.bitrate = 60, .hw_value = 0x04,},
85 {.bitrate = 90, .hw_value = 0x05,},
86 {.bitrate = 120, .hw_value = 0x06,},
87 {.bitrate = 180, .hw_value = 0x07,},
88 {.bitrate = 240, .hw_value = 0x08,},
89 {.bitrate = 360, .hw_value = 0x09,},
90 {.bitrate = 480, .hw_value = 0x0a,},
91 {.bitrate = 540, .hw_value = 0x0b,},
92};
93
94u16 rtw_desc_to_bitrate(u8 desc_rate)
95{
96 struct ieee80211_rate rate;
97
98 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n"))
99 return 0;
100
101 rate = rtw_ratetable[desc_rate];
102
103 return rate.bitrate;
104}
105
106static struct ieee80211_supported_band rtw_band_2ghz = {
107 .band = NL80211_BAND_2GHZ,
108
109 .channels = rtw_channeltable_2g,
110 .n_channels = ARRAY_SIZE(rtw_channeltable_2g),
111
112 .bitrates = rtw_ratetable,
113 .n_bitrates = ARRAY_SIZE(rtw_ratetable),
114
115 .ht_cap = {0},
116 .vht_cap = {0},
117};
118
119static struct ieee80211_supported_band rtw_band_5ghz = {
120 .band = NL80211_BAND_5GHZ,
121
122 .channels = rtw_channeltable_5g,
123 .n_channels = ARRAY_SIZE(rtw_channeltable_5g),
124
125
126 .bitrates = rtw_ratetable + 4,
127 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4,
128
129 .ht_cap = {0},
130 .vht_cap = {0},
131};
132
133struct rtw_watch_dog_iter_data {
134 struct rtw_dev *rtwdev;
135 struct rtw_vif *rtwvif;
136};
137
138static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif)
139{
140 struct rtw_bf_info *bf_info = &rtwdev->bf_info;
141 u8 fix_rate_enable = 0;
142 u8 new_csi_rate_idx;
143
144 if (rtwvif->bfee.role != RTW_BFEE_SU &&
145 rtwvif->bfee.role != RTW_BFEE_MU)
146 return;
147
148 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi,
149 bf_info->cur_csi_rpt_rate,
150 fix_rate_enable, &new_csi_rate_idx);
151
152 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
153 bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
154}
155
156static void rtw_vif_watch_dog_iter(void *data, u8 *mac,
157 struct ieee80211_vif *vif)
158{
159 struct rtw_watch_dog_iter_data *iter_data = data;
160 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
161
162 if (vif->type == NL80211_IFTYPE_STATION)
163 if (vif->bss_conf.assoc)
164 iter_data->rtwvif = rtwvif;
165
166 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif);
167
168 rtwvif->stats.tx_unicast = 0;
169 rtwvif->stats.rx_unicast = 0;
170 rtwvif->stats.tx_cnt = 0;
171 rtwvif->stats.rx_cnt = 0;
172}
173
174
175
176
177static void rtw_watch_dog_work(struct work_struct *work)
178{
179 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
180 watch_dog_work.work);
181 struct rtw_traffic_stats *stats = &rtwdev->stats;
182 struct rtw_watch_dog_iter_data data = {};
183 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
184 bool ps_active;
185
186 mutex_lock(&rtwdev->mutex);
187
188 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags))
189 goto unlock;
190
191 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
192 RTW_WATCH_DOG_DELAY_TIME);
193
194 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100)
195 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
196 else
197 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
198
199 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags))
200 rtw_coex_wl_status_change_notify(rtwdev, 0);
201
202 if (stats->tx_cnt > RTW_LPS_THRESHOLD ||
203 stats->rx_cnt > RTW_LPS_THRESHOLD)
204 ps_active = true;
205 else
206 ps_active = false;
207
208 ewma_tp_add(&stats->tx_ewma_tp,
209 (u32)(stats->tx_unicast >> RTW_TP_SHIFT));
210 ewma_tp_add(&stats->rx_ewma_tp,
211 (u32)(stats->rx_unicast >> RTW_TP_SHIFT));
212 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
213 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
214
215
216 stats->tx_unicast = 0;
217 stats->rx_unicast = 0;
218 stats->tx_cnt = 0;
219 stats->rx_cnt = 0;
220
221 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
222 goto unlock;
223
224
225 rtw_leave_lps(rtwdev);
226
227 rtw_phy_dynamic_mechanism(rtwdev);
228
229 data.rtwdev = rtwdev;
230
231 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data);
232
233
234
235
236
237
238
239
240
241
242 if (rtwdev->ps_enabled && data.rtwvif && !ps_active)
243 rtw_enter_lps(rtwdev, data.rtwvif->port);
244
245 rtwdev->watch_dog_cnt++;
246
247unlock:
248 mutex_unlock(&rtwdev->mutex);
249}
250
251static void rtw_c2h_work(struct work_struct *work)
252{
253 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work);
254 struct sk_buff *skb, *tmp;
255
256 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
257 skb_unlink(skb, &rtwdev->c2h_queue);
258 rtw_fw_c2h_cmd_handle(rtwdev, skb);
259 dev_kfree_skb_any(skb);
260 }
261}
262
263static u8 rtw_acquire_macid(struct rtw_dev *rtwdev)
264{
265 unsigned long mac_id;
266
267 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM);
268 if (mac_id < RTW_MAX_MAC_ID_NUM)
269 set_bit(mac_id, rtwdev->mac_id_map);
270
271 return mac_id;
272}
273
274int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
275 struct ieee80211_vif *vif)
276{
277 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
278 int i;
279
280 si->mac_id = rtw_acquire_macid(rtwdev);
281 if (si->mac_id >= RTW_MAX_MAC_ID_NUM)
282 return -ENOSPC;
283
284 si->sta = sta;
285 si->vif = vif;
286 si->init_ra_lv = 1;
287 ewma_rssi_init(&si->avg_rssi);
288 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
289 rtw_txq_init(rtwdev, sta->txq[i]);
290
291 rtw_update_sta_info(rtwdev, si);
292 rtw_fw_media_status_report(rtwdev, si->mac_id, true);
293
294 rtwdev->sta_cnt++;
295 rtw_info(rtwdev, "sta %pM joined with macid %d\n",
296 sta->addr, si->mac_id);
297
298 return 0;
299}
300
301void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
302 bool fw_exist)
303{
304 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
305 int i;
306
307 rtw_release_macid(rtwdev, si->mac_id);
308 if (fw_exist)
309 rtw_fw_media_status_report(rtwdev, si->mac_id, false);
310
311 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
312 rtw_txq_cleanup(rtwdev, sta->txq[i]);
313
314 kfree(si->mask);
315
316 rtwdev->sta_cnt--;
317 rtw_info(rtwdev, "sta %pM with macid %d left\n",
318 sta->addr, si->mac_id);
319}
320
321static bool rtw_fw_dump_crash_log(struct rtw_dev *rtwdev)
322{
323 u32 size = rtwdev->chip->fw_rxff_size;
324 u32 *buf;
325 u8 seq;
326 bool ret = true;
327
328 buf = vmalloc(size);
329 if (!buf)
330 goto exit;
331
332 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) {
333 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n");
334 goto free_buf;
335 }
336
337 if (GET_FW_DUMP_LEN(buf) == 0) {
338 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n");
339 goto free_buf;
340 }
341
342 seq = GET_FW_DUMP_SEQ(buf);
343 if (seq > 0 && seq != (rtwdev->fw.prev_dump_seq + 1)) {
344 rtw_dbg(rtwdev, RTW_DBG_FW,
345 "fw crash dump's seq is wrong: %d\n", seq);
346 goto free_buf;
347 }
348 if (seq == 0 &&
349 (GET_FW_DUMP_TLV_TYPE(buf) != FW_CD_TYPE ||
350 GET_FW_DUMP_TLV_LEN(buf) != FW_CD_LEN ||
351 GET_FW_DUMP_TLV_VAL(buf) != FW_CD_VAL)) {
352 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's tlv is wrong\n");
353 goto free_buf;
354 }
355
356 print_hex_dump_bytes("rtw88 fw dump: ", DUMP_PREFIX_OFFSET, buf, size);
357
358 if (GET_FW_DUMP_MORE(buf) == 1) {
359 rtwdev->fw.prev_dump_seq = seq;
360 ret = false;
361 }
362
363free_buf:
364 vfree(buf);
365exit:
366 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0);
367
368 return ret;
369}
370
371void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
372 struct ieee80211_bss_conf *conf)
373{
374 if (conf && conf->assoc) {
375 rtwvif->aid = conf->aid;
376 rtwvif->net_type = RTW_NET_MGD_LINKED;
377 } else {
378 rtwvif->aid = 0;
379 rtwvif->net_type = RTW_NET_NO_LINK;
380 }
381}
382
383static void rtw_reset_key_iter(struct ieee80211_hw *hw,
384 struct ieee80211_vif *vif,
385 struct ieee80211_sta *sta,
386 struct ieee80211_key_conf *key,
387 void *data)
388{
389 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
390 struct rtw_sec_desc *sec = &rtwdev->sec;
391
392 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx);
393}
394
395static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta)
396{
397 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
398
399 if (rtwdev->sta_cnt == 0) {
400 rtw_warn(rtwdev, "sta count before reset should not be 0\n");
401 return;
402 }
403 rtw_sta_remove(rtwdev, sta, false);
404}
405
406static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
407{
408 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
409 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
410
411 rtw_bf_disassoc(rtwdev, vif, NULL);
412 rtw_vif_assoc_changed(rtwvif, NULL);
413 rtw_txq_cleanup(rtwdev, vif->txq);
414}
415
416void rtw_fw_recovery(struct rtw_dev *rtwdev)
417{
418 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags))
419 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work);
420}
421
422static void rtw_fw_recovery_work(struct work_struct *work)
423{
424 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
425 fw_recovery_work);
426
427
428
429
430
431
432 if (!rtw_fw_dump_crash_log(rtwdev)) {
433 rtw_write8(rtwdev, REG_HRCV_MSG, 1);
434 return;
435 }
436 rtwdev->fw.prev_dump_seq = 0;
437
438 WARN(1, "firmware crash, start reset and recover\n");
439
440 mutex_lock(&rtwdev->mutex);
441
442 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags);
443 rcu_read_lock();
444 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev);
445 rcu_read_unlock();
446 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev);
447 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev);
448 rtw_enter_ips(rtwdev);
449
450 mutex_unlock(&rtwdev->mutex);
451
452 ieee80211_restart_hw(rtwdev->hw);
453}
454
455struct rtw_txq_ba_iter_data {
456};
457
458static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta)
459{
460 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
461 int ret;
462 u8 tid;
463
464 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
465 while (tid != IEEE80211_NUM_TIDS) {
466 clear_bit(tid, si->tid_ba);
467 ret = ieee80211_start_tx_ba_session(sta, tid, 0);
468 if (ret == -EINVAL) {
469 struct ieee80211_txq *txq;
470 struct rtw_txq *rtwtxq;
471
472 txq = sta->txq[tid];
473 rtwtxq = (struct rtw_txq *)txq->drv_priv;
474 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags);
475 }
476
477 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
478 }
479}
480
481static void rtw_txq_ba_work(struct work_struct *work)
482{
483 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work);
484 struct rtw_txq_ba_iter_data data;
485
486 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data);
487}
488
489void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
490 struct rtw_channel_params *chan_params)
491{
492 struct ieee80211_channel *channel = chandef->chan;
493 enum nl80211_chan_width width = chandef->width;
494 u8 *cch_by_bw = chan_params->cch_by_bw;
495 u32 primary_freq, center_freq;
496 u8 center_chan;
497 u8 bandwidth = RTW_CHANNEL_WIDTH_20;
498 u8 primary_chan_idx = 0;
499 u8 i;
500
501 center_chan = channel->hw_value;
502 primary_freq = channel->center_freq;
503 center_freq = chandef->center_freq1;
504
505
506 cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value;
507
508 switch (width) {
509 case NL80211_CHAN_WIDTH_20_NOHT:
510 case NL80211_CHAN_WIDTH_20:
511 bandwidth = RTW_CHANNEL_WIDTH_20;
512 primary_chan_idx = RTW_SC_DONT_CARE;
513 break;
514 case NL80211_CHAN_WIDTH_40:
515 bandwidth = RTW_CHANNEL_WIDTH_40;
516 if (primary_freq > center_freq) {
517 primary_chan_idx = RTW_SC_20_UPPER;
518 center_chan -= 2;
519 } else {
520 primary_chan_idx = RTW_SC_20_LOWER;
521 center_chan += 2;
522 }
523 break;
524 case NL80211_CHAN_WIDTH_80:
525 bandwidth = RTW_CHANNEL_WIDTH_80;
526 if (primary_freq > center_freq) {
527 if (primary_freq - center_freq == 10) {
528 primary_chan_idx = RTW_SC_20_UPPER;
529 center_chan -= 2;
530 } else {
531 primary_chan_idx = RTW_SC_20_UPMOST;
532 center_chan -= 6;
533 }
534
535
536
537 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4;
538 } else {
539 if (center_freq - primary_freq == 10) {
540 primary_chan_idx = RTW_SC_20_LOWER;
541 center_chan += 2;
542 } else {
543 primary_chan_idx = RTW_SC_20_LOWEST;
544 center_chan += 6;
545 }
546
547
548
549 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4;
550 }
551 break;
552 default:
553 center_chan = 0;
554 break;
555 }
556
557 chan_params->center_chan = center_chan;
558 chan_params->bandwidth = bandwidth;
559 chan_params->primary_chan_idx = primary_chan_idx;
560
561
562 cch_by_bw[bandwidth] = center_chan;
563
564 for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++)
565 cch_by_bw[i] = 0;
566}
567
568void rtw_set_channel(struct rtw_dev *rtwdev)
569{
570 struct ieee80211_hw *hw = rtwdev->hw;
571 struct rtw_hal *hal = &rtwdev->hal;
572 struct rtw_chip_info *chip = rtwdev->chip;
573 struct rtw_channel_params ch_param;
574 u8 center_chan, bandwidth, primary_chan_idx;
575 u8 i;
576
577 rtw_get_channel_params(&hw->conf.chandef, &ch_param);
578 if (WARN(ch_param.center_chan == 0, "Invalid channel\n"))
579 return;
580
581 center_chan = ch_param.center_chan;
582 bandwidth = ch_param.bandwidth;
583 primary_chan_idx = ch_param.primary_chan_idx;
584
585 hal->current_band_width = bandwidth;
586 hal->current_channel = center_chan;
587 hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G;
588
589 for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++)
590 hal->cch_by_bw[i] = ch_param.cch_by_bw[i];
591
592 chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx);
593
594 if (hal->current_band_type == RTW_BAND_5G) {
595 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G);
596 } else {
597 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
598 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G);
599 else
600 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN);
601 }
602
603 rtw_phy_set_tx_power_level(rtwdev, center_chan);
604
605
606
607
608
609 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
610 rtwdev->need_rfk = true;
611}
612
613void rtw_chip_prepare_tx(struct rtw_dev *rtwdev)
614{
615 struct rtw_chip_info *chip = rtwdev->chip;
616
617 if (rtwdev->need_rfk) {
618 rtwdev->need_rfk = false;
619 chip->ops->phy_calibration(rtwdev);
620 }
621}
622
623static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr)
624{
625 int i;
626
627 for (i = 0; i < ETH_ALEN; i++)
628 rtw_write8(rtwdev, start + i, addr[i]);
629}
630
631void rtw_vif_port_config(struct rtw_dev *rtwdev,
632 struct rtw_vif *rtwvif,
633 u32 config)
634{
635 u32 addr, mask;
636
637 if (config & PORT_SET_MAC_ADDR) {
638 addr = rtwvif->conf->mac_addr.addr;
639 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr);
640 }
641 if (config & PORT_SET_BSSID) {
642 addr = rtwvif->conf->bssid.addr;
643 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid);
644 }
645 if (config & PORT_SET_NET_TYPE) {
646 addr = rtwvif->conf->net_type.addr;
647 mask = rtwvif->conf->net_type.mask;
648 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type);
649 }
650 if (config & PORT_SET_AID) {
651 addr = rtwvif->conf->aid.addr;
652 mask = rtwvif->conf->aid.mask;
653 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid);
654 }
655 if (config & PORT_SET_BCN_CTRL) {
656 addr = rtwvif->conf->bcn_ctrl.addr;
657 mask = rtwvif->conf->bcn_ctrl.mask;
658 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl);
659 }
660}
661
662static u8 hw_bw_cap_to_bitamp(u8 bw_cap)
663{
664 u8 bw = 0;
665
666 switch (bw_cap) {
667 case EFUSE_HW_CAP_IGNORE:
668 case EFUSE_HW_CAP_SUPP_BW80:
669 bw |= BIT(RTW_CHANNEL_WIDTH_80);
670 fallthrough;
671 case EFUSE_HW_CAP_SUPP_BW40:
672 bw |= BIT(RTW_CHANNEL_WIDTH_40);
673 fallthrough;
674 default:
675 bw |= BIT(RTW_CHANNEL_WIDTH_20);
676 break;
677 }
678
679 return bw;
680}
681
682static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num)
683{
684 struct rtw_hal *hal = &rtwdev->hal;
685 struct rtw_chip_info *chip = rtwdev->chip;
686
687 if (hw_ant_num == EFUSE_HW_CAP_IGNORE ||
688 hw_ant_num >= hal->rf_path_num)
689 return;
690
691 switch (hw_ant_num) {
692 case 1:
693 hal->rf_type = RF_1T1R;
694 hal->rf_path_num = 1;
695 if (!chip->fix_rf_phy_num)
696 hal->rf_phy_num = hal->rf_path_num;
697 hal->antenna_tx = BB_PATH_A;
698 hal->antenna_rx = BB_PATH_A;
699 break;
700 default:
701 WARN(1, "invalid hw configuration from efuse\n");
702 break;
703 }
704}
705
706static u64 get_vht_ra_mask(struct ieee80211_sta *sta)
707{
708 u64 ra_mask = 0;
709 u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map);
710 u8 vht_mcs_cap;
711 int i, nss;
712
713
714 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) {
715 vht_mcs_cap = mcs_map & 0x3;
716 switch (vht_mcs_cap) {
717 case 2:
718 ra_mask |= 0x3ffULL << nss;
719 break;
720 case 1:
721 ra_mask |= 0x1ffULL << nss;
722 break;
723 case 0:
724 ra_mask |= 0x0ffULL << nss;
725 break;
726 default:
727 break;
728 }
729 }
730
731 return ra_mask;
732}
733
734static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num)
735{
736 u8 rate_id = 0;
737
738 switch (wireless_set) {
739 case WIRELESS_CCK:
740 rate_id = RTW_RATEID_B_20M;
741 break;
742 case WIRELESS_OFDM:
743 rate_id = RTW_RATEID_G;
744 break;
745 case WIRELESS_CCK | WIRELESS_OFDM:
746 rate_id = RTW_RATEID_BG;
747 break;
748 case WIRELESS_OFDM | WIRELESS_HT:
749 if (tx_num == 1)
750 rate_id = RTW_RATEID_GN_N1SS;
751 else if (tx_num == 2)
752 rate_id = RTW_RATEID_GN_N2SS;
753 else if (tx_num == 3)
754 rate_id = RTW_RATEID_ARFR5_N_3SS;
755 break;
756 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT:
757 if (bw_mode == RTW_CHANNEL_WIDTH_40) {
758 if (tx_num == 1)
759 rate_id = RTW_RATEID_BGN_40M_1SS;
760 else if (tx_num == 2)
761 rate_id = RTW_RATEID_BGN_40M_2SS;
762 else if (tx_num == 3)
763 rate_id = RTW_RATEID_ARFR5_N_3SS;
764 else if (tx_num == 4)
765 rate_id = RTW_RATEID_ARFR7_N_4SS;
766 } else {
767 if (tx_num == 1)
768 rate_id = RTW_RATEID_BGN_20M_1SS;
769 else if (tx_num == 2)
770 rate_id = RTW_RATEID_BGN_20M_2SS;
771 else if (tx_num == 3)
772 rate_id = RTW_RATEID_ARFR5_N_3SS;
773 else if (tx_num == 4)
774 rate_id = RTW_RATEID_ARFR7_N_4SS;
775 }
776 break;
777 case WIRELESS_OFDM | WIRELESS_VHT:
778 if (tx_num == 1)
779 rate_id = RTW_RATEID_ARFR1_AC_1SS;
780 else if (tx_num == 2)
781 rate_id = RTW_RATEID_ARFR0_AC_2SS;
782 else if (tx_num == 3)
783 rate_id = RTW_RATEID_ARFR4_AC_3SS;
784 else if (tx_num == 4)
785 rate_id = RTW_RATEID_ARFR6_AC_4SS;
786 break;
787 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT:
788 if (bw_mode >= RTW_CHANNEL_WIDTH_80) {
789 if (tx_num == 1)
790 rate_id = RTW_RATEID_ARFR1_AC_1SS;
791 else if (tx_num == 2)
792 rate_id = RTW_RATEID_ARFR0_AC_2SS;
793 else if (tx_num == 3)
794 rate_id = RTW_RATEID_ARFR4_AC_3SS;
795 else if (tx_num == 4)
796 rate_id = RTW_RATEID_ARFR6_AC_4SS;
797 } else {
798 if (tx_num == 1)
799 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS;
800 else if (tx_num == 2)
801 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS;
802 else if (tx_num == 3)
803 rate_id = RTW_RATEID_ARFR4_AC_3SS;
804 else if (tx_num == 4)
805 rate_id = RTW_RATEID_ARFR6_AC_4SS;
806 }
807 break;
808 default:
809 break;
810 }
811
812 return rate_id;
813}
814
815#define RA_MASK_CCK_RATES 0x0000f
816#define RA_MASK_OFDM_RATES 0x00ff0
817#define RA_MASK_HT_RATES_1SS (0xff000ULL << 0)
818#define RA_MASK_HT_RATES_2SS (0xff000ULL << 8)
819#define RA_MASK_HT_RATES_3SS (0xff000ULL << 16)
820#define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \
821 RA_MASK_HT_RATES_2SS | \
822 RA_MASK_HT_RATES_3SS)
823#define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0)
824#define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10)
825#define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20)
826#define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \
827 RA_MASK_VHT_RATES_2SS | \
828 RA_MASK_VHT_RATES_3SS)
829#define RA_MASK_CCK_IN_HT 0x00005
830#define RA_MASK_CCK_IN_VHT 0x00005
831#define RA_MASK_OFDM_IN_VHT 0x00010
832#define RA_MASK_OFDM_IN_HT_2G 0x00010
833#define RA_MASK_OFDM_IN_HT_5G 0x00030
834
835static u64 rtw_update_rate_mask(struct rtw_dev *rtwdev,
836 struct rtw_sta_info *si,
837 u64 ra_mask, bool is_vht_enable,
838 u8 wireless_set)
839{
840 struct rtw_hal *hal = &rtwdev->hal;
841 const struct cfg80211_bitrate_mask *mask = si->mask;
842 u64 cfg_mask = GENMASK_ULL(63, 0);
843 u8 rssi_level, band;
844
845 if (wireless_set != WIRELESS_CCK) {
846 rssi_level = si->rssi_level;
847 if (rssi_level == 0)
848 ra_mask &= 0xffffffffffffffffULL;
849 else if (rssi_level == 1)
850 ra_mask &= 0xfffffffffffffff0ULL;
851 else if (rssi_level == 2)
852 ra_mask &= 0xffffffffffffefe0ULL;
853 else if (rssi_level == 3)
854 ra_mask &= 0xffffffffffffcfc0ULL;
855 else if (rssi_level == 4)
856 ra_mask &= 0xffffffffffff8f80ULL;
857 else if (rssi_level >= 5)
858 ra_mask &= 0xffffffffffff0f00ULL;
859 }
860
861 if (!si->use_cfg_mask)
862 return ra_mask;
863
864 band = hal->current_band_type;
865 if (band == RTW_BAND_2G) {
866 band = NL80211_BAND_2GHZ;
867 cfg_mask = mask->control[band].legacy;
868 } else if (band == RTW_BAND_5G) {
869 band = NL80211_BAND_5GHZ;
870 cfg_mask = u64_encode_bits(mask->control[band].legacy,
871 RA_MASK_OFDM_RATES);
872 }
873
874 if (!is_vht_enable) {
875 if (ra_mask & RA_MASK_HT_RATES_1SS)
876 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
877 RA_MASK_HT_RATES_1SS);
878 if (ra_mask & RA_MASK_HT_RATES_2SS)
879 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
880 RA_MASK_HT_RATES_2SS);
881 } else {
882 if (ra_mask & RA_MASK_VHT_RATES_1SS)
883 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
884 RA_MASK_VHT_RATES_1SS);
885 if (ra_mask & RA_MASK_VHT_RATES_2SS)
886 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
887 RA_MASK_VHT_RATES_2SS);
888 }
889
890 ra_mask &= cfg_mask;
891
892 return ra_mask;
893}
894
895void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si)
896{
897 struct ieee80211_sta *sta = si->sta;
898 struct rtw_efuse *efuse = &rtwdev->efuse;
899 struct rtw_hal *hal = &rtwdev->hal;
900 u8 wireless_set;
901 u8 bw_mode;
902 u8 rate_id;
903 u8 rf_type = RF_1T1R;
904 u8 stbc_en = 0;
905 u8 ldpc_en = 0;
906 u8 tx_num = 1;
907 u64 ra_mask = 0;
908 bool is_vht_enable = false;
909 bool is_support_sgi = false;
910
911 if (sta->vht_cap.vht_supported) {
912 is_vht_enable = true;
913 ra_mask |= get_vht_ra_mask(sta);
914 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
915 stbc_en = VHT_STBC_EN;
916 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
917 ldpc_en = VHT_LDPC_EN;
918 } else if (sta->ht_cap.ht_supported) {
919 ra_mask |= (sta->ht_cap.mcs.rx_mask[1] << 20) |
920 (sta->ht_cap.mcs.rx_mask[0] << 12);
921 if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
922 stbc_en = HT_STBC_EN;
923 if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
924 ldpc_en = HT_LDPC_EN;
925 }
926
927 if (efuse->hw_cap.nss == 1)
928 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS;
929
930 if (hal->current_band_type == RTW_BAND_5G) {
931 ra_mask |= (u64)sta->supp_rates[NL80211_BAND_5GHZ] << 4;
932 if (sta->vht_cap.vht_supported) {
933 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT;
934 wireless_set = WIRELESS_OFDM | WIRELESS_VHT;
935 } else if (sta->ht_cap.ht_supported) {
936 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G;
937 wireless_set = WIRELESS_OFDM | WIRELESS_HT;
938 } else {
939 wireless_set = WIRELESS_OFDM;
940 }
941 } else if (hal->current_band_type == RTW_BAND_2G) {
942 ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ];
943 if (sta->vht_cap.vht_supported) {
944 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT |
945 RA_MASK_OFDM_IN_VHT;
946 wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
947 WIRELESS_HT | WIRELESS_VHT;
948 } else if (sta->ht_cap.ht_supported) {
949 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT |
950 RA_MASK_OFDM_IN_HT_2G;
951 wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
952 WIRELESS_HT;
953 } else if (sta->supp_rates[0] <= 0xf) {
954 wireless_set = WIRELESS_CCK;
955 } else {
956 wireless_set = WIRELESS_CCK | WIRELESS_OFDM;
957 }
958 } else {
959 rtw_err(rtwdev, "Unknown band type\n");
960 wireless_set = 0;
961 }
962
963 switch (sta->bandwidth) {
964 case IEEE80211_STA_RX_BW_80:
965 bw_mode = RTW_CHANNEL_WIDTH_80;
966 is_support_sgi = sta->vht_cap.vht_supported &&
967 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
968 break;
969 case IEEE80211_STA_RX_BW_40:
970 bw_mode = RTW_CHANNEL_WIDTH_40;
971 is_support_sgi = sta->ht_cap.ht_supported &&
972 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
973 break;
974 default:
975 bw_mode = RTW_CHANNEL_WIDTH_20;
976 is_support_sgi = sta->ht_cap.ht_supported &&
977 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
978 break;
979 }
980
981 if (sta->vht_cap.vht_supported && ra_mask & 0xffc00000) {
982 tx_num = 2;
983 rf_type = RF_2T2R;
984 } else if (sta->ht_cap.ht_supported && ra_mask & 0xfff00000) {
985 tx_num = 2;
986 rf_type = RF_2T2R;
987 }
988
989 rate_id = get_rate_id(wireless_set, bw_mode, tx_num);
990
991 ra_mask = rtw_update_rate_mask(rtwdev, si, ra_mask, is_vht_enable,
992 wireless_set);
993
994 si->bw_mode = bw_mode;
995 si->stbc_en = stbc_en;
996 si->ldpc_en = ldpc_en;
997 si->rf_type = rf_type;
998 si->wireless_set = wireless_set;
999 si->sgi_enable = is_support_sgi;
1000 si->vht_enable = is_vht_enable;
1001 si->ra_mask = ra_mask;
1002 si->rate_id = rate_id;
1003
1004 rtw_fw_send_ra_info(rtwdev, si);
1005}
1006
1007static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev)
1008{
1009 struct rtw_chip_info *chip = rtwdev->chip;
1010 struct rtw_fw_state *fw;
1011
1012 fw = &rtwdev->fw;
1013 wait_for_completion(&fw->completion);
1014 if (!fw->firmware)
1015 return -EINVAL;
1016
1017 if (chip->wow_fw_name) {
1018 fw = &rtwdev->wow_fw;
1019 wait_for_completion(&fw->completion);
1020 if (!fw->firmware)
1021 return -EINVAL;
1022 }
1023
1024 return 0;
1025}
1026
1027static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev,
1028 struct rtw_fw_state *fw)
1029{
1030 struct rtw_chip_info *chip = rtwdev->chip;
1031
1032 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported ||
1033 !fw->feature)
1034 return LPS_DEEP_MODE_NONE;
1035
1036 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) &&
1037 (fw->feature & FW_FEATURE_PG))
1038 return LPS_DEEP_MODE_PG;
1039
1040 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) &&
1041 (fw->feature & FW_FEATURE_LCLK))
1042 return LPS_DEEP_MODE_LCLK;
1043
1044 return LPS_DEEP_MODE_NONE;
1045}
1046
1047static int rtw_power_on(struct rtw_dev *rtwdev)
1048{
1049 struct rtw_chip_info *chip = rtwdev->chip;
1050 struct rtw_fw_state *fw = &rtwdev->fw;
1051 bool wifi_only;
1052 int ret;
1053
1054 ret = rtw_hci_setup(rtwdev);
1055 if (ret) {
1056 rtw_err(rtwdev, "failed to setup hci\n");
1057 goto err;
1058 }
1059
1060
1061 ret = rtw_mac_power_on(rtwdev);
1062 if (ret) {
1063 rtw_err(rtwdev, "failed to power on mac\n");
1064 goto err;
1065 }
1066
1067 ret = rtw_wait_firmware_completion(rtwdev);
1068 if (ret) {
1069 rtw_err(rtwdev, "failed to wait firmware completion\n");
1070 goto err_off;
1071 }
1072
1073 ret = rtw_download_firmware(rtwdev, fw);
1074 if (ret) {
1075 rtw_err(rtwdev, "failed to download firmware\n");
1076 goto err_off;
1077 }
1078
1079
1080 ret = rtw_mac_init(rtwdev);
1081 if (ret) {
1082 rtw_err(rtwdev, "failed to configure mac\n");
1083 goto err_off;
1084 }
1085
1086 chip->ops->phy_set_param(rtwdev);
1087
1088 ret = rtw_hci_start(rtwdev);
1089 if (ret) {
1090 rtw_err(rtwdev, "failed to start hci\n");
1091 goto err_off;
1092 }
1093
1094
1095 rtw_fw_send_general_info(rtwdev);
1096 rtw_fw_send_phydm_info(rtwdev);
1097
1098 wifi_only = !rtwdev->efuse.btcoex;
1099 rtw_coex_power_on_setting(rtwdev);
1100 rtw_coex_init_hw_config(rtwdev, wifi_only);
1101
1102 return 0;
1103
1104err_off:
1105 rtw_mac_power_off(rtwdev);
1106
1107err:
1108 return ret;
1109}
1110
1111int rtw_core_start(struct rtw_dev *rtwdev)
1112{
1113 int ret;
1114
1115 ret = rtw_power_on(rtwdev);
1116 if (ret)
1117 return ret;
1118
1119 rtw_sec_enable_sec_engine(rtwdev);
1120
1121 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw);
1122 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw);
1123
1124
1125 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr);
1126
1127 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
1128 RTW_WATCH_DOG_DELAY_TIME);
1129
1130 set_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1131
1132 return 0;
1133}
1134
1135static void rtw_power_off(struct rtw_dev *rtwdev)
1136{
1137 rtw_hci_stop(rtwdev);
1138 rtw_mac_power_off(rtwdev);
1139}
1140
1141void rtw_core_stop(struct rtw_dev *rtwdev)
1142{
1143 struct rtw_coex *coex = &rtwdev->coex;
1144
1145 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1146 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
1147
1148 mutex_unlock(&rtwdev->mutex);
1149
1150 cancel_work_sync(&rtwdev->c2h_work);
1151 cancel_delayed_work_sync(&rtwdev->watch_dog_work);
1152 cancel_delayed_work_sync(&coex->bt_relink_work);
1153 cancel_delayed_work_sync(&coex->bt_reenable_work);
1154 cancel_delayed_work_sync(&coex->defreeze_work);
1155 cancel_delayed_work_sync(&coex->wl_remain_work);
1156 cancel_delayed_work_sync(&coex->bt_remain_work);
1157 cancel_delayed_work_sync(&coex->wl_connecting_work);
1158 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work);
1159 cancel_delayed_work_sync(&coex->wl_ccklock_work);
1160
1161 mutex_lock(&rtwdev->mutex);
1162
1163 rtw_power_off(rtwdev);
1164}
1165
1166static void rtw_init_ht_cap(struct rtw_dev *rtwdev,
1167 struct ieee80211_sta_ht_cap *ht_cap)
1168{
1169 struct rtw_efuse *efuse = &rtwdev->efuse;
1170
1171 ht_cap->ht_supported = true;
1172 ht_cap->cap = 0;
1173 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
1174 IEEE80211_HT_CAP_MAX_AMSDU |
1175 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
1176
1177 if (rtw_chip_has_rx_ldpc(rtwdev))
1178 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
1179
1180 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40))
1181 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1182 IEEE80211_HT_CAP_DSSSCCK40 |
1183 IEEE80211_HT_CAP_SGI_40;
1184 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1185 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
1186 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
1187 if (efuse->hw_cap.nss > 1) {
1188 ht_cap->mcs.rx_mask[0] = 0xFF;
1189 ht_cap->mcs.rx_mask[1] = 0xFF;
1190 ht_cap->mcs.rx_mask[4] = 0x01;
1191 ht_cap->mcs.rx_highest = cpu_to_le16(300);
1192 } else {
1193 ht_cap->mcs.rx_mask[0] = 0xFF;
1194 ht_cap->mcs.rx_mask[1] = 0x00;
1195 ht_cap->mcs.rx_mask[4] = 0x01;
1196 ht_cap->mcs.rx_highest = cpu_to_le16(150);
1197 }
1198}
1199
1200static void rtw_init_vht_cap(struct rtw_dev *rtwdev,
1201 struct ieee80211_sta_vht_cap *vht_cap)
1202{
1203 struct rtw_efuse *efuse = &rtwdev->efuse;
1204 u16 mcs_map;
1205 __le16 highest;
1206
1207 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE &&
1208 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT)
1209 return;
1210
1211 vht_cap->vht_supported = true;
1212 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
1213 IEEE80211_VHT_CAP_SHORT_GI_80 |
1214 IEEE80211_VHT_CAP_RXSTBC_1 |
1215 IEEE80211_VHT_CAP_HTC_VHT |
1216 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
1217 0;
1218 if (rtwdev->hal.rf_path_num > 1)
1219 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
1220 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
1221 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
1222 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap <<
1223 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT);
1224
1225 if (rtw_chip_has_rx_ldpc(rtwdev))
1226 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
1227
1228 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
1229 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
1230 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
1231 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
1232 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
1233 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
1234 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14;
1235 if (efuse->hw_cap.nss > 1) {
1236 highest = cpu_to_le16(780);
1237 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2;
1238 } else {
1239 highest = cpu_to_le16(390);
1240 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2;
1241 }
1242
1243 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
1244 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
1245 vht_cap->vht_mcs.rx_highest = highest;
1246 vht_cap->vht_mcs.tx_highest = highest;
1247}
1248
1249static void rtw_set_supported_band(struct ieee80211_hw *hw,
1250 struct rtw_chip_info *chip)
1251{
1252 struct rtw_dev *rtwdev = hw->priv;
1253 struct ieee80211_supported_band *sband;
1254
1255 if (chip->band & RTW_BAND_2G) {
1256 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL);
1257 if (!sband)
1258 goto err_out;
1259 if (chip->ht_supported)
1260 rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1261 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
1262 }
1263
1264 if (chip->band & RTW_BAND_5G) {
1265 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL);
1266 if (!sband)
1267 goto err_out;
1268 if (chip->ht_supported)
1269 rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1270 if (chip->vht_supported)
1271 rtw_init_vht_cap(rtwdev, &sband->vht_cap);
1272 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
1273 }
1274
1275 return;
1276
1277err_out:
1278 rtw_err(rtwdev, "failed to set supported band\n");
1279 kfree(sband);
1280}
1281
1282static void rtw_unset_supported_band(struct ieee80211_hw *hw,
1283 struct rtw_chip_info *chip)
1284{
1285 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
1286 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
1287}
1288
1289static void __update_firmware_feature(struct rtw_dev *rtwdev,
1290 struct rtw_fw_state *fw)
1291{
1292 u32 feature;
1293 const struct rtw_fw_hdr *fw_hdr =
1294 (const struct rtw_fw_hdr *)fw->firmware->data;
1295
1296 feature = le32_to_cpu(fw_hdr->feature);
1297 fw->feature = feature & FW_FEATURE_SIG ? feature : 0;
1298}
1299
1300static void __update_firmware_info(struct rtw_dev *rtwdev,
1301 struct rtw_fw_state *fw)
1302{
1303 const struct rtw_fw_hdr *fw_hdr =
1304 (const struct rtw_fw_hdr *)fw->firmware->data;
1305
1306 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver);
1307 fw->version = le16_to_cpu(fw_hdr->version);
1308 fw->sub_version = fw_hdr->subversion;
1309 fw->sub_index = fw_hdr->subindex;
1310
1311 __update_firmware_feature(rtwdev, fw);
1312}
1313
1314static void __update_firmware_info_legacy(struct rtw_dev *rtwdev,
1315 struct rtw_fw_state *fw)
1316{
1317 struct rtw_fw_hdr_legacy *legacy =
1318 (struct rtw_fw_hdr_legacy *)fw->firmware->data;
1319
1320 fw->h2c_version = 0;
1321 fw->version = le16_to_cpu(legacy->version);
1322 fw->sub_version = legacy->subversion1;
1323 fw->sub_index = legacy->subversion2;
1324}
1325
1326static void update_firmware_info(struct rtw_dev *rtwdev,
1327 struct rtw_fw_state *fw)
1328{
1329 if (rtw_chip_wcpu_11n(rtwdev))
1330 __update_firmware_info_legacy(rtwdev, fw);
1331 else
1332 __update_firmware_info(rtwdev, fw);
1333}
1334
1335static void rtw_load_firmware_cb(const struct firmware *firmware, void *context)
1336{
1337 struct rtw_fw_state *fw = context;
1338 struct rtw_dev *rtwdev = fw->rtwdev;
1339
1340 if (!firmware || !firmware->data) {
1341 rtw_err(rtwdev, "failed to request firmware\n");
1342 complete_all(&fw->completion);
1343 return;
1344 }
1345
1346 fw->firmware = firmware;
1347 update_firmware_info(rtwdev, fw);
1348 complete_all(&fw->completion);
1349
1350 rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n",
1351 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version);
1352}
1353
1354static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type)
1355{
1356 const char *fw_name;
1357 struct rtw_fw_state *fw;
1358 int ret;
1359
1360 switch (type) {
1361 case RTW_WOWLAN_FW:
1362 fw = &rtwdev->wow_fw;
1363 fw_name = rtwdev->chip->wow_fw_name;
1364 break;
1365
1366 case RTW_NORMAL_FW:
1367 fw = &rtwdev->fw;
1368 fw_name = rtwdev->chip->fw_name;
1369 break;
1370
1371 default:
1372 rtw_warn(rtwdev, "unsupported firmware type\n");
1373 return -ENOENT;
1374 }
1375
1376 fw->rtwdev = rtwdev;
1377 init_completion(&fw->completion);
1378
1379 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev,
1380 GFP_KERNEL, fw, rtw_load_firmware_cb);
1381 if (ret) {
1382 rtw_err(rtwdev, "failed to async firmware request\n");
1383 return ret;
1384 }
1385
1386 return 0;
1387}
1388
1389static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev)
1390{
1391 struct rtw_chip_info *chip = rtwdev->chip;
1392 struct rtw_hal *hal = &rtwdev->hal;
1393 struct rtw_efuse *efuse = &rtwdev->efuse;
1394 int ret = 0;
1395
1396 switch (rtw_hci_type(rtwdev)) {
1397 case RTW_HCI_TYPE_PCIE:
1398 rtwdev->hci.rpwm_addr = 0x03d9;
1399 rtwdev->hci.cpwm_addr = 0x03da;
1400 break;
1401 default:
1402 rtw_err(rtwdev, "unsupported hci type\n");
1403 return -EINVAL;
1404 }
1405
1406 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1);
1407 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version);
1408 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1;
1409 if (hal->chip_version & BIT_RF_TYPE_ID) {
1410 hal->rf_type = RF_2T2R;
1411 hal->rf_path_num = 2;
1412 hal->antenna_tx = BB_PATH_AB;
1413 hal->antenna_rx = BB_PATH_AB;
1414 } else {
1415 hal->rf_type = RF_1T1R;
1416 hal->rf_path_num = 1;
1417 hal->antenna_tx = BB_PATH_A;
1418 hal->antenna_rx = BB_PATH_A;
1419 }
1420 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num :
1421 hal->rf_path_num;
1422
1423 efuse->physical_size = chip->phy_efuse_size;
1424 efuse->logical_size = chip->log_efuse_size;
1425 efuse->protect_size = chip->ptct_efuse_size;
1426
1427
1428 rtwdev->hal.rcr |= BIT_VHT_DACK;
1429
1430 hal->bfee_sts_cap = 3;
1431
1432 return ret;
1433}
1434
1435static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev)
1436{
1437 struct rtw_fw_state *fw = &rtwdev->fw;
1438 int ret;
1439
1440 ret = rtw_hci_setup(rtwdev);
1441 if (ret) {
1442 rtw_err(rtwdev, "failed to setup hci\n");
1443 goto err;
1444 }
1445
1446 ret = rtw_mac_power_on(rtwdev);
1447 if (ret) {
1448 rtw_err(rtwdev, "failed to power on mac\n");
1449 goto err;
1450 }
1451
1452 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP);
1453
1454 wait_for_completion(&fw->completion);
1455 if (!fw->firmware) {
1456 ret = -EINVAL;
1457 rtw_err(rtwdev, "failed to load firmware\n");
1458 goto err;
1459 }
1460
1461 ret = rtw_download_firmware(rtwdev, fw);
1462 if (ret) {
1463 rtw_err(rtwdev, "failed to download firmware\n");
1464 goto err_off;
1465 }
1466
1467 return 0;
1468
1469err_off:
1470 rtw_mac_power_off(rtwdev);
1471
1472err:
1473 return ret;
1474}
1475
1476static int rtw_dump_hw_feature(struct rtw_dev *rtwdev)
1477{
1478 struct rtw_efuse *efuse = &rtwdev->efuse;
1479 u8 hw_feature[HW_FEATURE_LEN];
1480 u8 id;
1481 u8 bw;
1482 int i;
1483
1484 id = rtw_read8(rtwdev, REG_C2HEVT);
1485 if (id != C2H_HW_FEATURE_REPORT) {
1486 rtw_err(rtwdev, "failed to read hw feature report\n");
1487 return -EBUSY;
1488 }
1489
1490 for (i = 0; i < HW_FEATURE_LEN; i++)
1491 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i);
1492
1493 rtw_write8(rtwdev, REG_C2HEVT, 0);
1494
1495 bw = GET_EFUSE_HW_CAP_BW(hw_feature);
1496 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw);
1497 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature);
1498 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature);
1499 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature);
1500 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature);
1501
1502 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num);
1503
1504 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE ||
1505 efuse->hw_cap.nss > rtwdev->hal.rf_path_num)
1506 efuse->hw_cap.nss = rtwdev->hal.rf_path_num;
1507
1508 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
1509 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
1510 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
1511 efuse->hw_cap.ant_num, efuse->hw_cap.nss);
1512
1513 return 0;
1514}
1515
1516static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev)
1517{
1518 rtw_hci_stop(rtwdev);
1519 rtw_mac_power_off(rtwdev);
1520}
1521
1522static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev)
1523{
1524 struct rtw_efuse *efuse = &rtwdev->efuse;
1525 int ret;
1526
1527 mutex_lock(&rtwdev->mutex);
1528
1529
1530 ret = rtw_chip_efuse_enable(rtwdev);
1531 if (ret)
1532 goto out_unlock;
1533
1534 ret = rtw_parse_efuse_map(rtwdev);
1535 if (ret)
1536 goto out_disable;
1537
1538 ret = rtw_dump_hw_feature(rtwdev);
1539 if (ret)
1540 goto out_disable;
1541
1542 ret = rtw_check_supported_rfe(rtwdev);
1543 if (ret)
1544 goto out_disable;
1545
1546 if (efuse->crystal_cap == 0xff)
1547 efuse->crystal_cap = 0;
1548 if (efuse->pa_type_2g == 0xff)
1549 efuse->pa_type_2g = 0;
1550 if (efuse->pa_type_5g == 0xff)
1551 efuse->pa_type_5g = 0;
1552 if (efuse->lna_type_2g == 0xff)
1553 efuse->lna_type_2g = 0;
1554 if (efuse->lna_type_5g == 0xff)
1555 efuse->lna_type_5g = 0;
1556 if (efuse->channel_plan == 0xff)
1557 efuse->channel_plan = 0x7f;
1558 if (efuse->rf_board_option == 0xff)
1559 efuse->rf_board_option = 0;
1560 if (efuse->bt_setting & BIT(0))
1561 efuse->share_ant = true;
1562 if (efuse->regd == 0xff)
1563 efuse->regd = 0;
1564 if (efuse->tx_bb_swing_setting_2g == 0xff)
1565 efuse->tx_bb_swing_setting_2g = 0;
1566 if (efuse->tx_bb_swing_setting_5g == 0xff)
1567 efuse->tx_bb_swing_setting_5g = 0;
1568
1569 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;
1570 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;
1571 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0;
1572 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0;
1573 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0;
1574
1575out_disable:
1576 rtw_chip_efuse_disable(rtwdev);
1577
1578out_unlock:
1579 mutex_unlock(&rtwdev->mutex);
1580 return ret;
1581}
1582
1583static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev)
1584{
1585 struct rtw_hal *hal = &rtwdev->hal;
1586 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
1587
1588 if (!rfe_def)
1589 return -ENODEV;
1590
1591 rtw_phy_setup_phy_cond(rtwdev, 0);
1592
1593 rtw_phy_init_tx_power(rtwdev);
1594 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl);
1595 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl);
1596 rtw_phy_tx_power_by_rate_config(hal);
1597 rtw_phy_tx_power_limit_config(hal);
1598
1599 return 0;
1600}
1601
1602int rtw_chip_info_setup(struct rtw_dev *rtwdev)
1603{
1604 int ret;
1605
1606 ret = rtw_chip_parameter_setup(rtwdev);
1607 if (ret) {
1608 rtw_err(rtwdev, "failed to setup chip parameters\n");
1609 goto err_out;
1610 }
1611
1612 ret = rtw_chip_efuse_info_setup(rtwdev);
1613 if (ret) {
1614 rtw_err(rtwdev, "failed to setup chip efuse info\n");
1615 goto err_out;
1616 }
1617
1618 ret = rtw_chip_board_info_setup(rtwdev);
1619 if (ret) {
1620 rtw_err(rtwdev, "failed to setup chip board info\n");
1621 goto err_out;
1622 }
1623
1624 return 0;
1625
1626err_out:
1627 return ret;
1628}
1629EXPORT_SYMBOL(rtw_chip_info_setup);
1630
1631static void rtw_stats_init(struct rtw_dev *rtwdev)
1632{
1633 struct rtw_traffic_stats *stats = &rtwdev->stats;
1634 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1635 int i;
1636
1637 ewma_tp_init(&stats->tx_ewma_tp);
1638 ewma_tp_init(&stats->rx_ewma_tp);
1639
1640 for (i = 0; i < RTW_EVM_NUM; i++)
1641 ewma_evm_init(&dm_info->ewma_evm[i]);
1642 for (i = 0; i < RTW_SNR_NUM; i++)
1643 ewma_snr_init(&dm_info->ewma_snr[i]);
1644}
1645
1646int rtw_core_init(struct rtw_dev *rtwdev)
1647{
1648 struct rtw_chip_info *chip = rtwdev->chip;
1649 struct rtw_coex *coex = &rtwdev->coex;
1650 int ret;
1651
1652 INIT_LIST_HEAD(&rtwdev->rsvd_page_list);
1653 INIT_LIST_HEAD(&rtwdev->txqs);
1654
1655 timer_setup(&rtwdev->tx_report.purge_timer,
1656 rtw_tx_report_purge_timer, 0);
1657 tasklet_setup(&rtwdev->tx_tasklet, rtw_tx_tasklet);
1658
1659 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work);
1660 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work);
1661 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work);
1662 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work);
1663 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work);
1664 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work);
1665 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work);
1666 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work,
1667 rtw_coex_bt_multi_link_remain_work);
1668 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work);
1669 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work);
1670 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work);
1671 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work);
1672 skb_queue_head_init(&rtwdev->c2h_queue);
1673 skb_queue_head_init(&rtwdev->coex.queue);
1674 skb_queue_head_init(&rtwdev->tx_report.queue);
1675
1676 spin_lock_init(&rtwdev->rf_lock);
1677 spin_lock_init(&rtwdev->h2c.lock);
1678 spin_lock_init(&rtwdev->txq_lock);
1679 spin_lock_init(&rtwdev->tx_report.q_lock);
1680
1681 mutex_init(&rtwdev->mutex);
1682 mutex_init(&rtwdev->coex.mutex);
1683 mutex_init(&rtwdev->hal.tx_power_mutex);
1684
1685 init_waitqueue_head(&rtwdev->coex.wait);
1686 init_completion(&rtwdev->lps_leave_check);
1687
1688 rtwdev->sec.total_cam_num = 32;
1689 rtwdev->hal.current_channel = 1;
1690 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map);
1691
1692 rtw_stats_init(rtwdev);
1693
1694
1695 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV |
1696 BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS |
1697 BIT_AB | BIT_AM | BIT_APM;
1698
1699 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW);
1700 if (ret) {
1701 rtw_warn(rtwdev, "no firmware loaded\n");
1702 return ret;
1703 }
1704
1705 if (chip->wow_fw_name) {
1706 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW);
1707 if (ret) {
1708 rtw_warn(rtwdev, "no wow firmware loaded\n");
1709 wait_for_completion(&rtwdev->fw.completion);
1710 if (rtwdev->fw.firmware)
1711 release_firmware(rtwdev->fw.firmware);
1712 return ret;
1713 }
1714 }
1715
1716 return 0;
1717}
1718EXPORT_SYMBOL(rtw_core_init);
1719
1720void rtw_core_deinit(struct rtw_dev *rtwdev)
1721{
1722 struct rtw_fw_state *fw = &rtwdev->fw;
1723 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw;
1724 struct rtw_rsvd_page *rsvd_pkt, *tmp;
1725 unsigned long flags;
1726
1727 rtw_wait_firmware_completion(rtwdev);
1728
1729 if (fw->firmware)
1730 release_firmware(fw->firmware);
1731
1732 if (wow_fw->firmware)
1733 release_firmware(wow_fw->firmware);
1734
1735 tasklet_kill(&rtwdev->tx_tasklet);
1736 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags);
1737 skb_queue_purge(&rtwdev->tx_report.queue);
1738 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags);
1739
1740 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list,
1741 build_list) {
1742 list_del(&rsvd_pkt->build_list);
1743 kfree(rsvd_pkt);
1744 }
1745
1746 mutex_destroy(&rtwdev->mutex);
1747 mutex_destroy(&rtwdev->coex.mutex);
1748 mutex_destroy(&rtwdev->hal.tx_power_mutex);
1749}
1750EXPORT_SYMBOL(rtw_core_deinit);
1751
1752int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
1753{
1754 struct rtw_hal *hal = &rtwdev->hal;
1755 int max_tx_headroom = 0;
1756 int ret;
1757
1758
1759 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz;
1760
1761 hw->extra_tx_headroom = max_tx_headroom;
1762 hw->queues = IEEE80211_NUM_ACS;
1763 hw->txq_data_size = sizeof(struct rtw_txq);
1764 hw->sta_data_size = sizeof(struct rtw_sta_info);
1765 hw->vif_data_size = sizeof(struct rtw_vif);
1766
1767 ieee80211_hw_set(hw, SIGNAL_DBM);
1768 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
1769 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
1770 ieee80211_hw_set(hw, MFP_CAPABLE);
1771 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
1772 ieee80211_hw_set(hw, SUPPORTS_PS);
1773 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
1774 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
1775 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
1776 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
1777 ieee80211_hw_set(hw, TX_AMSDU);
1778
1779 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1780 BIT(NL80211_IFTYPE_AP) |
1781 BIT(NL80211_IFTYPE_ADHOC) |
1782 BIT(NL80211_IFTYPE_MESH_POINT);
1783 hw->wiphy->available_antennas_tx = hal->antenna_tx;
1784 hw->wiphy->available_antennas_rx = hal->antenna_rx;
1785
1786 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
1787 WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
1788
1789 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
1790
1791 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
1792
1793#ifdef CONFIG_PM
1794 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
1795 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids;
1796#endif
1797 rtw_set_supported_band(hw, rtwdev->chip);
1798 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr);
1799
1800 rtw_regd_init(rtwdev, rtw_regd_notifier);
1801
1802 ret = ieee80211_register_hw(hw);
1803 if (ret) {
1804 rtw_err(rtwdev, "failed to register hw\n");
1805 return ret;
1806 }
1807
1808 if (regulatory_hint(hw->wiphy, rtwdev->regd.alpha2))
1809 rtw_err(rtwdev, "regulatory_hint fail\n");
1810
1811 rtw_debugfs_init(rtwdev);
1812
1813 rtwdev->bf_info.bfer_mu_cnt = 0;
1814 rtwdev->bf_info.bfer_su_cnt = 0;
1815
1816 return 0;
1817}
1818EXPORT_SYMBOL(rtw_register_hw);
1819
1820void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
1821{
1822 struct rtw_chip_info *chip = rtwdev->chip;
1823
1824 ieee80211_unregister_hw(hw);
1825 rtw_unset_supported_band(hw, chip);
1826}
1827EXPORT_SYMBOL(rtw_unregister_hw);
1828
1829MODULE_AUTHOR("Realtek Corporation");
1830MODULE_DESCRIPTION("Realtek 802.11ac wireless core module");
1831MODULE_LICENSE("Dual BSD/GPL");
1832
