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5
6#include <linux/kernel.h>
7#include <linux/delay.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/msi.h>
11#include <linux/of_device.h>
12#include <linux/of_pci.h>
13#include <linux/pci_hotplug.h>
14#include <linux/slab.h>
15#include <linux/module.h>
16#include <linux/cpumask.h>
17#include <linux/aer.h>
18#include <linux/acpi.h>
19#include <linux/hypervisor.h>
20#include <linux/irqdomain.h>
21#include <linux/pm_runtime.h>
22#include "pci.h"
23
24#define CARDBUS_LATENCY_TIMER 176
25#define CARDBUS_RESERVE_BUSNR 3
26
27static struct resource busn_resource = {
28 .name = "PCI busn",
29 .start = 0,
30 .end = 255,
31 .flags = IORESOURCE_BUS,
32};
33
34
35LIST_HEAD(pci_root_buses);
36EXPORT_SYMBOL(pci_root_buses);
37
38static LIST_HEAD(pci_domain_busn_res_list);
39
40struct pci_domain_busn_res {
41 struct list_head list;
42 struct resource res;
43 int domain_nr;
44};
45
46static struct resource *get_pci_domain_busn_res(int domain_nr)
47{
48 struct pci_domain_busn_res *r;
49
50 list_for_each_entry(r, &pci_domain_busn_res_list, list)
51 if (r->domain_nr == domain_nr)
52 return &r->res;
53
54 r = kzalloc(sizeof(*r), GFP_KERNEL);
55 if (!r)
56 return NULL;
57
58 r->domain_nr = domain_nr;
59 r->res.start = 0;
60 r->res.end = 0xff;
61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
62
63 list_add_tail(&r->list, &pci_domain_busn_res_list);
64
65 return &r->res;
66}
67
68
69
70
71
72
73int no_pci_devices(void)
74{
75 struct device *dev;
76 int no_devices;
77
78 dev = bus_find_next_device(&pci_bus_type, NULL);
79 no_devices = (dev == NULL);
80 put_device(dev);
81 return no_devices;
82}
83EXPORT_SYMBOL(no_pci_devices);
84
85
86
87
88static void release_pcibus_dev(struct device *dev)
89{
90 struct pci_bus *pci_bus = to_pci_bus(dev);
91
92 put_device(pci_bus->bridge);
93 pci_bus_remove_resources(pci_bus);
94 pci_release_bus_of_node(pci_bus);
95 kfree(pci_bus);
96}
97
98static struct class pcibus_class = {
99 .name = "pci_bus",
100 .dev_release = &release_pcibus_dev,
101 .dev_groups = pcibus_groups,
102};
103
104static int __init pcibus_class_init(void)
105{
106 return class_register(&pcibus_class);
107}
108postcore_initcall(pcibus_class_init);
109
110static u64 pci_size(u64 base, u64 maxbase, u64 mask)
111{
112 u64 size = mask & maxbase;
113 if (!size)
114 return 0;
115
116
117
118
119
120 size = size & ~(size-1);
121
122
123
124
125
126 if (base == maxbase && ((base | (size - 1)) & mask) != mask)
127 return 0;
128
129 return size;
130}
131
132static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
133{
134 u32 mem_type;
135 unsigned long flags;
136
137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
139 flags |= IORESOURCE_IO;
140 return flags;
141 }
142
143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
144 flags |= IORESOURCE_MEM;
145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
146 flags |= IORESOURCE_PREFETCH;
147
148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
149 switch (mem_type) {
150 case PCI_BASE_ADDRESS_MEM_TYPE_32:
151 break;
152 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
153
154 break;
155 case PCI_BASE_ADDRESS_MEM_TYPE_64:
156 flags |= IORESOURCE_MEM_64;
157 break;
158 default:
159
160 break;
161 }
162 return flags;
163}
164
165#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
166
167
168
169
170
171
172
173
174
175
176int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
177 struct resource *res, unsigned int pos)
178{
179 u32 l = 0, sz = 0, mask;
180 u64 l64, sz64, mask64;
181 u16 orig_cmd;
182 struct pci_bus_region region, inverted_region;
183
184 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
185
186
187 if (!dev->mmio_always_on) {
188 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
189 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
190 pci_write_config_word(dev, PCI_COMMAND,
191 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
192 }
193 }
194
195 res->name = pci_name(dev);
196
197 pci_read_config_dword(dev, pos, &l);
198 pci_write_config_dword(dev, pos, l | mask);
199 pci_read_config_dword(dev, pos, &sz);
200 pci_write_config_dword(dev, pos, l);
201
202
203
204
205
206
207
208 if (sz == 0xffffffff)
209 sz = 0;
210
211
212
213
214
215 if (l == 0xffffffff)
216 l = 0;
217
218 if (type == pci_bar_unknown) {
219 res->flags = decode_bar(dev, l);
220 res->flags |= IORESOURCE_SIZEALIGN;
221 if (res->flags & IORESOURCE_IO) {
222 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
223 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
224 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
225 } else {
226 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
227 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
228 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
229 }
230 } else {
231 if (l & PCI_ROM_ADDRESS_ENABLE)
232 res->flags |= IORESOURCE_ROM_ENABLE;
233 l64 = l & PCI_ROM_ADDRESS_MASK;
234 sz64 = sz & PCI_ROM_ADDRESS_MASK;
235 mask64 = PCI_ROM_ADDRESS_MASK;
236 }
237
238 if (res->flags & IORESOURCE_MEM_64) {
239 pci_read_config_dword(dev, pos + 4, &l);
240 pci_write_config_dword(dev, pos + 4, ~0);
241 pci_read_config_dword(dev, pos + 4, &sz);
242 pci_write_config_dword(dev, pos + 4, l);
243
244 l64 |= ((u64)l << 32);
245 sz64 |= ((u64)sz << 32);
246 mask64 |= ((u64)~0 << 32);
247 }
248
249 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
250 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
251
252 if (!sz64)
253 goto fail;
254
255 sz64 = pci_size(l64, sz64, mask64);
256 if (!sz64) {
257 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
258 pos);
259 goto fail;
260 }
261
262 if (res->flags & IORESOURCE_MEM_64) {
263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
264 && sz64 > 0x100000000ULL) {
265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
266 res->start = 0;
267 res->end = 0;
268 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
269 pos, (unsigned long long)sz64);
270 goto out;
271 }
272
273 if ((sizeof(pci_bus_addr_t) < 8) && l) {
274
275 res->flags |= IORESOURCE_UNSET;
276 res->start = 0;
277 res->end = sz64 - 1;
278 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
279 pos, (unsigned long long)l64);
280 goto out;
281 }
282 }
283
284 region.start = l64;
285 region.end = l64 + sz64 - 1;
286
287 pcibios_bus_to_resource(dev->bus, res, ®ion);
288 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
289
290
291
292
293
294
295
296
297
298
299
300
301 if (inverted_region.start != region.start) {
302 res->flags |= IORESOURCE_UNSET;
303 res->start = 0;
304 res->end = region.end - region.start;
305 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
306 pos, (unsigned long long)region.start);
307 }
308
309 goto out;
310
311
312fail:
313 res->flags = 0;
314out:
315 if (res->flags)
316 pci_info(dev, "reg 0x%x: %pR\n", pos, res);
317
318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
319}
320
321static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
322{
323 unsigned int pos, reg;
324
325 if (dev->non_compliant_bars)
326 return;
327
328
329 if (dev->is_virtfn)
330 return;
331
332 for (pos = 0; pos < howmany; pos++) {
333 struct resource *res = &dev->resource[pos];
334 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
336 }
337
338 if (rom) {
339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
340 dev->rom_base_reg = rom;
341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
342 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
343 __pci_read_base(dev, pci_bar_mem32, res, rom);
344 }
345}
346
347static void pci_read_bridge_windows(struct pci_dev *bridge)
348{
349 u16 io;
350 u32 pmem, tmp;
351
352 pci_read_config_word(bridge, PCI_IO_BASE, &io);
353 if (!io) {
354 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
355 pci_read_config_word(bridge, PCI_IO_BASE, &io);
356 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
357 }
358 if (io)
359 bridge->io_window = 1;
360
361
362
363
364
365
366 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
367 return;
368
369 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
370 if (!pmem) {
371 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
372 0xffe0fff0);
373 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
374 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
375 }
376 if (!pmem)
377 return;
378
379 bridge->pref_window = 1;
380
381 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
382
383
384
385
386
387
388 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
389 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
390 0xffffffff);
391 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
392 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
393 if (tmp)
394 bridge->pref_64_window = 1;
395 }
396}
397
398static void pci_read_bridge_io(struct pci_bus *child)
399{
400 struct pci_dev *dev = child->self;
401 u8 io_base_lo, io_limit_lo;
402 unsigned long io_mask, io_granularity, base, limit;
403 struct pci_bus_region region;
404 struct resource *res;
405
406 io_mask = PCI_IO_RANGE_MASK;
407 io_granularity = 0x1000;
408 if (dev->io_window_1k) {
409
410 io_mask = PCI_IO_1K_RANGE_MASK;
411 io_granularity = 0x400;
412 }
413
414 res = child->resource[0];
415 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
416 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
417 base = (io_base_lo & io_mask) << 8;
418 limit = (io_limit_lo & io_mask) << 8;
419
420 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
421 u16 io_base_hi, io_limit_hi;
422
423 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
424 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
425 base |= ((unsigned long) io_base_hi << 16);
426 limit |= ((unsigned long) io_limit_hi << 16);
427 }
428
429 if (base <= limit) {
430 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
431 region.start = base;
432 region.end = limit + io_granularity - 1;
433 pcibios_bus_to_resource(dev->bus, res, ®ion);
434 pci_info(dev, " bridge window %pR\n", res);
435 }
436}
437
438static void pci_read_bridge_mmio(struct pci_bus *child)
439{
440 struct pci_dev *dev = child->self;
441 u16 mem_base_lo, mem_limit_lo;
442 unsigned long base, limit;
443 struct pci_bus_region region;
444 struct resource *res;
445
446 res = child->resource[1];
447 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
448 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
449 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
450 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
451 if (base <= limit) {
452 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
453 region.start = base;
454 region.end = limit + 0xfffff;
455 pcibios_bus_to_resource(dev->bus, res, ®ion);
456 pci_info(dev, " bridge window %pR\n", res);
457 }
458}
459
460static void pci_read_bridge_mmio_pref(struct pci_bus *child)
461{
462 struct pci_dev *dev = child->self;
463 u16 mem_base_lo, mem_limit_lo;
464 u64 base64, limit64;
465 pci_bus_addr_t base, limit;
466 struct pci_bus_region region;
467 struct resource *res;
468
469 res = child->resource[2];
470 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
471 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
472 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
473 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
474
475 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
476 u32 mem_base_hi, mem_limit_hi;
477
478 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
479 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
480
481
482
483
484
485
486 if (mem_base_hi <= mem_limit_hi) {
487 base64 |= (u64) mem_base_hi << 32;
488 limit64 |= (u64) mem_limit_hi << 32;
489 }
490 }
491
492 base = (pci_bus_addr_t) base64;
493 limit = (pci_bus_addr_t) limit64;
494
495 if (base != base64) {
496 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
497 (unsigned long long) base64);
498 return;
499 }
500
501 if (base <= limit) {
502 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
503 IORESOURCE_MEM | IORESOURCE_PREFETCH;
504 if (res->flags & PCI_PREF_RANGE_TYPE_64)
505 res->flags |= IORESOURCE_MEM_64;
506 region.start = base;
507 region.end = limit + 0xfffff;
508 pcibios_bus_to_resource(dev->bus, res, ®ion);
509 pci_info(dev, " bridge window %pR\n", res);
510 }
511}
512
513void pci_read_bridge_bases(struct pci_bus *child)
514{
515 struct pci_dev *dev = child->self;
516 struct resource *res;
517 int i;
518
519 if (pci_is_root_bus(child))
520 return;
521
522 pci_info(dev, "PCI bridge to %pR%s\n",
523 &child->busn_res,
524 dev->transparent ? " (subtractive decode)" : "");
525
526 pci_bus_remove_resources(child);
527 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
528 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
529
530 pci_read_bridge_io(child);
531 pci_read_bridge_mmio(child);
532 pci_read_bridge_mmio_pref(child);
533
534 if (dev->transparent) {
535 pci_bus_for_each_resource(child->parent, res, i) {
536 if (res && res->flags) {
537 pci_bus_add_resource(child, res,
538 PCI_SUBTRACTIVE_DECODE);
539 pci_info(dev, " bridge window %pR (subtractive decode)\n",
540 res);
541 }
542 }
543 }
544}
545
546static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
547{
548 struct pci_bus *b;
549
550 b = kzalloc(sizeof(*b), GFP_KERNEL);
551 if (!b)
552 return NULL;
553
554 INIT_LIST_HEAD(&b->node);
555 INIT_LIST_HEAD(&b->children);
556 INIT_LIST_HEAD(&b->devices);
557 INIT_LIST_HEAD(&b->slots);
558 INIT_LIST_HEAD(&b->resources);
559 b->max_bus_speed = PCI_SPEED_UNKNOWN;
560 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
561#ifdef CONFIG_PCI_DOMAINS_GENERIC
562 if (parent)
563 b->domain_nr = parent->domain_nr;
564#endif
565 return b;
566}
567
568static void pci_release_host_bridge_dev(struct device *dev)
569{
570 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
571
572 if (bridge->release_fn)
573 bridge->release_fn(bridge);
574
575 pci_free_resource_list(&bridge->windows);
576 pci_free_resource_list(&bridge->dma_ranges);
577 kfree(bridge);
578}
579
580static void pci_init_host_bridge(struct pci_host_bridge *bridge)
581{
582 INIT_LIST_HEAD(&bridge->windows);
583 INIT_LIST_HEAD(&bridge->dma_ranges);
584
585
586
587
588
589
590
591 bridge->native_aer = 1;
592 bridge->native_pcie_hotplug = 1;
593 bridge->native_shpc_hotplug = 1;
594 bridge->native_pme = 1;
595 bridge->native_ltr = 1;
596 bridge->native_dpc = 1;
597
598 device_initialize(&bridge->dev);
599}
600
601struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
602{
603 struct pci_host_bridge *bridge;
604
605 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
606 if (!bridge)
607 return NULL;
608
609 pci_init_host_bridge(bridge);
610 bridge->dev.release = pci_release_host_bridge_dev;
611
612 return bridge;
613}
614EXPORT_SYMBOL(pci_alloc_host_bridge);
615
616static void devm_pci_alloc_host_bridge_release(void *data)
617{
618 pci_free_host_bridge(data);
619}
620
621struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
622 size_t priv)
623{
624 int ret;
625 struct pci_host_bridge *bridge;
626
627 bridge = pci_alloc_host_bridge(priv);
628 if (!bridge)
629 return NULL;
630
631 bridge->dev.parent = dev;
632
633 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,
634 bridge);
635 if (ret)
636 return NULL;
637
638 ret = devm_of_pci_bridge_init(dev, bridge);
639 if (ret)
640 return NULL;
641
642 return bridge;
643}
644EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
645
646void pci_free_host_bridge(struct pci_host_bridge *bridge)
647{
648 put_device(&bridge->dev);
649}
650EXPORT_SYMBOL(pci_free_host_bridge);
651
652
653static const unsigned char pcix_bus_speed[] = {
654 PCI_SPEED_UNKNOWN,
655 PCI_SPEED_66MHz_PCIX,
656 PCI_SPEED_100MHz_PCIX,
657 PCI_SPEED_133MHz_PCIX,
658 PCI_SPEED_UNKNOWN,
659 PCI_SPEED_66MHz_PCIX_ECC,
660 PCI_SPEED_100MHz_PCIX_ECC,
661 PCI_SPEED_133MHz_PCIX_ECC,
662 PCI_SPEED_UNKNOWN,
663 PCI_SPEED_66MHz_PCIX_266,
664 PCI_SPEED_100MHz_PCIX_266,
665 PCI_SPEED_133MHz_PCIX_266,
666 PCI_SPEED_UNKNOWN,
667 PCI_SPEED_66MHz_PCIX_533,
668 PCI_SPEED_100MHz_PCIX_533,
669 PCI_SPEED_133MHz_PCIX_533
670};
671
672
673const unsigned char pcie_link_speed[] = {
674 PCI_SPEED_UNKNOWN,
675 PCIE_SPEED_2_5GT,
676 PCIE_SPEED_5_0GT,
677 PCIE_SPEED_8_0GT,
678 PCIE_SPEED_16_0GT,
679 PCIE_SPEED_32_0GT,
680 PCIE_SPEED_64_0GT,
681 PCI_SPEED_UNKNOWN,
682 PCI_SPEED_UNKNOWN,
683 PCI_SPEED_UNKNOWN,
684 PCI_SPEED_UNKNOWN,
685 PCI_SPEED_UNKNOWN,
686 PCI_SPEED_UNKNOWN,
687 PCI_SPEED_UNKNOWN,
688 PCI_SPEED_UNKNOWN,
689 PCI_SPEED_UNKNOWN
690};
691EXPORT_SYMBOL_GPL(pcie_link_speed);
692
693const char *pci_speed_string(enum pci_bus_speed speed)
694{
695
696 static const char *speed_strings[] = {
697 "33 MHz PCI",
698 "66 MHz PCI",
699 "66 MHz PCI-X",
700 "100 MHz PCI-X",
701 "133 MHz PCI-X",
702 NULL,
703 NULL,
704 NULL,
705 NULL,
706 "66 MHz PCI-X 266",
707 "100 MHz PCI-X 266",
708 "133 MHz PCI-X 266",
709 "Unknown AGP",
710 "1x AGP",
711 "2x AGP",
712 "4x AGP",
713 "8x AGP",
714 "66 MHz PCI-X 533",
715 "100 MHz PCI-X 533",
716 "133 MHz PCI-X 533",
717 "2.5 GT/s PCIe",
718 "5.0 GT/s PCIe",
719 "8.0 GT/s PCIe",
720 "16.0 GT/s PCIe",
721 "32.0 GT/s PCIe",
722 "64.0 GT/s PCIe",
723 };
724
725 if (speed < ARRAY_SIZE(speed_strings))
726 return speed_strings[speed];
727 return "Unknown";
728}
729EXPORT_SYMBOL_GPL(pci_speed_string);
730
731void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
732{
733 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
734}
735EXPORT_SYMBOL_GPL(pcie_update_link_speed);
736
737static unsigned char agp_speeds[] = {
738 AGP_UNKNOWN,
739 AGP_1X,
740 AGP_2X,
741 AGP_4X,
742 AGP_8X
743};
744
745static enum pci_bus_speed agp_speed(int agp3, int agpstat)
746{
747 int index = 0;
748
749 if (agpstat & 4)
750 index = 3;
751 else if (agpstat & 2)
752 index = 2;
753 else if (agpstat & 1)
754 index = 1;
755 else
756 goto out;
757
758 if (agp3) {
759 index += 2;
760 if (index == 5)
761 index = 0;
762 }
763
764 out:
765 return agp_speeds[index];
766}
767
768static void pci_set_bus_speed(struct pci_bus *bus)
769{
770 struct pci_dev *bridge = bus->self;
771 int pos;
772
773 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
774 if (!pos)
775 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
776 if (pos) {
777 u32 agpstat, agpcmd;
778
779 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
780 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
781
782 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
783 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
784 }
785
786 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
787 if (pos) {
788 u16 status;
789 enum pci_bus_speed max;
790
791 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
792 &status);
793
794 if (status & PCI_X_SSTATUS_533MHZ) {
795 max = PCI_SPEED_133MHz_PCIX_533;
796 } else if (status & PCI_X_SSTATUS_266MHZ) {
797 max = PCI_SPEED_133MHz_PCIX_266;
798 } else if (status & PCI_X_SSTATUS_133MHZ) {
799 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
800 max = PCI_SPEED_133MHz_PCIX_ECC;
801 else
802 max = PCI_SPEED_133MHz_PCIX;
803 } else {
804 max = PCI_SPEED_66MHz_PCIX;
805 }
806
807 bus->max_bus_speed = max;
808 bus->cur_bus_speed = pcix_bus_speed[
809 (status & PCI_X_SSTATUS_FREQ) >> 6];
810
811 return;
812 }
813
814 if (pci_is_pcie(bridge)) {
815 u32 linkcap;
816 u16 linksta;
817
818 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
819 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
820 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);
821
822 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
823 pcie_update_link_speed(bus, linksta);
824 }
825}
826
827static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
828{
829 struct irq_domain *d;
830
831
832
833
834
835 d = pci_host_bridge_of_msi_domain(bus);
836 if (!d)
837 d = pci_host_bridge_acpi_msi_domain(bus);
838
839#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
840
841
842
843
844 if (!d) {
845 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
846
847 if (fwnode)
848 d = irq_find_matching_fwnode(fwnode,
849 DOMAIN_BUS_PCI_MSI);
850 }
851#endif
852
853 return d;
854}
855
856static void pci_set_bus_msi_domain(struct pci_bus *bus)
857{
858 struct irq_domain *d;
859 struct pci_bus *b;
860
861
862
863
864
865
866 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
867 if (b->self)
868 d = dev_get_msi_domain(&b->self->dev);
869 }
870
871 if (!d)
872 d = pci_host_bridge_msi_domain(b);
873
874 dev_set_msi_domain(&bus->dev, d);
875}
876
877static int pci_register_host_bridge(struct pci_host_bridge *bridge)
878{
879 struct device *parent = bridge->dev.parent;
880 struct resource_entry *window, *n;
881 struct pci_bus *bus, *b;
882 resource_size_t offset;
883 LIST_HEAD(resources);
884 struct resource *res;
885 char addr[64], *fmt;
886 const char *name;
887 int err;
888
889 bus = pci_alloc_bus(NULL);
890 if (!bus)
891 return -ENOMEM;
892
893 bridge->bus = bus;
894
895
896 list_splice_init(&bridge->windows, &resources);
897 bus->sysdata = bridge->sysdata;
898 bus->msi = bridge->msi;
899 bus->ops = bridge->ops;
900 bus->number = bus->busn_res.start = bridge->busnr;
901#ifdef CONFIG_PCI_DOMAINS_GENERIC
902 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
903#endif
904
905 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
906 if (b) {
907
908 dev_dbg(&b->dev, "bus already known\n");
909 err = -EEXIST;
910 goto free;
911 }
912
913 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
914 bridge->busnr);
915
916 err = pcibios_root_bridge_prepare(bridge);
917 if (err)
918 goto free;
919
920 err = device_add(&bridge->dev);
921 if (err) {
922 put_device(&bridge->dev);
923 goto free;
924 }
925 bus->bridge = get_device(&bridge->dev);
926 device_enable_async_suspend(bus->bridge);
927 pci_set_bus_of_node(bus);
928 pci_set_bus_msi_domain(bus);
929
930 if (!parent)
931 set_dev_node(bus->bridge, pcibus_to_node(bus));
932
933 bus->dev.class = &pcibus_class;
934 bus->dev.parent = bus->bridge;
935
936 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
937 name = dev_name(&bus->dev);
938
939 err = device_register(&bus->dev);
940 if (err)
941 goto unregister;
942
943 pcibios_add_bus(bus);
944
945 if (bus->ops->add_bus) {
946 err = bus->ops->add_bus(bus);
947 if (WARN_ON(err < 0))
948 dev_err(&bus->dev, "failed to add bus: %d\n", err);
949 }
950
951
952 pci_create_legacy_files(bus);
953
954 if (parent)
955 dev_info(parent, "PCI host bridge to bus %s\n", name);
956 else
957 pr_info("PCI host bridge to bus %s\n", name);
958
959 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
960 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
961
962
963 resource_list_for_each_entry_safe(window, n, &resources) {
964 list_move_tail(&window->node, &bridge->windows);
965 offset = window->offset;
966 res = window->res;
967
968 if (res->flags & IORESOURCE_BUS)
969 pci_bus_insert_busn_res(bus, bus->number, res->end);
970 else
971 pci_bus_add_resource(bus, res, 0);
972
973 if (offset) {
974 if (resource_type(res) == IORESOURCE_IO)
975 fmt = " (bus address [%#06llx-%#06llx])";
976 else
977 fmt = " (bus address [%#010llx-%#010llx])";
978
979 snprintf(addr, sizeof(addr), fmt,
980 (unsigned long long)(res->start - offset),
981 (unsigned long long)(res->end - offset));
982 } else
983 addr[0] = '\0';
984
985 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
986 }
987
988 down_write(&pci_bus_sem);
989 list_add_tail(&bus->node, &pci_root_buses);
990 up_write(&pci_bus_sem);
991
992 return 0;
993
994unregister:
995 put_device(&bridge->dev);
996 device_del(&bridge->dev);
997
998free:
999 kfree(bus);
1000 return err;
1001}
1002
1003static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
1004{
1005 int pos;
1006 u32 status;
1007
1008
1009
1010
1011
1012 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1013 return false;
1014
1015
1016
1017
1018
1019
1020 if (pci_is_pcie(bridge) &&
1021 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
1022 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
1023 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
1024 return true;
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
1035 if (!pos)
1036 return false;
1037
1038 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
1039 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
1040}
1041
1042static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
1043 struct pci_dev *bridge, int busnr)
1044{
1045 struct pci_bus *child;
1046 struct pci_host_bridge *host;
1047 int i;
1048 int ret;
1049
1050
1051 child = pci_alloc_bus(parent);
1052 if (!child)
1053 return NULL;
1054
1055 child->parent = parent;
1056 child->msi = parent->msi;
1057 child->sysdata = parent->sysdata;
1058 child->bus_flags = parent->bus_flags;
1059
1060 host = pci_find_host_bridge(parent);
1061 if (host->child_ops)
1062 child->ops = host->child_ops;
1063 else
1064 child->ops = parent->ops;
1065
1066
1067
1068
1069
1070 child->dev.class = &pcibus_class;
1071 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1072
1073
1074 child->number = child->busn_res.start = busnr;
1075 child->primary = parent->busn_res.start;
1076 child->busn_res.end = 0xff;
1077
1078 if (!bridge) {
1079 child->dev.parent = parent->bridge;
1080 goto add_dev;
1081 }
1082
1083 child->self = bridge;
1084 child->bridge = get_device(&bridge->dev);
1085 child->dev.parent = child->bridge;
1086 pci_set_bus_of_node(child);
1087 pci_set_bus_speed(child);
1088
1089
1090
1091
1092
1093
1094 if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1095 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1096 pci_info(child, "extended config space not accessible\n");
1097 }
1098
1099
1100 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1101 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1102 child->resource[i]->name = child->name;
1103 }
1104 bridge->subordinate = child;
1105
1106add_dev:
1107 pci_set_bus_msi_domain(child);
1108 ret = device_register(&child->dev);
1109 WARN_ON(ret < 0);
1110
1111 pcibios_add_bus(child);
1112
1113 if (child->ops->add_bus) {
1114 ret = child->ops->add_bus(child);
1115 if (WARN_ON(ret < 0))
1116 dev_err(&child->dev, "failed to add bus: %d\n", ret);
1117 }
1118
1119
1120 pci_create_legacy_files(child);
1121
1122 return child;
1123}
1124
1125struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1126 int busnr)
1127{
1128 struct pci_bus *child;
1129
1130 child = pci_alloc_child_bus(parent, dev, busnr);
1131 if (child) {
1132 down_write(&pci_bus_sem);
1133 list_add_tail(&child->node, &parent->children);
1134 up_write(&pci_bus_sem);
1135 }
1136 return child;
1137}
1138EXPORT_SYMBOL(pci_add_new_bus);
1139
1140static void pci_enable_crs(struct pci_dev *pdev)
1141{
1142 u16 root_cap = 0;
1143
1144
1145 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1146 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1147 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1148 PCI_EXP_RTCTL_CRSSVE);
1149}
1150
1151static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1152 unsigned int available_buses);
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1165{
1166 int ea, offset;
1167 u32 dw;
1168 u8 ea_sec, ea_sub;
1169
1170 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1171 return false;
1172
1173
1174 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1175 if (!ea)
1176 return false;
1177
1178 offset = ea + PCI_EA_FIRST_ENT;
1179 pci_read_config_dword(dev, offset, &dw);
1180 ea_sec = dw & PCI_EA_SEC_BUS_MASK;
1181 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1182 if (ea_sec == 0 || ea_sub < ea_sec)
1183 return false;
1184
1185 *sec = ea_sec;
1186 *sub = ea_sub;
1187 return true;
1188}
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1214 int max, unsigned int available_buses,
1215 int pass)
1216{
1217 struct pci_bus *child;
1218 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1219 u32 buses, i, j = 0;
1220 u16 bctl;
1221 u8 primary, secondary, subordinate;
1222 int broken = 0;
1223 bool fixed_buses;
1224 u8 fixed_sec, fixed_sub;
1225 int next_busnr;
1226
1227
1228
1229
1230
1231 pm_runtime_get_sync(&dev->dev);
1232
1233 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1234 primary = buses & 0xFF;
1235 secondary = (buses >> 8) & 0xFF;
1236 subordinate = (buses >> 16) & 0xFF;
1237
1238 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1239 secondary, subordinate, pass);
1240
1241 if (!primary && (primary != bus->number) && secondary && subordinate) {
1242 pci_warn(dev, "Primary bus is hard wired to 0\n");
1243 primary = bus->number;
1244 }
1245
1246
1247 if (!pass &&
1248 (primary != bus->number || secondary <= bus->number ||
1249 secondary > subordinate)) {
1250 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1251 secondary, subordinate);
1252 broken = 1;
1253 }
1254
1255
1256
1257
1258
1259 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1260 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1261 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1262
1263 pci_enable_crs(dev);
1264
1265 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1266 !is_cardbus && !broken) {
1267 unsigned int cmax;
1268
1269
1270
1271
1272
1273 if (pass)
1274 goto out;
1275
1276
1277
1278
1279
1280
1281
1282 child = pci_find_bus(pci_domain_nr(bus), secondary);
1283 if (!child) {
1284 child = pci_add_new_bus(bus, dev, secondary);
1285 if (!child)
1286 goto out;
1287 child->primary = primary;
1288 pci_bus_insert_busn_res(child, secondary, subordinate);
1289 child->bridge_ctl = bctl;
1290 }
1291
1292 cmax = pci_scan_child_bus(child);
1293 if (cmax > subordinate)
1294 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1295 subordinate, cmax);
1296
1297
1298 if (subordinate > max)
1299 max = subordinate;
1300 } else {
1301
1302
1303
1304
1305
1306 if (!pass) {
1307 if (pcibios_assign_all_busses() || broken || is_cardbus)
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1318 buses & ~0xffffff);
1319 goto out;
1320 }
1321
1322
1323 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1324
1325
1326 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1327 if (fixed_buses)
1328 next_busnr = fixed_sec;
1329 else
1330 next_busnr = max + 1;
1331
1332
1333
1334
1335
1336
1337 child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1338 if (!child) {
1339 child = pci_add_new_bus(bus, dev, next_busnr);
1340 if (!child)
1341 goto out;
1342 pci_bus_insert_busn_res(child, next_busnr,
1343 bus->busn_res.end);
1344 }
1345 max++;
1346 if (available_buses)
1347 available_buses--;
1348
1349 buses = (buses & 0xff000000)
1350 | ((unsigned int)(child->primary) << 0)
1351 | ((unsigned int)(child->busn_res.start) << 8)
1352 | ((unsigned int)(child->busn_res.end) << 16);
1353
1354
1355
1356
1357
1358 if (is_cardbus) {
1359 buses &= ~0xff000000;
1360 buses |= CARDBUS_LATENCY_TIMER << 24;
1361 }
1362
1363
1364 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1365
1366 if (!is_cardbus) {
1367 child->bridge_ctl = bctl;
1368 max = pci_scan_child_bus_extend(child, available_buses);
1369 } else {
1370
1371
1372
1373
1374
1375
1376 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1377 struct pci_bus *parent = bus;
1378 if (pci_find_bus(pci_domain_nr(bus),
1379 max+i+1))
1380 break;
1381 while (parent->parent) {
1382 if ((!pcibios_assign_all_busses()) &&
1383 (parent->busn_res.end > max) &&
1384 (parent->busn_res.end <= max+i)) {
1385 j = 1;
1386 }
1387 parent = parent->parent;
1388 }
1389 if (j) {
1390
1391
1392
1393
1394
1395
1396 i /= 2;
1397 break;
1398 }
1399 }
1400 max += i;
1401 }
1402
1403
1404
1405
1406
1407
1408 if (fixed_buses)
1409 max = fixed_sub;
1410 pci_bus_update_busn_res_end(child, max);
1411 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1412 }
1413
1414 sprintf(child->name,
1415 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1416 pci_domain_nr(bus), child->number);
1417
1418
1419 while (bus->parent) {
1420 if ((child->busn_res.end > bus->busn_res.end) ||
1421 (child->number > bus->busn_res.end) ||
1422 (child->number < bus->number) ||
1423 (child->busn_res.end < bus->number)) {
1424 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1425 &child->busn_res);
1426 break;
1427 }
1428 bus = bus->parent;
1429 }
1430
1431out:
1432 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1433
1434 pm_runtime_put(&dev->dev);
1435
1436 return max;
1437}
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1459{
1460 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1461}
1462EXPORT_SYMBOL(pci_scan_bridge);
1463
1464
1465
1466
1467
1468static void pci_read_irq(struct pci_dev *dev)
1469{
1470 unsigned char irq;
1471
1472
1473 if (dev->is_virtfn) {
1474 dev->pin = 0;
1475 dev->irq = 0;
1476 return;
1477 }
1478
1479 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1480 dev->pin = irq;
1481 if (irq)
1482 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1483 dev->irq = irq;
1484}
1485
1486void set_pcie_port_type(struct pci_dev *pdev)
1487{
1488 int pos;
1489 u16 reg16;
1490 int type;
1491 struct pci_dev *parent;
1492
1493 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1494 if (!pos)
1495 return;
1496
1497 pdev->pcie_cap = pos;
1498 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1499 pdev->pcie_flags_reg = reg16;
1500 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1501 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1502
1503 parent = pci_upstream_bridge(pdev);
1504 if (!parent)
1505 return;
1506
1507
1508
1509
1510
1511
1512 type = pci_pcie_type(pdev);
1513 if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1514
1515
1516
1517
1518
1519 if (pcie_downstream_port(parent)) {
1520 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1521 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1522 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1523 }
1524 } else if (type == PCI_EXP_TYPE_UPSTREAM) {
1525
1526
1527
1528
1529
1530 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1531 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1532 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1533 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1534 }
1535 }
1536}
1537
1538void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1539{
1540 u32 reg32;
1541
1542 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1543 if (reg32 & PCI_EXP_SLTCAP_HPC)
1544 pdev->is_hotplug_bridge = 1;
1545}
1546
1547static void set_pcie_thunderbolt(struct pci_dev *dev)
1548{
1549 int vsec = 0;
1550 u32 header;
1551
1552 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1553 PCI_EXT_CAP_ID_VNDR))) {
1554 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1555
1556
1557 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1558 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1559 dev->is_thunderbolt = 1;
1560 return;
1561 }
1562 }
1563}
1564
1565static void set_pcie_untrusted(struct pci_dev *dev)
1566{
1567 struct pci_dev *parent;
1568
1569
1570
1571
1572
1573 parent = pci_upstream_bridge(dev);
1574 if (parent && (parent->untrusted || parent->external_facing))
1575 dev->untrusted = true;
1576}
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1595{
1596#ifdef CONFIG_PCI_QUIRKS
1597 int pos;
1598 u32 header, tmp;
1599
1600 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1601
1602 for (pos = PCI_CFG_SPACE_SIZE;
1603 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1604 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1605 || header != tmp)
1606 return false;
1607 }
1608
1609 return true;
1610#else
1611 return false;
1612#endif
1613}
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626static int pci_cfg_space_size_ext(struct pci_dev *dev)
1627{
1628 u32 status;
1629 int pos = PCI_CFG_SPACE_SIZE;
1630
1631 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1632 return PCI_CFG_SPACE_SIZE;
1633 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1634 return PCI_CFG_SPACE_SIZE;
1635
1636 return PCI_CFG_SPACE_EXP_SIZE;
1637}
1638
1639int pci_cfg_space_size(struct pci_dev *dev)
1640{
1641 int pos;
1642 u32 status;
1643 u16 class;
1644
1645#ifdef CONFIG_PCI_IOV
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656 if (dev->is_virtfn)
1657 return PCI_CFG_SPACE_EXP_SIZE;
1658#endif
1659
1660 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1661 return PCI_CFG_SPACE_SIZE;
1662
1663 class = dev->class >> 8;
1664 if (class == PCI_CLASS_BRIDGE_HOST)
1665 return pci_cfg_space_size_ext(dev);
1666
1667 if (pci_is_pcie(dev))
1668 return pci_cfg_space_size_ext(dev);
1669
1670 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1671 if (!pos)
1672 return PCI_CFG_SPACE_SIZE;
1673
1674 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1675 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1676 return pci_cfg_space_size_ext(dev);
1677
1678 return PCI_CFG_SPACE_SIZE;
1679}
1680
1681static u32 pci_class(struct pci_dev *dev)
1682{
1683 u32 class;
1684
1685#ifdef CONFIG_PCI_IOV
1686 if (dev->is_virtfn)
1687 return dev->physfn->sriov->class;
1688#endif
1689 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1690 return class;
1691}
1692
1693static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1694{
1695#ifdef CONFIG_PCI_IOV
1696 if (dev->is_virtfn) {
1697 *vendor = dev->physfn->sriov->subsystem_vendor;
1698 *device = dev->physfn->sriov->subsystem_device;
1699 return;
1700 }
1701#endif
1702 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1703 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1704}
1705
1706static u8 pci_hdr_type(struct pci_dev *dev)
1707{
1708 u8 hdr_type;
1709
1710#ifdef CONFIG_PCI_IOV
1711 if (dev->is_virtfn)
1712 return dev->physfn->sriov->hdr_type;
1713#endif
1714 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1715 return hdr_type;
1716}
1717
1718#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1719
1720
1721
1722
1723
1724
1725
1726
1727static int pci_intx_mask_broken(struct pci_dev *dev)
1728{
1729 u16 orig, toggle, new;
1730
1731 pci_read_config_word(dev, PCI_COMMAND, &orig);
1732 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1733 pci_write_config_word(dev, PCI_COMMAND, toggle);
1734 pci_read_config_word(dev, PCI_COMMAND, &new);
1735
1736 pci_write_config_word(dev, PCI_COMMAND, orig);
1737
1738
1739
1740
1741
1742
1743 if (new != toggle)
1744 return 1;
1745 return 0;
1746}
1747
1748static void early_dump_pci_device(struct pci_dev *pdev)
1749{
1750 u32 value[256 / 4];
1751 int i;
1752
1753 pci_info(pdev, "config space:\n");
1754
1755 for (i = 0; i < 256; i += 4)
1756 pci_read_config_dword(pdev, i, &value[i / 4]);
1757
1758 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1759 value, 256, false);
1760}
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772int pci_setup_device(struct pci_dev *dev)
1773{
1774 u32 class;
1775 u16 cmd;
1776 u8 hdr_type;
1777 int pos = 0;
1778 struct pci_bus_region region;
1779 struct resource *res;
1780
1781 hdr_type = pci_hdr_type(dev);
1782
1783 dev->sysdata = dev->bus->sysdata;
1784 dev->dev.parent = dev->bus->bridge;
1785 dev->dev.bus = &pci_bus_type;
1786 dev->hdr_type = hdr_type & 0x7f;
1787 dev->multifunction = !!(hdr_type & 0x80);
1788 dev->error_state = pci_channel_io_normal;
1789 set_pcie_port_type(dev);
1790
1791 pci_dev_assign_slot(dev);
1792
1793
1794
1795
1796
1797 dev->dma_mask = 0xffffffff;
1798
1799 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1800 dev->bus->number, PCI_SLOT(dev->devfn),
1801 PCI_FUNC(dev->devfn));
1802
1803 class = pci_class(dev);
1804
1805 dev->revision = class & 0xff;
1806 dev->class = class >> 8;
1807
1808 if (pci_early_dump)
1809 early_dump_pci_device(dev);
1810
1811
1812 dev->cfg_size = pci_cfg_space_size(dev);
1813
1814
1815 set_pcie_thunderbolt(dev);
1816
1817 set_pcie_untrusted(dev);
1818
1819
1820 dev->current_state = PCI_UNKNOWN;
1821
1822
1823 pci_fixup_device(pci_fixup_early, dev);
1824
1825 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1826 dev->vendor, dev->device, dev->hdr_type, dev->class);
1827
1828
1829 class = dev->class >> 8;
1830
1831 if (dev->non_compliant_bars && !dev->mmio_always_on) {
1832 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1833 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1834 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1835 cmd &= ~PCI_COMMAND_IO;
1836 cmd &= ~PCI_COMMAND_MEMORY;
1837 pci_write_config_word(dev, PCI_COMMAND, cmd);
1838 }
1839 }
1840
1841 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1842
1843 switch (dev->hdr_type) {
1844 case PCI_HEADER_TYPE_NORMAL:
1845 if (class == PCI_CLASS_BRIDGE_PCI)
1846 goto bad;
1847 pci_read_irq(dev);
1848 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1849
1850 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1851
1852
1853
1854
1855
1856
1857
1858 if (class == PCI_CLASS_STORAGE_IDE) {
1859 u8 progif;
1860 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1861 if ((progif & 1) == 0) {
1862 region.start = 0x1F0;
1863 region.end = 0x1F7;
1864 res = &dev->resource[0];
1865 res->flags = LEGACY_IO_RESOURCE;
1866 pcibios_bus_to_resource(dev->bus, res, ®ion);
1867 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1868 res);
1869 region.start = 0x3F6;
1870 region.end = 0x3F6;
1871 res = &dev->resource[1];
1872 res->flags = LEGACY_IO_RESOURCE;
1873 pcibios_bus_to_resource(dev->bus, res, ®ion);
1874 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1875 res);
1876 }
1877 if ((progif & 4) == 0) {
1878 region.start = 0x170;
1879 region.end = 0x177;
1880 res = &dev->resource[2];
1881 res->flags = LEGACY_IO_RESOURCE;
1882 pcibios_bus_to_resource(dev->bus, res, ®ion);
1883 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1884 res);
1885 region.start = 0x376;
1886 region.end = 0x376;
1887 res = &dev->resource[3];
1888 res->flags = LEGACY_IO_RESOURCE;
1889 pcibios_bus_to_resource(dev->bus, res, ®ion);
1890 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1891 res);
1892 }
1893 }
1894 break;
1895
1896 case PCI_HEADER_TYPE_BRIDGE:
1897
1898
1899
1900
1901
1902 pci_read_irq(dev);
1903 dev->transparent = ((dev->class & 0xff) == 1);
1904 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1905 pci_read_bridge_windows(dev);
1906 set_pcie_hotplug_bridge(dev);
1907 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1908 if (pos) {
1909 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1910 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1911 }
1912 break;
1913
1914 case PCI_HEADER_TYPE_CARDBUS:
1915 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1916 goto bad;
1917 pci_read_irq(dev);
1918 pci_read_bases(dev, 1, 0);
1919 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1920 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1921 break;
1922
1923 default:
1924 pci_err(dev, "unknown header type %02x, ignoring device\n",
1925 dev->hdr_type);
1926 return -EIO;
1927
1928 bad:
1929 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1930 dev->class, dev->hdr_type);
1931 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1932 }
1933
1934
1935 return 0;
1936}
1937
1938static void pci_configure_mps(struct pci_dev *dev)
1939{
1940 struct pci_dev *bridge = pci_upstream_bridge(dev);
1941 int mps, mpss, p_mps, rc;
1942
1943 if (!pci_is_pcie(dev))
1944 return;
1945
1946
1947 if (dev->is_virtfn)
1948 return;
1949
1950
1951
1952
1953
1954 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
1955 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1956 mps = 128;
1957 else
1958 mps = 128 << dev->pcie_mpss;
1959 rc = pcie_set_mps(dev, mps);
1960 if (rc) {
1961 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1962 mps);
1963 }
1964 return;
1965 }
1966
1967 if (!bridge || !pci_is_pcie(bridge))
1968 return;
1969
1970 mps = pcie_get_mps(dev);
1971 p_mps = pcie_get_mps(bridge);
1972
1973 if (mps == p_mps)
1974 return;
1975
1976 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1977 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1978 mps, pci_name(bridge), p_mps);
1979 return;
1980 }
1981
1982
1983
1984
1985
1986 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1987 return;
1988
1989 mpss = 128 << dev->pcie_mpss;
1990 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
1991 pcie_set_mps(bridge, mpss);
1992 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
1993 mpss, p_mps, 128 << bridge->pcie_mpss);
1994 p_mps = pcie_get_mps(bridge);
1995 }
1996
1997 rc = pcie_set_mps(dev, p_mps);
1998 if (rc) {
1999 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2000 p_mps);
2001 return;
2002 }
2003
2004 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
2005 p_mps, mps, mpss);
2006}
2007
2008int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
2009{
2010 struct pci_host_bridge *host;
2011 u32 cap;
2012 u16 ctl;
2013 int ret;
2014
2015 if (!pci_is_pcie(dev))
2016 return 0;
2017
2018 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
2019 if (ret)
2020 return 0;
2021
2022 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
2023 return 0;
2024
2025 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
2026 if (ret)
2027 return 0;
2028
2029 host = pci_find_host_bridge(dev->bus);
2030 if (!host)
2031 return 0;
2032
2033
2034
2035
2036
2037 if (host->no_ext_tags) {
2038 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
2039 pci_info(dev, "disabling Extended Tags\n");
2040 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2041 PCI_EXP_DEVCTL_EXT_TAG);
2042 }
2043 return 0;
2044 }
2045
2046 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
2047 pci_info(dev, "enabling Extended Tags\n");
2048 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
2049 PCI_EXP_DEVCTL_EXT_TAG);
2050 }
2051 return 0;
2052}
2053
2054
2055
2056
2057
2058
2059
2060bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
2061{
2062 u16 v;
2063
2064 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
2065
2066 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
2067}
2068EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
2069
2070static void pci_configure_relaxed_ordering(struct pci_dev *dev)
2071{
2072 struct pci_dev *root;
2073
2074
2075 if (dev->is_virtfn)
2076 return;
2077
2078 if (!pcie_relaxed_ordering_enabled(dev))
2079 return;
2080
2081
2082
2083
2084
2085 root = pcie_find_root_port(dev);
2086 if (!root)
2087 return;
2088
2089 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2090 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2091 PCI_EXP_DEVCTL_RELAX_EN);
2092 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2093 }
2094}
2095
2096static void pci_configure_ltr(struct pci_dev *dev)
2097{
2098#ifdef CONFIG_PCIEASPM
2099 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2100 struct pci_dev *bridge;
2101 u32 cap, ctl;
2102
2103 if (!pci_is_pcie(dev))
2104 return;
2105
2106
2107 dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
2108
2109 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2110 if (!(cap & PCI_EXP_DEVCAP2_LTR))
2111 return;
2112
2113 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2114 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2115 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2116 dev->ltr_path = 1;
2117 return;
2118 }
2119
2120 bridge = pci_upstream_bridge(dev);
2121 if (bridge && bridge->ltr_path)
2122 dev->ltr_path = 1;
2123
2124 return;
2125 }
2126
2127 if (!host->native_ltr)
2128 return;
2129
2130
2131
2132
2133
2134
2135 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
2136 ((bridge = pci_upstream_bridge(dev)) &&
2137 bridge->ltr_path)) {
2138 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2139 PCI_EXP_DEVCTL2_LTR_EN);
2140 dev->ltr_path = 1;
2141 }
2142#endif
2143}
2144
2145static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2146{
2147#ifdef CONFIG_PCI_PASID
2148 struct pci_dev *bridge;
2149 int pcie_type;
2150 u32 cap;
2151
2152 if (!pci_is_pcie(dev))
2153 return;
2154
2155 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2156 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2157 return;
2158
2159 pcie_type = pci_pcie_type(dev);
2160 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2161 pcie_type == PCI_EXP_TYPE_RC_END)
2162 dev->eetlp_prefix_path = 1;
2163 else {
2164 bridge = pci_upstream_bridge(dev);
2165 if (bridge && bridge->eetlp_prefix_path)
2166 dev->eetlp_prefix_path = 1;
2167 }
2168#endif
2169}
2170
2171static void pci_configure_serr(struct pci_dev *dev)
2172{
2173 u16 control;
2174
2175 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2176
2177
2178
2179
2180
2181 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2182 if (!(control & PCI_BRIDGE_CTL_SERR)) {
2183 control |= PCI_BRIDGE_CTL_SERR;
2184 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2185 }
2186 }
2187}
2188
2189static void pci_configure_device(struct pci_dev *dev)
2190{
2191 pci_configure_mps(dev);
2192 pci_configure_extended_tags(dev, NULL);
2193 pci_configure_relaxed_ordering(dev);
2194 pci_configure_ltr(dev);
2195 pci_configure_eetlp_prefix(dev);
2196 pci_configure_serr(dev);
2197
2198 pci_acpi_program_hp_params(dev);
2199}
2200
2201static void pci_release_capabilities(struct pci_dev *dev)
2202{
2203 pci_aer_exit(dev);
2204 pci_rcec_exit(dev);
2205 pci_vpd_release(dev);
2206 pci_iov_release(dev);
2207 pci_free_cap_save_buffers(dev);
2208}
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218static void pci_release_dev(struct device *dev)
2219{
2220 struct pci_dev *pci_dev;
2221
2222 pci_dev = to_pci_dev(dev);
2223 pci_release_capabilities(pci_dev);
2224 pci_release_of_node(pci_dev);
2225 pcibios_release_device(pci_dev);
2226 pci_bus_put(pci_dev->bus);
2227 kfree(pci_dev->driver_override);
2228 bitmap_free(pci_dev->dma_alias_mask);
2229 kfree(pci_dev);
2230}
2231
2232struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2233{
2234 struct pci_dev *dev;
2235
2236 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2237 if (!dev)
2238 return NULL;
2239
2240 INIT_LIST_HEAD(&dev->bus_list);
2241 dev->dev.type = &pci_dev_type;
2242 dev->bus = pci_bus_get(bus);
2243
2244 return dev;
2245}
2246EXPORT_SYMBOL(pci_alloc_dev);
2247
2248static bool pci_bus_crs_vendor_id(u32 l)
2249{
2250 return (l & 0xffff) == 0x0001;
2251}
2252
2253static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2254 int timeout)
2255{
2256 int delay = 1;
2257
2258 if (!pci_bus_crs_vendor_id(*l))
2259 return true;
2260
2261 if (!timeout)
2262 return false;
2263
2264
2265
2266
2267
2268
2269 while (pci_bus_crs_vendor_id(*l)) {
2270 if (delay > timeout) {
2271 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2272 pci_domain_nr(bus), bus->number,
2273 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2274
2275 return false;
2276 }
2277 if (delay >= 1000)
2278 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2279 pci_domain_nr(bus), bus->number,
2280 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2281
2282 msleep(delay);
2283 delay *= 2;
2284
2285 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2286 return false;
2287 }
2288
2289 if (delay >= 1000)
2290 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2291 pci_domain_nr(bus), bus->number,
2292 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2293
2294 return true;
2295}
2296
2297bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2298 int timeout)
2299{
2300 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2301 return false;
2302
2303
2304 if (*l == 0xffffffff || *l == 0x00000000 ||
2305 *l == 0x0000ffff || *l == 0xffff0000)
2306 return false;
2307
2308 if (pci_bus_crs_vendor_id(*l))
2309 return pci_bus_wait_crs(bus, devfn, l, timeout);
2310
2311 return true;
2312}
2313
2314bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2315 int timeout)
2316{
2317#ifdef CONFIG_PCI_QUIRKS
2318 struct pci_dev *bridge = bus->self;
2319
2320
2321
2322
2323
2324 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2325 bridge->device == 0x80b5)
2326 return pci_idt_bus_quirk(bus, devfn, l, timeout);
2327#endif
2328
2329 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2330}
2331EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2332
2333
2334
2335
2336
2337static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2338{
2339 struct pci_dev *dev;
2340 u32 l;
2341
2342 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2343 return NULL;
2344
2345 dev = pci_alloc_dev(bus);
2346 if (!dev)
2347 return NULL;
2348
2349 dev->devfn = devfn;
2350 dev->vendor = l & 0xffff;
2351 dev->device = (l >> 16) & 0xffff;
2352
2353 pci_set_of_node(dev);
2354
2355 if (pci_setup_device(dev)) {
2356 pci_bus_put(dev->bus);
2357 kfree(dev);
2358 return NULL;
2359 }
2360
2361 return dev;
2362}
2363
2364void pcie_report_downtraining(struct pci_dev *dev)
2365{
2366 if (!pci_is_pcie(dev))
2367 return;
2368
2369
2370 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2371 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2372 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2373 return;
2374
2375
2376 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2377 return;
2378
2379
2380 __pcie_print_link_status(dev, false);
2381}
2382
2383static void pci_init_capabilities(struct pci_dev *dev)
2384{
2385 pci_ea_init(dev);
2386 pci_msi_init(dev);
2387 pci_msix_init(dev);
2388
2389
2390 pci_allocate_cap_save_buffers(dev);
2391
2392 pci_pm_init(dev);
2393 pci_vpd_init(dev);
2394 pci_configure_ari(dev);
2395 pci_iov_init(dev);
2396 pci_ats_init(dev);
2397 pci_pri_init(dev);
2398 pci_pasid_init(dev);
2399 pci_acs_init(dev);
2400 pci_ptm_init(dev);
2401 pci_aer_init(dev);
2402 pci_dpc_init(dev);
2403 pci_rcec_init(dev);
2404
2405 pcie_report_downtraining(dev);
2406
2407 if (pci_probe_reset_function(dev) == 0)
2408 dev->reset_fn = 1;
2409}
2410
2411
2412
2413
2414
2415
2416static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2417{
2418 struct irq_domain *d;
2419
2420
2421
2422
2423
2424 d = dev_get_msi_domain(&dev->dev);
2425 if (d)
2426 return d;
2427
2428
2429
2430
2431
2432 d = pci_msi_get_device_domain(dev);
2433 if (d)
2434 return d;
2435
2436 return NULL;
2437}
2438
2439static void pci_set_msi_domain(struct pci_dev *dev)
2440{
2441 struct irq_domain *d;
2442
2443
2444
2445
2446
2447
2448 d = pci_dev_msi_domain(dev);
2449 if (!d)
2450 d = dev_get_msi_domain(&dev->bus->dev);
2451
2452 dev_set_msi_domain(&dev->dev, d);
2453}
2454
2455void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2456{
2457 int ret;
2458
2459 pci_configure_device(dev);
2460
2461 device_initialize(&dev->dev);
2462 dev->dev.release = pci_release_dev;
2463
2464 set_dev_node(&dev->dev, pcibus_to_node(bus));
2465 dev->dev.dma_mask = &dev->dma_mask;
2466 dev->dev.dma_parms = &dev->dma_parms;
2467 dev->dev.coherent_dma_mask = 0xffffffffull;
2468
2469 dma_set_max_seg_size(&dev->dev, 65536);
2470 dma_set_seg_boundary(&dev->dev, 0xffffffff);
2471
2472
2473 pci_fixup_device(pci_fixup_header, dev);
2474
2475 pci_reassigndev_resource_alignment(dev);
2476
2477 dev->state_saved = false;
2478
2479 pci_init_capabilities(dev);
2480
2481
2482
2483
2484
2485 down_write(&pci_bus_sem);
2486 list_add_tail(&dev->bus_list, &bus->devices);
2487 up_write(&pci_bus_sem);
2488
2489 ret = pcibios_add_device(dev);
2490 WARN_ON(ret < 0);
2491
2492
2493 pci_set_msi_domain(dev);
2494
2495
2496 dev->match_driver = false;
2497 ret = device_add(&dev->dev);
2498 WARN_ON(ret < 0);
2499}
2500
2501struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2502{
2503 struct pci_dev *dev;
2504
2505 dev = pci_get_slot(bus, devfn);
2506 if (dev) {
2507 pci_dev_put(dev);
2508 return dev;
2509 }
2510
2511 dev = pci_scan_device(bus, devfn);
2512 if (!dev)
2513 return NULL;
2514
2515 pci_device_add(dev, bus);
2516
2517 return dev;
2518}
2519EXPORT_SYMBOL(pci_scan_single_device);
2520
2521static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
2522{
2523 int pos;
2524 u16 cap = 0;
2525 unsigned next_fn;
2526
2527 if (pci_ari_enabled(bus)) {
2528 if (!dev)
2529 return 0;
2530 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2531 if (!pos)
2532 return 0;
2533
2534 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2535 next_fn = PCI_ARI_CAP_NFN(cap);
2536 if (next_fn <= fn)
2537 return 0;
2538
2539 return next_fn;
2540 }
2541
2542
2543 if (!dev || dev->multifunction)
2544 return (fn + 1) % 8;
2545
2546 return 0;
2547}
2548
2549static int only_one_child(struct pci_bus *bus)
2550{
2551 struct pci_dev *bridge = bus->self;
2552
2553
2554
2555
2556
2557 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2558 return 0;
2559
2560
2561
2562
2563
2564
2565 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
2566 return 1;
2567
2568 return 0;
2569}
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582int pci_scan_slot(struct pci_bus *bus, int devfn)
2583{
2584 unsigned fn, nr = 0;
2585 struct pci_dev *dev;
2586
2587 if (only_one_child(bus) && (devfn > 0))
2588 return 0;
2589
2590 dev = pci_scan_single_device(bus, devfn);
2591 if (!dev)
2592 return 0;
2593 if (!pci_dev_is_added(dev))
2594 nr++;
2595
2596 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2597 dev = pci_scan_single_device(bus, devfn + fn);
2598 if (dev) {
2599 if (!pci_dev_is_added(dev))
2600 nr++;
2601 dev->multifunction = 1;
2602 }
2603 }
2604
2605
2606 if (bus->self && nr)
2607 pcie_aspm_init_link_state(bus->self);
2608
2609 return nr;
2610}
2611EXPORT_SYMBOL(pci_scan_slot);
2612
2613static int pcie_find_smpss(struct pci_dev *dev, void *data)
2614{
2615 u8 *smpss = data;
2616
2617 if (!pci_is_pcie(dev))
2618 return 0;
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635 if (dev->is_hotplug_bridge &&
2636 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2637 *smpss = 0;
2638
2639 if (*smpss > dev->pcie_mpss)
2640 *smpss = dev->pcie_mpss;
2641
2642 return 0;
2643}
2644
2645static void pcie_write_mps(struct pci_dev *dev, int mps)
2646{
2647 int rc;
2648
2649 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2650 mps = 128 << dev->pcie_mpss;
2651
2652 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2653 dev->bus->self)
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668 mps = min(mps, pcie_get_mps(dev->bus->self));
2669 }
2670
2671 rc = pcie_set_mps(dev, mps);
2672 if (rc)
2673 pci_err(dev, "Failed attempting to set the MPS\n");
2674}
2675
2676static void pcie_write_mrrs(struct pci_dev *dev)
2677{
2678 int rc, mrrs;
2679
2680
2681
2682
2683
2684 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2685 return;
2686
2687
2688
2689
2690
2691
2692
2693 mrrs = pcie_get_mps(dev);
2694
2695
2696
2697
2698
2699
2700
2701 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2702 rc = pcie_set_readrq(dev, mrrs);
2703 if (!rc)
2704 break;
2705
2706 pci_warn(dev, "Failed attempting to set the MRRS\n");
2707 mrrs /= 2;
2708 }
2709
2710 if (mrrs < 128)
2711 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2712}
2713
2714static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2715{
2716 int mps, orig_mps;
2717
2718 if (!pci_is_pcie(dev))
2719 return 0;
2720
2721 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2722 pcie_bus_config == PCIE_BUS_DEFAULT)
2723 return 0;
2724
2725 mps = 128 << *(u8 *)data;
2726 orig_mps = pcie_get_mps(dev);
2727
2728 pcie_write_mps(dev, mps);
2729 pcie_write_mrrs(dev);
2730
2731 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2732 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2733 orig_mps, pcie_get_readrq(dev));
2734
2735 return 0;
2736}
2737
2738
2739
2740
2741
2742
2743void pcie_bus_configure_settings(struct pci_bus *bus)
2744{
2745 u8 smpss = 0;
2746
2747 if (!bus->self)
2748 return;
2749
2750 if (!pci_is_pcie(bus->self))
2751 return;
2752
2753
2754
2755
2756
2757
2758 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2759 smpss = 0;
2760
2761 if (pcie_bus_config == PCIE_BUS_SAFE) {
2762 smpss = bus->self->pcie_mpss;
2763
2764 pcie_find_smpss(bus->self, &smpss);
2765 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2766 }
2767
2768 pcie_bus_configure_set(bus->self, &smpss);
2769 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2770}
2771EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2772
2773
2774
2775
2776
2777void __weak pcibios_fixup_bus(struct pci_bus *bus)
2778{
2779
2780}
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2795 unsigned int available_buses)
2796{
2797 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2798 unsigned int start = bus->busn_res.start;
2799 unsigned int devfn, fn, cmax, max = start;
2800 struct pci_dev *dev;
2801 int nr_devs;
2802
2803 dev_dbg(&bus->dev, "scanning bus\n");
2804
2805
2806 for (devfn = 0; devfn < 256; devfn += 8) {
2807 nr_devs = pci_scan_slot(bus, devfn);
2808
2809
2810
2811
2812
2813
2814 if (jailhouse_paravirt() && nr_devs == 0) {
2815 for (fn = 1; fn < 8; fn++) {
2816 dev = pci_scan_single_device(bus, devfn + fn);
2817 if (dev)
2818 dev->multifunction = 1;
2819 }
2820 }
2821 }
2822
2823
2824 used_buses = pci_iov_bus_range(bus);
2825 max += used_buses;
2826
2827
2828
2829
2830
2831 if (!bus->is_added) {
2832 dev_dbg(&bus->dev, "fixups for bus\n");
2833 pcibios_fixup_bus(bus);
2834 bus->is_added = 1;
2835 }
2836
2837
2838
2839
2840
2841
2842 for_each_pci_bridge(dev, bus) {
2843 if (dev->is_hotplug_bridge)
2844 hotplug_bridges++;
2845 else
2846 normal_bridges++;
2847 }
2848
2849
2850
2851
2852
2853
2854 for_each_pci_bridge(dev, bus) {
2855 cmax = max;
2856 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2857
2858
2859
2860
2861
2862 used_buses++;
2863 if (cmax - max > 1)
2864 used_buses += cmax - max - 1;
2865 }
2866
2867
2868 for_each_pci_bridge(dev, bus) {
2869 unsigned int buses = 0;
2870
2871 if (!hotplug_bridges && normal_bridges == 1) {
2872
2873
2874
2875
2876
2877
2878
2879 buses = available_buses;
2880 } else if (dev->is_hotplug_bridge) {
2881
2882
2883
2884
2885
2886 buses = available_buses / hotplug_bridges;
2887 buses = min(buses, available_buses - used_buses + 1);
2888 }
2889
2890 cmax = max;
2891 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2892
2893 if (max - cmax > 1)
2894 used_buses += max - cmax - 1;
2895 }
2896
2897
2898
2899
2900
2901
2902 if (bus->self && bus->self->is_hotplug_bridge) {
2903 used_buses = max_t(unsigned int, available_buses,
2904 pci_hotplug_bus_size - 1);
2905 if (max - start < used_buses) {
2906 max = start + used_buses;
2907
2908
2909 if (max > bus->busn_res.end)
2910 max = bus->busn_res.end;
2911
2912 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2913 &bus->busn_res, max - start);
2914 }
2915 }
2916
2917
2918
2919
2920
2921
2922
2923
2924 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2925 return max;
2926}
2927
2928
2929
2930
2931
2932
2933
2934
2935unsigned int pci_scan_child_bus(struct pci_bus *bus)
2936{
2937 return pci_scan_child_bus_extend(bus, 0);
2938}
2939EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2940
2941
2942
2943
2944
2945
2946
2947
2948int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2949{
2950 return 0;
2951}
2952
2953void __weak pcibios_add_bus(struct pci_bus *bus)
2954{
2955}
2956
2957void __weak pcibios_remove_bus(struct pci_bus *bus)
2958{
2959}
2960
2961struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2962 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2963{
2964 int error;
2965 struct pci_host_bridge *bridge;
2966
2967 bridge = pci_alloc_host_bridge(0);
2968 if (!bridge)
2969 return NULL;
2970
2971 bridge->dev.parent = parent;
2972
2973 list_splice_init(resources, &bridge->windows);
2974 bridge->sysdata = sysdata;
2975 bridge->busnr = bus;
2976 bridge->ops = ops;
2977
2978 error = pci_register_host_bridge(bridge);
2979 if (error < 0)
2980 goto err_out;
2981
2982 return bridge->bus;
2983
2984err_out:
2985 put_device(&bridge->dev);
2986 return NULL;
2987}
2988EXPORT_SYMBOL_GPL(pci_create_root_bus);
2989
2990int pci_host_probe(struct pci_host_bridge *bridge)
2991{
2992 struct pci_bus *bus, *child;
2993 int ret;
2994
2995 ret = pci_scan_root_bus_bridge(bridge);
2996 if (ret < 0) {
2997 dev_err(bridge->dev.parent, "Scanning root bridge failed");
2998 return ret;
2999 }
3000
3001 bus = bridge->bus;
3002
3003
3004
3005
3006
3007
3008 if (pci_has_flag(PCI_PROBE_ONLY)) {
3009 pci_bus_claim_resources(bus);
3010 } else {
3011 pci_bus_size_bridges(bus);
3012 pci_bus_assign_resources(bus);
3013
3014 list_for_each_entry(child, &bus->children, node)
3015 pcie_bus_configure_settings(child);
3016 }
3017
3018 pci_bus_add_devices(bus);
3019 return 0;
3020}
3021EXPORT_SYMBOL_GPL(pci_host_probe);
3022
3023int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
3024{
3025 struct resource *res = &b->busn_res;
3026 struct resource *parent_res, *conflict;
3027
3028 res->start = bus;
3029 res->end = bus_max;
3030 res->flags = IORESOURCE_BUS;
3031
3032 if (!pci_is_root_bus(b))
3033 parent_res = &b->parent->busn_res;
3034 else {
3035 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
3036 res->flags |= IORESOURCE_PCI_FIXED;
3037 }
3038
3039 conflict = request_resource_conflict(parent_res, res);
3040
3041 if (conflict)
3042 dev_info(&b->dev,
3043 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3044 res, pci_is_root_bus(b) ? "domain " : "",
3045 parent_res, conflict->name, conflict);
3046
3047 return conflict == NULL;
3048}
3049
3050int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
3051{
3052 struct resource *res = &b->busn_res;
3053 struct resource old_res = *res;
3054 resource_size_t size;
3055 int ret;
3056
3057 if (res->start > bus_max)
3058 return -EINVAL;
3059
3060 size = bus_max - res->start + 1;
3061 ret = adjust_resource(res, res->start, size);
3062 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
3063 &old_res, ret ? "can not be" : "is", bus_max);
3064
3065 if (!ret && !res->parent)
3066 pci_bus_insert_busn_res(b, res->start, res->end);
3067
3068 return ret;
3069}
3070
3071void pci_bus_release_busn_res(struct pci_bus *b)
3072{
3073 struct resource *res = &b->busn_res;
3074 int ret;
3075
3076 if (!res->flags || !res->parent)
3077 return;
3078
3079 ret = release_resource(res);
3080 dev_info(&b->dev, "busn_res: %pR %s released\n",
3081 res, ret ? "can not be" : "is");
3082}
3083
3084int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3085{
3086 struct resource_entry *window;
3087 bool found = false;
3088 struct pci_bus *b;
3089 int max, bus, ret;
3090
3091 if (!bridge)
3092 return -EINVAL;
3093
3094 resource_list_for_each_entry(window, &bridge->windows)
3095 if (window->res->flags & IORESOURCE_BUS) {
3096 bridge->busnr = window->res->start;
3097 found = true;
3098 break;
3099 }
3100
3101 ret = pci_register_host_bridge(bridge);
3102 if (ret < 0)
3103 return ret;
3104
3105 b = bridge->bus;
3106 bus = bridge->busnr;
3107
3108 if (!found) {
3109 dev_info(&b->dev,
3110 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3111 bus);
3112 pci_bus_insert_busn_res(b, bus, 255);
3113 }
3114
3115 max = pci_scan_child_bus(b);
3116
3117 if (!found)
3118 pci_bus_update_busn_res_end(b, max);
3119
3120 return 0;
3121}
3122EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3123
3124struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3125 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3126{
3127 struct resource_entry *window;
3128 bool found = false;
3129 struct pci_bus *b;
3130 int max;
3131
3132 resource_list_for_each_entry(window, resources)
3133 if (window->res->flags & IORESOURCE_BUS) {
3134 found = true;
3135 break;
3136 }
3137
3138 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3139 if (!b)
3140 return NULL;
3141
3142 if (!found) {
3143 dev_info(&b->dev,
3144 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3145 bus);
3146 pci_bus_insert_busn_res(b, bus, 255);
3147 }
3148
3149 max = pci_scan_child_bus(b);
3150
3151 if (!found)
3152 pci_bus_update_busn_res_end(b, max);
3153
3154 return b;
3155}
3156EXPORT_SYMBOL(pci_scan_root_bus);
3157
3158struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3159 void *sysdata)
3160{
3161 LIST_HEAD(resources);
3162 struct pci_bus *b;
3163
3164 pci_add_resource(&resources, &ioport_resource);
3165 pci_add_resource(&resources, &iomem_resource);
3166 pci_add_resource(&resources, &busn_resource);
3167 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3168 if (b) {
3169 pci_scan_child_bus(b);
3170 } else {
3171 pci_free_resource_list(&resources);
3172 }
3173 return b;
3174}
3175EXPORT_SYMBOL(pci_scan_bus);
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3189{
3190 unsigned int max;
3191 struct pci_bus *bus = bridge->subordinate;
3192
3193 max = pci_scan_child_bus(bus);
3194
3195 pci_assign_unassigned_bridge_resources(bridge);
3196
3197 pci_bus_add_devices(bus);
3198
3199 return max;
3200}
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211unsigned int pci_rescan_bus(struct pci_bus *bus)
3212{
3213 unsigned int max;
3214
3215 max = pci_scan_child_bus(bus);
3216 pci_assign_unassigned_bus_resources(bus);
3217 pci_bus_add_devices(bus);
3218
3219 return max;
3220}
3221EXPORT_SYMBOL_GPL(pci_rescan_bus);
3222
3223
3224
3225
3226
3227static DEFINE_MUTEX(pci_rescan_remove_lock);
3228
3229void pci_lock_rescan_remove(void)
3230{
3231 mutex_lock(&pci_rescan_remove_lock);
3232}
3233EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3234
3235void pci_unlock_rescan_remove(void)
3236{
3237 mutex_unlock(&pci_rescan_remove_lock);
3238}
3239EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3240
3241static int __init pci_sort_bf_cmp(const struct device *d_a,
3242 const struct device *d_b)
3243{
3244 const struct pci_dev *a = to_pci_dev(d_a);
3245 const struct pci_dev *b = to_pci_dev(d_b);
3246
3247 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3248 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3249
3250 if (a->bus->number < b->bus->number) return -1;
3251 else if (a->bus->number > b->bus->number) return 1;
3252
3253 if (a->devfn < b->devfn) return -1;
3254 else if (a->devfn > b->devfn) return 1;
3255
3256 return 0;
3257}
3258
3259void __init pci_sort_breadthfirst(void)
3260{
3261 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3262}
3263
3264int pci_hp_add_bridge(struct pci_dev *dev)
3265{
3266 struct pci_bus *parent = dev->bus;
3267 int busnr, start = parent->busn_res.start;
3268 unsigned int available_buses = 0;
3269 int end = parent->busn_res.end;
3270
3271 for (busnr = start; busnr <= end; busnr++) {
3272 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3273 break;
3274 }
3275 if (busnr-- > end) {
3276 pci_err(dev, "No bus number available for hot-added bridge\n");
3277 return -1;
3278 }
3279
3280
3281 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3282
3283
3284
3285
3286
3287 available_buses = end - busnr;
3288
3289
3290 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3291
3292 if (!dev->subordinate)
3293 return -1;
3294
3295 return 0;
3296}
3297EXPORT_SYMBOL_GPL(pci_hp_add_bridge);
3298