LXR linux/drivers/phy/qualcomm/phy-qcom-qmp.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/clk.h>
   7#include <linux/clk-provider.h>
   8#include <linux/delay.h>
   9#include <linux/err.h>
  10#include <linux/io.h>
  11#include <linux/iopoll.h>
  12#include <linux/kernel.h>
  13#include <linux/module.h>
  14#include <linux/of.h>
  15#include <linux/of_device.h>
  16#include <linux/of_address.h>
  17#include <linux/phy/phy.h>
  18#include <linux/platform_device.h>
  19#include <linux/regulator/consumer.h>
  20#include <linux/reset.h>
  21#include <linux/slab.h>
  22
  23#include <dt-bindings/phy/phy.h>
  24
  25#include "phy-qcom-qmp.h"
  26
  27/* QPHY_SW_RESET bit */
  28#define SW_RESET                                BIT(0)
  29/* QPHY_POWER_DOWN_CONTROL */
  30#define SW_PWRDN                                BIT(0)
  31#define REFCLK_DRV_DSBL                         BIT(1)
  32/* QPHY_START_CONTROL bits */
  33#define SERDES_START                            BIT(0)
  34#define PCS_START                               BIT(1)
  35#define PLL_READY_GATE_EN                       BIT(3)
  36/* QPHY_PCS_STATUS bit */
  37#define PHYSTATUS                               BIT(6)
  38/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
  39#define PCS_READY                               BIT(0)
  40
  41/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  42/* DP PHY soft reset */
  43#define SW_DPPHY_RESET                          BIT(0)
  44/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  45#define SW_DPPHY_RESET_MUX                      BIT(1)
  46/* USB3 PHY soft reset */
  47#define SW_USB3PHY_RESET                        BIT(2)
  48/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  49#define SW_USB3PHY_RESET_MUX                    BIT(3)
  50
  51/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  52#define USB3_MODE                               BIT(0) /* enables USB3 mode */
  53#define DP_MODE                                 BIT(1) /* enables DP mode */
  54
  55/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  56#define ARCVR_DTCT_EN                           BIT(0)
  57#define ALFPS_DTCT_EN                           BIT(1)
  58#define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  59
  60/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  61#define IRQ_CLEAR                               BIT(0)
  62
  63/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
  64#define RCVR_DETECT                             BIT(0)
  65
  66/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
  67#define CLAMP_EN                                BIT(0) /* enables i/o clamp_n */
  68
  69#define PHY_INIT_COMPLETE_TIMEOUT               10000
  70#define POWER_DOWN_DELAY_US_MIN                 10
  71#define POWER_DOWN_DELAY_US_MAX                 11
  72
  73#define MAX_PROP_NAME                           32
  74
  75/* Define the assumed distance between lanes for underspecified device trees. */
  76#define QMP_PHY_LEGACY_LANE_STRIDE              0x400
  77
  78struct qmp_phy_init_tbl {
  79        unsigned int offset;
  80        unsigned int val;
  81        /*
  82         * register part of layout ?
  83         * if yes, then offset gives index in the reg-layout
  84         */
  85        bool in_layout;
  86        /*
  87         * mask of lanes for which this register is written
  88         * for cases when second lane needs different values
  89         */
  90        u8 lane_mask;
  91};
  92
  93#define QMP_PHY_INIT_CFG(o, v)          \
  94        {                               \
  95                .offset = o,            \
  96                .val = v,               \
  97                .lane_mask = 0xff,      \
  98        }
  99
 100#define QMP_PHY_INIT_CFG_L(o, v)        \
 101        {                               \
 102                .offset = o,            \
 103                .val = v,               \
 104                .in_layout = true,      \
 105                .lane_mask = 0xff,      \
 106        }
 107
 108#define QMP_PHY_INIT_CFG_LANE(o, v, l)  \
 109        {                               \
 110                .offset = o,            \
 111                .val = v,               \
 112                .lane_mask = l,         \
 113        }
 114
 115/* set of registers with offsets different per-PHY */
 116enum qphy_reg_layout {
 117        /* Common block control registers */
 118        QPHY_COM_SW_RESET,
 119        QPHY_COM_POWER_DOWN_CONTROL,
 120        QPHY_COM_START_CONTROL,
 121        QPHY_COM_PCS_READY_STATUS,
 122        /* PCS registers */
 123        QPHY_PLL_LOCK_CHK_DLY_TIME,
 124        QPHY_FLL_CNTRL1,
 125        QPHY_FLL_CNTRL2,
 126        QPHY_FLL_CNT_VAL_L,
 127        QPHY_FLL_CNT_VAL_H_TOL,
 128        QPHY_FLL_MAN_CODE,
 129        QPHY_SW_RESET,
 130        QPHY_START_CTRL,
 131        QPHY_PCS_READY_STATUS,
 132        QPHY_PCS_STATUS,
 133        QPHY_PCS_AUTONOMOUS_MODE_CTRL,
 134        QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
 135        QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
 136        QPHY_PCS_POWER_DOWN_CONTROL,
 137        /* Keep last to ensure regs_layout arrays are properly initialized */
 138        QPHY_LAYOUT_SIZE
 139};
 140
 141static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 142        [QPHY_START_CTRL]               = 0x00,
 143        [QPHY_PCS_READY_STATUS]         = 0x168,
 144};
 145
 146static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 147        [QPHY_COM_SW_RESET]             = 0x400,
 148        [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
 149        [QPHY_COM_START_CONTROL]        = 0x408,
 150        [QPHY_COM_PCS_READY_STATUS]     = 0x448,
 151        [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
 152        [QPHY_FLL_CNTRL1]               = 0xc4,
 153        [QPHY_FLL_CNTRL2]               = 0xc8,
 154        [QPHY_FLL_CNT_VAL_L]            = 0xcc,
 155        [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
 156        [QPHY_FLL_MAN_CODE]             = 0xd4,
 157        [QPHY_SW_RESET]                 = 0x00,
 158        [QPHY_START_CTRL]               = 0x08,
 159        [QPHY_PCS_STATUS]               = 0x174,
 160};
 161
 162static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 163        [QPHY_FLL_CNTRL1]               = 0xc0,
 164        [QPHY_FLL_CNTRL2]               = 0xc4,
 165        [QPHY_FLL_CNT_VAL_L]            = 0xc8,
 166        [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
 167        [QPHY_FLL_MAN_CODE]             = 0xd0,
 168        [QPHY_SW_RESET]                 = 0x00,
 169        [QPHY_START_CTRL]               = 0x08,
 170        [QPHY_PCS_STATUS]               = 0x17c,
 171        [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
 172        [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
 173        [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
 174};
 175
 176static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 177        [QPHY_SW_RESET]                 = 0x00,
 178        [QPHY_START_CTRL]               = 0x08,
 179        [QPHY_PCS_STATUS]               = 0x174,
 180        [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
 181        [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
 182        [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
 183};
 184
 185static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 186        [QPHY_SW_RESET]                 = 0x00,
 187        [QPHY_START_CTRL]               = 0x08,
 188        [QPHY_PCS_STATUS]               = 0x174,
 189};
 190
 191static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 192        [QPHY_SW_RESET]                 = 0x00,
 193        [QPHY_START_CTRL]               = 0x08,
 194        [QPHY_PCS_STATUS]               = 0x2ac,
 195};
 196
 197static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 198        [QPHY_SW_RESET]                 = 0x00,
 199        [QPHY_START_CTRL]               = 0x44,
 200        [QPHY_PCS_STATUS]               = 0x14,
 201        [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 202        [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
 203        [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
 204};
 205
 206static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 207        [QPHY_SW_RESET]                 = 0x00,
 208        [QPHY_START_CTRL]               = 0x44,
 209        [QPHY_PCS_STATUS]               = 0x14,
 210        [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 211        [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
 212        [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x614,
 213};
 214
 215static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 216        [QPHY_START_CTRL]               = 0x00,
 217        [QPHY_PCS_READY_STATUS]         = 0x160,
 218};
 219
 220static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
 221        [QPHY_SW_RESET]                 = 0x00,
 222        [QPHY_START_CTRL]               = 0x44,
 223        [QPHY_PCS_STATUS]               = 0x14,
 224        [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 225};
 226
 227static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 228        [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
 229        [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
 230        [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
 231};
 232
 233static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
 234        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
 235        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 236        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 237        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 238        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 239        QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 240        QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 241        QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 242        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 243        QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 244        /* PLL and Loop filter settings */
 245        QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 246        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 247        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 248        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 249        QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 250        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 251        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 252        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 253        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 254        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 255        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 256        QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 257        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 258        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 259        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 260        /* SSC settings */
 261        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 262        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 263        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 264        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 265        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 266        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 267        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 268};
 269
 270static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
 271        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
 272        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 273        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 274        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
 275        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 276        QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 277        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 278        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 279        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
 280};
 281
 282static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
 283        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 284        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
 285        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 286        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 287        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 288        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 289        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
 290        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 291        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 292        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 293        QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 294        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 295        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 296        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 297        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 298        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 299        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 300        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 301        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 302        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 303        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
 304        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
 305        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
 306};
 307
 308static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
 309        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
 310        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 311        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 312        QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 313        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
 314        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 315        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 316        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 317        QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
 318        QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 319        QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 320        QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 321        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
 322        QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 323        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 324        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 325        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 326        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 327        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
 328        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
 329        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 330        QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
 331        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 332        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
 333        QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 334        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 335        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 336        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 337        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 338        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 339        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 340        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 341        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
 342        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 343        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 344        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 345        QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
 346        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 347        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 348        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 349        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 350        QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 351        QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
 352};
 353
 354static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
 355        QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 356        QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 357};
 358
 359static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
 360        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 361        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
 362        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
 363        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 364        QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
 365        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 366        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
 367        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 368        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 369        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
 370};
 371
 372static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
 373        QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
 374        QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
 375        QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 376
 377        QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
 378
 379        QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
 380        QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
 381        QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
 382        QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
 383        QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
 384};
 385
 386static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
 387        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 388        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 389        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
 390        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 391        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 392        QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 393        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 394        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 395        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 396        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 397        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 398        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 399        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 400        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 401        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 402        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 403        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 404        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
 405        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
 406        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
 407        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 408        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 409        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 410        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 411        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
 412        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 413        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
 414        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 415        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 416        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 417        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
 418        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 419        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 420        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 421        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 422        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 423        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 424        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 425        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 426        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 427        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 428        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 429};
 430
 431static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
 432        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 433        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 434        QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 435        QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 436};
 437
 438static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
 439        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 440        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
 441        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 442        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
 443        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 444        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 445        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 446        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 447        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 448        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
 449        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 450        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 451        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 452        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 453};
 454
 455static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
 456        QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 457        QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 458        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 459        QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 460        QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 461        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 462        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 463        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 464        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
 465        QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 466};
 467
 468static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
 469        QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
 470        QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
 471        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
 472        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 473        QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 474        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 475        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 476        QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
 477        QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 478        QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
 479        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
 480        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
 481        QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 482        QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 483        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 484        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 485        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
 486        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
 487        QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
 488        QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 489        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
 490        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
 491        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
 492        QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 493        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 494        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 495        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 496        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 497        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
 498        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
 499        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
 500        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
 501        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 502        QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
 503        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
 504        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
 505        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
 506        QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
 507        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
 508        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
 509        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
 510        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 511        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
 512        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
 513        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
 514        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
 515        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
 516};
 517
 518static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
 519        QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 520        QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
 521};
 522
 523static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
 524        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
 525        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
 526        QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
 527        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
 528        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
 529        QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
 530        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
 531        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
 532        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
 533        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
 534        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
 535};
 536
 537static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
 538        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 539        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 540        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 541        QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 542        QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 543        QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 544        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 545        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 546        QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
 547        /* PLL and Loop filter settings */
 548        QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 549        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 550        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 551        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 552        QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 553        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 554        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 555        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 556        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 557        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 558        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 559        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 560        QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 561        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 562        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 563        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 564        /* SSC settings */
 565        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 566        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 567        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 568        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 569        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 570        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 571        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 572};
 573
 574static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
 575        QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 576        QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 577        QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 578};
 579
 580static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
 581        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 582        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 583        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 584        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 585        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
 586        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 587        QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 588        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 589        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
 590        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 591};
 592
 593static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
 594        /* FLL settings */
 595        QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
 596        QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
 597        QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
 598        QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
 599        QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
 600
 601        /* Lock Det settings */
 602        QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
 603        QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
 604        QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
 605        QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
 606};
 607
 608static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
 609        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
 610        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 611        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
 612        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
 613        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
 614        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 615        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 616        QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
 617        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
 618        QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
 619        QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
 620        QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
 621        QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
 622        QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 623        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
 624        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
 625        QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 626        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
 627        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 628        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 629        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
 630        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
 631        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
 632        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 633        QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
 634        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 635        QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
 636        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 637        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 638        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
 639        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 640        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
 641        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
 642        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 643        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
 644        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
 645        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
 646        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 647        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 648        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 649};
 650
 651static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
 652        QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 653        QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
 654        QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
 655        QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 656        QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
 657        QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
 658};
 659
 660static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
 661        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 662        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 663        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
 664        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
 665        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 666        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 667        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
 668};
 669
 670static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
 671        QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
 672        QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
 673        QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
 674        QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
 675        QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
 676        QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
 677        QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
 678        QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
 679        QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
 680        QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
 681        QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
 682        QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
 683        QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
 684};
 685
 686static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
 687        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 688        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 689        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
 690        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 691        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 692        QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 693        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 694        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 695        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 696        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 697        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 698        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 699        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 700        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 701        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 702        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 703        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 704        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 705        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 706        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 707        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 708        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 709        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 710        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 711        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 712        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 713        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 714        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
 715        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 716        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 717        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
 718        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 719        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 720        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 721        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 722        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 723        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 724        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 725        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 726        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 727        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 728        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 729};
 730
 731static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
 732        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 733        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 734        QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 735        QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 736};
 737
 738static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
 739        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 740        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
 741        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 742        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 743        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 744        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 745        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 746        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 747        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 748        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
 749        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 750        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
 751        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 752        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 753        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 754        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 755};
 756
 757static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
 758        QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 759
 760        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 761        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 762        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 763        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 764        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 765
 766        QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 767        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 768        QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 769        QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 770        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 771        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 772        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 773
 774        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
 775        QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 776        QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
 777
 778        QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
 779};
 780
 781static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
 782        QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
 783        QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
 784        QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
 785        QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
 786        QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
 787};
 788
 789static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
 790        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
 791        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
 792        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
 793        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
 794        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
 795        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
 796        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
 797        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
 798        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
 799        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
 800        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
 801        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
 802        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
 803        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
 804        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
 805        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
 806        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
 807        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
 808        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
 809        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
 810        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
 811        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
 812        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
 813        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
 814        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
 815        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
 816        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
 817        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
 818        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
 819        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
 820        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 821        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
 822        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
 823        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
 824        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
 825        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
 826        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
 827        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
 828        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
 829        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
 830        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
 831        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
 832        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
 833        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
 834        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
 835};
 836
 837static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
 838        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
 839        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
 840        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
 841        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
 842        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
 843        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
 844        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
 845        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
 846        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
 847        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
 848        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
 849        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
 850        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
 851        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
 852        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
 853        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
 854        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
 855        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
 856        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
 857        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
 858        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
 859        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
 860        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
 861        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
 862        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
 863        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
 864        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
 865        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
 866        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
 867        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
 868        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
 869        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
 870        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
 871        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
 872        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
 873        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
 874        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
 875        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
 876        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
 877        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
 878        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
 879        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
 880        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
 881        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
 882        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
 883        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
 884        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
 885        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
 886        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
 887        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
 888        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
 889        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
 890        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
 891        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
 892        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
 893        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
 894};
 895
 896static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
 897};
 898
 899static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
 900        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
 901        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
 902        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
 903        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
 904        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
 905        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
 906        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
 907};
 908
 909static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
 910        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 911        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 912        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 913        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 914        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 915        QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 916        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
 917        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 918        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 919        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 920        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 921        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 922        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 923        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 924        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 925        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 926        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 927        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 928        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 929        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 930        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 931        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 932        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 933        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 934        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 935        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 936        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 937        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 938        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 939        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 940        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 941        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 942        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 943        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 944        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 945        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 946};
 947
 948static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
 949        QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 950        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 951        QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 952        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 953        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 954};
 955
 956static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
 957        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 958        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
 959        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 960        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
 961        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
 962        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 963        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
 964        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
 965        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 966        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 967        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 968        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 969        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 970        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 971        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
 972        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
 973        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
 974        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 975        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 976        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 977        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 978};
 979
 980static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
 981        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
 982        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
 983        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
 984        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
 985        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
 986        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
 987        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
 988};
 989
 990static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
 991        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
 992        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
 993        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
 994        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
 995        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
 996        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
 997        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
 998};
 999
1000static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {

1001        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1002        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
1003        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
1004        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
1005        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
1006        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
1007        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1008};
1009
1010static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
1011        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
1012        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1013        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1014        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1015        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
1016        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
1017        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
1018};
1019
1020static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
1021        QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
1022        QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
1023        QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
1024        QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
1025        QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
1026        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
1027        QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
1028        QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1029        QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
1030        QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
1031        QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
1032        QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
1033        QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
1034        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1035        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1036};
1037
1038static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
1039        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1040        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1041        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1042        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1043        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1044        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1045        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1046        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
1047        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1048};
1049
1050static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
1051        /* FLL settings */
1052        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1053        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1054        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1055        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1056        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1057
1058        /* Lock Det settings */
1059        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1060        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1061        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1062        QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1063
1064        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1065        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1066        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1067        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1068        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1069        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1070        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1071        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1072        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1073        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1074        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1075        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1076        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1077        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1078        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1079        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1080        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1081        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1082        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1083
1084        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1085        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1086        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1087        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1088        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1089        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1090        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1091        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1092        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1093        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1094        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1095};
1096
1097static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
1098        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1099        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1100        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1101        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1102        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1103        QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1104        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1105        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1106        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1107        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1108        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1109        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1110        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1111        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1112        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1113        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1114        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1115        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1116        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1117        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1118        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1119        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1120        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1121        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1122        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1123        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1124        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1125        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1126        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
1127        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1128        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1129        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1130        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1131        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1132        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1133        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1134};
1135
1136static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
1137        QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1138        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1139        QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
1140        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
1141        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1142};
1143
1144static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
1145        QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
1146        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
1147        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1148        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1149        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1150        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1151        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1152        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1153        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1154        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1155        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1156};
1157
1158static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
1159        /* FLL settings */
1160        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1161        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1162        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1163        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1164        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1165
1166        /* Lock Det settings */
1167        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1168        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1169        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1170        QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1171
1172        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1173        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1174        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1175        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
1176        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
1177        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
1178        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
1179        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1180        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1181        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1182        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1183        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1184        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1185        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1186        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1187        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1188        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1189        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1190        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1191
1192        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1193        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1194        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1195        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1196        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1197        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1198        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1199        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1200        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1201        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1202        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1203
1204        QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
1205        QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
1206};
1207
1208static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
1209        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1210        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1211        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1212        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1213        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1214        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
1215        QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
1216        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1217        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1218        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
1219        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1220        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1221        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
1222        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
1223        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
1224        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
1225        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1226        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1227        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1228        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1229        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1230        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1231        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
1232        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1233        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
1234        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
1235        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
1236        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
1237        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
1238        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
1239        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
1240        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1241        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
1242        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
1243        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
1244        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
1245
1246        /* Rate B */
1247        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
1248};
1249
1250static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
1251        QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
1252        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
1253        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1254};
1255
1256static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
1257        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
1258        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
1259        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1260        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
1261        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1262        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
1263        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1264        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1265        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
1266        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1267        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1268        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
1269        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1270        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
1271        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1272        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
1273};
1274
1275static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
1276        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
1277        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1278        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
1279        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
1280        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
1281        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
1282        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
1283        QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
1284};
1285
1286static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
1287        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1288        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1289        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1290        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
1291        QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1292        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1293        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1294        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1295        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1296        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1297        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1298        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1299        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1300        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1301        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1302        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1303        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1304        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1305        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1306        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1307        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1308        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1309        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1310        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1311        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1312        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1313        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1314        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1315        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1316        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
1317        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
1318        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1319        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1320        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1321        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1322        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1323        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1324        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1325};
1326
1327static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
1328        QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1329        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1330        QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1331        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1332};
1333
1334static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
1335        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1336        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1337        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1338        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1339        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
1340        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1341        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
1342        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1343        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1344        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1345        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1346        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
1347        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1348        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1349        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1350        QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
1351        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
1352};
1353
1354static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
1355        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1356        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1357        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1358        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1359        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1360        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1361        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1362        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1363        QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1364        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1365        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1366        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1367        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1368        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1369        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1370        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1371        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1372        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
1373        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1374        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1375        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1376        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1377        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
1378        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1379        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1380        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1381        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1382        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1383        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1384        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1385        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1386        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1387        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1388        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1389        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
1390        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1391        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1392        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1393};
1394
1395static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
1396        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
1397        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
1398        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1399        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
1400        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1401        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1402        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
1403        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1404        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1405        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1406        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1407        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1408        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
1409        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
1410        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
1411        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1412        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
1413        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1414        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1415        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1416        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
1417        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
1418        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
1419        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
1420
1421        /* Rate B */
1422        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
1423};
1424
1425static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
1426        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
1427        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
1428        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
1429        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
1430        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
1431        QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
1432};
1433
1434static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
1435        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
1436        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
1437        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1438        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
1439        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
1440        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1441        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
1442        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1443        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
1444        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1445        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1446        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
1447        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1448        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1449        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
1450        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1451        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
1452        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1453        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1454        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
1455        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
1456        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
1457        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
1458        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
1459        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
1460        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
1461        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
1462        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1463        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
1464        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
1465        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
1466        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
1467        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1468        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
1469
1470};
1471
1472static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
1473        QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
1474        QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1475        QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
1476        QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
1477        QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
1478        QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
1479        QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
1480};
1481
1482static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
1483        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1484        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1485        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1486        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1487        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1488        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1489        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1490        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1491        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1492        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1493        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1494        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1495        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1496        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1497        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1498        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1499        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1500        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1501        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1502        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1503        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1504        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1505        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1506        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1507        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1508        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1509        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1510        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1511        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1512        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1513        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1514        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1515        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1516        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1517        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1518        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1519        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1520        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1521        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1522        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1523};
1524
1525static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
1526        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
1527        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
1528        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1529        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1530        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1531};
1532
1533static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
1534        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
1535        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1536        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1537        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1538        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1539        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1540        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1541        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1542        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1543        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1544        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1545        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
1546        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1547        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1548        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1549        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1550        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1551        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1552        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1553        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1554        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1555        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
1556        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
1557        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1558        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
1559        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1560        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1561        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1562        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1563        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1564        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1565        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1566        QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1567        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1568        QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1569        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1570};
1571
1572static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
1573        /* Lock Det settings */
1574        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1575        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1576        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1577
1578        QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1579        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1580        QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1581        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1582        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1583        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1584        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1585        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1586        QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1587        QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1588};
1589
1590static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
1591        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1592        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1593        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1594        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1595        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1596        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1597        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1598        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1599        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1600        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1601        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1602        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1603        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1604        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1605        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1606        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1607        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1608        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1609        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1610        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1611        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1612        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1613        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1614        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1615        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1616        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1617        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1618        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1619        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1620        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1621        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1622        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1623        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1624        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1625        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1626        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1627        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1628        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1629        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1630        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1631};
1632
1633static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
1634        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1635        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
1636        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
1637        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
1638};
1639
1640static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
1641        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
1642        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1643        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
1644        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
1645        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
1646        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1647        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1648        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1649        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1650        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1651        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1652        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1653        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1654        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1655        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1656        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1657        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1658        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1659        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1660        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
1661        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1662        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1663        QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1664        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1665        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1666        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1667        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1668        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1669        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1670        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1671        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1672        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1673        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1674        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
1675        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1676        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1677};
1678
1679static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
1680        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1681        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1682        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1683        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1684        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1685        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1686        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1687        QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
1688        QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1689        QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
1690        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1691        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1692        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1693        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1694        QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1695        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1696};
1697
1698static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
1699        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
1700        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
1701        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1702        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
1703        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1704        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1705        QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
1706        QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
1707};
1708
1709static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
1710        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
1711        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1712        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1713        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1714        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1715        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1716        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1717        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1718        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1719        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1720        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1721        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1722        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1723        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1724        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1725        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1726        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1727        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1728        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1729        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1730        QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
1731        QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
1732        QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
1733        QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
1734        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
1735        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1736        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
1737        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1738        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1739        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1740        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1741        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1742        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1743        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1744        QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1745        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1746        QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1747        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1748};
1749
1750static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
1751        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1752        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1753        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1754        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1755        QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1756        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
1757        QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1758        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1759        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1760        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1761        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1762        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1763        QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1764        QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1765};
1766
1767static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
1768        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1769        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1770        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
1771        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
1772        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1773        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
1774};
1775
1776static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
1777        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
1778        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
1779        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
1780        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
1781        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
1782        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1783        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1784        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1785        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1786        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1787        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1788        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1789        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1790        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1791        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1792        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1793        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1794        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1795        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1796        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
1797        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1798        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1799        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1800        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1801        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1802        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1803        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1804        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1805        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1806        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1807        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1808        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1809        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1810        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
1811        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1812        QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1813};
1814
1815static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
1816        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1817        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1818        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1819        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1820        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1821        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1822        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
1823        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1824        QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
1825        QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1826        QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1827        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1828        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1829        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1830        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1831        QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1832};
1833
1834static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
1835        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
1836        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
1837        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1838        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1839        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
1840        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1841        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
1842        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
1843        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1844        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1845        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1846        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
1847        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
1848        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
1849        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
1850        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
1851        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
1852        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1853        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
1854        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1855        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
1856        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
1857        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1858        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1859        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1860        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1861        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1862        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1863        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1864        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1865        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1866        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1867        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1868        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1869        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1870        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1871        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1872        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1873        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1874        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1875        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
1876};
1877
1878static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
1879        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
1880};
1881
1882static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
1883        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1884        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
1885        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1886};
1887
1888static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
1889        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1890        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
1891        QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
1892        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1893        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1894        QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
1895        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
1896        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
1897        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1898        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
1899        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1900        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1901        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
1902        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
1903        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
1904        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1905        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
1906        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
1907        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
1908        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
1909        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1910        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
1911        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
1912        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
1913        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1914        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1915        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
1916        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
1917        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1918        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
1919};
1920
1921static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
1922        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
1923        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
1924        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1925        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
1926        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
1927        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
1928};
1929
1930static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
1931        QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1932        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
1933        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
1934};
1935
1936static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
1937        QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
1938        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
1939};
1940
1941static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
1942        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1943        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1944        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1945        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
1946        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
1947        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
1948        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1949};
1950
1951static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
1952        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1953        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
1954};
1955
1956static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
1957        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1958};
1959
1960static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
1961        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
1962        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1963        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
1964        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1965};
1966
1967static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
1968        QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
1969        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
1970};
1971
1972static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
1973        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
1974        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
1975};
1976
1977/* struct qmp_phy_cfg - per-PHY initialization config */
1978struct qmp_phy_cfg {
1979        /* phy-type - PCIE/UFS/USB */
1980        unsigned int type;
1981        /* number of lanes provided by phy */
1982        int nlanes;
1983
1984        /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1985        const struct qmp_phy_init_tbl *serdes_tbl;
1986        int serdes_tbl_num;
1987        const struct qmp_phy_init_tbl *serdes_tbl_sec;
1988        int serdes_tbl_num_sec;
1989        const struct qmp_phy_init_tbl *tx_tbl;
1990        int tx_tbl_num;
1991        const struct qmp_phy_init_tbl *tx_tbl_sec;
1992        int tx_tbl_num_sec;
1993        const struct qmp_phy_init_tbl *rx_tbl;
1994        int rx_tbl_num;
1995        const struct qmp_phy_init_tbl *rx_tbl_sec;
1996        int rx_tbl_num_sec;
1997        const struct qmp_phy_init_tbl *pcs_tbl;
1998        int pcs_tbl_num;
1999        const struct qmp_phy_init_tbl *pcs_tbl_sec;
2000        int pcs_tbl_num_sec;

2001        const struct qmp_phy_init_tbl *pcs_misc_tbl;
2002        int pcs_misc_tbl_num;
2003        const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
2004        int pcs_misc_tbl_num_sec;
2005
2006        /* Init sequence for DP PHY block link rates */
2007        const struct qmp_phy_init_tbl *serdes_tbl_rbr;
2008        int serdes_tbl_rbr_num;
2009        const struct qmp_phy_init_tbl *serdes_tbl_hbr;
2010        int serdes_tbl_hbr_num;
2011        const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
2012        int serdes_tbl_hbr2_num;
2013        const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
2014        int serdes_tbl_hbr3_num;
2015
2016        /* clock ids to be requested */
2017        const char * const *clk_list;
2018        int num_clks;
2019        /* resets to be requested */
2020        const char * const *reset_list;
2021        int num_resets;
2022        /* regulators to be requested */
2023        const char * const *vreg_list;
2024        int num_vregs;
2025
2026        /* array of registers with different offsets */
2027        const unsigned int *regs;
2028
2029        unsigned int start_ctrl;
2030        unsigned int pwrdn_ctrl;
2031        unsigned int mask_com_pcs_ready;
2032
2033        /* true, if PHY has a separate PHY_COM control block */
2034        bool has_phy_com_ctrl;
2035        /* true, if PHY has a reset for individual lanes */
2036        bool has_lane_rst;
2037        /* true, if PHY needs delay after POWER_DOWN */
2038        bool has_pwrdn_delay;
2039        /* power_down delay in usec */
2040        int pwrdn_delay_min;
2041        int pwrdn_delay_max;
2042
2043        /* true, if PHY has a separate DP_COM control block */
2044        bool has_phy_dp_com_ctrl;
2045        /* true, if PHY has secondary tx/rx lanes to be configured */
2046        bool is_dual_lane_phy;
2047
2048        /* true, if PCS block has no separate SW_RESET register */
2049        bool no_pcs_sw_reset;
2050};
2051
2052struct qmp_phy_combo_cfg {
2053        const struct qmp_phy_cfg *usb_cfg;
2054        const struct qmp_phy_cfg *dp_cfg;
2055};
2056
2057/**
2058 * struct qmp_phy - per-lane phy descriptor
2059 *
2060 * @phy: generic phy
2061 * @cfg: phy specific configuration
2062 * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
2063 * @tx: iomapped memory space for lane's tx
2064 * @rx: iomapped memory space for lane's rx
2065 * @pcs: iomapped memory space for lane's pcs
2066 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
2067 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
2068 * @pcs_misc: iomapped memory space for lane's pcs_misc
2069 * @pipe_clk: pipe lock
2070 * @index: lane index
2071 * @qmp: QMP phy to which this lane belongs
2072 * @lane_rst: lane's reset controller
2073 * @mode: current PHY mode
2074 */
2075struct qmp_phy {
2076        struct phy *phy;
2077        const struct qmp_phy_cfg *cfg;
2078        void __iomem *serdes;
2079        void __iomem *tx;
2080        void __iomem *rx;
2081        void __iomem *pcs;
2082        void __iomem *tx2;
2083        void __iomem *rx2;
2084        void __iomem *pcs_misc;
2085        struct clk *pipe_clk;
2086        unsigned int index;
2087        struct qcom_qmp *qmp;
2088        struct reset_control *lane_rst;
2089        enum phy_mode mode;
2090        unsigned int dp_aux_cfg;
2091        struct phy_configure_opts_dp dp_opts;
2092        struct qmp_phy_dp_clks *dp_clks;
2093};
2094
2095struct qmp_phy_dp_clks {
2096        struct qmp_phy *qphy;
2097        struct clk_hw dp_link_hw;
2098        struct clk_hw dp_pixel_hw;
2099};
2100
2101/**
2102 * struct qcom_qmp - structure holding QMP phy block attributes
2103 *
2104 * @dev: device
2105 * @dp_com: iomapped memory space for phy's dp_com control block
2106 *
2107 * @clks: array of clocks required by phy
2108 * @resets: array of resets required by phy
2109 * @vregs: regulator supplies bulk data
2110 *
2111 * @phys: array of per-lane phy descriptors
2112 * @phy_mutex: mutex lock for PHY common block initialization
2113 * @init_count: phy common block initialization count
2114 * @ufs_reset: optional UFS PHY reset handle
2115 */
2116struct qcom_qmp {
2117        struct device *dev;
2118        void __iomem *dp_com;
2119
2120        struct clk_bulk_data *clks;
2121        struct reset_control **resets;
2122        struct regulator_bulk_data *vregs;
2123
2124        struct qmp_phy **phys;
2125
2126        struct mutex phy_mutex;
2127        int init_count;
2128
2129        struct reset_control *ufs_reset;
2130};
2131
2132static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
2133{
2134        u32 reg;
2135
2136        reg = readl(base + offset);
2137        reg |= val;
2138        writel(reg, base + offset);
2139
2140        /* ensure that above write is through */
2141        readl(base + offset);
2142}
2143
2144static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
2145{
2146        u32 reg;
2147
2148        reg = readl(base + offset);
2149        reg &= ~val;
2150        writel(reg, base + offset);
2151
2152        /* ensure that above write is through */
2153        readl(base + offset);
2154}
2155
2156/* list of clocks required by phy */
2157static const char * const msm8996_phy_clk_l[] = {
2158        "aux", "cfg_ahb", "ref",
2159};
2160
2161static const char * const msm8996_ufs_phy_clk_l[] = {
2162        "ref",
2163};
2164
2165static const char * const qmp_v3_phy_clk_l[] = {
2166        "aux", "cfg_ahb", "ref", "com_aux",
2167};
2168
2169static const char * const sdm845_pciephy_clk_l[] = {
2170        "aux", "cfg_ahb", "ref", "refgen",
2171};
2172
2173static const char * const qmp_v4_phy_clk_l[] = {
2174        "aux", "ref_clk_src", "ref", "com_aux",
2175};
2176
2177/* the primary usb3 phy on sm8250 doesn't have a ref clock */
2178static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
2179        "aux", "ref_clk_src", "com_aux"
2180};
2181
2182static const char * const sdm845_ufs_phy_clk_l[] = {
2183        "ref", "ref_aux",
2184};
2185
2186/* list of resets */
2187static const char * const msm8996_pciephy_reset_l[] = {
2188        "phy", "common", "cfg",
2189};
2190
2191static const char * const msm8996_usb3phy_reset_l[] = {
2192        "phy", "common",
2193};
2194
2195static const char * const sc7180_usb3phy_reset_l[] = {
2196        "phy",
2197};
2198
2199static const char * const sdm845_pciephy_reset_l[] = {
2200        "phy",
2201};
2202
2203/* list of regulators */
2204static const char * const qmp_phy_vreg_l[] = {
2205        "vdda-phy", "vdda-pll",
2206};
2207
2208static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
2209        .type                   = PHY_TYPE_USB3,
2210        .nlanes                 = 1,
2211
2212        .serdes_tbl             = ipq8074_usb3_serdes_tbl,
2213        .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
2214        .tx_tbl                 = msm8996_usb3_tx_tbl,
2215        .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
2216        .rx_tbl                 = ipq8074_usb3_rx_tbl,
2217        .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
2218        .pcs_tbl                = ipq8074_usb3_pcs_tbl,
2219        .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
2220        .clk_list               = msm8996_phy_clk_l,
2221        .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
2222        .reset_list             = msm8996_usb3phy_reset_l,
2223        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2224        .vreg_list              = qmp_phy_vreg_l,
2225        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2226        .regs                   = usb3phy_regs_layout,
2227
2228        .start_ctrl             = SERDES_START | PCS_START,
2229        .pwrdn_ctrl             = SW_PWRDN,
2230};
2231
2232static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
2233        .type                   = PHY_TYPE_PCIE,
2234        .nlanes                 = 3,
2235
2236        .serdes_tbl             = msm8996_pcie_serdes_tbl,
2237        .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
2238        .tx_tbl                 = msm8996_pcie_tx_tbl,
2239        .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
2240        .rx_tbl                 = msm8996_pcie_rx_tbl,
2241        .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
2242        .pcs_tbl                = msm8996_pcie_pcs_tbl,
2243        .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
2244        .clk_list               = msm8996_phy_clk_l,
2245        .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
2246        .reset_list             = msm8996_pciephy_reset_l,
2247        .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
2248        .vreg_list              = qmp_phy_vreg_l,
2249        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2250        .regs                   = pciephy_regs_layout,
2251
2252        .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
2253        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2254        .mask_com_pcs_ready     = PCS_READY,
2255
2256        .has_phy_com_ctrl       = true,
2257        .has_lane_rst           = true,
2258        .has_pwrdn_delay        = true,
2259        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
2260        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
2261};
2262
2263static const struct qmp_phy_cfg msm8996_ufs_cfg = {
2264        .type                   = PHY_TYPE_UFS,
2265        .nlanes                 = 1,
2266
2267        .serdes_tbl             = msm8996_ufs_serdes_tbl,
2268        .serdes_tbl_num         = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
2269        .tx_tbl                 = msm8996_ufs_tx_tbl,
2270        .tx_tbl_num             = ARRAY_SIZE(msm8996_ufs_tx_tbl),
2271        .rx_tbl                 = msm8996_ufs_rx_tbl,
2272        .rx_tbl_num             = ARRAY_SIZE(msm8996_ufs_rx_tbl),
2273
2274        .clk_list               = msm8996_ufs_phy_clk_l,
2275        .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
2276
2277        .vreg_list              = qmp_phy_vreg_l,
2278        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2279
2280        .regs                   = msm8996_ufsphy_regs_layout,
2281
2282        .start_ctrl             = SERDES_START,
2283        .pwrdn_ctrl             = SW_PWRDN,
2284
2285        .no_pcs_sw_reset        = true,
2286};
2287
2288static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
2289        .type                   = PHY_TYPE_USB3,
2290        .nlanes                 = 1,
2291
2292        .serdes_tbl             = msm8996_usb3_serdes_tbl,
2293        .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
2294        .tx_tbl                 = msm8996_usb3_tx_tbl,
2295        .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
2296        .rx_tbl                 = msm8996_usb3_rx_tbl,
2297        .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
2298        .pcs_tbl                = msm8996_usb3_pcs_tbl,
2299        .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
2300        .clk_list               = msm8996_phy_clk_l,
2301        .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
2302        .reset_list             = msm8996_usb3phy_reset_l,
2303        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2304        .vreg_list              = qmp_phy_vreg_l,
2305        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2306        .regs                   = usb3phy_regs_layout,
2307
2308        .start_ctrl             = SERDES_START | PCS_START,
2309        .pwrdn_ctrl             = SW_PWRDN,
2310};
2311
2312static const char * const ipq8074_pciephy_clk_l[] = {
2313        "aux", "cfg_ahb",
2314};
2315/* list of resets */
2316static const char * const ipq8074_pciephy_reset_l[] = {
2317        "phy", "common",
2318};
2319
2320static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
2321        .type                   = PHY_TYPE_PCIE,
2322        .nlanes                 = 1,
2323
2324        .serdes_tbl             = ipq8074_pcie_serdes_tbl,
2325        .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
2326        .tx_tbl                 = ipq8074_pcie_tx_tbl,
2327        .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
2328        .rx_tbl                 = ipq8074_pcie_rx_tbl,
2329        .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
2330        .pcs_tbl                = ipq8074_pcie_pcs_tbl,
2331        .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
2332        .clk_list               = ipq8074_pciephy_clk_l,
2333        .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
2334        .reset_list             = ipq8074_pciephy_reset_l,
2335        .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2336        .vreg_list              = NULL,
2337        .num_vregs              = 0,
2338        .regs                   = pciephy_regs_layout,
2339
2340        .start_ctrl             = SERDES_START | PCS_START,
2341        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2342
2343        .has_phy_com_ctrl       = false,
2344        .has_lane_rst           = false,
2345        .has_pwrdn_delay        = true,
2346        .pwrdn_delay_min        = 995,          /* us */
2347        .pwrdn_delay_max        = 1005,         /* us */
2348};
2349
2350static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
2351        .type = PHY_TYPE_PCIE,
2352        .nlanes = 1,
2353
2354        .serdes_tbl             = sdm845_qmp_pcie_serdes_tbl,
2355        .serdes_tbl_num         = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
2356        .tx_tbl                 = sdm845_qmp_pcie_tx_tbl,
2357        .tx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
2358        .rx_tbl                 = sdm845_qmp_pcie_rx_tbl,
2359        .rx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
2360        .pcs_tbl                = sdm845_qmp_pcie_pcs_tbl,
2361        .pcs_tbl_num            = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
2362        .pcs_misc_tbl           = sdm845_qmp_pcie_pcs_misc_tbl,
2363        .pcs_misc_tbl_num       = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
2364        .clk_list               = sdm845_pciephy_clk_l,
2365        .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
2366        .reset_list             = sdm845_pciephy_reset_l,
2367        .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2368        .vreg_list              = qmp_phy_vreg_l,
2369        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2370        .regs                   = sdm845_qmp_pciephy_regs_layout,
2371
2372        .start_ctrl             = PCS_START | SERDES_START,
2373        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2374
2375        .has_pwrdn_delay        = true,
2376        .pwrdn_delay_min        = 995,          /* us */
2377        .pwrdn_delay_max        = 1005,         /* us */
2378};
2379
2380static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
2381        .type = PHY_TYPE_PCIE,
2382        .nlanes = 1,
2383
2384        .serdes_tbl             = sdm845_qhp_pcie_serdes_tbl,
2385        .serdes_tbl_num         = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
2386        .tx_tbl                 = sdm845_qhp_pcie_tx_tbl,
2387        .tx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
2388        .rx_tbl                 = sdm845_qhp_pcie_rx_tbl,
2389        .rx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
2390        .pcs_tbl                = sdm845_qhp_pcie_pcs_tbl,
2391        .pcs_tbl_num            = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
2392        .clk_list               = sdm845_pciephy_clk_l,
2393        .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
2394        .reset_list             = sdm845_pciephy_reset_l,
2395        .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2396        .vreg_list              = qmp_phy_vreg_l,
2397        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2398        .regs                   = sdm845_qhp_pciephy_regs_layout,
2399
2400        .start_ctrl             = PCS_START | SERDES_START,
2401        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2402
2403        .has_pwrdn_delay        = true,
2404        .pwrdn_delay_min        = 995,          /* us */
2405        .pwrdn_delay_max        = 1005,         /* us */
2406};
2407
2408static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
2409        .type = PHY_TYPE_PCIE,
2410        .nlanes = 1,
2411
2412        .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
2413        .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
2414        .serdes_tbl_sec         = sm8250_qmp_gen3x1_pcie_serdes_tbl,
2415        .serdes_tbl_num_sec     = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
2416        .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
2417        .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
2418        .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
2419        .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
2420        .rx_tbl_sec             = sm8250_qmp_gen3x1_pcie_rx_tbl,
2421        .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
2422        .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
2423        .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
2424        .pcs_tbl_sec            = sm8250_qmp_gen3x1_pcie_pcs_tbl,
2425        .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
2426        .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
2427        .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
2428        .pcs_misc_tbl_sec               = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
2429        .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
2430        .clk_list               = sdm845_pciephy_clk_l,
2431        .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
2432        .reset_list             = sdm845_pciephy_reset_l,
2433        .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2434        .vreg_list              = qmp_phy_vreg_l,
2435        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2436        .regs                   = sm8250_pcie_regs_layout,
2437
2438        .start_ctrl             = PCS_START | SERDES_START,
2439        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2440
2441        .has_pwrdn_delay        = true,
2442        .pwrdn_delay_min        = 995,          /* us */
2443        .pwrdn_delay_max        = 1005,         /* us */
2444};
2445
2446static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
2447        .type = PHY_TYPE_PCIE,
2448        .nlanes = 2,
2449
2450        .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
2451        .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
2452        .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
2453        .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
2454        .tx_tbl_sec             = sm8250_qmp_gen3x2_pcie_tx_tbl,
2455        .tx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
2456        .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
2457        .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
2458        .rx_tbl_sec             = sm8250_qmp_gen3x2_pcie_rx_tbl,
2459        .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
2460        .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
2461        .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
2462        .pcs_tbl_sec            = sm8250_qmp_gen3x2_pcie_pcs_tbl,
2463        .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
2464        .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
2465        .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
2466        .pcs_misc_tbl_sec               = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
2467        .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
2468        .clk_list               = sdm845_pciephy_clk_l,
2469        .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
2470        .reset_list             = sdm845_pciephy_reset_l,
2471        .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2472        .vreg_list              = qmp_phy_vreg_l,
2473        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2474        .regs                   = sm8250_pcie_regs_layout,
2475
2476        .start_ctrl             = PCS_START | SERDES_START,
2477        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2478
2479        .is_dual_lane_phy       = true,
2480        .has_pwrdn_delay        = true,
2481        .pwrdn_delay_min        = 995,          /* us */
2482        .pwrdn_delay_max        = 1005,         /* us */
2483};
2484
2485static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
2486        .type                   = PHY_TYPE_USB3,
2487        .nlanes                 = 1,
2488
2489        .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
2490        .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
2491        .tx_tbl                 = qmp_v3_usb3_tx_tbl,
2492        .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
2493        .rx_tbl                 = qmp_v3_usb3_rx_tbl,
2494        .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
2495        .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
2496        .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
2497        .clk_list               = qmp_v3_phy_clk_l,
2498        .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
2499        .reset_list             = msm8996_usb3phy_reset_l,
2500        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2501        .vreg_list              = qmp_phy_vreg_l,
2502        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2503        .regs                   = qmp_v3_usb3phy_regs_layout,
2504
2505        .start_ctrl             = SERDES_START | PCS_START,
2506        .pwrdn_ctrl             = SW_PWRDN,
2507
2508        .has_pwrdn_delay        = true,
2509        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
2510        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
2511
2512        .has_phy_dp_com_ctrl    = true,
2513        .is_dual_lane_phy       = true,
2514};
2515
2516static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
2517        .type                   = PHY_TYPE_USB3,
2518        .nlanes                 = 1,
2519
2520        .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
2521        .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
2522        .tx_tbl                 = qmp_v3_usb3_tx_tbl,
2523        .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
2524        .rx_tbl                 = qmp_v3_usb3_rx_tbl,
2525        .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
2526        .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
2527        .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
2528        .clk_list               = qmp_v3_phy_clk_l,
2529        .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
2530        .reset_list             = sc7180_usb3phy_reset_l,
2531        .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
2532        .vreg_list              = qmp_phy_vreg_l,
2533        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2534        .regs                   = qmp_v3_usb3phy_regs_layout,
2535
2536        .start_ctrl             = SERDES_START | PCS_START,
2537        .pwrdn_ctrl             = SW_PWRDN,
2538
2539        .has_pwrdn_delay        = true,
2540        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
2541        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
2542
2543        .has_phy_dp_com_ctrl    = true,
2544        .is_dual_lane_phy       = true,
2545};
2546
2547static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
2548        .type                   = PHY_TYPE_DP,
2549        .nlanes                 = 1,
2550
2551        .serdes_tbl             = qmp_v3_dp_serdes_tbl,
2552        .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
2553        .tx_tbl                 = qmp_v3_dp_tx_tbl,
2554        .tx_tbl_num             = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
2555
2556        .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
2557        .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
2558        .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
2559        .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
2560        .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
2561        .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
2562        .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
2563        .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
2564
2565        .clk_list               = qmp_v3_phy_clk_l,
2566        .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
2567        .reset_list             = sc7180_usb3phy_reset_l,
2568        .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
2569        .vreg_list              = qmp_phy_vreg_l,
2570        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2571        .regs                   = qmp_v3_usb3phy_regs_layout,
2572
2573        .has_phy_dp_com_ctrl    = true,
2574        .is_dual_lane_phy       = true,
2575};
2576
2577static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
2578        .usb_cfg                = &sc7180_usb3phy_cfg,
2579        .dp_cfg                 = &sc7180_dpphy_cfg,
2580};
2581
2582static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
2583        .type                   = PHY_TYPE_USB3,
2584        .nlanes                 = 1,
2585
2586        .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
2587        .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
2588        .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
2589        .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
2590        .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
2591        .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
2592        .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
2593        .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
2594        .clk_list               = qmp_v3_phy_clk_l,
2595        .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
2596        .reset_list             = msm8996_usb3phy_reset_l,
2597        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2598        .vreg_list              = qmp_phy_vreg_l,
2599        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2600        .regs                   = qmp_v3_usb3phy_regs_layout,
2601
2602        .start_ctrl             = SERDES_START | PCS_START,
2603        .pwrdn_ctrl             = SW_PWRDN,
2604
2605        .has_pwrdn_delay        = true,
2606        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
2607        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
2608};
2609
2610static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
2611        .type                   = PHY_TYPE_UFS,
2612        .nlanes                 = 2,
2613
2614        .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
2615        .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
2616        .tx_tbl                 = sdm845_ufsphy_tx_tbl,
2617        .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
2618        .rx_tbl                 = sdm845_ufsphy_rx_tbl,
2619        .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
2620        .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
2621        .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
2622        .clk_list               = sdm845_ufs_phy_clk_l,
2623        .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
2624        .vreg_list              = qmp_phy_vreg_l,
2625        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2626        .regs                   = sdm845_ufsphy_regs_layout,
2627
2628        .start_ctrl             = SERDES_START,
2629        .pwrdn_ctrl             = SW_PWRDN,
2630
2631        .is_dual_lane_phy       = true,
2632        .no_pcs_sw_reset        = true,
2633};
2634
2635static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
2636        .type                   = PHY_TYPE_PCIE,
2637        .nlanes                 = 1,
2638
2639        .serdes_tbl             = msm8998_pcie_serdes_tbl,
2640        .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
2641        .tx_tbl                 = msm8998_pcie_tx_tbl,
2642        .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
2643        .rx_tbl                 = msm8998_pcie_rx_tbl,
2644        .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
2645        .pcs_tbl                = msm8998_pcie_pcs_tbl,
2646        .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
2647        .clk_list               = msm8996_phy_clk_l,
2648        .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
2649        .reset_list             = ipq8074_pciephy_reset_l,
2650        .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2651        .vreg_list              = qmp_phy_vreg_l,
2652        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2653        .regs                   = pciephy_regs_layout,
2654
2655        .start_ctrl             = SERDES_START | PCS_START,
2656        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2657};
2658
2659static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
2660        .type                   = PHY_TYPE_USB3,
2661        .nlanes                 = 1,
2662
2663        .serdes_tbl             = msm8998_usb3_serdes_tbl,
2664        .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
2665        .tx_tbl                 = msm8998_usb3_tx_tbl,
2666        .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
2667        .rx_tbl                 = msm8998_usb3_rx_tbl,
2668        .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
2669        .pcs_tbl                = msm8998_usb3_pcs_tbl,
2670        .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
2671        .clk_list               = msm8996_phy_clk_l,
2672        .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
2673        .reset_list             = msm8996_usb3phy_reset_l,
2674        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2675        .vreg_list              = qmp_phy_vreg_l,
2676        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2677        .regs                   = qmp_v3_usb3phy_regs_layout,
2678
2679        .start_ctrl             = SERDES_START | PCS_START,
2680        .pwrdn_ctrl             = SW_PWRDN,
2681
2682        .is_dual_lane_phy       = true,
2683};
2684
2685static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
2686        .type                   = PHY_TYPE_UFS,
2687        .nlanes                 = 2,
2688
2689        .serdes_tbl             = sm8150_ufsphy_serdes_tbl,
2690        .serdes_tbl_num         = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
2691        .tx_tbl                 = sm8150_ufsphy_tx_tbl,
2692        .tx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
2693        .rx_tbl                 = sm8150_ufsphy_rx_tbl,
2694        .rx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
2695        .pcs_tbl                = sm8150_ufsphy_pcs_tbl,
2696        .pcs_tbl_num            = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
2697        .clk_list               = sdm845_ufs_phy_clk_l,
2698        .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
2699        .vreg_list              = qmp_phy_vreg_l,
2700        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2701        .regs                   = sm8150_ufsphy_regs_layout,
2702
2703        .start_ctrl             = SERDES_START,
2704        .pwrdn_ctrl             = SW_PWRDN,
2705
2706        .is_dual_lane_phy       = true,
2707};
2708
2709static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
2710        .type                   = PHY_TYPE_USB3,
2711        .nlanes                 = 1,
2712
2713        .serdes_tbl             = sm8150_usb3_serdes_tbl,
2714        .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
2715        .tx_tbl                 = sm8150_usb3_tx_tbl,
2716        .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
2717        .rx_tbl                 = sm8150_usb3_rx_tbl,
2718        .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
2719        .pcs_tbl                = sm8150_usb3_pcs_tbl,
2720        .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
2721        .clk_list               = qmp_v4_phy_clk_l,
2722        .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
2723        .reset_list             = msm8996_usb3phy_reset_l,
2724        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2725        .vreg_list              = qmp_phy_vreg_l,
2726        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2727        .regs                   = qmp_v4_usb3phy_regs_layout,
2728
2729        .start_ctrl             = SERDES_START | PCS_START,
2730        .pwrdn_ctrl             = SW_PWRDN,
2731
2732        .has_pwrdn_delay        = true,
2733        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
2734        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
2735
2736        .has_phy_dp_com_ctrl    = true,
2737        .is_dual_lane_phy       = true,
2738};
2739
2740static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
2741        .type                   = PHY_TYPE_USB3,
2742        .nlanes                 = 1,
2743
2744        .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
2745        .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
2746        .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
2747        .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
2748        .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
2749        .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
2750        .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
2751        .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
2752        .clk_list               = qmp_v4_phy_clk_l,
2753        .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
2754        .reset_list             = msm8996_usb3phy_reset_l,
2755        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2756        .vreg_list              = qmp_phy_vreg_l,
2757        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2758        .regs                   = qmp_v4_usb3_uniphy_regs_layout,
2759
2760        .start_ctrl             = SERDES_START | PCS_START,
2761        .pwrdn_ctrl             = SW_PWRDN,
2762
2763        .has_pwrdn_delay        = true,
2764        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
2765        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
2766};
2767
2768static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
2769        .type                   = PHY_TYPE_USB3,
2770        .nlanes                 = 1,
2771
2772        .serdes_tbl             = sm8150_usb3_serdes_tbl,
2773        .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
2774        .tx_tbl                 = sm8250_usb3_tx_tbl,
2775        .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
2776        .rx_tbl                 = sm8250_usb3_rx_tbl,
2777        .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
2778        .pcs_tbl                = sm8250_usb3_pcs_tbl,
2779        .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
2780        .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
2781        .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
2782        .reset_list             = msm8996_usb3phy_reset_l,
2783        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2784        .vreg_list              = qmp_phy_vreg_l,
2785        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2786        .regs                   = qmp_v4_usb3phy_regs_layout,
2787
2788        .start_ctrl             = SERDES_START | PCS_START,
2789        .pwrdn_ctrl             = SW_PWRDN,
2790
2791        .has_pwrdn_delay        = true,
2792        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
2793        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
2794
2795        .has_phy_dp_com_ctrl    = true,
2796        .is_dual_lane_phy       = true,
2797};
2798
2799static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
2800        .type                   = PHY_TYPE_USB3,
2801        .nlanes                 = 1,
2802
2803        .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
2804        .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
2805        .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
2806        .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
2807        .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
2808        .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
2809        .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
2810        .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
2811        .clk_list               = qmp_v4_phy_clk_l,
2812        .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
2813        .reset_list             = msm8996_usb3phy_reset_l,
2814        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2815        .vreg_list              = qmp_phy_vreg_l,
2816        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2817        .regs                   = qmp_v4_usb3_uniphy_regs_layout,
2818
2819        .start_ctrl             = SERDES_START | PCS_START,
2820        .pwrdn_ctrl             = SW_PWRDN,
2821
2822        .has_pwrdn_delay        = true,
2823        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
2824        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
2825};
2826
2827static void qcom_qmp_phy_configure_lane(void __iomem *base,
2828                                        const unsigned int *regs,
2829                                        const struct qmp_phy_init_tbl tbl[],
2830                                        int num,
2831                                        u8 lane_mask)
2832{
2833        int i;
2834        const struct qmp_phy_init_tbl *t = tbl;
2835
2836        if (!t)
2837                return;
2838
2839        for (i = 0; i < num; i++, t++) {
2840                if (!(t->lane_mask & lane_mask))
2841                        continue;
2842
2843                if (t->in_layout)
2844                        writel(t->val, base + regs[t->offset]);
2845                else
2846                        writel(t->val, base + t->offset);
2847        }
2848}
2849
2850static void qcom_qmp_phy_configure(void __iomem *base,
2851                                   const unsigned int *regs,
2852                                   const struct qmp_phy_init_tbl tbl[],
2853                                   int num)
2854{
2855        qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
2856}
2857
2858static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
2859{
2860        struct qcom_qmp *qmp = qphy->qmp;
2861        const struct qmp_phy_cfg *cfg = qphy->cfg;
2862        void __iomem *serdes = qphy->serdes;
2863        const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
2864        const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
2865        int serdes_tbl_num = cfg->serdes_tbl_num;
2866        int ret;
2867
2868        qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
2869        if (cfg->serdes_tbl_sec)
2870                qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
2871                                       cfg->serdes_tbl_num_sec);
2872
2873        if (cfg->type == PHY_TYPE_DP) {
2874                switch (dp_opts->link_rate) {
2875                case 1620:
2876                        qcom_qmp_phy_configure(serdes, cfg->regs,
2877                                               cfg->serdes_tbl_rbr,
2878                                               cfg->serdes_tbl_rbr_num);
2879                        break;
2880                case 2700:
2881                        qcom_qmp_phy_configure(serdes, cfg->regs,
2882                                               cfg->serdes_tbl_hbr,
2883                                               cfg->serdes_tbl_hbr_num);
2884                        break;
2885                case 5400:
2886                        qcom_qmp_phy_configure(serdes, cfg->regs,
2887                                               cfg->serdes_tbl_hbr2,
2888                                               cfg->serdes_tbl_hbr2_num);
2889                        break;
2890                case 8100:
2891                        qcom_qmp_phy_configure(serdes, cfg->regs,
2892                                               cfg->serdes_tbl_hbr3,
2893                                               cfg->serdes_tbl_hbr3_num);
2894                        break;
2895                default:
2896                        /* Other link rates aren't supported */
2897                        return -EINVAL;
2898                }
2899        }
2900
2901
2902        if (cfg->has_phy_com_ctrl) {
2903                void __iomem *status;
2904                unsigned int mask, val;
2905
2906                qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
2907                qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
2908                             SERDES_START | PCS_START);
2909
2910                status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
2911                mask = cfg->mask_com_pcs_ready;
2912
2913                ret = readl_poll_timeout(status, val, (val & mask), 10,
2914                                         PHY_INIT_COMPLETE_TIMEOUT);
2915                if (ret) {
2916                        dev_err(qmp->dev,
2917                                "phy common block init timed-out\n");
2918                        return ret;
2919                }
2920        }
2921
2922        return 0;
2923}
2924
2925static void qcom_qmp_phy_dp_aux_init(struct qmp_phy *qphy)
2926{
2927        writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2928               DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
2929               qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
2930
2931        /* Turn on BIAS current for PHY/PLL */
2932        writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
2933               QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
2934               qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
2935
2936        writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
2937
2938        writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2939               DP_PHY_PD_CTL_LANE_0_1_PWRDN |
2940               DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
2941               DP_PHY_PD_CTL_DP_CLAMP_EN,
2942               qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
2943
2944        writel(QSERDES_V3_COM_BIAS_EN |
2945               QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
2946               QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
2947               QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
2948               qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
2949
2950        writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0);
2951        writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
2952        writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
2953        writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3);
2954        writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4);
2955        writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5);
2956        writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6);
2957        writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7);
2958        writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8);
2959        writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9);
2960        qphy->dp_aux_cfg = 0;
2961
2962        writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2963               PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2964               PHY_AUX_REQ_ERR_MASK,
2965               qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
2966}
2967
2968static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
2969        { 0x00, 0x0c, 0x14, 0x19 },
2970        { 0x00, 0x0b, 0x12, 0xff },
2971        { 0x00, 0x0b, 0xff, 0xff },
2972        { 0x04, 0xff, 0xff, 0xff }
2973};
2974
2975static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
2976        { 0x08, 0x0f, 0x16, 0x1f },
2977        { 0x11, 0x1e, 0x1f, 0xff },
2978        { 0x19, 0x1f, 0xff, 0xff },
2979        { 0x1f, 0xff, 0xff, 0xff }
2980};
2981
2982static void qcom_qmp_phy_configure_dp_tx(struct qmp_phy *qphy)
2983{
2984        const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
2985        unsigned int v_level = 0, p_level = 0;
2986        u32 bias_en, drvr_en;
2987        u8 voltage_swing_cfg, pre_emphasis_cfg;
2988        int i;
2989
2990        for (i = 0; i < dp_opts->lanes; i++) {
2991                v_level = max(v_level, dp_opts->voltage[i]);
2992                p_level = max(p_level, dp_opts->pre[i]);
2993        }
2994
2995        if (dp_opts->lanes == 1) {
2996                bias_en = 0x3e;
2997                drvr_en = 0x13;
2998        } else {
2999                bias_en = 0x3f;
3000                drvr_en = 0x10;

3001        }
3002
3003        voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
3004        pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
3005
3006        /* TODO: Move check to config check */
3007        if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
3008                return;
3009
3010        /* Enable MUX to use Cursor values from these registers */
3011        voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
3012        pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
3013
3014        writel(voltage_swing_cfg, qphy->tx + QSERDES_V3_TX_TX_DRV_LVL);
3015        writel(pre_emphasis_cfg, qphy->tx + QSERDES_V3_TX_TX_EMP_POST1_LVL);
3016        writel(voltage_swing_cfg, qphy->tx2 + QSERDES_V3_TX_TX_DRV_LVL);
3017        writel(pre_emphasis_cfg, qphy->tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL);
3018
3019        writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
3020        writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
3021        writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
3022        writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
3023}
3024
3025static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
3026{
3027        const struct phy_configure_opts_dp *dp_opts = &opts->dp;
3028        struct qmp_phy *qphy = phy_get_drvdata(phy);
3029
3030        memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
3031        if (qphy->dp_opts.set_voltages) {
3032                qcom_qmp_phy_configure_dp_tx(qphy);
3033                qphy->dp_opts.set_voltages = 0;
3034        }
3035
3036        return 0;
3037}
3038
3039static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy)
3040{
3041        const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
3042        const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
3043        u32 val, phy_vco_div, status;
3044        unsigned long pixel_freq;
3045
3046        val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
3047              DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
3048
3049        /*
3050         * TODO: Assume orientation is CC1 for now and two lanes, need to
3051         * use type-c connector to understand orientation and lanes.
3052         *
3053         * Otherwise val changes to be like below if this code understood
3054         * the orientation of the type-c cable.
3055         *
3056         * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
3057         *      val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
3058         * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
3059         *      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
3060         * if (orientation == ORIENTATION_CC2)
3061         *      writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
3062         */
3063        val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
3064        writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
3065
3066        writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
3067        writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
3068        writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
3069
3070        switch (dp_opts->link_rate) {
3071        case 1620:
3072                phy_vco_div = 0x1;
3073                pixel_freq = 1620000000UL / 2;
3074                break;
3075        case 2700:
3076                phy_vco_div = 0x1;
3077                pixel_freq = 2700000000UL / 2;
3078                break;
3079        case 5400:
3080                phy_vco_div = 0x2;
3081                pixel_freq = 5400000000UL / 4;
3082                break;
3083        case 8100:
3084                phy_vco_div = 0x0;
3085                pixel_freq = 8100000000UL / 6;
3086                break;
3087        default:
3088                /* Other link rates aren't supported */
3089                return -EINVAL;
3090        }
3091        writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
3092
3093        clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
3094        clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
3095
3096        writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
3097        writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
3098        writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
3099        writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
3100        writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
3101
3102        writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
3103
3104        if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
3105                        status,
3106                        ((status & BIT(0)) > 0),
3107                        500,
3108                        10000))
3109                return -ETIMEDOUT;
3110
3111        writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
3112
3113        if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
3114                        status,
3115                        ((status & BIT(1)) > 0),
3116                        500,
3117                        10000))
3118                return -ETIMEDOUT;
3119
3120        writel(0x18, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
3121        udelay(2000);
3122        writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
3123
3124        return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
3125                        status,
3126                        ((status & BIT(1)) > 0),
3127                        500,
3128                        10000);
3129}
3130
3131/*
3132 * We need to calibrate the aux setting here as many times
3133 * as the caller tries
3134 */
3135static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
3136{
3137        struct qmp_phy *qphy = phy_get_drvdata(phy);
3138        const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
3139        u8 val;
3140
3141        qphy->dp_aux_cfg++;
3142        qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
3143        val = cfg1_settings[qphy->dp_aux_cfg];
3144
3145        writel(val, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
3146
3147        return 0;
3148}
3149
3150static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
3151{
3152        struct qcom_qmp *qmp = qphy->qmp;
3153        const struct qmp_phy_cfg *cfg = qphy->cfg;
3154        void __iomem *serdes = qphy->serdes;
3155        void __iomem *pcs = qphy->pcs;
3156        void __iomem *dp_com = qmp->dp_com;
3157        int ret, i;
3158
3159        mutex_lock(&qmp->phy_mutex);
3160        if (qmp->init_count++) {
3161                mutex_unlock(&qmp->phy_mutex);
3162                return 0;
3163        }
3164
3165        /* turn on regulator supplies */
3166        ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
3167        if (ret) {
3168                dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
3169                goto err_reg_enable;
3170        }
3171
3172        for (i = 0; i < cfg->num_resets; i++) {
3173                ret = reset_control_assert(qmp->resets[i]);
3174                if (ret) {
3175                        dev_err(qmp->dev, "%s reset assert failed\n",
3176                                cfg->reset_list[i]);
3177                        goto err_rst_assert;
3178                }
3179        }
3180
3181        for (i = cfg->num_resets - 1; i >= 0; i--) {
3182                ret = reset_control_deassert(qmp->resets[i]);
3183                if (ret) {
3184                        dev_err(qmp->dev, "%s reset deassert failed\n",
3185                                qphy->cfg->reset_list[i]);
3186                        goto err_rst;
3187                }
3188        }
3189
3190        ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
3191        if (ret) {
3192                dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
3193                goto err_rst;
3194        }
3195
3196        if (cfg->has_phy_dp_com_ctrl) {
3197                qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
3198                             SW_PWRDN);
3199                /* override hardware control for reset of qmp phy */
3200                qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
3201                             SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
3202                             SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
3203
3204                /* Default type-c orientation, i.e CC1 */
3205                qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
3206
3207                qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
3208                             USB3_MODE | DP_MODE);
3209
3210                /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
3211                qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
3212                             SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
3213                             SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
3214
3215                qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
3216                qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
3217        }
3218
3219        if (cfg->has_phy_com_ctrl) {
3220                qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
3221                             SW_PWRDN);
3222        } else {
3223                if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
3224                        qphy_setbits(pcs,
3225                                        cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
3226                                        cfg->pwrdn_ctrl);
3227                else
3228                        qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
3229                                        cfg->pwrdn_ctrl);
3230        }
3231
3232        mutex_unlock(&qmp->phy_mutex);
3233
3234        return 0;
3235
3236err_rst:
3237        while (++i < cfg->num_resets)
3238                reset_control_assert(qmp->resets[i]);
3239err_rst_assert:
3240        regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
3241err_reg_enable:
3242        mutex_unlock(&qmp->phy_mutex);
3243
3244        return ret;
3245}
3246
3247static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
3248{
3249        struct qcom_qmp *qmp = qphy->qmp;
3250        const struct qmp_phy_cfg *cfg = qphy->cfg;
3251        void __iomem *serdes = qphy->serdes;
3252        int i = cfg->num_resets;
3253
3254        mutex_lock(&qmp->phy_mutex);
3255        if (--qmp->init_count) {
3256                mutex_unlock(&qmp->phy_mutex);
3257                return 0;
3258        }
3259
3260        reset_control_assert(qmp->ufs_reset);
3261        if (cfg->has_phy_com_ctrl) {
3262                qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
3263                             SERDES_START | PCS_START);
3264                qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
3265                             SW_RESET);
3266                qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
3267                             SW_PWRDN);
3268        }
3269
3270        while (--i >= 0)
3271                reset_control_assert(qmp->resets[i]);
3272
3273        clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
3274
3275        regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
3276
3277        mutex_unlock(&qmp->phy_mutex);
3278
3279        return 0;
3280}
3281
3282static int qcom_qmp_phy_init(struct phy *phy)
3283{
3284        struct qmp_phy *qphy = phy_get_drvdata(phy);
3285        struct qcom_qmp *qmp = qphy->qmp;
3286        const struct qmp_phy_cfg *cfg = qphy->cfg;
3287        int ret;
3288        dev_vdbg(qmp->dev, "Initializing QMP phy\n");
3289
3290        if (cfg->no_pcs_sw_reset) {
3291                /*
3292                 * Get UFS reset, which is delayed until now to avoid a
3293                 * circular dependency where UFS needs its PHY, but the PHY
3294                 * needs this UFS reset.
3295                 */
3296                if (!qmp->ufs_reset) {
3297                        qmp->ufs_reset =
3298                                devm_reset_control_get_exclusive(qmp->dev,
3299                                                                 "ufsphy");
3300
3301                        if (IS_ERR(qmp->ufs_reset)) {
3302                                ret = PTR_ERR(qmp->ufs_reset);
3303                                dev_err(qmp->dev,
3304                                        "failed to get UFS reset: %d\n",
3305                                        ret);
3306
3307                                qmp->ufs_reset = NULL;
3308                                return ret;
3309                        }
3310                }
3311
3312                ret = reset_control_assert(qmp->ufs_reset);
3313                if (ret)
3314                        return ret;
3315        }
3316
3317        ret = qcom_qmp_phy_com_init(qphy);
3318        if (ret)
3319                return ret;
3320
3321        if (cfg->type == PHY_TYPE_DP)
3322                qcom_qmp_phy_dp_aux_init(qphy);
3323
3324        return 0;
3325}
3326
3327static int qcom_qmp_phy_power_on(struct phy *phy)
3328{
3329        struct qmp_phy *qphy = phy_get_drvdata(phy);
3330        struct qcom_qmp *qmp = qphy->qmp;
3331        const struct qmp_phy_cfg *cfg = qphy->cfg;
3332        void __iomem *tx = qphy->tx;
3333        void __iomem *rx = qphy->rx;
3334        void __iomem *pcs = qphy->pcs;
3335        void __iomem *pcs_misc = qphy->pcs_misc;
3336        void __iomem *status;
3337        unsigned int mask, val, ready;
3338        int ret;
3339
3340        qcom_qmp_phy_serdes_init(qphy);
3341
3342        if (cfg->has_lane_rst) {
3343                ret = reset_control_deassert(qphy->lane_rst);
3344                if (ret) {
3345                        dev_err(qmp->dev, "lane%d reset deassert failed\n",
3346                                qphy->index);
3347                        goto err_lane_rst;
3348                }
3349        }
3350
3351        ret = clk_prepare_enable(qphy->pipe_clk);
3352        if (ret) {
3353                dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
3354                goto err_clk_enable;
3355        }
3356
3357        /* Tx, Rx, and PCS configurations */
3358        qcom_qmp_phy_configure_lane(tx, cfg->regs,
3359                                    cfg->tx_tbl, cfg->tx_tbl_num, 1);
3360        if (cfg->tx_tbl_sec)
3361                qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
3362                                            cfg->tx_tbl_num_sec, 1);
3363
3364        /* Configuration for other LANE for USB-DP combo PHY */
3365        if (cfg->is_dual_lane_phy) {
3366                qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
3367                                            cfg->tx_tbl, cfg->tx_tbl_num, 2);
3368                if (cfg->tx_tbl_sec)
3369                        qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
3370                                                    cfg->tx_tbl_sec,
3371                                                    cfg->tx_tbl_num_sec, 2);
3372        }
3373
3374        /* Configure special DP tx tunings */
3375        if (cfg->type == PHY_TYPE_DP)
3376                qcom_qmp_phy_configure_dp_tx(qphy);
3377
3378        qcom_qmp_phy_configure_lane(rx, cfg->regs,
3379                                    cfg->rx_tbl, cfg->rx_tbl_num, 1);
3380        if (cfg->rx_tbl_sec)
3381                qcom_qmp_phy_configure_lane(rx, cfg->regs,
3382                                            cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
3383
3384        if (cfg->is_dual_lane_phy) {
3385                qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
3386                                            cfg->rx_tbl, cfg->rx_tbl_num, 2);
3387                if (cfg->rx_tbl_sec)
3388                        qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
3389                                                    cfg->rx_tbl_sec,
3390                                                    cfg->rx_tbl_num_sec, 2);
3391        }
3392
3393        /* Configure link rate, swing, etc. */
3394        if (cfg->type == PHY_TYPE_DP) {
3395                qcom_qmp_phy_configure_dp_phy(qphy);
3396        } else {
3397                qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
3398                if (cfg->pcs_tbl_sec)
3399                        qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
3400                                               cfg->pcs_tbl_num_sec);
3401        }
3402
3403        ret = reset_control_deassert(qmp->ufs_reset);
3404        if (ret)
3405                goto err_lane_rst;
3406
3407        qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
3408                               cfg->pcs_misc_tbl_num);
3409        if (cfg->pcs_misc_tbl_sec)
3410                qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
3411                                       cfg->pcs_misc_tbl_num_sec);
3412
3413        /*
3414         * Pull out PHY from POWER DOWN state.
3415         * This is active low enable signal to power-down PHY.
3416         */
3417        if(cfg->type == PHY_TYPE_PCIE)
3418                qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
3419
3420        if (cfg->has_pwrdn_delay)
3421                usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
3422
3423        if (cfg->type != PHY_TYPE_DP) {
3424                /* Pull PHY out of reset state */
3425                if (!cfg->no_pcs_sw_reset)
3426                        qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3427                /* start SerDes and Phy-Coding-Sublayer */
3428                qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
3429
3430                if (cfg->type == PHY_TYPE_UFS) {
3431                        status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
3432                        mask = PCS_READY;
3433                        ready = PCS_READY;
3434                } else {
3435                        status = pcs + cfg->regs[QPHY_PCS_STATUS];
3436                        mask = PHYSTATUS;
3437                        ready = 0;
3438                }
3439
3440                ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
3441                                         PHY_INIT_COMPLETE_TIMEOUT);
3442                if (ret) {
3443                        dev_err(qmp->dev, "phy initialization timed-out\n");
3444                        goto err_pcs_ready;
3445                }
3446        }
3447        return 0;
3448
3449err_pcs_ready:
3450        clk_disable_unprepare(qphy->pipe_clk);
3451err_clk_enable:
3452        if (cfg->has_lane_rst)
3453                reset_control_assert(qphy->lane_rst);
3454err_lane_rst:
3455        return ret;
3456}
3457
3458static int qcom_qmp_phy_power_off(struct phy *phy)
3459{
3460        struct qmp_phy *qphy = phy_get_drvdata(phy);
3461        const struct qmp_phy_cfg *cfg = qphy->cfg;
3462
3463        clk_disable_unprepare(qphy->pipe_clk);
3464
3465        if (cfg->type == PHY_TYPE_DP) {
3466                /* Assert DP PHY power down */
3467                writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
3468        } else {
3469                /* PHY reset */
3470                if (!cfg->no_pcs_sw_reset)
3471                        qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3472
3473                /* stop SerDes and Phy-Coding-Sublayer */
3474                qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
3475
3476                /* Put PHY into POWER DOWN state: active low */
3477                if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
3478                        qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
3479                                     cfg->pwrdn_ctrl);
3480                } else {
3481                        qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
3482                                        cfg->pwrdn_ctrl);
3483                }
3484        }
3485
3486        return 0;
3487}
3488
3489static int qcom_qmp_phy_exit(struct phy *phy)
3490{
3491        struct qmp_phy *qphy = phy_get_drvdata(phy);
3492        const struct qmp_phy_cfg *cfg = qphy->cfg;
3493
3494        if (cfg->has_lane_rst)
3495                reset_control_assert(qphy->lane_rst);
3496
3497        qcom_qmp_phy_com_exit(qphy);
3498
3499        return 0;
3500}
3501
3502static int qcom_qmp_phy_enable(struct phy *phy)
3503{
3504        int ret;
3505
3506        ret = qcom_qmp_phy_init(phy);
3507        if (ret)
3508                return ret;
3509
3510        ret = qcom_qmp_phy_power_on(phy);
3511        if (ret)
3512                qcom_qmp_phy_exit(phy);
3513
3514        return ret;
3515}
3516
3517static int qcom_qmp_phy_disable(struct phy *phy)
3518{
3519        int ret;
3520
3521        ret = qcom_qmp_phy_power_off(phy);
3522        if (ret)
3523                return ret;
3524        return qcom_qmp_phy_exit(phy);
3525}
3526
3527static int qcom_qmp_phy_set_mode(struct phy *phy,
3528                                 enum phy_mode mode, int submode)
3529{
3530        struct qmp_phy *qphy = phy_get_drvdata(phy);
3531
3532        qphy->mode = mode;
3533
3534        return 0;
3535}
3536
3537static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
3538{
3539        const struct qmp_phy_cfg *cfg = qphy->cfg;
3540        void __iomem *pcs = qphy->pcs;
3541        void __iomem *pcs_misc = qphy->pcs_misc;
3542        u32 intr_mask;
3543
3544        if (qphy->mode == PHY_MODE_USB_HOST_SS ||
3545            qphy->mode == PHY_MODE_USB_DEVICE_SS)
3546                intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
3547        else
3548                intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
3549
3550        /* Clear any pending interrupts status */
3551        qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3552        /* Writing 1 followed by 0 clears the interrupt */
3553        qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3554
3555        qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
3556                     ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
3557
3558        /* Enable required PHY autonomous mode interrupts */
3559        qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
3560
3561        /* Enable i/o clamp_n for autonomous mode */
3562        if (pcs_misc)
3563                qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
3564}
3565
3566static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
3567{
3568        const struct qmp_phy_cfg *cfg = qphy->cfg;
3569        void __iomem *pcs = qphy->pcs;
3570        void __iomem *pcs_misc = qphy->pcs_misc;
3571
3572        /* Disable i/o clamp_n on resume for normal mode */
3573        if (pcs_misc)
3574                qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
3575
3576        qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
3577                     ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
3578
3579        qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3580        /* Writing 1 followed by 0 clears the interrupt */
3581        qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3582}
3583
3584static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
3585{
3586        struct qcom_qmp *qmp = dev_get_drvdata(dev);
3587        struct qmp_phy *qphy = qmp->phys[0];
3588        const struct qmp_phy_cfg *cfg = qphy->cfg;
3589
3590        dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
3591
3592        /* Supported only for USB3 PHY and luckily USB3 is the first phy */
3593        if (cfg->type != PHY_TYPE_USB3)
3594                return 0;
3595
3596        if (!qmp->init_count) {
3597                dev_vdbg(dev, "PHY not initialized, bailing out\n");
3598                return 0;
3599        }
3600
3601        qcom_qmp_phy_enable_autonomous_mode(qphy);
3602
3603        clk_disable_unprepare(qphy->pipe_clk);
3604        clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
3605
3606        return 0;
3607}
3608
3609static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
3610{
3611        struct qcom_qmp *qmp = dev_get_drvdata(dev);
3612        struct qmp_phy *qphy = qmp->phys[0];
3613        const struct qmp_phy_cfg *cfg = qphy->cfg;
3614        int ret = 0;
3615
3616        dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
3617
3618        /* Supported only for USB3 PHY and luckily USB3 is the first phy */
3619        if (cfg->type != PHY_TYPE_USB3)
3620                return 0;
3621
3622        if (!qmp->init_count) {
3623                dev_vdbg(dev, "PHY not initialized, bailing out\n");
3624                return 0;
3625        }
3626
3627        ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
3628        if (ret) {
3629                dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
3630                return ret;
3631        }
3632
3633        ret = clk_prepare_enable(qphy->pipe_clk);
3634        if (ret) {
3635                dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
3636                clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
3637                return ret;
3638        }
3639
3640        qcom_qmp_phy_disable_autonomous_mode(qphy);
3641
3642        return 0;
3643}
3644
3645static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
3646{
3647        struct qcom_qmp *qmp = dev_get_drvdata(dev);
3648        int num = cfg->num_vregs;
3649        int i;
3650
3651        qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
3652        if (!qmp->vregs)
3653                return -ENOMEM;
3654
3655        for (i = 0; i < num; i++)
3656                qmp->vregs[i].supply = cfg->vreg_list[i];
3657
3658        return devm_regulator_bulk_get(dev, num, qmp->vregs);
3659}
3660
3661static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
3662{
3663        struct qcom_qmp *qmp = dev_get_drvdata(dev);
3664        int i;
3665
3666        qmp->resets = devm_kcalloc(dev, cfg->num_resets,
3667                                   sizeof(*qmp->resets), GFP_KERNEL);
3668        if (!qmp->resets)
3669                return -ENOMEM;
3670
3671        for (i = 0; i < cfg->num_resets; i++) {
3672                struct reset_control *rst;
3673                const char *name = cfg->reset_list[i];
3674
3675                rst = devm_reset_control_get(dev, name);
3676                if (IS_ERR(rst)) {
3677                        dev_err(dev, "failed to get %s reset\n", name);
3678                        return PTR_ERR(rst);
3679                }
3680                qmp->resets[i] = rst;
3681        }
3682
3683        return 0;
3684}
3685
3686static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
3687{
3688        struct qcom_qmp *qmp = dev_get_drvdata(dev);
3689        int num = cfg->num_clks;
3690        int i;
3691
3692        qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
3693        if (!qmp->clks)
3694                return -ENOMEM;
3695
3696        for (i = 0; i < num; i++)
3697                qmp->clks[i].id = cfg->clk_list[i];
3698
3699        return devm_clk_bulk_get(dev, num, qmp->clks);
3700}
3701
3702static void phy_clk_release_provider(void *res)
3703{
3704        of_clk_del_provider(res);
3705}
3706
3707/*
3708 * Register a fixed rate pipe clock.
3709 *
3710 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
3711 * controls it. The <s>_pipe_clk coming out of the GCC is requested
3712 * by the PHY driver for its operations.
3713 * We register the <s>_pipe_clksrc here. The gcc driver takes care
3714 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
3715 * Below picture shows this relationship.
3716 *
3717 *         +---------------+
3718 *         |   PHY block   |<<---------------------------------------+
3719 *         |               |                                         |
3720 *         |   +-------+   |                   +-----+               |
3721 *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
3722 *    clk  |   +-------+   |                   +-----+
3723 *         +---------------+
3724 */
3725static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
3726{
3727        struct clk_fixed_rate *fixed;
3728        struct clk_init_data init = { };
3729        int ret;
3730
3731        ret = of_property_read_string(np, "clock-output-names", &init.name);
3732        if (ret) {
3733                dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
3734                return ret;
3735        }
3736
3737        fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
3738        if (!fixed)
3739                return -ENOMEM;
3740
3741        init.ops = &clk_fixed_rate_ops;
3742
3743        /* controllers using QMP phys use 125MHz pipe clock interface */
3744        fixed->fixed_rate = 125000000;
3745        fixed->hw.init = &init;
3746
3747        ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
3748        if (ret)
3749                return ret;
3750
3751        ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
3752        if (ret)
3753                return ret;
3754
3755        /*
3756         * Roll a devm action because the clock provider is the child node, but
3757         * the child node is not actually a device.
3758         */
3759        ret = devm_add_action(qmp->dev, phy_clk_release_provider, np);
3760        if (ret)
3761                phy_clk_release_provider(np);
3762
3763        return ret;
3764}
3765
3766/*
3767 * Display Port PLL driver block diagram for branch clocks
3768 *
3769 *              +------------------------------+
3770 *              |         DP_VCO_CLK           |
3771 *              |                              |
3772 *              |    +-------------------+     |
3773 *              |    |   (DP PLL/VCO)    |     |
3774 *              |    +---------+---------+     |
3775 *              |              v               |
3776 *              |   +----------+-----------+   |
3777 *              |   | hsclk_divsel_clk_src |   |
3778 *              |   +----------+-----------+   |
3779 *              +------------------------------+
3780 *                              |
3781 *          +---------<---------v------------>----------+
3782 *          |                                           |
3783 * +--------v----------------+                          |
3784 * |    dp_phy_pll_link_clk  |                          |
3785 * |     link_clk            |                          |
3786 * +--------+----------------+                          |
3787 *          |                                           |
3788 *          |                                           |
3789 *          v                                           v
3790 * Input to DISPCC block                                |
3791 * for link clk, crypto clk                             |
3792 * and interface clock                                  |
3793 *                                                      |
3794 *                                                      |
3795 *      +--------<------------+-----------------+---<---+
3796 *      |                     |                 |
3797 * +----v---------+  +--------v-----+  +--------v------+
3798 * | vco_divided  |  | vco_divided  |  | vco_divided   |
3799 * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
3800 * |              |  |              |  |               |
3801 * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
3802 * +-------+------+  +-----+--------+  +--------+------+
3803 *         |                 |                  |
3804 *         v---->----------v-------------<------v
3805 *                         |
3806 *              +----------+-----------------+
3807 *              |   dp_phy_pll_vco_div_clk   |
3808 *              +---------+------------------+
3809 *                        |
3810 *                        v
3811 *              Input to DISPCC block
3812 *              for DP pixel clock
3813 *
3814 */
3815static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
3816                                                struct clk_rate_request *req)
3817{
3818        switch (req->rate) {
3819        case 1620000000UL / 2:
3820        case 2700000000UL / 2:
3821        /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
3822                return 0;
3823        default:
3824                return -EINVAL;
3825        }
3826}
3827
3828static unsigned long
3829qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
3830{
3831        const struct qmp_phy_dp_clks *dp_clks;
3832        const struct qmp_phy *qphy;
3833        const struct phy_configure_opts_dp *dp_opts;
3834
3835        dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
3836        qphy = dp_clks->qphy;
3837        dp_opts = &qphy->dp_opts;
3838
3839        switch (dp_opts->link_rate) {
3840        case 1620:
3841                return 1620000000UL / 2;
3842        case 2700:
3843                return 2700000000UL / 2;
3844        case 5400:
3845                return 5400000000UL / 4;
3846        case 8100:
3847                return 8100000000UL / 6;
3848        default:
3849                return 0;
3850        }
3851}
3852
3853static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
3854        .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
3855        .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
3856};
3857
3858static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
3859                                               struct clk_rate_request *req)
3860{
3861        switch (req->rate) {
3862        case 162000000:
3863        case 270000000:
3864        case 540000000:
3865        case 810000000:
3866                return 0;
3867        default:
3868                return -EINVAL;
3869        }
3870}
3871
3872static unsigned long
3873qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
3874{
3875        const struct qmp_phy_dp_clks *dp_clks;
3876        const struct qmp_phy *qphy;
3877        const struct phy_configure_opts_dp *dp_opts;
3878
3879        dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
3880        qphy = dp_clks->qphy;
3881        dp_opts = &qphy->dp_opts;
3882
3883        switch (dp_opts->link_rate) {
3884        case 1620:
3885        case 2700:
3886        case 5400:
3887        case 8100:
3888                return dp_opts->link_rate * 100000;
3889        default:
3890                return 0;
3891        }
3892}
3893
3894static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
3895        .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
3896        .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
3897};
3898
3899static struct clk_hw *
3900qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
3901{
3902        struct qmp_phy_dp_clks *dp_clks = data;
3903        unsigned int idx = clkspec->args[0];
3904
3905        if (idx >= 2) {
3906                pr_err("%s: invalid index %u\n", __func__, idx);
3907                return ERR_PTR(-EINVAL);
3908        }
3909
3910        if (idx == 0)
3911                return &dp_clks->dp_link_hw;
3912
3913        return &dp_clks->dp_pixel_hw;
3914}
3915
3916static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
3917                                struct device_node *np)
3918{
3919        struct clk_init_data init = { };
3920        struct qmp_phy_dp_clks *dp_clks;
3921        int ret;
3922
3923        dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
3924        if (!dp_clks)
3925                return -ENOMEM;
3926
3927        dp_clks->qphy = qphy;
3928        qphy->dp_clks = dp_clks;
3929
3930        init.ops = &qcom_qmp_dp_link_clk_ops;
3931        init.name = "qmp_dp_phy_pll_link_clk";
3932        dp_clks->dp_link_hw.init = &init;
3933        ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
3934        if (ret)
3935                return ret;
3936
3937        init.ops = &qcom_qmp_dp_pixel_clk_ops;
3938        init.name = "qmp_dp_phy_pll_vco_div_clk";
3939        dp_clks->dp_pixel_hw.init = &init;
3940        ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
3941        if (ret)
3942                return ret;
3943
3944        ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
3945        if (ret)
3946                return ret;
3947
3948        /*
3949         * Roll a devm action because the clock provider is the child node, but
3950         * the child node is not actually a device.
3951         */
3952        ret = devm_add_action(qmp->dev, phy_clk_release_provider, np);
3953        if (ret)
3954                phy_clk_release_provider(np);
3955
3956        return ret;
3957}
3958
3959static const struct phy_ops qcom_qmp_phy_gen_ops = {
3960        .init           = qcom_qmp_phy_enable,
3961        .exit           = qcom_qmp_phy_disable,
3962        .set_mode       = qcom_qmp_phy_set_mode,
3963        .owner          = THIS_MODULE,
3964};
3965
3966static const struct phy_ops qcom_qmp_phy_dp_ops = {
3967        .init           = qcom_qmp_phy_init,
3968        .configure      = qcom_qmp_dp_phy_configure,
3969        .power_on       = qcom_qmp_phy_power_on,
3970        .calibrate      = qcom_qmp_dp_phy_calibrate,
3971        .power_off      = qcom_qmp_phy_power_off,
3972        .exit           = qcom_qmp_phy_exit,
3973        .set_mode       = qcom_qmp_phy_set_mode,
3974        .owner          = THIS_MODULE,
3975};
3976
3977static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
3978        .power_on       = qcom_qmp_phy_enable,
3979        .power_off      = qcom_qmp_phy_disable,
3980        .set_mode       = qcom_qmp_phy_set_mode,
3981        .owner          = THIS_MODULE,
3982};
3983
3984static
3985int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
3986                        void __iomem *serdes, const struct qmp_phy_cfg *cfg)
3987{
3988        struct qcom_qmp *qmp = dev_get_drvdata(dev);
3989        struct phy *generic_phy;
3990        struct qmp_phy *qphy;
3991        const struct phy_ops *ops;
3992        char prop_name[MAX_PROP_NAME];
3993        int ret;
3994
3995        qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
3996        if (!qphy)
3997                return -ENOMEM;
3998
3999        qphy->cfg = cfg;
4000        qphy->serdes = serdes;

4001        /*
4002         * Get memory resources for each phy lane:
4003         * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
4004         * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
4005         * For single lane PHYs: pcs_misc (optional) -> 3.
4006         */
4007        qphy->tx = of_iomap(np, 0);
4008        if (!qphy->tx)
4009                return -ENOMEM;
4010
4011        qphy->rx = of_iomap(np, 1);
4012        if (!qphy->rx)
4013                return -ENOMEM;
4014
4015        qphy->pcs = of_iomap(np, 2);
4016        if (!qphy->pcs)
4017                return -ENOMEM;
4018
4019        /*
4020         * If this is a dual-lane PHY, then there should be registers for the
4021         * second lane. Some old device trees did not specify this, so fall
4022         * back to old legacy behavior of assuming they can be reached at an
4023         * offset from the first lane.
4024         */
4025        if (cfg->is_dual_lane_phy) {
4026                qphy->tx2 = of_iomap(np, 3);
4027                qphy->rx2 = of_iomap(np, 4);
4028                if (!qphy->tx2 || !qphy->rx2) {
4029                        dev_warn(dev,
4030                                 "Underspecified device tree, falling back to legacy register regions\n");
4031
4032                        /* In the old version, pcs_misc is at index 3. */
4033                        qphy->pcs_misc = qphy->tx2;
4034                        qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
4035                        qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
4036
4037                } else {
4038                        qphy->pcs_misc = of_iomap(np, 5);
4039                }
4040
4041        } else {
4042                qphy->pcs_misc = of_iomap(np, 3);
4043        }
4044
4045        if (!qphy->pcs_misc)
4046                dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
4047
4048        /*
4049         * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
4050         * based phys, so they essentially have pipe clock. So,
4051         * we return error in case phy is USB3 or PIPE type.
4052         * Otherwise, we initialize pipe clock to NULL for
4053         * all phys that don't need this.
4054         */
4055        snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
4056        qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
4057        if (IS_ERR(qphy->pipe_clk)) {
4058                if (cfg->type == PHY_TYPE_PCIE ||
4059                    cfg->type == PHY_TYPE_USB3) {
4060                        ret = PTR_ERR(qphy->pipe_clk);
4061                        if (ret != -EPROBE_DEFER)
4062                                dev_err(dev,
4063                                        "failed to get lane%d pipe_clk, %d\n",
4064                                        id, ret);
4065                        return ret;
4066                }
4067                qphy->pipe_clk = NULL;
4068        }
4069
4070        /* Get lane reset, if any */
4071        if (cfg->has_lane_rst) {
4072                snprintf(prop_name, sizeof(prop_name), "lane%d", id);
4073                qphy->lane_rst = of_reset_control_get(np, prop_name);
4074                if (IS_ERR(qphy->lane_rst)) {
4075                        dev_err(dev, "failed to get lane%d reset\n", id);
4076                        return PTR_ERR(qphy->lane_rst);
4077                }
4078        }
4079
4080        if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
4081                ops = &qcom_qmp_pcie_ufs_ops;
4082        else if (cfg->type == PHY_TYPE_DP)
4083                ops = &qcom_qmp_phy_dp_ops;
4084        else
4085                ops = &qcom_qmp_phy_gen_ops;
4086
4087        generic_phy = devm_phy_create(dev, np, ops);
4088        if (IS_ERR(generic_phy)) {
4089                ret = PTR_ERR(generic_phy);
4090                dev_err(dev, "failed to create qphy %d\n", ret);
4091                return ret;
4092        }
4093
4094        qphy->phy = generic_phy;
4095        qphy->index = id;
4096        qphy->qmp = qmp;
4097        qmp->phys[id] = qphy;
4098        phy_set_drvdata(generic_phy, qphy);
4099
4100        return 0;
4101}
4102
4103static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
4104        {
4105                .compatible = "qcom,ipq8074-qmp-usb3-phy",
4106                .data = &ipq8074_usb3phy_cfg,
4107        }, {
4108                .compatible = "qcom,msm8996-qmp-pcie-phy",
4109                .data = &msm8996_pciephy_cfg,
4110        }, {
4111                .compatible = "qcom,msm8996-qmp-ufs-phy",
4112                .data = &msm8996_ufs_cfg,
4113        }, {
4114                .compatible = "qcom,msm8996-qmp-usb3-phy",
4115                .data = &msm8996_usb3phy_cfg,
4116        }, {
4117                .compatible = "qcom,msm8998-qmp-pcie-phy",
4118                .data = &msm8998_pciephy_cfg,
4119        }, {
4120                .compatible = "qcom,msm8998-qmp-ufs-phy",
4121                .data = &sdm845_ufsphy_cfg,
4122        }, {
4123                .compatible = "qcom,ipq8074-qmp-pcie-phy",
4124                .data = &ipq8074_pciephy_cfg,
4125        }, {
4126                .compatible = "qcom,sc7180-qmp-usb3-phy",
4127                .data = &sc7180_usb3phy_cfg,
4128        }, {
4129                .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
4130                /* It's a combo phy */
4131        }, {
4132                .compatible = "qcom,sdm845-qhp-pcie-phy",
4133                .data = &sdm845_qhp_pciephy_cfg,
4134        }, {
4135                .compatible = "qcom,sdm845-qmp-pcie-phy",
4136                .data = &sdm845_qmp_pciephy_cfg,
4137        }, {
4138                .compatible = "qcom,sdm845-qmp-usb3-phy",
4139                .data = &qmp_v3_usb3phy_cfg,
4140        }, {
4141                .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
4142                .data = &qmp_v3_usb3_uniphy_cfg,
4143        }, {
4144                .compatible = "qcom,sdm845-qmp-ufs-phy",
4145                .data = &sdm845_ufsphy_cfg,
4146        }, {
4147                .compatible = "qcom,msm8998-qmp-usb3-phy",
4148                .data = &msm8998_usb3phy_cfg,
4149        }, {
4150                .compatible = "qcom,sm8150-qmp-ufs-phy",
4151                .data = &sm8150_ufsphy_cfg,
4152        }, {
4153                .compatible = "qcom,sm8250-qmp-ufs-phy",
4154                .data = &sm8150_ufsphy_cfg,
4155        }, {
4156                .compatible = "qcom,sm8150-qmp-usb3-phy",
4157                .data = &sm8150_usb3phy_cfg,
4158        }, {
4159                .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
4160                .data = &sm8150_usb3_uniphy_cfg,
4161        }, {
4162                .compatible = "qcom,sm8250-qmp-usb3-phy",
4163                .data = &sm8250_usb3phy_cfg,
4164        }, {
4165                .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
4166                .data = &sm8250_usb3_uniphy_cfg,
4167        }, {
4168                .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
4169                .data = &sm8250_qmp_gen3x1_pciephy_cfg,
4170        }, {
4171                .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
4172                .data = &sm8250_qmp_gen3x2_pciephy_cfg,
4173        }, {
4174                .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
4175                .data = &sm8250_qmp_gen3x2_pciephy_cfg,
4176        },
4177        { },
4178};
4179MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
4180
4181static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
4182        {
4183                .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
4184                .data = &sc7180_usb3dpphy_cfg,
4185        },
4186        { }
4187};
4188
4189static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
4190        SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
4191                           qcom_qmp_phy_runtime_resume, NULL)
4192};
4193
4194static int qcom_qmp_phy_probe(struct platform_device *pdev)
4195{
4196        struct qcom_qmp *qmp;
4197        struct device *dev = &pdev->dev;
4198        struct device_node *child;
4199        struct phy_provider *phy_provider;
4200        void __iomem *serdes;
4201        void __iomem *usb_serdes;
4202        void __iomem *dp_serdes = NULL;
4203        const struct qmp_phy_combo_cfg *combo_cfg = NULL;
4204        const struct qmp_phy_cfg *cfg = NULL;
4205        const struct qmp_phy_cfg *usb_cfg = NULL;
4206        const struct qmp_phy_cfg *dp_cfg = NULL;
4207        int num, id, expected_phys;
4208        int ret;
4209
4210        qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
4211        if (!qmp)
4212                return -ENOMEM;
4213
4214        qmp->dev = dev;
4215        dev_set_drvdata(dev, qmp);
4216
4217        /* Get the specific init parameters of QMP phy */
4218        cfg = of_device_get_match_data(dev);
4219        if (!cfg) {
4220                const struct of_device_id *match;
4221
4222                match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
4223                if (!match)
4224                        return -EINVAL;
4225
4226                combo_cfg = match->data;
4227                if (!combo_cfg)
4228                        return -EINVAL;
4229
4230                usb_cfg = combo_cfg->usb_cfg;
4231                cfg = usb_cfg; /* Setup clks and regulators */
4232        }
4233
4234        /* per PHY serdes; usually located at base address */
4235        usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
4236        if (IS_ERR(serdes))
4237                return PTR_ERR(serdes);
4238
4239        /* per PHY dp_com; if PHY has dp_com control block */
4240        if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
4241                qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
4242                if (IS_ERR(qmp->dp_com))
4243                        return PTR_ERR(qmp->dp_com);
4244        }
4245
4246        if (combo_cfg) {
4247                /* Only two serdes for combo PHY */
4248                dp_serdes = devm_platform_ioremap_resource(pdev, 2);
4249                if (IS_ERR(dp_serdes))
4250                        return PTR_ERR(dp_serdes);
4251
4252                dp_cfg = combo_cfg->dp_cfg;
4253                expected_phys = 2;
4254        } else {
4255                expected_phys = cfg->nlanes;
4256        }
4257
4258        mutex_init(&qmp->phy_mutex);
4259
4260        ret = qcom_qmp_phy_clk_init(dev, cfg);
4261        if (ret)
4262                return ret;
4263
4264        ret = qcom_qmp_phy_reset_init(dev, cfg);
4265        if (ret)
4266                return ret;
4267
4268        ret = qcom_qmp_phy_vreg_init(dev, cfg);
4269        if (ret) {
4270                if (ret != -EPROBE_DEFER)
4271                        dev_err(dev, "failed to get regulator supplies: %d\n",
4272                                ret);
4273                return ret;
4274        }
4275
4276        num = of_get_available_child_count(dev->of_node);
4277        /* do we have a rogue child node ? */
4278        if (num > expected_phys)
4279                return -EINVAL;
4280
4281        qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
4282        if (!qmp->phys)
4283                return -ENOMEM;
4284
4285        pm_runtime_set_active(dev);
4286        pm_runtime_enable(dev);
4287        /*
4288         * Prevent runtime pm from being ON by default. Users can enable
4289         * it using power/control in sysfs.
4290         */
4291        pm_runtime_forbid(dev);
4292
4293        id = 0;
4294        for_each_available_child_of_node(dev->of_node, child) {
4295                if (of_node_name_eq(child, "dp-phy")) {
4296                        cfg = dp_cfg;
4297                        serdes = dp_serdes;
4298                } else if (of_node_name_eq(child, "usb3-phy")) {
4299                        cfg = usb_cfg;
4300                        serdes = usb_serdes;
4301                }
4302
4303                /* Create per-lane phy */
4304                ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
4305                if (ret) {
4306                        dev_err(dev, "failed to create lane%d phy, %d\n",
4307                                id, ret);
4308                        goto err_node_put;
4309                }
4310
4311                /*
4312                 * Register the pipe clock provided by phy.
4313                 * See function description to see details of this pipe clock.
4314                 */
4315                if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
4316                        ret = phy_pipe_clk_register(qmp, child);
4317                        if (ret) {
4318                                dev_err(qmp->dev,
4319                                        "failed to register pipe clock source\n");
4320                                goto err_node_put;
4321                        }
4322                } else if (cfg->type == PHY_TYPE_DP) {
4323                        ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
4324                        if (ret) {
4325                                dev_err(qmp->dev,
4326                                        "failed to register DP clock source\n");
4327                                goto err_node_put;
4328                        }
4329                }
4330                id++;
4331        }
4332
4333        phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
4334        if (!IS_ERR(phy_provider))
4335                dev_info(dev, "Registered Qcom-QMP phy\n");
4336        else
4337                pm_runtime_disable(dev);
4338
4339        return PTR_ERR_OR_ZERO(phy_provider);
4340
4341err_node_put:
4342        pm_runtime_disable(dev);
4343        of_node_put(child);
4344        return ret;
4345}
4346
4347static struct platform_driver qcom_qmp_phy_driver = {
4348        .probe          = qcom_qmp_phy_probe,
4349        .driver = {
4350                .name   = "qcom-qmp-phy",
4351                .pm     = &qcom_qmp_phy_pm_ops,
4352                .of_match_table = qcom_qmp_phy_of_match_table,
4353        },
4354};
4355
4356module_platform_driver(qcom_qmp_phy_driver);
4357
4358MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
4359MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
4360MODULE_LICENSE("GPL v2");
4361