linux/drivers/pinctrl/renesas/pfc-r8a7792.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * r8a7792 processor support - PFC hardware block.
   4 *
   5 * Copyright (C) 2013-2014 Renesas Electronics Corporation
   6 * Copyright (C) 2016 Cogent Embedded, Inc., <source@cogentembedded.com>
   7 */
   8
   9#include <linux/kernel.h>
  10
  11#include "core.h"
  12#include "sh_pfc.h"
  13
  14#define CPU_ALL_GP(fn, sfx)                                             \
  15        PORT_GP_29(0, fn, sfx),                                         \
  16        PORT_GP_23(1, fn, sfx),                                         \
  17        PORT_GP_32(2, fn, sfx),                                         \
  18        PORT_GP_28(3, fn, sfx),                                         \
  19        PORT_GP_17(4, fn, sfx),                                         \
  20        PORT_GP_17(5, fn, sfx),                                         \
  21        PORT_GP_17(6, fn, sfx),                                         \
  22        PORT_GP_17(7, fn, sfx),                                         \
  23        PORT_GP_17(8, fn, sfx),                                         \
  24        PORT_GP_17(9, fn, sfx),                                         \
  25        PORT_GP_32(10, fn, sfx),                                        \
  26        PORT_GP_30(11, fn, sfx)
  27
  28enum {
  29        PINMUX_RESERVED = 0,
  30
  31        PINMUX_DATA_BEGIN,
  32        GP_ALL(DATA),
  33        PINMUX_DATA_END,
  34
  35        PINMUX_FUNCTION_BEGIN,
  36        GP_ALL(FN),
  37
  38        /* GPSR0 */
  39        FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  40        FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  41        FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16,
  42        FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21,
  43        FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2,
  44        FN_IP1_3, FN_IP1_4,
  45
  46        /* GPSR1 */
  47        FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10,
  48        FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
  49        FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14,
  50        FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5,
  51        FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
  52        FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
  53
  54        /* GPSR2 */
  55        FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7,
  56        FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
  57        FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7,
  58        FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15,
  59
  60        /* GPSR3 */
  61        FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18,
  62        FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N,
  63        FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N,
  64        FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3,
  65        FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N,
  66
  67        /* GPSR4 */
  68        FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N,
  69        FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
  70        FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
  71        FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
  72        FN_VI0_FIELD,
  73
  74        /* GPSR5 */
  75        FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N,
  76        FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
  77        FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
  78        FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
  79        FN_VI1_FIELD,
  80
  81        /* GPSR6 */
  82        FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6,
  83        FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12,
  84        FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16,
  85
  86        /* GPSR7 */
  87        FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6,
  88        FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12,
  89        FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD,
  90
  91        /* GPSR8 */
  92        FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5,
  93        FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15,
  94        FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
  95
  96        /* GPSR9 */
  97        FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5,
  98        FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11,
  99        FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD,
 100
 101        /* GPSR10 */
 102        FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5,
 103        FN_HCTS1_N, FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0_N, FN_RTS0_N,
 104        FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1,
 105        FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16,
 106        FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK,
 107        FN_CAN1_TX, FN_CAN1_RX,
 108
 109        /* GPSR11 */
 110        FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK,
 111        FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3,
 112        FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
 113        FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20,
 114        FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1,
 115        FN_ADICHS2, FN_AVS1, FN_AVS2,
 116
 117        /* IPSR0 */
 118        FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2,
 119        FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5,
 120        FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8,
 121        FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
 122        FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14,
 123        FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0,
 124        FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4,
 125        FN_DU0_DB7_C5,
 126
 127        /* IPSR1 */
 128        FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC,
 129        FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE,
 130        FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
 131        FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5,
 132        FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8,
 133        FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11,
 134        FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2,
 135        FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
 136
 137        /* IPSR2 */
 138        FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
 139        FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1,
 140        FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
 141        FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
 142        FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
 143        FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
 144        FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
 145        FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
 146        FN_VI2_FIELD, FN_AVB_TXD2,
 147
 148        /* IPSR3 */
 149        FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
 150        FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6,
 151        FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
 152        FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
 153        FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
 154        FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
 155        FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
 156        FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
 157
 158        /* IPSR4 */
 159        FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
 160        FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT,
 161        FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
 162        FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4,
 163        FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
 164        FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6,
 165        FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7,
 166        FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4,
 167        FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
 168        FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6,
 169        FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
 170        FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
 171        FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
 172
 173        /* IPSR5 */
 174        FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
 175        FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
 176        FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
 177        FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
 178        FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
 179        FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
 180
 181        /* IPSR6 */
 182        FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N,
 183        FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
 184        FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N,
 185        FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
 186        FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2,
 187        FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3,
 188
 189        /* IPSR7 */
 190        FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
 191        FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
 192        FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1,
 193        FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
 194        FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT,
 195        FN_AUDIO_CLKA, FN_AUDIO_CLKB,
 196
 197        /* MOD_SEL */
 198        FN_SEL_VI1_0, FN_SEL_VI1_1,
 199        PINMUX_FUNCTION_END,
 200
 201        PINMUX_MARK_BEGIN,
 202        DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
 203        DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
 204        DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
 205        DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
 206        DU1_DISP_MARK, DU1_CDE_MARK,
 207
 208        D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK,
 209        D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK,
 210        D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK,
 211        A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK,
 212        A12_MARK, A13_MARK, A14_MARK, A15_MARK,
 213
 214        A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK,
 215        EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK,
 216        EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK,
 217        WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK,
 218        IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK,
 219
 220        VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
 221        VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK,
 222        VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
 223        VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK,
 224        VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
 225        VI0_FIELD_MARK,
 226
 227        VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
 228        VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK,
 229        VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
 230        VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK,
 231        VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
 232        VI1_FIELD_MARK,
 233
 234        VI3_D10_Y2_MARK, VI3_FIELD_MARK,
 235
 236        VI4_CLK_MARK,
 237
 238        VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
 239        VI5_FIELD_MARK,
 240
 241        HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK,
 242        TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK,
 243        TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
 244        CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
 245
 246        SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK,
 247        SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK,
 248        ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
 249        ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
 250
 251        /* IPSR0 */
 252        DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
 253        DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
 254        DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
 255        DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
 256        DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
 257        DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
 258        DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK,
 259        DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
 260
 261        /* IPSR1 */
 262        DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
 263        DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
 264        DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
 265        DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
 266        DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
 267        DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
 268        A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
 269        A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
 270
 271        /* IPSR2 */
 272        VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
 273        VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK,
 274        VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK,
 275        VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
 276        VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
 277        VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
 278        VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
 279        VI2_D10_Y2_MARK, AVB_TXD0_MARK,
 280        VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK,
 281
 282        /* IPSR3 */
 283        VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
 284        VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK,
 285        VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
 286        VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
 287        VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
 288        VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
 289        VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
 290        VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK,
 291
 292        /* IPSR4 */
 293        VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK,
 294        VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK,
 295        RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK,
 296        VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK,
 297        VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK,
 298        VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK,
 299        VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK,
 300        VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
 301        VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK,
 302        VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK,
 303        VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
 304
 305        /* IPSR5 */
 306        VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK,
 307        VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK,
 308        VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK,
 309        VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK,
 310        VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK,
 311        VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK,
 312        VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
 313
 314        /* IPSR6 */
 315        MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK,
 316        MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
 317        MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK,
 318        MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
 319        DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK,
 320        RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK,
 321        RX3_MARK,
 322
 323        /* IPSR7 */
 324        PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK,
 325        FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK,
 326        PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK,
 327        SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK,
 328        SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK,
 329        AUDIO_CLKB_MARK,
 330        PINMUX_MARK_END,
 331};
 332
 333static const u16 pinmux_data[] = {
 334        PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 335
 336        PINMUX_SINGLE(DU1_DB2_C0_DATA12),
 337        PINMUX_SINGLE(DU1_DB3_C1_DATA13),
 338        PINMUX_SINGLE(DU1_DB4_C2_DATA14),
 339        PINMUX_SINGLE(DU1_DB5_C3_DATA15),
 340        PINMUX_SINGLE(DU1_DB6_C4),
 341        PINMUX_SINGLE(DU1_DB7_C5),
 342        PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC),
 343        PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC),
 344        PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE),
 345        PINMUX_SINGLE(DU1_DISP),
 346        PINMUX_SINGLE(DU1_CDE),
 347        PINMUX_SINGLE(D0),
 348        PINMUX_SINGLE(D1),
 349        PINMUX_SINGLE(D2),
 350        PINMUX_SINGLE(D3),
 351        PINMUX_SINGLE(D4),
 352        PINMUX_SINGLE(D5),
 353        PINMUX_SINGLE(D6),
 354        PINMUX_SINGLE(D7),
 355        PINMUX_SINGLE(D8),
 356        PINMUX_SINGLE(D9),
 357        PINMUX_SINGLE(D10),
 358        PINMUX_SINGLE(D11),
 359        PINMUX_SINGLE(D12),
 360        PINMUX_SINGLE(D13),
 361        PINMUX_SINGLE(D14),
 362        PINMUX_SINGLE(D15),
 363        PINMUX_SINGLE(A0),
 364        PINMUX_SINGLE(A1),
 365        PINMUX_SINGLE(A2),
 366        PINMUX_SINGLE(A3),
 367        PINMUX_SINGLE(A4),
 368        PINMUX_SINGLE(A5),
 369        PINMUX_SINGLE(A6),
 370        PINMUX_SINGLE(A7),
 371        PINMUX_SINGLE(A8),
 372        PINMUX_SINGLE(A9),
 373        PINMUX_SINGLE(A10),
 374        PINMUX_SINGLE(A11),
 375        PINMUX_SINGLE(A12),
 376        PINMUX_SINGLE(A13),
 377        PINMUX_SINGLE(A14),
 378        PINMUX_SINGLE(A15),
 379        PINMUX_SINGLE(A16),
 380        PINMUX_SINGLE(A17),
 381        PINMUX_SINGLE(A18),
 382        PINMUX_SINGLE(A19),
 383        PINMUX_SINGLE(CS1_N_A26),
 384        PINMUX_SINGLE(EX_CS0_N),
 385        PINMUX_SINGLE(EX_CS1_N),
 386        PINMUX_SINGLE(EX_CS2_N),
 387        PINMUX_SINGLE(EX_CS3_N),
 388        PINMUX_SINGLE(EX_CS4_N),
 389        PINMUX_SINGLE(EX_CS5_N),
 390        PINMUX_SINGLE(BS_N),
 391        PINMUX_SINGLE(RD_N),
 392        PINMUX_SINGLE(RD_WR_N),
 393        PINMUX_SINGLE(WE0_N),
 394        PINMUX_SINGLE(WE1_N),
 395        PINMUX_SINGLE(EX_WAIT0),
 396        PINMUX_SINGLE(IRQ0),
 397        PINMUX_SINGLE(IRQ1),
 398        PINMUX_SINGLE(IRQ2),
 399        PINMUX_SINGLE(IRQ3),
 400        PINMUX_SINGLE(CS0_N),
 401        PINMUX_SINGLE(VI0_CLK),
 402        PINMUX_SINGLE(VI0_CLKENB),
 403        PINMUX_SINGLE(VI0_HSYNC_N),
 404        PINMUX_SINGLE(VI0_VSYNC_N),
 405        PINMUX_SINGLE(VI0_D0_B0_C0),
 406        PINMUX_SINGLE(VI0_D1_B1_C1),
 407        PINMUX_SINGLE(VI0_D2_B2_C2),
 408        PINMUX_SINGLE(VI0_D3_B3_C3),
 409        PINMUX_SINGLE(VI0_D4_B4_C4),
 410        PINMUX_SINGLE(VI0_D5_B5_C5),
 411        PINMUX_SINGLE(VI0_D6_B6_C6),
 412        PINMUX_SINGLE(VI0_D7_B7_C7),
 413        PINMUX_SINGLE(VI0_D8_G0_Y0),
 414        PINMUX_SINGLE(VI0_D9_G1_Y1),
 415        PINMUX_SINGLE(VI0_D10_G2_Y2),
 416        PINMUX_SINGLE(VI0_D11_G3_Y3),
 417        PINMUX_SINGLE(VI0_FIELD),
 418        PINMUX_SINGLE(VI1_CLK),
 419        PINMUX_SINGLE(VI1_CLKENB),
 420        PINMUX_SINGLE(VI1_HSYNC_N),
 421        PINMUX_SINGLE(VI1_VSYNC_N),
 422        PINMUX_SINGLE(VI1_D0_B0_C0),
 423        PINMUX_SINGLE(VI1_D1_B1_C1),
 424        PINMUX_SINGLE(VI1_D2_B2_C2),
 425        PINMUX_SINGLE(VI1_D3_B3_C3),
 426        PINMUX_SINGLE(VI1_D4_B4_C4),
 427        PINMUX_SINGLE(VI1_D5_B5_C5),
 428        PINMUX_SINGLE(VI1_D6_B6_C6),
 429        PINMUX_SINGLE(VI1_D7_B7_C7),
 430        PINMUX_SINGLE(VI1_D8_G0_Y0),
 431        PINMUX_SINGLE(VI1_D9_G1_Y1),
 432        PINMUX_SINGLE(VI1_D10_G2_Y2),
 433        PINMUX_SINGLE(VI1_D11_G3_Y3),
 434        PINMUX_SINGLE(VI1_FIELD),
 435        PINMUX_SINGLE(VI3_D10_Y2),
 436        PINMUX_SINGLE(VI3_FIELD),
 437        PINMUX_SINGLE(VI4_CLK),
 438        PINMUX_SINGLE(VI5_CLK),
 439        PINMUX_SINGLE(VI5_D9_Y1),
 440        PINMUX_SINGLE(VI5_D10_Y2),
 441        PINMUX_SINGLE(VI5_D11_Y3),
 442        PINMUX_SINGLE(VI5_FIELD),
 443        PINMUX_SINGLE(HRTS0_N),
 444        PINMUX_SINGLE(HCTS1_N),
 445        PINMUX_SINGLE(SCK0),
 446        PINMUX_SINGLE(CTS0_N),
 447        PINMUX_SINGLE(RTS0_N),
 448        PINMUX_SINGLE(TX0),
 449        PINMUX_SINGLE(RX0),
 450        PINMUX_SINGLE(SCK1),
 451        PINMUX_SINGLE(CTS1_N),
 452        PINMUX_SINGLE(RTS1_N),
 453        PINMUX_SINGLE(TX1),
 454        PINMUX_SINGLE(RX1),
 455        PINMUX_SINGLE(SCIF_CLK),
 456        PINMUX_SINGLE(CAN0_TX),
 457        PINMUX_SINGLE(CAN0_RX),
 458        PINMUX_SINGLE(CAN_CLK),
 459        PINMUX_SINGLE(CAN1_TX),
 460        PINMUX_SINGLE(CAN1_RX),
 461        PINMUX_SINGLE(SD0_CLK),
 462        PINMUX_SINGLE(SD0_CMD),
 463        PINMUX_SINGLE(SD0_DAT0),
 464        PINMUX_SINGLE(SD0_DAT1),
 465        PINMUX_SINGLE(SD0_DAT2),
 466        PINMUX_SINGLE(SD0_DAT3),
 467        PINMUX_SINGLE(SD0_CD),
 468        PINMUX_SINGLE(SD0_WP),
 469        PINMUX_SINGLE(ADICLK),
 470        PINMUX_SINGLE(ADICS_SAMP),
 471        PINMUX_SINGLE(ADIDATA),
 472        PINMUX_SINGLE(ADICHS0),
 473        PINMUX_SINGLE(ADICHS1),
 474        PINMUX_SINGLE(ADICHS2),
 475        PINMUX_SINGLE(AVS1),
 476        PINMUX_SINGLE(AVS2),
 477
 478        /* IPSR0 */
 479        PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0),
 480        PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1),
 481        PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2),
 482        PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3),
 483        PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4),
 484        PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5),
 485        PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6),
 486        PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7),
 487        PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8),
 488        PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9),
 489        PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10),
 490        PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11),
 491        PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12),
 492        PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13),
 493        PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14),
 494        PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15),
 495        PINMUX_IPSR_GPSR(IP0_16, DU0_DB0),
 496        PINMUX_IPSR_GPSR(IP0_17, DU0_DB1),
 497        PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0),
 498        PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1),
 499        PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2),
 500        PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3),
 501        PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4),
 502        PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5),
 503
 504        /* IPSR1 */
 505        PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
 506        PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
 507        PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 508        PINMUX_IPSR_GPSR(IP1_3, DU0_DISP),
 509        PINMUX_IPSR_GPSR(IP1_4, DU0_CDE),
 510        PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0),
 511        PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1),
 512        PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2),
 513        PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3),
 514        PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4),
 515        PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5),
 516        PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6),
 517        PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7),
 518        PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8),
 519        PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9),
 520        PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10),
 521        PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11),
 522        PINMUX_IPSR_GPSR(IP1_17, A20),
 523        PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0),
 524        PINMUX_IPSR_GPSR(IP1_18, A21),
 525        PINMUX_IPSR_GPSR(IP1_18, MISO_IO1),
 526        PINMUX_IPSR_GPSR(IP1_19, A22),
 527        PINMUX_IPSR_GPSR(IP1_19, IO2),
 528        PINMUX_IPSR_GPSR(IP1_20, A23),
 529        PINMUX_IPSR_GPSR(IP1_20, IO3),
 530        PINMUX_IPSR_GPSR(IP1_21, A24),
 531        PINMUX_IPSR_GPSR(IP1_21, SPCLK),
 532        PINMUX_IPSR_GPSR(IP1_22, A25),
 533        PINMUX_IPSR_GPSR(IP1_22, SSL),
 534
 535        /* IPSR2 */
 536        PINMUX_IPSR_GPSR(IP2_0, VI2_CLK),
 537        PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK),
 538        PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB),
 539        PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV),
 540        PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N),
 541        PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0),
 542        PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N),
 543        PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1),
 544        PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0),
 545        PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2),
 546        PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1),
 547        PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3),
 548        PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2),
 549        PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4),
 550        PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3),
 551        PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5),
 552        PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4),
 553        PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6),
 554        PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5),
 555        PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7),
 556        PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6),
 557        PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER),
 558        PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7),
 559        PINMUX_IPSR_GPSR(IP2_11, AVB_COL),
 560        PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0),
 561        PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3),
 562        PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1),
 563        PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN),
 564        PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2),
 565        PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0),
 566        PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3),
 567        PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1),
 568        PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD),
 569        PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2),
 570
 571        /* IPSR3 */
 572        PINMUX_IPSR_GPSR(IP3_0, VI3_CLK),
 573        PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK),
 574        PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB),
 575        PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4),
 576        PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N),
 577        PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5),
 578        PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N),
 579        PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6),
 580        PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0),
 581        PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7),
 582        PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1),
 583        PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER),
 584        PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2),
 585        PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK),
 586        PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3),
 587        PINMUX_IPSR_GPSR(IP3_7, AVB_MDC),
 588        PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4),
 589        PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO),
 590        PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5),
 591        PINMUX_IPSR_GPSR(IP3_9, AVB_LINK),
 592        PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6),
 593        PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC),
 594        PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7),
 595        PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT),
 596        PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0),
 597        PINMUX_IPSR_GPSR(IP3_12, AVB_CRS),
 598        PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1),
 599        PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK),
 600        PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3),
 601        PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH),
 602
 603        /* IPSR4 */
 604        PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB),
 605        PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4),
 606        PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N),
 607        PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5),
 608        PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N),
 609        PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6),
 610        PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0),
 611        PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7),
 612        PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1),
 613        PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0),
 614        PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),
 615        PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2),
 616        PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1),
 617        PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),
 618        PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3),
 619        PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2),
 620        PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),
 621        PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4),
 622        PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3),
 623        PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),
 624        PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5),
 625        PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),
 626        PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4),
 627        PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6),
 628        PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5),
 629        PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5),
 630        PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7),
 631        PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6),
 632        PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6),
 633        PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0),
 634        PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7),
 635        PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7),
 636        PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1),
 637        PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4),
 638        PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),
 639        PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5),
 640        PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3),
 641        PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6),
 642        PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD),
 643        PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7),
 644
 645        /* IPSR5 */
 646        PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB),
 647        PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),
 648        PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N),
 649        PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),
 650        PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N),
 651        PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),
 652        PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0),
 653        PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),
 654        PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1),
 655        PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0),
 656        PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2),
 657        PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1),
 658        PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3),
 659        PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2),
 660        PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4),
 661        PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3),
 662        PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5),
 663        PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4),
 664        PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6),
 665        PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5),
 666        PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7),
 667        PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6),
 668        PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0),
 669        PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7),
 670
 671        /* IPSR6 */
 672        PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK),
 673        PINMUX_IPSR_GPSR(IP6_0, HSCK0),
 674        PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC),
 675        PINMUX_IPSR_GPSR(IP6_1, HCTS0_N),
 676        PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD),
 677        PINMUX_IPSR_GPSR(IP6_2, HTX0),
 678        PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD),
 679        PINMUX_IPSR_GPSR(IP6_3, HRX0),
 680        PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK),
 681        PINMUX_IPSR_GPSR(IP6_4, HSCK1),
 682        PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC),
 683        PINMUX_IPSR_GPSR(IP6_5, HRTS1_N),
 684        PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD),
 685        PINMUX_IPSR_GPSR(IP6_6, HTX1),
 686        PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD),
 687        PINMUX_IPSR_GPSR(IP6_7, HRX1),
 688        PINMUX_IPSR_GPSR(IP6_9_8, DRACK0),
 689        PINMUX_IPSR_GPSR(IP6_9_8, SCK2),
 690        PINMUX_IPSR_GPSR(IP6_11_10, DACK0),
 691        PINMUX_IPSR_GPSR(IP6_11_10, TX2),
 692        PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N),
 693        PINMUX_IPSR_GPSR(IP6_13_12, RX2),
 694        PINMUX_IPSR_GPSR(IP6_15_14, DACK1),
 695        PINMUX_IPSR_GPSR(IP6_15_14, SCK3),
 696        PINMUX_IPSR_GPSR(IP6_16, TX3),
 697        PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N),
 698        PINMUX_IPSR_GPSR(IP6_18_17, RX3),
 699
 700        /* IPSR7 */
 701        PINMUX_IPSR_GPSR(IP7_1_0, PWM0),
 702        PINMUX_IPSR_GPSR(IP7_1_0, TCLK1),
 703        PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0),
 704        PINMUX_IPSR_GPSR(IP7_3_2, PWM1),
 705        PINMUX_IPSR_GPSR(IP7_3_2, TCLK2),
 706        PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1),
 707        PINMUX_IPSR_GPSR(IP7_5_4, PWM2),
 708        PINMUX_IPSR_GPSR(IP7_5_4, TCLK3),
 709        PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE),
 710        PINMUX_IPSR_GPSR(IP7_6, PWM3),
 711        PINMUX_IPSR_GPSR(IP7_7, PWM4),
 712        PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34),
 713        PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0),
 714        PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34),
 715        PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1),
 716        PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3),
 717        PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2),
 718        PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4),
 719        PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3),
 720        PINMUX_IPSR_GPSR(IP7_16, SSI_WS4),
 721        PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4),
 722        PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT),
 723        PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA),
 724        PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
 725};
 726
 727static const struct sh_pfc_pin pinmux_pins[] = {
 728        PINMUX_GPIO_GP_ALL(),
 729};
 730
 731/* - AVB -------------------------------------------------------------------- */
 732static const unsigned int avb_link_pins[] = {
 733        RCAR_GP_PIN(7, 9),
 734};
 735static const unsigned int avb_link_mux[] = {
 736        AVB_LINK_MARK,
 737};
 738static const unsigned int avb_magic_pins[] = {
 739        RCAR_GP_PIN(7, 10),
 740};
 741static const unsigned int avb_magic_mux[] = {
 742        AVB_MAGIC_MARK,
 743};
 744static const unsigned int avb_phy_int_pins[] = {
 745        RCAR_GP_PIN(7, 11),
 746};
 747static const unsigned int avb_phy_int_mux[] = {
 748        AVB_PHY_INT_MARK,
 749};
 750static const unsigned int avb_mdio_pins[] = {
 751        RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8),
 752};
 753static const unsigned int avb_mdio_mux[] = {
 754        AVB_MDC_MARK, AVB_MDIO_MARK,
 755};
 756static const unsigned int avb_mii_pins[] = {
 757        RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
 758        RCAR_GP_PIN(6, 12),
 759
 760        RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(6, 4),
 761        RCAR_GP_PIN(6, 5),
 762
 763        RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(6, 1),
 764        RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5),
 765        RCAR_GP_PIN(7, 0),  RCAR_GP_PIN(6, 11),
 766};
 767static const unsigned int avb_mii_mux[] = {
 768        AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
 769        AVB_TXD3_MARK,
 770
 771        AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
 772        AVB_RXD3_MARK,
 773
 774        AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
 775        AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
 776        AVB_TX_CLK_MARK, AVB_COL_MARK,
 777};
 778static const unsigned int avb_gmii_pins[] = {
 779        RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
 780        RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1),  RCAR_GP_PIN(7, 2),
 781        RCAR_GP_PIN(7, 3),  RCAR_GP_PIN(7, 4),
 782
 783        RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
 784        RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
 785        RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 9),
 786
 787        RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
 788        RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13),
 789        RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),
 790        RCAR_GP_PIN(6, 11),
 791};
 792static const unsigned int avb_gmii_mux[] = {
 793        AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
 794        AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
 795        AVB_TXD6_MARK, AVB_TXD7_MARK,
 796
 797        AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
 798        AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
 799        AVB_RXD6_MARK, AVB_RXD7_MARK,
 800
 801        AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
 802        AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
 803        AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
 804        AVB_COL_MARK,
 805};
 806static const unsigned int avb_avtp_match_pins[] = {
 807        RCAR_GP_PIN(7, 15),
 808};
 809static const unsigned int avb_avtp_match_mux[] = {
 810        AVB_AVTP_MATCH_MARK,
 811};
 812/* - CAN -------------------------------------------------------------------- */
 813static const unsigned int can0_data_pins[] = {
 814        /* TX, RX */
 815        RCAR_GP_PIN(10, 27), RCAR_GP_PIN(10, 28),
 816};
 817static const unsigned int can0_data_mux[] = {
 818        CAN0_TX_MARK, CAN0_RX_MARK,
 819};
 820static const unsigned int can1_data_pins[] = {
 821        /* TX, RX */
 822        RCAR_GP_PIN(10, 30), RCAR_GP_PIN(10, 31),
 823};
 824static const unsigned int can1_data_mux[] = {
 825        CAN1_TX_MARK, CAN1_RX_MARK,
 826};
 827static const unsigned int can_clk_pins[] = {
 828        /* CAN_CLK */
 829        RCAR_GP_PIN(10, 29),
 830};
 831static const unsigned int can_clk_mux[] = {
 832        CAN_CLK_MARK,
 833};
 834/* - DU --------------------------------------------------------------------- */
 835static const unsigned int du0_rgb666_pins[] = {
 836        /* R[7:2], G[7:2], B[7:2] */
 837        RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
 838        RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
 839        RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
 840        RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
 841        RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 842        RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
 843};
 844static const unsigned int du0_rgb666_mux[] = {
 845        DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
 846        DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
 847        DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
 848        DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
 849        DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
 850        DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
 851};
 852static const unsigned int du0_rgb888_pins[] = {
 853        /* R[7:0], G[7:0], B[7:0] */
 854        RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
 855        RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
 856        RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
 857        RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
 858        RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
 859        RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
 860        RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 861        RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
 862        RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
 863};
 864static const unsigned int du0_rgb888_mux[] = {
 865        DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
 866        DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
 867        DU0_DR1_DATA1_MARK, DU0_DR0_DATA0_MARK,
 868        DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
 869        DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
 870        DU0_DG1_DATA9_MARK, DU0_DG0_DATA8_MARK,
 871        DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
 872        DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
 873        DU0_DB1_MARK, DU0_DB0_MARK,
 874};
 875static const unsigned int du0_sync_pins[] = {
 876        /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 877        RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24),
 878};
 879static const unsigned int du0_sync_mux[] = {
 880        DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
 881};
 882static const unsigned int du0_oddf_pins[] = {
 883        /* EXODDF/ODDF/DISP/CDE */
 884        RCAR_GP_PIN(0, 26),
 885};
 886static const unsigned int du0_oddf_mux[] = {
 887        DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
 888};
 889static const unsigned int du0_disp_pins[] = {
 890        /* DISP */
 891        RCAR_GP_PIN(0, 27),
 892};
 893static const unsigned int du0_disp_mux[] = {
 894        DU0_DISP_MARK,
 895};
 896static const unsigned int du0_cde_pins[] = {
 897        /* CDE */
 898        RCAR_GP_PIN(0, 28),
 899};
 900static const unsigned int du0_cde_mux[] = {
 901        DU0_CDE_MARK,
 902};
 903static const unsigned int du1_rgb666_pins[] = {
 904        /* R[7:2], G[7:2], B[7:2] */
 905        RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
 906        RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
 907        RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
 908        RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
 909        RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
 910        RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
 911};
 912static const unsigned int du1_rgb666_mux[] = {
 913        DU1_DR7_DATA5_MARK, DU1_DR6_DATA4_MARK, DU1_DR5_Y7_DATA3_MARK,
 914        DU1_DR4_Y6_DATA2_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR2_Y4_DATA0_MARK,
 915        DU1_DG7_Y3_DATA11_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG5_Y1_DATA9_MARK,
 916        DU1_DG4_Y0_DATA8_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG2_C6_DATA6_MARK,
 917        DU1_DB7_C5_MARK, DU1_DB6_C4_MARK, DU1_DB5_C3_DATA15_MARK,
 918        DU1_DB4_C2_DATA14_MARK, DU1_DB3_C1_DATA13_MARK, DU1_DB2_C0_DATA12_MARK,
 919};
 920static const unsigned int du1_sync_pins[] = {
 921        /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 922        RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
 923};
 924static const unsigned int du1_sync_mux[] = {
 925        DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
 926};
 927static const unsigned int du1_oddf_pins[] = {
 928        /* EXODDF/ODDF/DISP/CDE */
 929        RCAR_GP_PIN(1, 20),
 930};
 931static const unsigned int du1_oddf_mux[] = {
 932        DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
 933};
 934static const unsigned int du1_disp_pins[] = {
 935        /* DISP */
 936        RCAR_GP_PIN(1, 21),
 937};
 938static const unsigned int du1_disp_mux[] = {
 939        DU1_DISP_MARK,
 940};
 941static const unsigned int du1_cde_pins[] = {
 942        /* CDE */
 943        RCAR_GP_PIN(1, 22),
 944};
 945static const unsigned int du1_cde_mux[] = {
 946        DU1_CDE_MARK,
 947};
 948/* - INTC ------------------------------------------------------------------- */
 949static const unsigned int intc_irq0_pins[] = {
 950        /* IRQ0 */
 951        RCAR_GP_PIN(3, 19),
 952};
 953static const unsigned int intc_irq0_mux[] = {
 954        IRQ0_MARK,
 955};
 956static const unsigned int intc_irq1_pins[] = {
 957        /* IRQ1 */
 958        RCAR_GP_PIN(3, 20),
 959};
 960static const unsigned int intc_irq1_mux[] = {
 961        IRQ1_MARK,
 962};
 963static const unsigned int intc_irq2_pins[] = {
 964        /* IRQ2 */
 965        RCAR_GP_PIN(3, 21),
 966};
 967static const unsigned int intc_irq2_mux[] = {
 968        IRQ2_MARK,
 969};
 970static const unsigned int intc_irq3_pins[] = {
 971        /* IRQ3 */
 972        RCAR_GP_PIN(3, 22),
 973};
 974static const unsigned int intc_irq3_mux[] = {
 975        IRQ3_MARK,
 976};
 977/* - LBSC ------------------------------------------------------------------- */
 978static const unsigned int lbsc_cs0_pins[] = {
 979        /* CS0# */
 980        RCAR_GP_PIN(3, 27),
 981};
 982static const unsigned int lbsc_cs0_mux[] = {
 983        CS0_N_MARK,
 984};
 985static const unsigned int lbsc_cs1_pins[] = {
 986        /* CS1#_A26 */
 987        RCAR_GP_PIN(3, 6),
 988};
 989static const unsigned int lbsc_cs1_mux[] = {
 990        CS1_N_A26_MARK,
 991};
 992static const unsigned int lbsc_ex_cs0_pins[] = {
 993        /* EX_CS0# */
 994        RCAR_GP_PIN(3, 7),
 995};
 996static const unsigned int lbsc_ex_cs0_mux[] = {
 997        EX_CS0_N_MARK,
 998};
 999static const unsigned int lbsc_ex_cs1_pins[] = {
1000        /* EX_CS1# */
1001        RCAR_GP_PIN(3, 8),
1002};
1003static const unsigned int lbsc_ex_cs1_mux[] = {
1004        EX_CS1_N_MARK,
1005};
1006static const unsigned int lbsc_ex_cs2_pins[] = {
1007        /* EX_CS2# */
1008        RCAR_GP_PIN(3, 9),
1009};
1010static const unsigned int lbsc_ex_cs2_mux[] = {
1011        EX_CS2_N_MARK,
1012};
1013static const unsigned int lbsc_ex_cs3_pins[] = {
1014        /* EX_CS3# */
1015        RCAR_GP_PIN(3, 10),
1016};
1017static const unsigned int lbsc_ex_cs3_mux[] = {
1018        EX_CS3_N_MARK,
1019};
1020static const unsigned int lbsc_ex_cs4_pins[] = {
1021        /* EX_CS4# */
1022        RCAR_GP_PIN(3, 11),
1023};
1024static const unsigned int lbsc_ex_cs4_mux[] = {
1025        EX_CS4_N_MARK,
1026};
1027static const unsigned int lbsc_ex_cs5_pins[] = {
1028        /* EX_CS5# */
1029        RCAR_GP_PIN(3, 12),
1030};
1031static const unsigned int lbsc_ex_cs5_mux[] = {
1032        EX_CS5_N_MARK,
1033};
1034/* - MSIOF0 ----------------------------------------------------------------- */
1035static const unsigned int msiof0_clk_pins[] = {
1036        /* SCK */
1037        RCAR_GP_PIN(10, 0),
1038};
1039static const unsigned int msiof0_clk_mux[] = {
1040        MSIOF0_SCK_MARK,
1041};
1042static const unsigned int msiof0_sync_pins[] = {
1043        /* SYNC */
1044        RCAR_GP_PIN(10, 1),
1045};
1046static const unsigned int msiof0_sync_mux[] = {
1047        MSIOF0_SYNC_MARK,
1048};
1049static const unsigned int msiof0_rx_pins[] = {
1050        /* RXD */
1051        RCAR_GP_PIN(10, 4),
1052};
1053static const unsigned int msiof0_rx_mux[] = {
1054        MSIOF0_RXD_MARK,
1055};
1056static const unsigned int msiof0_tx_pins[] = {
1057        /* TXD */
1058        RCAR_GP_PIN(10, 3),
1059};
1060static const unsigned int msiof0_tx_mux[] = {
1061        MSIOF0_TXD_MARK,
1062};
1063/* - MSIOF1 ----------------------------------------------------------------- */
1064static const unsigned int msiof1_clk_pins[] = {
1065        /* SCK */
1066        RCAR_GP_PIN(10, 5),
1067};
1068static const unsigned int msiof1_clk_mux[] = {
1069        MSIOF1_SCK_MARK,
1070};
1071static const unsigned int msiof1_sync_pins[] = {
1072        /* SYNC */
1073        RCAR_GP_PIN(10, 6),
1074};
1075static const unsigned int msiof1_sync_mux[] = {
1076        MSIOF1_SYNC_MARK,
1077};
1078static const unsigned int msiof1_rx_pins[] = {
1079        /* RXD */
1080        RCAR_GP_PIN(10, 9),
1081};
1082static const unsigned int msiof1_rx_mux[] = {
1083        MSIOF1_RXD_MARK,
1084};
1085static const unsigned int msiof1_tx_pins[] = {
1086        /* TXD */
1087        RCAR_GP_PIN(10, 8),
1088};
1089static const unsigned int msiof1_tx_mux[] = {
1090        MSIOF1_TXD_MARK,
1091};
1092/* - QSPI ------------------------------------------------------------------- */
1093static const unsigned int qspi_ctrl_pins[] = {
1094        /* SPCLK, SSL */
1095        RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1096};
1097static const unsigned int qspi_ctrl_mux[] = {
1098        SPCLK_MARK, SSL_MARK,
1099};
1100static const unsigned int qspi_data2_pins[] = {
1101        /* MOSI_IO0, MISO_IO1 */
1102        RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1103};
1104static const unsigned int qspi_data2_mux[] = {
1105        MOSI_IO0_MARK, MISO_IO1_MARK,
1106};
1107static const unsigned int qspi_data4_pins[] = {
1108        /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1109        RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
1110        RCAR_GP_PIN(3, 24),
1111};
1112static const unsigned int qspi_data4_mux[] = {
1113        MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
1114};
1115/* - SCIF0 ------------------------------------------------------------------ */
1116static const unsigned int scif0_data_pins[] = {
1117        /* RX, TX */
1118        RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13),
1119};
1120static const unsigned int scif0_data_mux[] = {
1121        RX0_MARK, TX0_MARK,
1122};
1123static const unsigned int scif0_clk_pins[] = {
1124        /* SCK */
1125        RCAR_GP_PIN(10, 10),
1126};
1127static const unsigned int scif0_clk_mux[] = {
1128        SCK0_MARK,
1129};
1130static const unsigned int scif0_ctrl_pins[] = {
1131        /* RTS, CTS */
1132        RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11),
1133};
1134static const unsigned int scif0_ctrl_mux[] = {
1135        RTS0_N_MARK, CTS0_N_MARK,
1136};
1137/* - SCIF1 ------------------------------------------------------------------ */
1138static const unsigned int scif1_data_pins[] = {
1139        /* RX, TX */
1140        RCAR_GP_PIN(10, 19), RCAR_GP_PIN(10, 18),
1141};
1142static const unsigned int scif1_data_mux[] = {
1143        RX1_MARK, TX1_MARK,
1144};
1145static const unsigned int scif1_clk_pins[] = {
1146        /* SCK */
1147        RCAR_GP_PIN(10, 15),
1148};
1149static const unsigned int scif1_clk_mux[] = {
1150        SCK1_MARK,
1151};
1152static const unsigned int scif1_ctrl_pins[] = {
1153        /* RTS, CTS */
1154        RCAR_GP_PIN(10, 17), RCAR_GP_PIN(10, 16),
1155};
1156static const unsigned int scif1_ctrl_mux[] = {
1157        RTS1_N_MARK, CTS1_N_MARK,
1158};
1159/* - SCIF2 ------------------------------------------------------------------ */
1160static const unsigned int scif2_data_pins[] = {
1161        /* RX, TX */
1162        RCAR_GP_PIN(10, 22), RCAR_GP_PIN(10, 21),
1163};
1164static const unsigned int scif2_data_mux[] = {
1165        RX2_MARK, TX2_MARK,
1166};
1167static const unsigned int scif2_clk_pins[] = {
1168        /* SCK */
1169        RCAR_GP_PIN(10, 20),
1170};
1171static const unsigned int scif2_clk_mux[] = {
1172        SCK2_MARK,
1173};
1174/* - SCIF3 ------------------------------------------------------------------ */
1175static const unsigned int scif3_data_pins[] = {
1176        /* RX, TX */
1177        RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24),
1178};
1179static const unsigned int scif3_data_mux[] = {
1180        RX3_MARK, TX3_MARK,
1181};
1182static const unsigned int scif3_clk_pins[] = {
1183        /* SCK */
1184        RCAR_GP_PIN(10, 23),
1185};
1186static const unsigned int scif3_clk_mux[] = {
1187        SCK3_MARK,
1188};
1189/* - SDHI0 ------------------------------------------------------------------ */
1190static const unsigned int sdhi0_data1_pins[] = {
1191        /* DAT0 */
1192        RCAR_GP_PIN(11, 7),
1193};
1194static const unsigned int sdhi0_data1_mux[] = {
1195        SD0_DAT0_MARK,
1196};
1197static const unsigned int sdhi0_data4_pins[] = {
1198        /* DAT[0-3] */
1199        RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
1200        RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
1201};
1202static const unsigned int sdhi0_data4_mux[] = {
1203        SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
1204};
1205static const unsigned int sdhi0_ctrl_pins[] = {
1206        /* CLK, CMD */
1207        RCAR_GP_PIN(11, 5), RCAR_GP_PIN(11, 6),
1208};
1209static const unsigned int sdhi0_ctrl_mux[] = {
1210        SD0_CLK_MARK, SD0_CMD_MARK,
1211};
1212static const unsigned int sdhi0_cd_pins[] = {
1213        /* CD */
1214        RCAR_GP_PIN(11, 11),
1215};
1216static const unsigned int sdhi0_cd_mux[] = {
1217        SD0_CD_MARK,
1218};
1219static const unsigned int sdhi0_wp_pins[] = {
1220        /* WP */
1221        RCAR_GP_PIN(11, 12),
1222};
1223static const unsigned int sdhi0_wp_mux[] = {
1224        SD0_WP_MARK,
1225};
1226/* - VIN0 ------------------------------------------------------------------- */
1227static const union vin_data vin0_data_pins = {
1228        .data24 = {
1229                /* B */
1230                RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1231                RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1232                RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1233                RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1234                /* G */
1235                RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1236                RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1237                RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1238                RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1239                /* R */
1240                RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1241                RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1242                RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1243                RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1244        },
1245};
1246static const union vin_data vin0_data_mux = {
1247        .data24 = {
1248                /* B */
1249                VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
1250                VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1251                VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1252                VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1253                /* G */
1254                VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
1255                VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1256                VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1257                VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1258                /* R */
1259                VI0_D16_R0_MARK, VI0_D17_R1_MARK,
1260                VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1261                VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1262                VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1263        },
1264};
1265static const unsigned int vin0_data18_pins[] = {
1266        /* B */
1267        RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1268        RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1269        RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1270        /* G */
1271        RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1272        RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1273        RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1274        /* R */
1275        RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1276        RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1277        RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1278};
1279static const unsigned int vin0_data18_mux[] = {
1280        /* B */
1281        VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1282        VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1283        VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1284        /* G */
1285        VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1286        VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1287        VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1288        /* R */
1289        VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1290        VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1291        VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1292};
1293static const unsigned int vin0_sync_pins[] = {
1294        /* HSYNC#, VSYNC# */
1295        RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1296};
1297static const unsigned int vin0_sync_mux[] = {
1298        VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1299};
1300static const unsigned int vin0_field_pins[] = {
1301        RCAR_GP_PIN(4, 16),
1302};
1303static const unsigned int vin0_field_mux[] = {
1304        VI0_FIELD_MARK,
1305};
1306static const unsigned int vin0_clkenb_pins[] = {
1307        RCAR_GP_PIN(4, 1),
1308};
1309static const unsigned int vin0_clkenb_mux[] = {
1310        VI0_CLKENB_MARK,
1311};
1312static const unsigned int vin0_clk_pins[] = {
1313        RCAR_GP_PIN(4, 0),
1314};
1315static const unsigned int vin0_clk_mux[] = {
1316        VI0_CLK_MARK,
1317};
1318/* - VIN1 ------------------------------------------------------------------- */
1319static const union vin_data vin1_data_pins = {
1320        .data24 = {
1321                /* B */
1322                RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1323                RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1324                RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1325                RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1326                /* G */
1327                RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1328                RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1329                RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1330                RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1331                /* R */
1332                RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1333                RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1334                RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1335                RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1336        },
1337};
1338static const union vin_data vin1_data_mux = {
1339        .data24 = {
1340                /* B */
1341                VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1342                VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1343                VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1344                VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1345                /* G */
1346                VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1347                VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1348                VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1349                VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1350                /* R */
1351                VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1352                VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1353                VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1354                VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1355        },
1356};
1357static const unsigned int vin1_data18_pins[] = {
1358        /* B */
1359        RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1360        RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1361        RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1362        /* G */
1363        RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1364        RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1365        RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1366        /* R */
1367        RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1368        RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1369        RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1370};
1371static const unsigned int vin1_data18_mux[] = {
1372        /* B */
1373        VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1374        VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1375        VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1376        /* G */
1377        VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1378        VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1379        VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1380        /* R */
1381        VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1382        VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1383        VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1384};
1385static const union vin_data vin1_data_b_pins = {
1386        .data24 = {
1387                /* B */
1388                RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1389                RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1390                RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1391                RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1392                /* G */
1393                RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1394                RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1395                RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1396                RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1397                /* R */
1398                RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1399                RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1400                RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1401                RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1402        },
1403};
1404static const union vin_data vin1_data_b_mux = {
1405        .data24 = {
1406                /* B */
1407                VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1408                VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1409                VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1410                VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1411                /* G */
1412                VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1413                VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1414                VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1415                VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1416                /* R */
1417                VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1418                VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1419                VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1420                VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1421        },
1422};
1423static const unsigned int vin1_data18_b_pins[] = {
1424        /* B */
1425        RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1426        RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1427        RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1428        /* G */
1429        RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1430        RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1431        RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1432        /* R */
1433        RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1434        RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1435        RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1436};
1437static const unsigned int vin1_data18_b_mux[] = {
1438        /* B */
1439        VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1440        VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1441        VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1442        /* G */
1443        VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1444        VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1445        VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1446        /* R */
1447        VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1448        VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1449        VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1450};
1451static const unsigned int vin1_sync_pins[] = {
1452        /* HSYNC#, VSYNC# */
1453        RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
1454};
1455static const unsigned int vin1_sync_mux[] = {
1456        VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1457};
1458static const unsigned int vin1_field_pins[] = {
1459        RCAR_GP_PIN(5, 16),
1460};
1461static const unsigned int vin1_field_mux[] = {
1462        VI1_FIELD_MARK,
1463};
1464static const unsigned int vin1_clkenb_pins[] = {
1465        RCAR_GP_PIN(5, 1),
1466};
1467static const unsigned int vin1_clkenb_mux[] = {
1468        VI1_CLKENB_MARK,
1469};
1470static const unsigned int vin1_clk_pins[] = {
1471        RCAR_GP_PIN(5, 0),
1472};
1473static const unsigned int vin1_clk_mux[] = {
1474        VI1_CLK_MARK,
1475};
1476/* - VIN2 ------------------------------------------------------------------- */
1477static const union vin_data16 vin2_data_pins = {
1478        .data16 = {
1479                RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1480                RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1481                RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1482                RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1483                RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
1484                RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1485                RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1486                RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1487        },
1488};
1489static const union vin_data16 vin2_data_mux = {
1490        .data16 = {
1491                VI2_D0_C0_MARK, VI2_D1_C1_MARK,
1492                VI2_D2_C2_MARK, VI2_D3_C3_MARK,
1493                VI2_D4_C4_MARK, VI2_D5_C5_MARK,
1494                VI2_D6_C6_MARK, VI2_D7_C7_MARK,
1495                VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
1496                VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
1497                VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
1498                VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
1499        },
1500};
1501static const unsigned int vin2_sync_pins[] = {
1502        /* HSYNC#, VSYNC# */
1503        RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
1504};
1505static const unsigned int vin2_sync_mux[] = {
1506        VI2_HSYNC_N_MARK, VI2_VSYNC_N_MARK,
1507};
1508static const unsigned int vin2_field_pins[] = {
1509        RCAR_GP_PIN(6, 16),
1510};
1511static const unsigned int vin2_field_mux[] = {
1512        VI2_FIELD_MARK,
1513};
1514static const unsigned int vin2_clkenb_pins[] = {
1515        RCAR_GP_PIN(6, 1),
1516};
1517static const unsigned int vin2_clkenb_mux[] = {
1518        VI2_CLKENB_MARK,
1519};
1520static const unsigned int vin2_clk_pins[] = {
1521        RCAR_GP_PIN(6, 0),
1522};
1523static const unsigned int vin2_clk_mux[] = {
1524        VI2_CLK_MARK,
1525};
1526/* - VIN3 ------------------------------------------------------------------- */
1527static const union vin_data16 vin3_data_pins = {
1528        .data16 = {
1529                RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1530                RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1531                RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1532                RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1533                RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
1534                RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
1535                RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
1536                RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
1537        },
1538};
1539static const union vin_data16 vin3_data_mux = {
1540        .data16 = {
1541                VI3_D0_C0_MARK, VI3_D1_C1_MARK,
1542                VI3_D2_C2_MARK, VI3_D3_C3_MARK,
1543                VI3_D4_C4_MARK, VI3_D5_C5_MARK,
1544                VI3_D6_C6_MARK, VI3_D7_C7_MARK,
1545                VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
1546                VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
1547                VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
1548                VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
1549        },
1550};
1551static const unsigned int vin3_sync_pins[] = {
1552        /* HSYNC#, VSYNC# */
1553        RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
1554};
1555static const unsigned int vin3_sync_mux[] = {
1556        VI3_HSYNC_N_MARK, VI3_VSYNC_N_MARK,
1557};
1558static const unsigned int vin3_field_pins[] = {
1559        RCAR_GP_PIN(7, 16),
1560};
1561static const unsigned int vin3_field_mux[] = {
1562        VI3_FIELD_MARK,
1563};
1564static const unsigned int vin3_clkenb_pins[] = {
1565        RCAR_GP_PIN(7, 1),
1566};
1567static const unsigned int vin3_clkenb_mux[] = {
1568        VI3_CLKENB_MARK,
1569};
1570static const unsigned int vin3_clk_pins[] = {
1571        RCAR_GP_PIN(7, 0),
1572};
1573static const unsigned int vin3_clk_mux[] = {
1574        VI3_CLK_MARK,
1575};
1576/* - VIN4 ------------------------------------------------------------------- */
1577static const union vin_data12 vin4_data_pins = {
1578        .data12 = {
1579                RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1580                RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1581                RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1582                RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1583                RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
1584                RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
1585        },
1586};
1587static const union vin_data12 vin4_data_mux = {
1588        .data12 = {
1589                VI4_D0_C0_MARK, VI4_D1_C1_MARK,
1590                VI4_D2_C2_MARK, VI4_D3_C3_MARK,
1591                VI4_D4_C4_MARK, VI4_D5_C5_MARK,
1592                VI4_D6_C6_MARK, VI4_D7_C7_MARK,
1593                VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
1594                VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
1595        },
1596};
1597static const unsigned int vin4_sync_pins[] = {
1598         /* HSYNC#, VSYNC# */
1599        RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
1600};
1601static const unsigned int vin4_sync_mux[] = {
1602        VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
1603};
1604static const unsigned int vin4_field_pins[] = {
1605        RCAR_GP_PIN(8, 16),
1606};
1607static const unsigned int vin4_field_mux[] = {
1608        VI4_FIELD_MARK,
1609};
1610static const unsigned int vin4_clkenb_pins[] = {
1611        RCAR_GP_PIN(8, 1),
1612};
1613static const unsigned int vin4_clkenb_mux[] = {
1614        VI4_CLKENB_MARK,
1615};
1616static const unsigned int vin4_clk_pins[] = {
1617        RCAR_GP_PIN(8, 0),
1618};
1619static const unsigned int vin4_clk_mux[] = {
1620        VI4_CLK_MARK,
1621};
1622/* - VIN5 ------------------------------------------------------------------- */
1623static const union vin_data12 vin5_data_pins = {
1624        .data12 = {
1625                RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1626                RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1627                RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1628                RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1629                RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
1630                RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
1631        },
1632};
1633static const union vin_data12 vin5_data_mux = {
1634        .data12 = {
1635                VI5_D0_C0_MARK, VI5_D1_C1_MARK,
1636                VI5_D2_C2_MARK, VI5_D3_C3_MARK,
1637                VI5_D4_C4_MARK, VI5_D5_C5_MARK,
1638                VI5_D6_C6_MARK, VI5_D7_C7_MARK,
1639                VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
1640                VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
1641        },
1642};
1643static const unsigned int vin5_sync_pins[] = {
1644        /* HSYNC#, VSYNC# */
1645        RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
1646};
1647static const unsigned int vin5_sync_mux[] = {
1648        VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
1649};
1650static const unsigned int vin5_field_pins[] = {
1651        RCAR_GP_PIN(9, 16),
1652};
1653static const unsigned int vin5_field_mux[] = {
1654        VI5_FIELD_MARK,
1655};
1656static const unsigned int vin5_clkenb_pins[] = {
1657        RCAR_GP_PIN(9, 1),
1658};
1659static const unsigned int vin5_clkenb_mux[] = {
1660        VI5_CLKENB_MARK,
1661};
1662static const unsigned int vin5_clk_pins[] = {
1663        RCAR_GP_PIN(9, 0),
1664};
1665static const unsigned int vin5_clk_mux[] = {
1666        VI5_CLK_MARK,
1667};
1668
1669static const struct sh_pfc_pin_group pinmux_groups[] = {
1670        SH_PFC_PIN_GROUP(avb_link),
1671        SH_PFC_PIN_GROUP(avb_magic),
1672        SH_PFC_PIN_GROUP(avb_phy_int),
1673        SH_PFC_PIN_GROUP(avb_mdio),
1674        SH_PFC_PIN_GROUP(avb_mii),
1675        SH_PFC_PIN_GROUP(avb_gmii),
1676        SH_PFC_PIN_GROUP(avb_avtp_match),
1677        SH_PFC_PIN_GROUP(can0_data),
1678        SH_PFC_PIN_GROUP(can1_data),
1679        SH_PFC_PIN_GROUP(can_clk),
1680        SH_PFC_PIN_GROUP(du0_rgb666),
1681        SH_PFC_PIN_GROUP(du0_rgb888),
1682        SH_PFC_PIN_GROUP(du0_sync),
1683        SH_PFC_PIN_GROUP(du0_oddf),
1684        SH_PFC_PIN_GROUP(du0_disp),
1685        SH_PFC_PIN_GROUP(du0_cde),
1686        SH_PFC_PIN_GROUP(du1_rgb666),
1687        SH_PFC_PIN_GROUP(du1_sync),
1688        SH_PFC_PIN_GROUP(du1_oddf),
1689        SH_PFC_PIN_GROUP(du1_disp),
1690        SH_PFC_PIN_GROUP(du1_cde),
1691        SH_PFC_PIN_GROUP(intc_irq0),
1692        SH_PFC_PIN_GROUP(intc_irq1),
1693        SH_PFC_PIN_GROUP(intc_irq2),
1694        SH_PFC_PIN_GROUP(intc_irq3),
1695        SH_PFC_PIN_GROUP(lbsc_cs0),
1696        SH_PFC_PIN_GROUP(lbsc_cs1),
1697        SH_PFC_PIN_GROUP(lbsc_ex_cs0),
1698        SH_PFC_PIN_GROUP(lbsc_ex_cs1),
1699        SH_PFC_PIN_GROUP(lbsc_ex_cs2),
1700        SH_PFC_PIN_GROUP(lbsc_ex_cs3),
1701        SH_PFC_PIN_GROUP(lbsc_ex_cs4),
1702        SH_PFC_PIN_GROUP(lbsc_ex_cs5),
1703        SH_PFC_PIN_GROUP(msiof0_clk),
1704        SH_PFC_PIN_GROUP(msiof0_sync),
1705        SH_PFC_PIN_GROUP(msiof0_rx),
1706        SH_PFC_PIN_GROUP(msiof0_tx),
1707        SH_PFC_PIN_GROUP(msiof1_clk),
1708        SH_PFC_PIN_GROUP(msiof1_sync),
1709        SH_PFC_PIN_GROUP(msiof1_rx),
1710        SH_PFC_PIN_GROUP(msiof1_tx),
1711        SH_PFC_PIN_GROUP(qspi_ctrl),
1712        SH_PFC_PIN_GROUP(qspi_data2),
1713        SH_PFC_PIN_GROUP(qspi_data4),
1714        SH_PFC_PIN_GROUP(scif0_data),
1715        SH_PFC_PIN_GROUP(scif0_clk),
1716        SH_PFC_PIN_GROUP(scif0_ctrl),
1717        SH_PFC_PIN_GROUP(scif1_data),
1718        SH_PFC_PIN_GROUP(scif1_clk),
1719        SH_PFC_PIN_GROUP(scif1_ctrl),
1720        SH_PFC_PIN_GROUP(scif2_data),
1721        SH_PFC_PIN_GROUP(scif2_clk),
1722        SH_PFC_PIN_GROUP(scif3_data),
1723        SH_PFC_PIN_GROUP(scif3_clk),
1724        SH_PFC_PIN_GROUP(sdhi0_data1),
1725        SH_PFC_PIN_GROUP(sdhi0_data4),
1726        SH_PFC_PIN_GROUP(sdhi0_ctrl),
1727        SH_PFC_PIN_GROUP(sdhi0_cd),
1728        SH_PFC_PIN_GROUP(sdhi0_wp),
1729        VIN_DATA_PIN_GROUP(vin0_data, 24),
1730        VIN_DATA_PIN_GROUP(vin0_data, 20),
1731        SH_PFC_PIN_GROUP(vin0_data18),
1732        VIN_DATA_PIN_GROUP(vin0_data, 16),
1733        VIN_DATA_PIN_GROUP(vin0_data, 12),
1734        VIN_DATA_PIN_GROUP(vin0_data, 10),
1735        VIN_DATA_PIN_GROUP(vin0_data, 8),
1736        SH_PFC_PIN_GROUP(vin0_sync),
1737        SH_PFC_PIN_GROUP(vin0_field),
1738        SH_PFC_PIN_GROUP(vin0_clkenb),
1739        SH_PFC_PIN_GROUP(vin0_clk),
1740        VIN_DATA_PIN_GROUP(vin1_data, 24),
1741        VIN_DATA_PIN_GROUP(vin1_data, 20),
1742        SH_PFC_PIN_GROUP(vin1_data18),
1743        VIN_DATA_PIN_GROUP(vin1_data, 16),
1744        VIN_DATA_PIN_GROUP(vin1_data, 12),
1745        VIN_DATA_PIN_GROUP(vin1_data, 10),
1746        VIN_DATA_PIN_GROUP(vin1_data, 8),
1747        VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
1748        VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
1749        SH_PFC_PIN_GROUP(vin1_data18_b),
1750        VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
1751        SH_PFC_PIN_GROUP(vin1_sync),
1752        SH_PFC_PIN_GROUP(vin1_field),
1753        SH_PFC_PIN_GROUP(vin1_clkenb),
1754        SH_PFC_PIN_GROUP(vin1_clk),
1755        VIN_DATA_PIN_GROUP(vin2_data, 16),
1756        VIN_DATA_PIN_GROUP(vin2_data, 12),
1757        VIN_DATA_PIN_GROUP(vin2_data, 10),
1758        VIN_DATA_PIN_GROUP(vin2_data, 8),
1759        SH_PFC_PIN_GROUP(vin2_sync),
1760        SH_PFC_PIN_GROUP(vin2_field),
1761        SH_PFC_PIN_GROUP(vin2_clkenb),
1762        SH_PFC_PIN_GROUP(vin2_clk),
1763        VIN_DATA_PIN_GROUP(vin3_data, 16),
1764        VIN_DATA_PIN_GROUP(vin3_data, 12),
1765        VIN_DATA_PIN_GROUP(vin3_data, 10),
1766        VIN_DATA_PIN_GROUP(vin3_data, 8),
1767        SH_PFC_PIN_GROUP(vin3_sync),
1768        SH_PFC_PIN_GROUP(vin3_field),
1769        SH_PFC_PIN_GROUP(vin3_clkenb),
1770        SH_PFC_PIN_GROUP(vin3_clk),
1771        VIN_DATA_PIN_GROUP(vin4_data, 12),
1772        VIN_DATA_PIN_GROUP(vin4_data, 10),
1773        VIN_DATA_PIN_GROUP(vin4_data, 8),
1774        SH_PFC_PIN_GROUP(vin4_sync),
1775        SH_PFC_PIN_GROUP(vin4_field),
1776        SH_PFC_PIN_GROUP(vin4_clkenb),
1777        SH_PFC_PIN_GROUP(vin4_clk),
1778        VIN_DATA_PIN_GROUP(vin5_data, 12),
1779        VIN_DATA_PIN_GROUP(vin5_data, 10),
1780        VIN_DATA_PIN_GROUP(vin5_data, 8),
1781        SH_PFC_PIN_GROUP(vin5_sync),
1782        SH_PFC_PIN_GROUP(vin5_field),
1783        SH_PFC_PIN_GROUP(vin5_clkenb),
1784        SH_PFC_PIN_GROUP(vin5_clk),
1785};
1786
1787static const char * const avb_groups[] = {
1788        "avb_link",
1789        "avb_magic",
1790        "avb_phy_int",
1791        "avb_mdio",
1792        "avb_mii",
1793        "avb_gmii",
1794        "avb_avtp_match",
1795};
1796
1797static const char * const can0_groups[] = {
1798        "can0_data",
1799        "can_clk",
1800};
1801
1802static const char * const can1_groups[] = {
1803        "can1_data",
1804        "can_clk",
1805};
1806
1807static const char * const du0_groups[] = {
1808        "du0_rgb666",
1809        "du0_rgb888",
1810        "du0_sync",
1811        "du0_oddf",
1812        "du0_disp",
1813        "du0_cde",
1814};
1815
1816static const char * const du1_groups[] = {
1817        "du1_rgb666",
1818        "du1_sync",
1819        "du1_oddf",
1820        "du1_disp",
1821        "du1_cde",
1822};
1823
1824static const char * const intc_groups[] = {
1825        "intc_irq0",
1826        "intc_irq1",
1827        "intc_irq2",
1828        "intc_irq3",
1829};
1830
1831static const char * const lbsc_groups[] = {
1832        "lbsc_cs0",
1833        "lbsc_cs1",
1834        "lbsc_ex_cs0",
1835        "lbsc_ex_cs1",
1836        "lbsc_ex_cs2",
1837        "lbsc_ex_cs3",
1838        "lbsc_ex_cs4",
1839        "lbsc_ex_cs5",
1840};
1841
1842static const char * const msiof0_groups[] = {
1843        "msiof0_clk",
1844        "msiof0_sync",
1845        "msiof0_rx",
1846        "msiof0_tx",
1847};
1848
1849static const char * const msiof1_groups[] = {
1850        "msiof1_clk",
1851        "msiof1_sync",
1852        "msiof1_rx",
1853        "msiof1_tx",
1854};
1855
1856static const char * const qspi_groups[] = {
1857        "qspi_ctrl",
1858        "qspi_data2",
1859        "qspi_data4",
1860};
1861
1862static const char * const scif0_groups[] = {
1863        "scif0_data",
1864        "scif0_clk",
1865        "scif0_ctrl",
1866};
1867
1868static const char * const scif1_groups[] = {
1869        "scif1_data",
1870        "scif1_clk",
1871        "scif1_ctrl",
1872};
1873
1874static const char * const scif2_groups[] = {
1875        "scif2_data",
1876        "scif2_clk",
1877};
1878
1879static const char * const scif3_groups[] = {
1880        "scif3_data",
1881        "scif3_clk",
1882};
1883
1884static const char * const sdhi0_groups[] = {
1885        "sdhi0_data1",
1886        "sdhi0_data4",
1887        "sdhi0_ctrl",
1888        "sdhi0_cd",
1889        "sdhi0_wp",
1890};
1891
1892static const char * const vin0_groups[] = {
1893        "vin0_data24",
1894        "vin0_data20",
1895        "vin0_data18",
1896        "vin0_data16",
1897        "vin0_data12",
1898        "vin0_data10",
1899        "vin0_data8",
1900        "vin0_sync",
1901        "vin0_field",
1902        "vin0_clkenb",
1903        "vin0_clk",
1904};
1905
1906static const char * const vin1_groups[] = {
1907        "vin1_data24",
1908        "vin1_data20",
1909        "vin1_data18",
1910        "vin1_data16",
1911        "vin1_data12",
1912        "vin1_data10",
1913        "vin1_data8",
1914        "vin1_data24_b",
1915        "vin1_data20_b",
1916        "vin1_data18_b",
1917        "vin1_data16_b",
1918        "vin1_sync",
1919        "vin1_field",
1920        "vin1_clkenb",
1921        "vin1_clk",
1922};
1923
1924static const char * const vin2_groups[] = {
1925        "vin2_data16",
1926        "vin2_data12",
1927        "vin2_data10",
1928        "vin2_data8",
1929        "vin2_sync",
1930        "vin2_field",
1931        "vin2_clkenb",
1932        "vin2_clk",
1933};
1934
1935static const char * const vin3_groups[] = {
1936        "vin3_data16",
1937        "vin3_data12",
1938        "vin3_data10",
1939        "vin3_data8",
1940        "vin3_sync",
1941        "vin3_field",
1942        "vin3_clkenb",
1943        "vin3_clk",
1944};
1945
1946static const char * const vin4_groups[] = {
1947        "vin4_data12",
1948        "vin4_data10",
1949        "vin4_data8",
1950        "vin4_sync",
1951        "vin4_field",
1952        "vin4_clkenb",
1953        "vin4_clk",
1954};
1955
1956static const char * const vin5_groups[] = {
1957        "vin5_data12",
1958        "vin5_data10",
1959        "vin5_data8",
1960        "vin5_sync",
1961        "vin5_field",
1962        "vin5_clkenb",
1963        "vin5_clk",
1964};
1965
1966static const struct sh_pfc_function pinmux_functions[] = {
1967        SH_PFC_FUNCTION(avb),
1968        SH_PFC_FUNCTION(can0),
1969        SH_PFC_FUNCTION(can1),
1970        SH_PFC_FUNCTION(du0),
1971        SH_PFC_FUNCTION(du1),
1972        SH_PFC_FUNCTION(intc),
1973        SH_PFC_FUNCTION(lbsc),
1974        SH_PFC_FUNCTION(msiof0),
1975        SH_PFC_FUNCTION(msiof1),
1976        SH_PFC_FUNCTION(qspi),
1977        SH_PFC_FUNCTION(scif0),
1978        SH_PFC_FUNCTION(scif1),
1979        SH_PFC_FUNCTION(scif2),
1980        SH_PFC_FUNCTION(scif3),
1981        SH_PFC_FUNCTION(sdhi0),
1982        SH_PFC_FUNCTION(vin0),
1983        SH_PFC_FUNCTION(vin1),
1984        SH_PFC_FUNCTION(vin2),
1985        SH_PFC_FUNCTION(vin3),
1986        SH_PFC_FUNCTION(vin4),
1987        SH_PFC_FUNCTION(vin5),
1988};
1989
1990static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1991        { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
1992                0, 0,
1993                0, 0,
1994                0, 0,
1995                GP_0_28_FN, FN_IP1_4,
1996                GP_0_27_FN, FN_IP1_3,
1997                GP_0_26_FN, FN_IP1_2,
1998                GP_0_25_FN, FN_IP1_1,
1999                GP_0_24_FN, FN_IP1_0,
2000                GP_0_23_FN, FN_IP0_23,
2001                GP_0_22_FN, FN_IP0_22,
2002                GP_0_21_FN, FN_IP0_21,
2003                GP_0_20_FN, FN_IP0_20,
2004                GP_0_19_FN, FN_IP0_19,
2005                GP_0_18_FN, FN_IP0_18,
2006                GP_0_17_FN, FN_IP0_17,
2007                GP_0_16_FN, FN_IP0_16,
2008                GP_0_15_FN, FN_IP0_15,
2009                GP_0_14_FN, FN_IP0_14,
2010                GP_0_13_FN, FN_IP0_13,
2011                GP_0_12_FN, FN_IP0_12,
2012                GP_0_11_FN, FN_IP0_11,
2013                GP_0_10_FN, FN_IP0_10,
2014                GP_0_9_FN, FN_IP0_9,
2015                GP_0_8_FN, FN_IP0_8,
2016                GP_0_7_FN, FN_IP0_7,
2017                GP_0_6_FN, FN_IP0_6,
2018                GP_0_5_FN, FN_IP0_5,
2019                GP_0_4_FN, FN_IP0_4,
2020                GP_0_3_FN, FN_IP0_3,
2021                GP_0_2_FN, FN_IP0_2,
2022                GP_0_1_FN, FN_IP0_1,
2023                GP_0_0_FN, FN_IP0_0 ))
2024        },
2025        { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
2026                0, 0,
2027                0, 0,
2028                0, 0,
2029                0, 0,
2030                0, 0,
2031                0, 0,
2032                0, 0,
2033                0, 0,
2034                0, 0,
2035                GP_1_22_FN, FN_DU1_CDE,
2036                GP_1_21_FN, FN_DU1_DISP,
2037                GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
2038                GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
2039                GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
2040                GP_1_17_FN, FN_DU1_DB7_C5,
2041                GP_1_16_FN, FN_DU1_DB6_C4,
2042                GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
2043                GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
2044                GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
2045                GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
2046                GP_1_11_FN, FN_IP1_16,
2047                GP_1_10_FN, FN_IP1_15,
2048                GP_1_9_FN, FN_IP1_14,
2049                GP_1_8_FN, FN_IP1_13,
2050                GP_1_7_FN, FN_IP1_12,
2051                GP_1_6_FN, FN_IP1_11,
2052                GP_1_5_FN, FN_IP1_10,
2053                GP_1_4_FN, FN_IP1_9,
2054                GP_1_3_FN, FN_IP1_8,
2055                GP_1_2_FN, FN_IP1_7,
2056                GP_1_1_FN, FN_IP1_6,
2057                GP_1_0_FN, FN_IP1_5, ))
2058        },
2059        { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
2060                GP_2_31_FN, FN_A15,
2061                GP_2_30_FN, FN_A14,
2062                GP_2_29_FN, FN_A13,
2063                GP_2_28_FN, FN_A12,
2064                GP_2_27_FN, FN_A11,
2065                GP_2_26_FN, FN_A10,
2066                GP_2_25_FN, FN_A9,
2067                GP_2_24_FN, FN_A8,
2068                GP_2_23_FN, FN_A7,
2069                GP_2_22_FN, FN_A6,
2070                GP_2_21_FN, FN_A5,
2071                GP_2_20_FN, FN_A4,
2072                GP_2_19_FN, FN_A3,
2073                GP_2_18_FN, FN_A2,
2074                GP_2_17_FN, FN_A1,
2075                GP_2_16_FN, FN_A0,
2076                GP_2_15_FN, FN_D15,
2077                GP_2_14_FN, FN_D14,
2078                GP_2_13_FN, FN_D13,
2079                GP_2_12_FN, FN_D12,
2080                GP_2_11_FN, FN_D11,
2081                GP_2_10_FN, FN_D10,
2082                GP_2_9_FN, FN_D9,
2083                GP_2_8_FN, FN_D8,
2084                GP_2_7_FN, FN_D7,
2085                GP_2_6_FN, FN_D6,
2086                GP_2_5_FN, FN_D5,
2087                GP_2_4_FN, FN_D4,
2088                GP_2_3_FN, FN_D3,
2089                GP_2_2_FN, FN_D2,
2090                GP_2_1_FN, FN_D1,
2091                GP_2_0_FN, FN_D0 ))
2092        },
2093        { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
2094                0, 0,
2095                0, 0,
2096                0, 0,
2097                0, 0,
2098                GP_3_27_FN, FN_CS0_N,
2099                GP_3_26_FN, FN_IP1_22,
2100                GP_3_25_FN, FN_IP1_21,
2101                GP_3_24_FN, FN_IP1_20,
2102                GP_3_23_FN, FN_IP1_19,
2103                GP_3_22_FN, FN_IRQ3,
2104                GP_3_21_FN, FN_IRQ2,
2105                GP_3_20_FN, FN_IRQ1,
2106                GP_3_19_FN, FN_IRQ0,
2107                GP_3_18_FN, FN_EX_WAIT0,
2108                GP_3_17_FN, FN_WE1_N,
2109                GP_3_16_FN, FN_WE0_N,
2110                GP_3_15_FN, FN_RD_WR_N,
2111                GP_3_14_FN, FN_RD_N,
2112                GP_3_13_FN, FN_BS_N,
2113                GP_3_12_FN, FN_EX_CS5_N,
2114                GP_3_11_FN, FN_EX_CS4_N,
2115                GP_3_10_FN, FN_EX_CS3_N,
2116                GP_3_9_FN, FN_EX_CS2_N,
2117                GP_3_8_FN, FN_EX_CS1_N,
2118                GP_3_7_FN, FN_EX_CS0_N,
2119                GP_3_6_FN, FN_CS1_N_A26,
2120                GP_3_5_FN, FN_IP1_18,
2121                GP_3_4_FN, FN_IP1_17,
2122                GP_3_3_FN, FN_A19,
2123                GP_3_2_FN, FN_A18,
2124                GP_3_1_FN, FN_A17,
2125                GP_3_0_FN, FN_A16 ))
2126        },
2127        { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
2128                0, 0,
2129                0, 0,
2130                0, 0,
2131                0, 0,
2132                0, 0,
2133                0, 0,
2134                0, 0,
2135                0, 0,
2136                0, 0,
2137                0, 0,
2138                0, 0,
2139                0, 0,
2140                0, 0,
2141                0, 0,
2142                0, 0,
2143                GP_4_16_FN, FN_VI0_FIELD,
2144                GP_4_15_FN, FN_VI0_D11_G3_Y3,
2145                GP_4_14_FN, FN_VI0_D10_G2_Y2,
2146                GP_4_13_FN, FN_VI0_D9_G1_Y1,
2147                GP_4_12_FN, FN_VI0_D8_G0_Y0,
2148                GP_4_11_FN, FN_VI0_D7_B7_C7,
2149                GP_4_10_FN, FN_VI0_D6_B6_C6,
2150                GP_4_9_FN, FN_VI0_D5_B5_C5,
2151                GP_4_8_FN, FN_VI0_D4_B4_C4,
2152                GP_4_7_FN, FN_VI0_D3_B3_C3,
2153                GP_4_6_FN, FN_VI0_D2_B2_C2,
2154                GP_4_5_FN, FN_VI0_D1_B1_C1,
2155                GP_4_4_FN, FN_VI0_D0_B0_C0,
2156                GP_4_3_FN, FN_VI0_VSYNC_N,
2157                GP_4_2_FN, FN_VI0_HSYNC_N,
2158                GP_4_1_FN, FN_VI0_CLKENB,
2159                GP_4_0_FN, FN_VI0_CLK ))
2160        },
2161        { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
2162                0, 0,
2163                0, 0,
2164                0, 0,
2165                0, 0,
2166                0, 0,
2167                0, 0,
2168                0, 0,
2169                0, 0,
2170                0, 0,
2171                0, 0,
2172                0, 0,
2173                0, 0,
2174                0, 0,
2175                0, 0,
2176                0, 0,
2177                GP_5_16_FN, FN_VI1_FIELD,
2178                GP_5_15_FN, FN_VI1_D11_G3_Y3,
2179                GP_5_14_FN, FN_VI1_D10_G2_Y2,
2180                GP_5_13_FN, FN_VI1_D9_G1_Y1,
2181                GP_5_12_FN, FN_VI1_D8_G0_Y0,
2182                GP_5_11_FN, FN_VI1_D7_B7_C7,
2183                GP_5_10_FN, FN_VI1_D6_B6_C6,
2184                GP_5_9_FN, FN_VI1_D5_B5_C5,
2185                GP_5_8_FN, FN_VI1_D4_B4_C4,
2186                GP_5_7_FN, FN_VI1_D3_B3_C3,
2187                GP_5_6_FN, FN_VI1_D2_B2_C2,
2188                GP_5_5_FN, FN_VI1_D1_B1_C1,
2189                GP_5_4_FN, FN_VI1_D0_B0_C0,
2190                GP_5_3_FN, FN_VI1_VSYNC_N,
2191                GP_5_2_FN, FN_VI1_HSYNC_N,
2192                GP_5_1_FN, FN_VI1_CLKENB,
2193                GP_5_0_FN, FN_VI1_CLK ))
2194        },
2195        { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
2196                0, 0,
2197                0, 0,
2198                0, 0,
2199                0, 0,
2200                0, 0,
2201                0, 0,
2202                0, 0,
2203                0, 0,
2204                0, 0,
2205                0, 0,
2206                0, 0,
2207                0, 0,
2208                0, 0,
2209                0, 0,
2210                0, 0,
2211                GP_6_16_FN, FN_IP2_16,
2212                GP_6_15_FN, FN_IP2_15,
2213                GP_6_14_FN, FN_IP2_14,
2214                GP_6_13_FN, FN_IP2_13,
2215                GP_6_12_FN, FN_IP2_12,
2216                GP_6_11_FN, FN_IP2_11,
2217                GP_6_10_FN, FN_IP2_10,
2218                GP_6_9_FN, FN_IP2_9,
2219                GP_6_8_FN, FN_IP2_8,
2220                GP_6_7_FN, FN_IP2_7,
2221                GP_6_6_FN, FN_IP2_6,
2222                GP_6_5_FN, FN_IP2_5,
2223                GP_6_4_FN, FN_IP2_4,
2224                GP_6_3_FN, FN_IP2_3,
2225                GP_6_2_FN, FN_IP2_2,
2226                GP_6_1_FN, FN_IP2_1,
2227                GP_6_0_FN, FN_IP2_0 ))
2228        },
2229        { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP(
2230                0, 0,
2231                0, 0,
2232                0, 0,
2233                0, 0,
2234                0, 0,
2235                0, 0,
2236                0, 0,
2237                0, 0,
2238                0, 0,
2239                0, 0,
2240                0, 0,
2241                0, 0,
2242                0, 0,
2243                0, 0,
2244                0, 0,
2245                GP_7_16_FN, FN_VI3_FIELD,
2246                GP_7_15_FN, FN_IP3_14,
2247                GP_7_14_FN, FN_VI3_D10_Y2,
2248                GP_7_13_FN, FN_IP3_13,
2249                GP_7_12_FN, FN_IP3_12,
2250                GP_7_11_FN, FN_IP3_11,
2251                GP_7_10_FN, FN_IP3_10,
2252                GP_7_9_FN, FN_IP3_9,
2253                GP_7_8_FN, FN_IP3_8,
2254                GP_7_7_FN, FN_IP3_7,
2255                GP_7_6_FN, FN_IP3_6,
2256                GP_7_5_FN, FN_IP3_5,
2257                GP_7_4_FN, FN_IP3_4,
2258                GP_7_3_FN, FN_IP3_3,
2259                GP_7_2_FN, FN_IP3_2,
2260                GP_7_1_FN, FN_IP3_1,
2261                GP_7_0_FN, FN_IP3_0 ))
2262        },
2263        { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP(
2264                0, 0,
2265                0, 0,
2266                0, 0,
2267                0, 0,
2268                0, 0,
2269                0, 0,
2270                0, 0,
2271                0, 0,
2272                0, 0,
2273                0, 0,
2274                0, 0,
2275                0, 0,
2276                0, 0,
2277                0, 0,
2278                0, 0,
2279                GP_8_16_FN, FN_IP4_24,
2280                GP_8_15_FN, FN_IP4_23,
2281                GP_8_14_FN, FN_IP4_22,
2282                GP_8_13_FN, FN_IP4_21,
2283                GP_8_12_FN, FN_IP4_20_19,
2284                GP_8_11_FN, FN_IP4_18_17,
2285                GP_8_10_FN, FN_IP4_16_15,
2286                GP_8_9_FN, FN_IP4_14_13,
2287                GP_8_8_FN, FN_IP4_12_11,
2288                GP_8_7_FN, FN_IP4_10_9,
2289                GP_8_6_FN, FN_IP4_8_7,
2290                GP_8_5_FN, FN_IP4_6_5,
2291                GP_8_4_FN, FN_IP4_4,
2292                GP_8_3_FN, FN_IP4_3_2,
2293                GP_8_2_FN, FN_IP4_1,
2294                GP_8_1_FN, FN_IP4_0,
2295                GP_8_0_FN, FN_VI4_CLK ))
2296        },
2297        { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP(
2298                0, 0,
2299                0, 0,
2300                0, 0,
2301                0, 0,
2302                0, 0,
2303                0, 0,
2304                0, 0,
2305                0, 0,
2306                0, 0,
2307                0, 0,
2308                0, 0,
2309                0, 0,
2310                0, 0,
2311                0, 0,
2312                0, 0,
2313                GP_9_16_FN, FN_VI5_FIELD,
2314                GP_9_15_FN, FN_VI5_D11_Y3,
2315                GP_9_14_FN, FN_VI5_D10_Y2,
2316                GP_9_13_FN, FN_VI5_D9_Y1,
2317                GP_9_12_FN, FN_IP5_11,
2318                GP_9_11_FN, FN_IP5_10,
2319                GP_9_10_FN, FN_IP5_9,
2320                GP_9_9_FN, FN_IP5_8,
2321                GP_9_8_FN, FN_IP5_7,
2322                GP_9_7_FN, FN_IP5_6,
2323                GP_9_6_FN, FN_IP5_5,
2324                GP_9_5_FN, FN_IP5_4,
2325                GP_9_4_FN, FN_IP5_3,
2326                GP_9_3_FN, FN_IP5_2,
2327                GP_9_2_FN, FN_IP5_1,
2328                GP_9_1_FN, FN_IP5_0,
2329                GP_9_0_FN, FN_VI5_CLK ))
2330        },
2331        { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP(
2332                GP_10_31_FN, FN_CAN1_RX,
2333                GP_10_30_FN, FN_CAN1_TX,
2334                GP_10_29_FN, FN_CAN_CLK,
2335                GP_10_28_FN, FN_CAN0_RX,
2336                GP_10_27_FN, FN_CAN0_TX,
2337                GP_10_26_FN, FN_SCIF_CLK,
2338                GP_10_25_FN, FN_IP6_18_17,
2339                GP_10_24_FN, FN_IP6_16,
2340                GP_10_23_FN, FN_IP6_15_14,
2341                GP_10_22_FN, FN_IP6_13_12,
2342                GP_10_21_FN, FN_IP6_11_10,
2343                GP_10_20_FN, FN_IP6_9_8,
2344                GP_10_19_FN, FN_RX1,
2345                GP_10_18_FN, FN_TX1,
2346                GP_10_17_FN, FN_RTS1_N,
2347                GP_10_16_FN, FN_CTS1_N,
2348                GP_10_15_FN, FN_SCK1,
2349                GP_10_14_FN, FN_RX0,
2350                GP_10_13_FN, FN_TX0,
2351                GP_10_12_FN, FN_RTS0_N,
2352                GP_10_11_FN, FN_CTS0_N,
2353                GP_10_10_FN, FN_SCK0,
2354                GP_10_9_FN, FN_IP6_7,
2355                GP_10_8_FN, FN_IP6_6,
2356                GP_10_7_FN, FN_HCTS1_N,
2357                GP_10_6_FN, FN_IP6_5,
2358                GP_10_5_FN, FN_IP6_4,
2359                GP_10_4_FN, FN_IP6_3,
2360                GP_10_3_FN, FN_IP6_2,
2361                GP_10_2_FN, FN_HRTS0_N,
2362                GP_10_1_FN, FN_IP6_1,
2363                GP_10_0_FN, FN_IP6_0 ))
2364        },
2365        { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP(
2366                0, 0,
2367                0, 0,
2368                GP_11_29_FN, FN_AVS2,
2369                GP_11_28_FN, FN_AVS1,
2370                GP_11_27_FN, FN_ADICHS2,
2371                GP_11_26_FN, FN_ADICHS1,
2372                GP_11_25_FN, FN_ADICHS0,
2373                GP_11_24_FN, FN_ADIDATA,
2374                GP_11_23_FN, FN_ADICS_SAMP,
2375                GP_11_22_FN, FN_ADICLK,
2376                GP_11_21_FN, FN_IP7_20,
2377                GP_11_20_FN, FN_IP7_19,
2378                GP_11_19_FN, FN_IP7_18,
2379                GP_11_18_FN, FN_IP7_17,
2380                GP_11_17_FN, FN_IP7_16,
2381                GP_11_16_FN, FN_IP7_15_14,
2382                GP_11_15_FN, FN_IP7_13_12,
2383                GP_11_14_FN, FN_IP7_11_10,
2384                GP_11_13_FN, FN_IP7_9_8,
2385                GP_11_12_FN, FN_SD0_WP,
2386                GP_11_11_FN, FN_SD0_CD,
2387                GP_11_10_FN, FN_SD0_DAT3,
2388                GP_11_9_FN, FN_SD0_DAT2,
2389                GP_11_8_FN, FN_SD0_DAT1,
2390                GP_11_7_FN, FN_SD0_DAT0,
2391                GP_11_6_FN, FN_SD0_CMD,
2392                GP_11_5_FN, FN_SD0_CLK,
2393                GP_11_4_FN, FN_IP7_7,
2394                GP_11_3_FN, FN_IP7_6,
2395                GP_11_2_FN, FN_IP7_5_4,
2396                GP_11_1_FN, FN_IP7_3_2,
2397                GP_11_0_FN, FN_IP7_1_0 ))
2398        },
2399        { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2400                             GROUP(4, 4,
2401                                   1, 1, 1, 1, 1, 1, 1, 1,
2402                                   1, 1, 1, 1, 1, 1, 1, 1,
2403                                   1, 1, 1, 1, 1, 1, 1, 1),
2404                             GROUP(
2405                /* IP0_31_28 [4] */
2406                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2407                /* IP0_27_24 [4] */
2408                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2409                /* IP0_23 [1] */
2410                FN_DU0_DB7_C5, 0,
2411                /* IP0_22 [1] */
2412                FN_DU0_DB6_C4, 0,
2413                /* IP0_21 [1] */
2414                FN_DU0_DB5_C3, 0,
2415                /* IP0_20 [1] */
2416                FN_DU0_DB4_C2, 0,
2417                /* IP0_19 [1] */
2418                FN_DU0_DB3_C1, 0,
2419                /* IP0_18 [1] */
2420                FN_DU0_DB2_C0, 0,
2421                /* IP0_17 [1] */
2422                FN_DU0_DB1, 0,
2423                /* IP0_16 [1] */
2424                FN_DU0_DB0, 0,
2425                /* IP0_15 [1] */
2426                FN_DU0_DG7_Y3_DATA15, 0,
2427                /* IP0_14 [1] */
2428                FN_DU0_DG6_Y2_DATA14, 0,
2429                /* IP0_13 [1] */
2430                FN_DU0_DG5_Y1_DATA13, 0,
2431                /* IP0_12 [1] */
2432                FN_DU0_DG4_Y0_DATA12, 0,
2433                /* IP0_11 [1] */
2434                FN_DU0_DG3_C7_DATA11, 0,
2435                /* IP0_10 [1] */
2436                FN_DU0_DG2_C6_DATA10, 0,
2437                /* IP0_9 [1] */
2438                FN_DU0_DG1_DATA9, 0,
2439                /* IP0_8 [1] */
2440                FN_DU0_DG0_DATA8, 0,
2441                /* IP0_7 [1] */
2442                FN_DU0_DR7_Y9_DATA7, 0,
2443                /* IP0_6 [1] */
2444                FN_DU0_DR6_Y8_DATA6, 0,
2445                /* IP0_5 [1] */
2446                FN_DU0_DR5_Y7_DATA5, 0,
2447                /* IP0_4 [1] */
2448                FN_DU0_DR4_Y6_DATA4, 0,
2449                /* IP0_3 [1] */
2450                FN_DU0_DR3_Y5_DATA3, 0,
2451                /* IP0_2 [1] */
2452                FN_DU0_DR2_Y4_DATA2, 0,
2453                /* IP0_1 [1] */
2454                FN_DU0_DR1_DATA1, 0,
2455                /* IP0_0 [1] */
2456                FN_DU0_DR0_DATA0, 0 ))
2457        },
2458        { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2459                             GROUP(4, 4,
2460                                   1, 1, 1, 1, 1, 1, 1, 1,
2461                                   1, 1, 1, 1, 1, 1, 1, 1,
2462                                   1, 1, 1, 1, 1, 1, 1, 1),
2463                             GROUP(
2464                /* IP1_31_28 [4] */
2465                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2466                /* IP1_27_24 [4] */
2467                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2468                /* IP1_23 [1] */
2469                0, 0,
2470                /* IP1_22 [1] */
2471                FN_A25, FN_SSL,
2472                /* IP1_21 [1] */
2473                FN_A24, FN_SPCLK,
2474                /* IP1_20 [1] */
2475                FN_A23, FN_IO3,
2476                /* IP1_19 [1] */
2477                FN_A22, FN_IO2,
2478                /* IP1_18 [1] */
2479                FN_A21, FN_MISO_IO1,
2480                /* IP1_17 [1] */
2481                FN_A20, FN_MOSI_IO0,
2482                /* IP1_16 [1] */
2483                FN_DU1_DG7_Y3_DATA11, 0,
2484                /* IP1_15 [1] */
2485                FN_DU1_DG6_Y2_DATA10, 0,
2486                /* IP1_14 [1] */
2487                FN_DU1_DG5_Y1_DATA9, 0,
2488                /* IP1_13 [1] */
2489                FN_DU1_DG4_Y0_DATA8, 0,
2490                /* IP1_12 [1] */
2491                FN_DU1_DG3_C7_DATA7, 0,
2492                /* IP1_11 [1] */
2493                FN_DU1_DG2_C6_DATA6, 0,
2494                /* IP1_10 [1] */
2495                FN_DU1_DR7_DATA5, 0,
2496                /* IP1_9 [1] */
2497                FN_DU1_DR6_DATA4, 0,
2498                /* IP1_8 [1] */
2499                FN_DU1_DR5_Y7_DATA3, 0,
2500                /* IP1_7 [1] */
2501                FN_DU1_DR4_Y6_DATA2, 0,
2502                /* IP1_6 [1] */
2503                FN_DU1_DR3_Y5_DATA1, 0,
2504                /* IP1_5 [1] */
2505                FN_DU1_DR2_Y4_DATA0, 0,
2506                /* IP1_4 [1] */
2507                FN_DU0_CDE, 0,
2508                /* IP1_3 [1] */
2509                FN_DU0_DISP, 0,
2510                /* IP1_2 [1] */
2511                FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
2512                /* IP1_1 [1] */
2513                FN_DU0_EXVSYNC_DU0_VSYNC, 0,
2514                /* IP1_0 [1] */
2515                FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))
2516        },
2517        { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2518                             GROUP(4, 4,
2519                                   4, 3, 1,
2520                                   1, 1, 1, 1, 1, 1, 1, 1,
2521                                   1, 1, 1, 1, 1, 1, 1, 1),
2522                             GROUP(
2523                /* IP2_31_28 [4] */
2524                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2525                /* IP2_27_24 [4] */
2526                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2527                /* IP2_23_20 [4] */
2528                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2529                /* IP2_19_17 [3] */
2530                0, 0, 0, 0, 0, 0, 0, 0,
2531                /* IP2_16 [1] */
2532                FN_VI2_FIELD, FN_AVB_TXD2,
2533                /* IP2_15 [1] */
2534                FN_VI2_D11_Y3, FN_AVB_TXD1,
2535                /* IP2_14 [1] */
2536                FN_VI2_D10_Y2, FN_AVB_TXD0,
2537                /* IP2_13 [1] */
2538                FN_VI2_D9_Y1, FN_AVB_TX_EN,
2539                /* IP2_12 [1] */
2540                FN_VI2_D8_Y0, FN_AVB_TXD3,
2541                /* IP2_11 [1] */
2542                FN_VI2_D7_C7, FN_AVB_COL,
2543                /* IP2_10 [1] */
2544                FN_VI2_D6_C6, FN_AVB_RX_ER,
2545                /* IP2_9 [1] */
2546                FN_VI2_D5_C5, FN_AVB_RXD7,
2547                /* IP2_8 [1] */
2548                FN_VI2_D4_C4, FN_AVB_RXD6,
2549                /* IP2_7 [1] */
2550                FN_VI2_D3_C3, FN_AVB_RXD5,
2551                /* IP2_6 [1] */
2552                FN_VI2_D2_C2, FN_AVB_RXD4,
2553                /* IP2_5 [1] */
2554                FN_VI2_D1_C1, FN_AVB_RXD3,
2555                /* IP2_4 [1] */
2556                FN_VI2_D0_C0, FN_AVB_RXD2,
2557                /* IP2_3 [1] */
2558                FN_VI2_VSYNC_N, FN_AVB_RXD1,
2559                /* IP2_2 [1] */
2560                FN_VI2_HSYNC_N, FN_AVB_RXD0,
2561                /* IP2_1 [1] */
2562                FN_VI2_CLKENB, FN_AVB_RX_DV,
2563                /* IP2_0 [1] */
2564                FN_VI2_CLK, FN_AVB_RX_CLK ))
2565        },
2566        { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2567                             GROUP(4, 4,
2568                                   4, 4,
2569                                   1, 1, 1, 1, 1, 1, 1, 1,
2570                                   1, 1, 1, 1, 1, 1, 1, 1),
2571                             GROUP(
2572                /* IP3_31_28 [4] */
2573                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2574                /* IP3_27_24 [4] */
2575                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2576                /* IP3_23_20 [4] */
2577                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2578                /* IP3_19_16 [4] */
2579                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2580                /* IP3_15 [1] */
2581                0, 0,
2582                /* IP3_14 [1] */
2583                FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
2584                /* IP3_13 [1] */
2585                FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
2586                /* IP3_12 [1] */
2587                FN_VI3_D8_Y0, FN_AVB_CRS,
2588                /* IP3_11 [1] */
2589                FN_VI3_D7_C7, FN_AVB_PHY_INT,
2590                /* IP3_10 [1] */
2591                FN_VI3_D6_C6, FN_AVB_MAGIC,
2592                /* IP3_9 [1] */
2593                FN_VI3_D5_C5, FN_AVB_LINK,
2594                /* IP3_8 [1] */
2595                FN_VI3_D4_C4, FN_AVB_MDIO,
2596                /* IP3_7 [1] */
2597                FN_VI3_D3_C3, FN_AVB_MDC,
2598                /* IP3_6 [1] */
2599                FN_VI3_D2_C2, FN_AVB_GTX_CLK,
2600                /* IP3_5 [1] */
2601                FN_VI3_D1_C1, FN_AVB_TX_ER,
2602                /* IP3_4 [1] */
2603                FN_VI3_D0_C0, FN_AVB_TXD7,
2604                /* IP3_3 [1] */
2605                FN_VI3_VSYNC_N, FN_AVB_TXD6,
2606                /* IP3_2 [1] */
2607                FN_VI3_HSYNC_N, FN_AVB_TXD5,
2608                /* IP3_1 [1] */
2609                FN_VI3_CLKENB, FN_AVB_TXD4,
2610                /* IP3_0 [1] */
2611                FN_VI3_CLK, FN_AVB_TX_CLK ))
2612        },
2613        { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2614                             GROUP(4, 3, 1,
2615                                   1, 1, 1, 2, 2, 2,
2616                                   2, 2, 2, 2, 2, 1, 2, 1, 1),
2617                             GROUP(
2618                /* IP4_31_28 [4] */
2619                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2620                /* IP4_27_25 [3] */
2621                0, 0, 0, 0, 0, 0, 0, 0,
2622                /* IP4_24 [1] */
2623                FN_VI4_FIELD, FN_VI3_D15_Y7,
2624                /* IP4_23 [1] */
2625                FN_VI4_D11_Y3, FN_VI3_D14_Y6,
2626                /* IP4_22 [1] */
2627                FN_VI4_D10_Y2, FN_VI3_D13_Y5,
2628                /* IP4_21 [1] */
2629                FN_VI4_D9_Y1, FN_VI3_D12_Y4,
2630                /* IP4_20_19 [2] */
2631                FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
2632                /* IP4_18_17 [2] */
2633                FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
2634                /* IP4_16_15 [2] */
2635                FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
2636                /* IP4_14_13 [2] */
2637                FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
2638                /* IP4_12_11 [2] */
2639                FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,
2640                /* IP4_10_9 [2] */
2641                FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,
2642                /* IP4_8_7 [2] */
2643                FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
2644                /* IP4_6_5 [2] */
2645                FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,
2646                /* IP4_4 [1] */
2647                FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
2648                /* IP4_3_2 [2] */
2649                FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,
2650                /* IP4_1 [1] */
2651                FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
2652                /* IP4_0 [1] */
2653                FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 ))
2654        },
2655        { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2656                             GROUP(4, 4,
2657                                   4, 4,
2658                                   4, 1, 1, 1, 1,
2659                                   1, 1, 1, 1, 1, 1, 1, 1),
2660                             GROUP(
2661                /* IP5_31_28 [4] */
2662                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2663                /* IP5_27_24 [4] */
2664                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2665                /* IP5_23_20 [4] */
2666                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2667                /* IP5_19_16 [4] */
2668                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2669                /* IP5_15_12 [4] */
2670                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2671                /* IP5_11 [1] */
2672                FN_VI5_D8_Y0, FN_VI1_D23_R7,
2673                /* IP5_10 [1] */
2674                FN_VI5_D7_C7, FN_VI1_D22_R6,
2675                /* IP5_9 [1] */
2676                FN_VI5_D6_C6, FN_VI1_D21_R5,
2677                /* IP5_8 [1] */
2678                FN_VI5_D5_C5, FN_VI1_D20_R4,
2679                /* IP5_7 [1] */
2680                FN_VI5_D4_C4, FN_VI1_D19_R3,
2681                /* IP5_6 [1] */
2682                FN_VI5_D3_C3, FN_VI1_D18_R2,
2683                /* IP5_5 [1] */
2684                FN_VI5_D2_C2, FN_VI1_D17_R1,
2685                /* IP5_4 [1] */
2686                FN_VI5_D1_C1, FN_VI1_D16_R0,
2687                /* IP5_3 [1] */
2688                FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
2689                /* IP5_2 [1] */
2690                FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B,
2691                /* IP5_1 [1] */
2692                FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
2693                /* IP5_0 [1] */
2694                FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B ))
2695        },
2696        { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2697                             GROUP(4, 4,
2698                                   4, 1, 2, 1,
2699                                   2, 2, 2, 2,
2700                                   1, 1, 1, 1, 1, 1, 1, 1),
2701                             GROUP(
2702                /* IP6_31_28 [4] */
2703                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2704                /* IP6_27_24 [4] */
2705                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2706                /* IP6_23_20 [4] */
2707                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2708                /* IP6_19 [1] */
2709                0, 0,
2710                /* IP6_18_17 [2] */
2711                FN_DREQ1_N, FN_RX3, 0, 0,
2712                /* IP6_16 [1] */
2713                FN_TX3, 0,
2714                /* IP6_15_14 [2] */
2715                FN_DACK1, FN_SCK3, 0, 0,
2716                /* IP6_13_12 [2] */
2717                FN_DREQ0_N, FN_RX2, 0, 0,
2718                /* IP6_11_10 [2] */
2719                FN_DACK0, FN_TX2, 0, 0,
2720                /* IP6_9_8 [2] */
2721                FN_DRACK0, FN_SCK2, 0, 0,
2722                /* IP6_7 [1] */
2723                FN_MSIOF1_RXD, FN_HRX1,
2724                /* IP6_6 [1] */
2725                FN_MSIOF1_TXD, FN_HTX1,
2726                /* IP6_5 [1] */
2727                FN_MSIOF1_SYNC, FN_HRTS1_N,
2728                /* IP6_4 [1] */
2729                FN_MSIOF1_SCK, FN_HSCK1,
2730                /* IP6_3 [1] */
2731                FN_MSIOF0_RXD, FN_HRX0,
2732                /* IP6_2 [1] */
2733                FN_MSIOF0_TXD, FN_HTX0,
2734                /* IP6_1 [1] */
2735                FN_MSIOF0_SYNC, FN_HCTS0_N,
2736                /* IP6_0 [1] */
2737                FN_MSIOF0_SCK, FN_HSCK0 ))
2738        },
2739        { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2740                             GROUP(4, 4,
2741                                   3, 1, 1, 1, 1, 1,
2742                                   2, 2, 2, 2,
2743                                   1, 1, 2, 2, 2),
2744                             GROUP(
2745                /* IP7_31_28 [4] */
2746                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2747                /* IP7_27_24 [4] */
2748                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2749                /* IP7_23_21 [3] */
2750                0, 0, 0, 0, 0, 0, 0, 0,
2751                /* IP7_20 [1] */
2752                FN_AUDIO_CLKB, 0,
2753                /* IP7_19 [1] */
2754                FN_AUDIO_CLKA, 0,
2755                /* IP7_18 [1] */
2756                FN_AUDIO_CLKOUT, 0,
2757                /* IP7_17 [1] */
2758                FN_SSI_SDATA4, 0,
2759                /* IP7_16 [1] */
2760                FN_SSI_WS4, 0,
2761                /* IP7_15_14 [2] */
2762                FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
2763                /* IP7_13_12 [2] */
2764                FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
2765                /* IP7_11_10 [2] */
2766                FN_SSI_WS34, FN_TPU0TO1, 0, 0,
2767                /* IP7_9_8 [2] */
2768                FN_SSI_SCK34, FN_TPU0TO0, 0, 0,
2769                /* IP7_7 [1] */
2770                FN_PWM4, 0,
2771                /* IP7_6 [1] */
2772                FN_PWM3, 0,
2773                /* IP7_5_4 [2] */
2774                FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
2775                /* IP7_3_2 [2] */
2776                FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
2777                /* IP7_1_0 [2] */
2778                FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
2779        },
2780        { },
2781};
2782
2783const struct sh_pfc_soc_info r8a7792_pinmux_info = {
2784        .name = "r8a77920_pfc",
2785        .unlock_reg = 0xe6060000, /* PMMR */
2786
2787        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2788
2789        .pins = pinmux_pins,
2790        .nr_pins = ARRAY_SIZE(pinmux_pins),
2791        .groups = pinmux_groups,
2792        .nr_groups = ARRAY_SIZE(pinmux_groups),
2793        .functions = pinmux_functions,
2794        .nr_functions = ARRAY_SIZE(pinmux_functions),
2795
2796        .cfg_regs = pinmux_config_regs,
2797
2798        .pinmux_data = pinmux_data,
2799        .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2800};
2801