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15#include <linux/errno.h>
16#include <linux/kernel.h>
17
18#include "core.h"
19#include "sh_pfc.h"
20
21#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
22
23#define CPU_ALL_GP(fn, sfx) \
24 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
28 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
33 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
36
37#define CPU_ALL_NOGP(fn) \
38 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
39 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
57 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
70 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
71 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
72 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
73 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
74 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
75 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
76 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
77 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
78 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
79 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
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86
87#define GPSR0_15 F_(D15, IP7_11_8)
88#define GPSR0_14 F_(D14, IP7_7_4)
89#define GPSR0_13 F_(D13, IP7_3_0)
90#define GPSR0_12 F_(D12, IP6_31_28)
91#define GPSR0_11 F_(D11, IP6_27_24)
92#define GPSR0_10 F_(D10, IP6_23_20)
93#define GPSR0_9 F_(D9, IP6_19_16)
94#define GPSR0_8 F_(D8, IP6_15_12)
95#define GPSR0_7 F_(D7, IP6_11_8)
96#define GPSR0_6 F_(D6, IP6_7_4)
97#define GPSR0_5 F_(D5, IP6_3_0)
98#define GPSR0_4 F_(D4, IP5_31_28)
99#define GPSR0_3 F_(D3, IP5_27_24)
100#define GPSR0_2 F_(D2, IP5_23_20)
101#define GPSR0_1 F_(D1, IP5_19_16)
102#define GPSR0_0 F_(D0, IP5_15_12)
103
104
105#define GPSR1_28 FM(CLKOUT)
106#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
107#define GPSR1_26 F_(WE1_N, IP5_7_4)
108#define GPSR1_25 F_(WE0_N, IP5_3_0)
109#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
110#define GPSR1_23 F_(RD_N, IP4_27_24)
111#define GPSR1_22 F_(BS_N, IP4_23_20)
112#define GPSR1_21 F_(CS1_N, IP4_19_16)
113#define GPSR1_20 F_(CS0_N, IP4_15_12)
114#define GPSR1_19 F_(A19, IP4_11_8)
115#define GPSR1_18 F_(A18, IP4_7_4)
116#define GPSR1_17 F_(A17, IP4_3_0)
117#define GPSR1_16 F_(A16, IP3_31_28)
118#define GPSR1_15 F_(A15, IP3_27_24)
119#define GPSR1_14 F_(A14, IP3_23_20)
120#define GPSR1_13 F_(A13, IP3_19_16)
121#define GPSR1_12 F_(A12, IP3_15_12)
122#define GPSR1_11 F_(A11, IP3_11_8)
123#define GPSR1_10 F_(A10, IP3_7_4)
124#define GPSR1_9 F_(A9, IP3_3_0)
125#define GPSR1_8 F_(A8, IP2_31_28)
126#define GPSR1_7 F_(A7, IP2_27_24)
127#define GPSR1_6 F_(A6, IP2_23_20)
128#define GPSR1_5 F_(A5, IP2_19_16)
129#define GPSR1_4 F_(A4, IP2_15_12)
130#define GPSR1_3 F_(A3, IP2_11_8)
131#define GPSR1_2 F_(A2, IP2_7_4)
132#define GPSR1_1 F_(A1, IP2_3_0)
133#define GPSR1_0 F_(A0, IP1_31_28)
134
135
136#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
137#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
138#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
139#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
140#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
141#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
142#define GPSR2_8 F_(PWM2_A, IP1_27_24)
143#define GPSR2_7 F_(PWM1_A, IP1_23_20)
144#define GPSR2_6 F_(PWM0, IP1_19_16)
145#define GPSR2_5 F_(IRQ5, IP1_15_12)
146#define GPSR2_4 F_(IRQ4, IP1_11_8)
147#define GPSR2_3 F_(IRQ3, IP1_7_4)
148#define GPSR2_2 F_(IRQ2, IP1_3_0)
149#define GPSR2_1 F_(IRQ1, IP0_31_28)
150#define GPSR2_0 F_(IRQ0, IP0_27_24)
151
152
153#define GPSR3_15 F_(SD1_WP, IP11_23_20)
154#define GPSR3_14 F_(SD1_CD, IP11_19_16)
155#define GPSR3_13 F_(SD0_WP, IP11_15_12)
156#define GPSR3_12 F_(SD0_CD, IP11_11_8)
157#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
158#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
159#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
160#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
161#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
162#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
163#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
164#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
165#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
166#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
167#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
168#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
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170
171#define GPSR4_17 F_(SD3_DS, IP11_7_4)
172#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
173#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
174#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
175#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
176#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
177#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
178#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
179#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
180#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
181#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
182#define GPSR4_6 F_(SD2_DS, IP9_27_24)
183#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
184#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
185#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
186#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
187#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
188#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
189
190
191#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
192#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
193#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
194#define GPSR5_22 FM(MSIOF0_RXD)
195#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
196#define GPSR5_20 FM(MSIOF0_TXD)
197#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
198#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
199#define GPSR5_17 FM(MSIOF0_SCK)
200#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
201#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
202#define GPSR5_14 F_(HTX0, IP13_19_16)
203#define GPSR5_13 F_(HRX0, IP13_15_12)
204#define GPSR5_12 F_(HSCK0, IP13_11_8)
205#define GPSR5_11 F_(RX2_A, IP13_7_4)
206#define GPSR5_10 F_(TX2_A, IP13_3_0)
207#define GPSR5_9 F_(SCK2, IP12_31_28)
208#define GPSR5_8 F_(RTS1_N, IP12_27_24)
209#define GPSR5_7 F_(CTS1_N, IP12_23_20)
210#define GPSR5_6 F_(TX1_A, IP12_19_16)
211#define GPSR5_5 F_(RX1_A, IP12_15_12)
212#define GPSR5_4 F_(RTS0_N, IP12_11_8)
213#define GPSR5_3 F_(CTS0_N, IP12_7_4)
214#define GPSR5_2 F_(TX0, IP12_3_0)
215#define GPSR5_1 F_(RX0, IP11_31_28)
216#define GPSR5_0 F_(SCK0, IP11_27_24)
217
218
219#define GPSR6_31 F_(GP6_31, IP18_7_4)
220#define GPSR6_30 F_(GP6_30, IP18_3_0)
221#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
222#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
223#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
224#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
225#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
226#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
227#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
228#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
229#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
230#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
231#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
232#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
233#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
234#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
235#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
236#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
237#define GPSR6_13 FM(SSI_SDATA5)
238#define GPSR6_12 FM(SSI_WS5)
239#define GPSR6_11 FM(SSI_SCK5)
240#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
241#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
242#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
243#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
244#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
245#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
246#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
247#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
248#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
249#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
250#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
251
252
253#define GPSR7_3 FM(GP7_03)
254#define GPSR7_2 FM(GP7_02)
255#define GPSR7_1 FM(AVS2)
256#define GPSR7_0 FM(AVS1)
257
258
259
260#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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289#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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319
320#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354
355
356#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
377#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384
385
386#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
405#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
406#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
407#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
408#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
409#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
410#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
411#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
412#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
413
414#define PINMUX_GPSR \
415\
416 GPSR6_31 \
417 GPSR6_30 \
418 GPSR6_29 \
419 GPSR1_28 GPSR6_28 \
420 GPSR1_27 GPSR6_27 \
421 GPSR1_26 GPSR6_26 \
422 GPSR1_25 GPSR5_25 GPSR6_25 \
423 GPSR1_24 GPSR5_24 GPSR6_24 \
424 GPSR1_23 GPSR5_23 GPSR6_23 \
425 GPSR1_22 GPSR5_22 GPSR6_22 \
426 GPSR1_21 GPSR5_21 GPSR6_21 \
427 GPSR1_20 GPSR5_20 GPSR6_20 \
428 GPSR1_19 GPSR5_19 GPSR6_19 \
429 GPSR1_18 GPSR5_18 GPSR6_18 \
430 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
431 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
432GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
433GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
434GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
435GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
436GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
437GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
438GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
439GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
440GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
441GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
442GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
443GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
444GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
445GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
446GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
447GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
448
449#define PINMUX_IPSR \
450\
451FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
452FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
453FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
454FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
455FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
456FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
457FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
458FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
459\
460FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
461FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
462FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
463FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
464FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
465FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
466FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
467FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
468\
469FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
470FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
471FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
472FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
473FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
474FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
475FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
476FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
477\
478FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
479FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
480FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
481FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
482FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
483FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
484FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
485FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
486\
487FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
488FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
489FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
490FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
491FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
492FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
493FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
494FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
495
496
497#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
498#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
499#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
500#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
501#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
502#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
503#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
504#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
505#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
506#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
507#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
508#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
509#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
510#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
511#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
512#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
513#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
514#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
515
516
517#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
518#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
519#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
520#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
521#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
522#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
523#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
524#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
525#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
526#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
527#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
528#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
529#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
530#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
531#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
532#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
533#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
534#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
535#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
536#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
537#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
538#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
539
540
541#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
542#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
543#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
544#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
545#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
546#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
547#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
548#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
549#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
550#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
551#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
552#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
553#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
554
555#define PINMUX_MOD_SELS \
556\
557MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
558 MOD_SEL2_30 \
559 MOD_SEL1_29_28_27 MOD_SEL2_29 \
560MOD_SEL0_28_27 MOD_SEL2_28_27 \
561MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
562 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
563MOD_SEL0_23 MOD_SEL1_23_22_21 \
564MOD_SEL0_22 MOD_SEL2_22 \
565MOD_SEL0_21 MOD_SEL2_21 \
566MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
567MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
568MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
569 MOD_SEL2_17 \
570MOD_SEL0_16 MOD_SEL1_16 \
571 MOD_SEL1_15_14 \
572MOD_SEL0_14_13 \
573 MOD_SEL1_13 \
574MOD_SEL0_12 MOD_SEL1_12 \
575MOD_SEL0_11 MOD_SEL1_11 \
576MOD_SEL0_10 MOD_SEL1_10 \
577MOD_SEL0_9_8 MOD_SEL1_9 \
578MOD_SEL0_7_6 \
579 MOD_SEL1_6 \
580MOD_SEL0_5 MOD_SEL1_5 \
581MOD_SEL0_4_3 MOD_SEL1_4 \
582 MOD_SEL1_3 \
583 MOD_SEL1_2 \
584 MOD_SEL1_1 \
585 MOD_SEL1_0 MOD_SEL2_0
586
587
588
589
590
591#define PINMUX_STATIC \
592 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
593 FM(QSPI0_IO2) FM(QSPI0_IO3) \
594 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
595 FM(QSPI1_IO2) FM(QSPI1_IO3) \
596 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
597 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
598 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
599 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
600 FM(PRESETOUT) \
601 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
602 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
603
604#define PINMUX_PHYS \
605 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
606
607enum {
608 PINMUX_RESERVED = 0,
609
610 PINMUX_DATA_BEGIN,
611 GP_ALL(DATA),
612 PINMUX_DATA_END,
613
614#define F_(x, y)
615#define FM(x) FN_##x,
616 PINMUX_FUNCTION_BEGIN,
617 GP_ALL(FN),
618 PINMUX_GPSR
619 PINMUX_IPSR
620 PINMUX_MOD_SELS
621 PINMUX_FUNCTION_END,
622#undef F_
623#undef FM
624
625#define F_(x, y)
626#define FM(x) x##_MARK,
627 PINMUX_MARK_BEGIN,
628 PINMUX_GPSR
629 PINMUX_IPSR
630 PINMUX_MOD_SELS
631 PINMUX_STATIC
632 PINMUX_PHYS
633 PINMUX_MARK_END,
634#undef F_
635#undef FM
636};
637
638static const u16 pinmux_data[] = {
639 PINMUX_DATA_GP_ALL(),
640
641 PINMUX_SINGLE(AVS1),
642 PINMUX_SINGLE(AVS2),
643 PINMUX_SINGLE(CLKOUT),
644 PINMUX_SINGLE(GP7_03),
645 PINMUX_SINGLE(GP7_02),
646 PINMUX_SINGLE(MSIOF0_RXD),
647 PINMUX_SINGLE(MSIOF0_SCK),
648 PINMUX_SINGLE(MSIOF0_TXD),
649 PINMUX_SINGLE(SSI_SCK5),
650 PINMUX_SINGLE(SSI_SDATA5),
651 PINMUX_SINGLE(SSI_WS5),
652
653
654 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
655 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
656
657 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
658 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
659 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
660
661 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
662 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
663 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
664
665 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
666 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
667 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
668 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
669
670 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
671 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
672 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
673 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
674
675 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
676 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
677 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
678 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
679
680 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
681 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
682 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
683 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
684 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
685 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
686 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
687
688 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
689 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
690 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
691 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
692 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
693 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
694 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
695
696
697 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
698 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
699 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
700 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
701 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
702 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
703
704 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
705 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
706 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
707 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
708 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
709 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
710
711 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
712 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
713 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
714 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
715 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
716 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
717
718 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
719 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
720 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
721 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
722 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
723 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
724 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
725
726 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
727 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
728 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
729 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
730
731 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
732 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
733 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
734 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
735 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
736
737 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
738 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
739 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
740 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
741
742 PINMUX_IPSR_GPSR(IP1_31_28, A0),
743 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
744 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
745 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
746 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
747 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
748
749
750 PINMUX_IPSR_GPSR(IP2_3_0, A1),
751 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
752 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
753 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
754 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
755 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
756
757 PINMUX_IPSR_GPSR(IP2_7_4, A2),
758 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
759 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
760 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
761 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
762 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
763
764 PINMUX_IPSR_GPSR(IP2_11_8, A3),
765 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
766 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
767 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
768 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
769 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
770
771 PINMUX_IPSR_GPSR(IP2_15_12, A4),
772 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
773 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
774 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
775 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
776 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
777
778 PINMUX_IPSR_GPSR(IP2_19_16, A5),
779 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
780 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
781 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
782 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
783 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
784 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
785
786 PINMUX_IPSR_GPSR(IP2_23_20, A6),
787 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
788 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
789 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
790 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
791 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
792 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
793
794 PINMUX_IPSR_GPSR(IP2_27_24, A7),
795 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
796 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
797 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
798 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
799 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
800 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
801
802 PINMUX_IPSR_GPSR(IP2_31_28, A8),
803 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
804 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
805 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
806 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
807 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
808 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
809
810
811 PINMUX_IPSR_GPSR(IP3_3_0, A9),
812 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
813 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
814 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
815
816 PINMUX_IPSR_GPSR(IP3_7_4, A10),
817 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
818 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
819 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
820
821 PINMUX_IPSR_GPSR(IP3_11_8, A11),
822 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
823 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
824 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
825 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
826 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
827 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
828 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
829 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
830
831 PINMUX_IPSR_GPSR(IP3_15_12, A12),
832 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
833 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
834 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
835 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
836 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
837
838 PINMUX_IPSR_GPSR(IP3_19_16, A13),
839 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
840 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
841 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
842 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
843 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
844
845 PINMUX_IPSR_GPSR(IP3_23_20, A14),
846 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
847 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
848 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
849 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
850 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
851
852 PINMUX_IPSR_GPSR(IP3_27_24, A15),
853 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
854 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
855 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
856 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
857 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
858
859 PINMUX_IPSR_GPSR(IP3_31_28, A16),
860 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
861 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
862 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
863
864
865 PINMUX_IPSR_GPSR(IP4_3_0, A17),
866 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
867 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
868 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
869
870 PINMUX_IPSR_GPSR(IP4_7_4, A18),
871 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
872 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
873 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
874
875 PINMUX_IPSR_GPSR(IP4_11_8, A19),
876 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
877 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
878 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
879
880 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
881 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
882
883 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
884 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
885 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
886
887 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
888 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
889 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
890 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
891 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
892 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
893 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
894 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
895
896 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
897 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
898 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
899 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
900 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
901 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
902
903 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
904 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
905 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
906 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
907 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
908 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
909
910
911 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
912 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
913 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
914 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
915 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
916 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
917 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
918
919 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
920 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
921 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
922 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
923 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
924 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
925 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
926 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
927
928 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
929 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
930 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
931 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
932
933 PINMUX_IPSR_GPSR(IP5_15_12, D0),
934 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
935 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
936 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
937 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
938
939 PINMUX_IPSR_GPSR(IP5_19_16, D1),
940 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
941 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
942 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
943 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
944
945 PINMUX_IPSR_GPSR(IP5_23_20, D2),
946 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
947 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
948 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
949
950 PINMUX_IPSR_GPSR(IP5_27_24, D3),
951 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
952 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
953 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
954
955 PINMUX_IPSR_GPSR(IP5_31_28, D4),
956 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
957 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
958 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
959
960
961 PINMUX_IPSR_GPSR(IP6_3_0, D5),
962 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
963 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
964 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
965
966 PINMUX_IPSR_GPSR(IP6_7_4, D6),
967 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
968 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
969 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
970
971 PINMUX_IPSR_GPSR(IP6_11_8, D7),
972 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
973 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
974 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
975
976 PINMUX_IPSR_GPSR(IP6_15_12, D8),
977 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
978 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
979 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
980 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
981 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
982
983 PINMUX_IPSR_GPSR(IP6_19_16, D9),
984 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
985 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
986 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
987 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
988
989 PINMUX_IPSR_GPSR(IP6_23_20, D10),
990 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
991 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
992 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
993 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
994 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
995 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
996
997 PINMUX_IPSR_GPSR(IP6_27_24, D11),
998 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
999 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
1000 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
1001 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
1002 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
1003 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
1004
1005 PINMUX_IPSR_GPSR(IP6_31_28, D12),
1006 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
1007 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
1008 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
1009 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
1010 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1011
1012
1013 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1014 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1015 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1016 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1017 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1018 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1019
1020 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1021 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1022 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1023 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1024 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1025 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1026 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1027
1028 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1029 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1030 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1031 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1032 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1033 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1034 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1035
1036 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1037 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1038 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1039
1040 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1041 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1042 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1043
1044 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1045 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1046 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1047 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1048
1049 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1050 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1051 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1052 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1053
1054
1055 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1056 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1057 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1058 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1059
1060 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1061 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1062 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1063 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1064
1065 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1066 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1067 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1068
1069 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1070 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1071 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
1072 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1073 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1074
1075 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1076 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1077 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1078 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
1079 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1080 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1081
1082 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1083 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1084 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1085 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1086 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1087 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1088
1089 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1090 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1091 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1092 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1093 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1094 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1095
1096 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1097 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1098 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1099 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
1100 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1101 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1102
1103
1104 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1105 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1106
1107 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1108 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1109
1110 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1111 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1112
1113 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1114 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1115
1116 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1117 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1118
1119 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1120 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1121
1122 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1123 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1124 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1125
1126 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1127 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1128
1129
1130 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1131 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1132
1133 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1134 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1135
1136 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1137 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1138
1139 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1140 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1141
1142 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1143 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1144
1145 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1146 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1147 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1148
1149 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1150 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1151 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1152
1153 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1154 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1155 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1156
1157
1158 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1159 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1160 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1161
1162 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1163 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1164
1165 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1166 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
1167 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1168 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1169
1170 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1171 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
1172 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1173
1174 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1175 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
1176 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1177 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
1178
1179 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1180 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
1181 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1182 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
1183
1184 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1185 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1186 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1187 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
1188 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1189 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1190 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1191 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1192 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1193 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1194
1195 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1196 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1197 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1198 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1199 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1200
1201
1202 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1203 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1204 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1205 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1206 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1207
1208 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1209 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1210 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1211 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1212 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1213 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1214 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1215 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1216
1217 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1218 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1219 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1220 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
1221 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1222 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1223 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1224 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1225
1226 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1227 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1228 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1229 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1230 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1231
1232 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1233 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1234 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1235 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1236 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1237
1238 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1239 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1240 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1241 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1242 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1243 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1244 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1245
1246 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1247 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1248 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1249 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1250 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1251 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1252 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1253
1254 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1255 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1256 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1257 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1258 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1259 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1260 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1261
1262
1263 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1264 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1265 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1266 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1267 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1268 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1269
1270 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1271 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1272 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1273 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1274 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1275 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1276
1277 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1278 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1279 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
1280 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1281 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1282 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1283 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1284 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1285
1286 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1287 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1288 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1289 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1290 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1291 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1292
1293 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1294 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1295 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1296 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1297 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1298 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1299
1300 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1301 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1302 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1303 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1304 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1305 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1306 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1307 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1308
1309 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1310 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1311 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1312 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1313 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1314 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1315 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1316
1317 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1318 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1319 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1320 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1321
1322
1323 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1324 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1325 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1326 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
1327 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1328 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1329 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1330 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1331
1332 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1333 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1334 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1335 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
1336 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1337 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1338 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1339 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1340
1341 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1342 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1343 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1344
1345 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1346 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1347 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1348 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1349
1350 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1351 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1352 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1353
1354 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1355 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1356
1357 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1358 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1359
1360 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1361 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1362
1363
1364 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1365
1366 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1367 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1368
1369 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1370 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1371 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1372
1373 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1374 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1375 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1376 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1377
1378 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1379 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1380 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1381 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1382 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1383 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1384 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1385
1386 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1387 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1388 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1389 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1390 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1391 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1392 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1393
1394 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1395 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1396 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1397 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1398 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1399 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1400 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1401
1402 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1403 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1404 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1405 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1406 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1407 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1408 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1409
1410
1411 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1412 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1413
1414 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1415 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1416
1417 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1418 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1419 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1420
1421 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1422 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1423 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1424 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1425 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1426 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1427 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1428
1429 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1430 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1431 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1432 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1433 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1434 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1435 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1436
1437 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1438 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1439 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1440 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1441 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1442 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1443 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1444 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1445
1446 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1447 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1448 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1449 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1450 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1451 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1452 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1453
1454 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1455 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1456 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1457 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1458 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1459 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1460 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1461 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1462
1463
1464 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
1465
1466 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
1467 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1468 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1469 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1470 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1471
1472 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1473 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1474 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1475 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1476 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1477 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1478 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1479
1480 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1481 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1482 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1483 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1484 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1485 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1486
1487 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1488 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1489 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1490 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1491 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1492 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1493 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1494 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1495 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1496
1497 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1498 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1499 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1500 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1501 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1502 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1503 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1504 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1505 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1506
1507 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1508 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1509 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1510 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1511 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1512 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1513 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1514 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1515 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1516 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1517 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1518
1519 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1520 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1521 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1522 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1523 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1524 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1525 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1526 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1527 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1528
1529
1530 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1531 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1532 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1533 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1534 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1535 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1536 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1537 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1538 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1539
1540 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1541 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1542 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1543 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1544 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1545 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1546 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1547 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1548 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1549
1550
1551
1552
1553
1554
1555
1556
1557#define FM(x) PINMUX_DATA(x##_MARK, 0),
1558 PINMUX_STATIC
1559#undef FM
1560};
1561
1562
1563
1564
1565enum {
1566 GP_ASSIGN_LAST(),
1567 NOGP_ALL(),
1568};
1569
1570static const struct sh_pfc_pin pinmux_pins[] = {
1571 PINMUX_GPIO_GP_ALL(),
1572 PINMUX_NOGP_ALL(),
1573};
1574
1575
1576static const unsigned int audio_clk_a_a_pins[] = {
1577
1578 RCAR_GP_PIN(6, 22),
1579};
1580static const unsigned int audio_clk_a_a_mux[] = {
1581 AUDIO_CLKA_A_MARK,
1582};
1583static const unsigned int audio_clk_a_b_pins[] = {
1584
1585 RCAR_GP_PIN(5, 4),
1586};
1587static const unsigned int audio_clk_a_b_mux[] = {
1588 AUDIO_CLKA_B_MARK,
1589};
1590static const unsigned int audio_clk_a_c_pins[] = {
1591
1592 RCAR_GP_PIN(5, 19),
1593};
1594static const unsigned int audio_clk_a_c_mux[] = {
1595 AUDIO_CLKA_C_MARK,
1596};
1597static const unsigned int audio_clk_b_a_pins[] = {
1598
1599 RCAR_GP_PIN(5, 12),
1600};
1601static const unsigned int audio_clk_b_a_mux[] = {
1602 AUDIO_CLKB_A_MARK,
1603};
1604static const unsigned int audio_clk_b_b_pins[] = {
1605
1606 RCAR_GP_PIN(6, 23),
1607};
1608static const unsigned int audio_clk_b_b_mux[] = {
1609 AUDIO_CLKB_B_MARK,
1610};
1611static const unsigned int audio_clk_c_a_pins[] = {
1612
1613 RCAR_GP_PIN(5, 21),
1614};
1615static const unsigned int audio_clk_c_a_mux[] = {
1616 AUDIO_CLKC_A_MARK,
1617};
1618static const unsigned int audio_clk_c_b_pins[] = {
1619
1620 RCAR_GP_PIN(5, 0),
1621};
1622static const unsigned int audio_clk_c_b_mux[] = {
1623 AUDIO_CLKC_B_MARK,
1624};
1625static const unsigned int audio_clkout_a_pins[] = {
1626
1627 RCAR_GP_PIN(5, 18),
1628};
1629static const unsigned int audio_clkout_a_mux[] = {
1630 AUDIO_CLKOUT_A_MARK,
1631};
1632static const unsigned int audio_clkout_b_pins[] = {
1633
1634 RCAR_GP_PIN(6, 28),
1635};
1636static const unsigned int audio_clkout_b_mux[] = {
1637 AUDIO_CLKOUT_B_MARK,
1638};
1639static const unsigned int audio_clkout_c_pins[] = {
1640
1641 RCAR_GP_PIN(5, 3),
1642};
1643static const unsigned int audio_clkout_c_mux[] = {
1644 AUDIO_CLKOUT_C_MARK,
1645};
1646static const unsigned int audio_clkout_d_pins[] = {
1647
1648 RCAR_GP_PIN(5, 21),
1649};
1650static const unsigned int audio_clkout_d_mux[] = {
1651 AUDIO_CLKOUT_D_MARK,
1652};
1653static const unsigned int audio_clkout1_a_pins[] = {
1654
1655 RCAR_GP_PIN(5, 15),
1656};
1657static const unsigned int audio_clkout1_a_mux[] = {
1658 AUDIO_CLKOUT1_A_MARK,
1659};
1660static const unsigned int audio_clkout1_b_pins[] = {
1661
1662 RCAR_GP_PIN(6, 29),
1663};
1664static const unsigned int audio_clkout1_b_mux[] = {
1665 AUDIO_CLKOUT1_B_MARK,
1666};
1667static const unsigned int audio_clkout2_a_pins[] = {
1668
1669 RCAR_GP_PIN(5, 16),
1670};
1671static const unsigned int audio_clkout2_a_mux[] = {
1672 AUDIO_CLKOUT2_A_MARK,
1673};
1674static const unsigned int audio_clkout2_b_pins[] = {
1675
1676 RCAR_GP_PIN(6, 30),
1677};
1678static const unsigned int audio_clkout2_b_mux[] = {
1679 AUDIO_CLKOUT2_B_MARK,
1680};
1681
1682static const unsigned int audio_clkout3_a_pins[] = {
1683
1684 RCAR_GP_PIN(5, 19),
1685};
1686static const unsigned int audio_clkout3_a_mux[] = {
1687 AUDIO_CLKOUT3_A_MARK,
1688};
1689static const unsigned int audio_clkout3_b_pins[] = {
1690
1691 RCAR_GP_PIN(6, 31),
1692};
1693static const unsigned int audio_clkout3_b_mux[] = {
1694 AUDIO_CLKOUT3_B_MARK,
1695};
1696
1697
1698static const unsigned int avb_link_pins[] = {
1699
1700 RCAR_GP_PIN(2, 12),
1701};
1702static const unsigned int avb_link_mux[] = {
1703 AVB_LINK_MARK,
1704};
1705static const unsigned int avb_magic_pins[] = {
1706
1707 RCAR_GP_PIN(2, 10),
1708};
1709static const unsigned int avb_magic_mux[] = {
1710 AVB_MAGIC_MARK,
1711};
1712static const unsigned int avb_phy_int_pins[] = {
1713
1714 RCAR_GP_PIN(2, 11),
1715};
1716static const unsigned int avb_phy_int_mux[] = {
1717 AVB_PHY_INT_MARK,
1718};
1719static const unsigned int avb_mdio_pins[] = {
1720
1721 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1722};
1723static const unsigned int avb_mdio_mux[] = {
1724 AVB_MDC_MARK, AVB_MDIO_MARK,
1725};
1726static const unsigned int avb_mii_pins[] = {
1727
1728
1729
1730
1731
1732
1733
1734 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1735 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1736 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1737 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1738 PIN_AVB_TXCREFCLK,
1739
1740};
1741static const unsigned int avb_mii_mux[] = {
1742 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1743 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1744 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1745 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1746 AVB_TXCREFCLK_MARK,
1747};
1748static const unsigned int avb_avtp_pps_pins[] = {
1749
1750 RCAR_GP_PIN(2, 6),
1751};
1752static const unsigned int avb_avtp_pps_mux[] = {
1753 AVB_AVTP_PPS_MARK,
1754};
1755static const unsigned int avb_avtp_match_a_pins[] = {
1756
1757 RCAR_GP_PIN(2, 13),
1758};
1759static const unsigned int avb_avtp_match_a_mux[] = {
1760 AVB_AVTP_MATCH_A_MARK,
1761};
1762static const unsigned int avb_avtp_capture_a_pins[] = {
1763
1764 RCAR_GP_PIN(2, 14),
1765};
1766static const unsigned int avb_avtp_capture_a_mux[] = {
1767 AVB_AVTP_CAPTURE_A_MARK,
1768};
1769static const unsigned int avb_avtp_match_b_pins[] = {
1770
1771 RCAR_GP_PIN(1, 8),
1772};
1773static const unsigned int avb_avtp_match_b_mux[] = {
1774 AVB_AVTP_MATCH_B_MARK,
1775};
1776static const unsigned int avb_avtp_capture_b_pins[] = {
1777
1778 RCAR_GP_PIN(1, 11),
1779};
1780static const unsigned int avb_avtp_capture_b_mux[] = {
1781 AVB_AVTP_CAPTURE_B_MARK,
1782};
1783
1784
1785static const unsigned int can0_data_a_pins[] = {
1786
1787 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1788};
1789
1790static const unsigned int can0_data_a_mux[] = {
1791 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1792};
1793
1794static const unsigned int can0_data_b_pins[] = {
1795
1796 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1797};
1798
1799static const unsigned int can0_data_b_mux[] = {
1800 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1801};
1802
1803static const unsigned int can1_data_pins[] = {
1804
1805 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1806};
1807
1808static const unsigned int can1_data_mux[] = {
1809 CAN1_TX_MARK, CAN1_RX_MARK,
1810};
1811
1812
1813static const unsigned int can_clk_pins[] = {
1814
1815 RCAR_GP_PIN(1, 25),
1816};
1817
1818static const unsigned int can_clk_mux[] = {
1819 CAN_CLK_MARK,
1820};
1821
1822
1823static const unsigned int canfd0_data_a_pins[] = {
1824
1825 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1826};
1827
1828static const unsigned int canfd0_data_a_mux[] = {
1829 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1830};
1831
1832static const unsigned int canfd0_data_b_pins[] = {
1833
1834 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1835};
1836
1837static const unsigned int canfd0_data_b_mux[] = {
1838 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1839};
1840
1841static const unsigned int canfd1_data_pins[] = {
1842
1843 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1844};
1845
1846static const unsigned int canfd1_data_mux[] = {
1847 CANFD1_TX_MARK, CANFD1_RX_MARK,
1848};
1849
1850#ifdef CONFIG_PINCTRL_PFC_R8A77965
1851
1852static const unsigned int drif0_ctrl_a_pins[] = {
1853
1854 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1855};
1856
1857static const unsigned int drif0_ctrl_a_mux[] = {
1858 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1859};
1860
1861static const unsigned int drif0_data0_a_pins[] = {
1862
1863 RCAR_GP_PIN(6, 10),
1864};
1865
1866static const unsigned int drif0_data0_a_mux[] = {
1867 RIF0_D0_A_MARK,
1868};
1869
1870static const unsigned int drif0_data1_a_pins[] = {
1871
1872 RCAR_GP_PIN(6, 7),
1873};
1874
1875static const unsigned int drif0_data1_a_mux[] = {
1876 RIF0_D1_A_MARK,
1877};
1878
1879static const unsigned int drif0_ctrl_b_pins[] = {
1880
1881 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1882};
1883
1884static const unsigned int drif0_ctrl_b_mux[] = {
1885 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1886};
1887
1888static const unsigned int drif0_data0_b_pins[] = {
1889
1890 RCAR_GP_PIN(5, 1),
1891};
1892
1893static const unsigned int drif0_data0_b_mux[] = {
1894 RIF0_D0_B_MARK,
1895};
1896
1897static const unsigned int drif0_data1_b_pins[] = {
1898
1899 RCAR_GP_PIN(5, 2),
1900};
1901
1902static const unsigned int drif0_data1_b_mux[] = {
1903 RIF0_D1_B_MARK,
1904};
1905
1906static const unsigned int drif0_ctrl_c_pins[] = {
1907
1908 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1909};
1910
1911static const unsigned int drif0_ctrl_c_mux[] = {
1912 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1913};
1914
1915static const unsigned int drif0_data0_c_pins[] = {
1916
1917 RCAR_GP_PIN(5, 13),
1918};
1919
1920static const unsigned int drif0_data0_c_mux[] = {
1921 RIF0_D0_C_MARK,
1922};
1923
1924static const unsigned int drif0_data1_c_pins[] = {
1925
1926 RCAR_GP_PIN(5, 14),
1927};
1928
1929static const unsigned int drif0_data1_c_mux[] = {
1930 RIF0_D1_C_MARK,
1931};
1932
1933
1934static const unsigned int drif1_ctrl_a_pins[] = {
1935
1936 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1937};
1938
1939static const unsigned int drif1_ctrl_a_mux[] = {
1940 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1941};
1942
1943static const unsigned int drif1_data0_a_pins[] = {
1944
1945 RCAR_GP_PIN(6, 19),
1946};
1947
1948static const unsigned int drif1_data0_a_mux[] = {
1949 RIF1_D0_A_MARK,
1950};
1951
1952static const unsigned int drif1_data1_a_pins[] = {
1953
1954 RCAR_GP_PIN(6, 20),
1955};
1956
1957static const unsigned int drif1_data1_a_mux[] = {
1958 RIF1_D1_A_MARK,
1959};
1960
1961static const unsigned int drif1_ctrl_b_pins[] = {
1962
1963 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1964};
1965
1966static const unsigned int drif1_ctrl_b_mux[] = {
1967 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1968};
1969
1970static const unsigned int drif1_data0_b_pins[] = {
1971
1972 RCAR_GP_PIN(5, 7),
1973};
1974
1975static const unsigned int drif1_data0_b_mux[] = {
1976 RIF1_D0_B_MARK,
1977};
1978
1979static const unsigned int drif1_data1_b_pins[] = {
1980
1981 RCAR_GP_PIN(5, 8),
1982};
1983
1984static const unsigned int drif1_data1_b_mux[] = {
1985 RIF1_D1_B_MARK,
1986};
1987
1988static const unsigned int drif1_ctrl_c_pins[] = {
1989
1990 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1991};
1992
1993static const unsigned int drif1_ctrl_c_mux[] = {
1994 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1995};
1996
1997static const unsigned int drif1_data0_c_pins[] = {
1998
1999 RCAR_GP_PIN(5, 6),
2000};
2001
2002static const unsigned int drif1_data0_c_mux[] = {
2003 RIF1_D0_C_MARK,
2004};
2005
2006static const unsigned int drif1_data1_c_pins[] = {
2007
2008 RCAR_GP_PIN(5, 10),
2009};
2010
2011static const unsigned int drif1_data1_c_mux[] = {
2012 RIF1_D1_C_MARK,
2013};
2014
2015
2016static const unsigned int drif2_ctrl_a_pins[] = {
2017
2018 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2019};
2020
2021static const unsigned int drif2_ctrl_a_mux[] = {
2022 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
2023};
2024
2025static const unsigned int drif2_data0_a_pins[] = {
2026
2027 RCAR_GP_PIN(6, 7),
2028};
2029
2030static const unsigned int drif2_data0_a_mux[] = {
2031 RIF2_D0_A_MARK,
2032};
2033
2034static const unsigned int drif2_data1_a_pins[] = {
2035
2036 RCAR_GP_PIN(6, 10),
2037};
2038
2039static const unsigned int drif2_data1_a_mux[] = {
2040 RIF2_D1_A_MARK,
2041};
2042
2043static const unsigned int drif2_ctrl_b_pins[] = {
2044
2045 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2046};
2047
2048static const unsigned int drif2_ctrl_b_mux[] = {
2049 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
2050};
2051
2052static const unsigned int drif2_data0_b_pins[] = {
2053
2054 RCAR_GP_PIN(6, 30),
2055};
2056
2057static const unsigned int drif2_data0_b_mux[] = {
2058 RIF2_D0_B_MARK,
2059};
2060
2061static const unsigned int drif2_data1_b_pins[] = {
2062
2063 RCAR_GP_PIN(6, 31),
2064};
2065
2066static const unsigned int drif2_data1_b_mux[] = {
2067 RIF2_D1_B_MARK,
2068};
2069
2070
2071static const unsigned int drif3_ctrl_a_pins[] = {
2072
2073 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2074};
2075
2076static const unsigned int drif3_ctrl_a_mux[] = {
2077 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2078};
2079
2080static const unsigned int drif3_data0_a_pins[] = {
2081
2082 RCAR_GP_PIN(6, 19),
2083};
2084
2085static const unsigned int drif3_data0_a_mux[] = {
2086 RIF3_D0_A_MARK,
2087};
2088
2089static const unsigned int drif3_data1_a_pins[] = {
2090
2091 RCAR_GP_PIN(6, 20),
2092};
2093
2094static const unsigned int drif3_data1_a_mux[] = {
2095 RIF3_D1_A_MARK,
2096};
2097
2098static const unsigned int drif3_ctrl_b_pins[] = {
2099
2100 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2101};
2102
2103static const unsigned int drif3_ctrl_b_mux[] = {
2104 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2105};
2106
2107static const unsigned int drif3_data0_b_pins[] = {
2108
2109 RCAR_GP_PIN(6, 28),
2110};
2111
2112static const unsigned int drif3_data0_b_mux[] = {
2113 RIF3_D0_B_MARK,
2114};
2115
2116static const unsigned int drif3_data1_b_pins[] = {
2117
2118 RCAR_GP_PIN(6, 29),
2119};
2120
2121static const unsigned int drif3_data1_b_mux[] = {
2122 RIF3_D1_B_MARK,
2123};
2124#endif
2125
2126
2127static const unsigned int du_rgb666_pins[] = {
2128
2129 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2130 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2131 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2132 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2133 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2134 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2135};
2136
2137static const unsigned int du_rgb666_mux[] = {
2138 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2139 DU_DR3_MARK, DU_DR2_MARK,
2140 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2141 DU_DG3_MARK, DU_DG2_MARK,
2142 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2143 DU_DB3_MARK, DU_DB2_MARK,
2144};
2145
2146static const unsigned int du_rgb888_pins[] = {
2147
2148 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2149 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2150 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2151 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2152 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2153 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2154 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2155 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2156 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2157};
2158
2159static const unsigned int du_rgb888_mux[] = {
2160 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2161 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2162 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2163 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2164 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2165 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2166};
2167
2168static const unsigned int du_clk_out_0_pins[] = {
2169
2170 RCAR_GP_PIN(1, 27),
2171};
2172
2173static const unsigned int du_clk_out_0_mux[] = {
2174 DU_DOTCLKOUT0_MARK
2175};
2176
2177static const unsigned int du_clk_out_1_pins[] = {
2178
2179 RCAR_GP_PIN(2, 3),
2180};
2181
2182static const unsigned int du_clk_out_1_mux[] = {
2183 DU_DOTCLKOUT1_MARK
2184};
2185
2186static const unsigned int du_sync_pins[] = {
2187
2188 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2189};
2190
2191static const unsigned int du_sync_mux[] = {
2192 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2193};
2194
2195static const unsigned int du_oddf_pins[] = {
2196
2197 RCAR_GP_PIN(2, 2),
2198};
2199
2200static const unsigned int du_oddf_mux[] = {
2201 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2202};
2203
2204static const unsigned int du_cde_pins[] = {
2205
2206 RCAR_GP_PIN(2, 0),
2207};
2208
2209static const unsigned int du_cde_mux[] = {
2210 DU_CDE_MARK,
2211};
2212
2213static const unsigned int du_disp_pins[] = {
2214
2215 RCAR_GP_PIN(2, 1),
2216};
2217
2218static const unsigned int du_disp_mux[] = {
2219 DU_DISP_MARK,
2220};
2221
2222
2223static const unsigned int hscif0_data_pins[] = {
2224
2225 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2226};
2227
2228static const unsigned int hscif0_data_mux[] = {
2229 HRX0_MARK, HTX0_MARK,
2230};
2231
2232static const unsigned int hscif0_clk_pins[] = {
2233
2234 RCAR_GP_PIN(5, 12),
2235};
2236
2237static const unsigned int hscif0_clk_mux[] = {
2238 HSCK0_MARK,
2239};
2240
2241static const unsigned int hscif0_ctrl_pins[] = {
2242
2243 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2244};
2245
2246static const unsigned int hscif0_ctrl_mux[] = {
2247 HRTS0_N_MARK, HCTS0_N_MARK,
2248};
2249
2250
2251static const unsigned int hscif1_data_a_pins[] = {
2252
2253 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2254};
2255
2256static const unsigned int hscif1_data_a_mux[] = {
2257 HRX1_A_MARK, HTX1_A_MARK,
2258};
2259
2260static const unsigned int hscif1_clk_a_pins[] = {
2261
2262 RCAR_GP_PIN(6, 21),
2263};
2264
2265static const unsigned int hscif1_clk_a_mux[] = {
2266 HSCK1_A_MARK,
2267};
2268
2269static const unsigned int hscif1_ctrl_a_pins[] = {
2270
2271 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2272};
2273
2274static const unsigned int hscif1_ctrl_a_mux[] = {
2275 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2276};
2277
2278static const unsigned int hscif1_data_b_pins[] = {
2279
2280 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2281};
2282
2283static const unsigned int hscif1_data_b_mux[] = {
2284 HRX1_B_MARK, HTX1_B_MARK,
2285};
2286
2287static const unsigned int hscif1_clk_b_pins[] = {
2288
2289 RCAR_GP_PIN(5, 0),
2290};
2291
2292static const unsigned int hscif1_clk_b_mux[] = {
2293 HSCK1_B_MARK,
2294};
2295
2296static const unsigned int hscif1_ctrl_b_pins[] = {
2297
2298 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2299};
2300
2301static const unsigned int hscif1_ctrl_b_mux[] = {
2302 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2303};
2304
2305
2306static const unsigned int hscif2_data_a_pins[] = {
2307
2308 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2309};
2310
2311static const unsigned int hscif2_data_a_mux[] = {
2312 HRX2_A_MARK, HTX2_A_MARK,
2313};
2314
2315static const unsigned int hscif2_clk_a_pins[] = {
2316
2317 RCAR_GP_PIN(6, 10),
2318};
2319
2320static const unsigned int hscif2_clk_a_mux[] = {
2321 HSCK2_A_MARK,
2322};
2323
2324static const unsigned int hscif2_ctrl_a_pins[] = {
2325
2326 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2327};
2328
2329static const unsigned int hscif2_ctrl_a_mux[] = {
2330 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2331};
2332
2333static const unsigned int hscif2_data_b_pins[] = {
2334
2335 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2336};
2337
2338static const unsigned int hscif2_data_b_mux[] = {
2339 HRX2_B_MARK, HTX2_B_MARK,
2340};
2341
2342static const unsigned int hscif2_clk_b_pins[] = {
2343
2344 RCAR_GP_PIN(6, 21),
2345};
2346
2347static const unsigned int hscif2_clk_b_mux[] = {
2348 HSCK2_B_MARK,
2349};
2350
2351static const unsigned int hscif2_ctrl_b_pins[] = {
2352
2353 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2354};
2355
2356static const unsigned int hscif2_ctrl_b_mux[] = {
2357 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2358};
2359
2360static const unsigned int hscif2_data_c_pins[] = {
2361
2362 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2363};
2364
2365static const unsigned int hscif2_data_c_mux[] = {
2366 HRX2_C_MARK, HTX2_C_MARK,
2367};
2368
2369static const unsigned int hscif2_clk_c_pins[] = {
2370
2371 RCAR_GP_PIN(6, 24),
2372};
2373
2374static const unsigned int hscif2_clk_c_mux[] = {
2375 HSCK2_C_MARK,
2376};
2377
2378static const unsigned int hscif2_ctrl_c_pins[] = {
2379
2380 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2381};
2382
2383static const unsigned int hscif2_ctrl_c_mux[] = {
2384 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2385};
2386
2387
2388static const unsigned int hscif3_data_a_pins[] = {
2389
2390 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2391};
2392
2393static const unsigned int hscif3_data_a_mux[] = {
2394 HRX3_A_MARK, HTX3_A_MARK,
2395};
2396
2397static const unsigned int hscif3_clk_pins[] = {
2398
2399 RCAR_GP_PIN(1, 22),
2400};
2401
2402static const unsigned int hscif3_clk_mux[] = {
2403 HSCK3_MARK,
2404};
2405
2406static const unsigned int hscif3_ctrl_pins[] = {
2407
2408 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2409};
2410
2411static const unsigned int hscif3_ctrl_mux[] = {
2412 HRTS3_N_MARK, HCTS3_N_MARK,
2413};
2414
2415static const unsigned int hscif3_data_b_pins[] = {
2416
2417 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2418};
2419
2420static const unsigned int hscif3_data_b_mux[] = {
2421 HRX3_B_MARK, HTX3_B_MARK,
2422};
2423
2424static const unsigned int hscif3_data_c_pins[] = {
2425
2426 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2427};
2428
2429static const unsigned int hscif3_data_c_mux[] = {
2430 HRX3_C_MARK, HTX3_C_MARK,
2431};
2432
2433static const unsigned int hscif3_data_d_pins[] = {
2434
2435 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2436};
2437
2438static const unsigned int hscif3_data_d_mux[] = {
2439 HRX3_D_MARK, HTX3_D_MARK,
2440};
2441
2442
2443static const unsigned int hscif4_data_a_pins[] = {
2444
2445 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2446};
2447
2448static const unsigned int hscif4_data_a_mux[] = {
2449 HRX4_A_MARK, HTX4_A_MARK,
2450};
2451
2452static const unsigned int hscif4_clk_pins[] = {
2453
2454 RCAR_GP_PIN(1, 11),
2455};
2456
2457static const unsigned int hscif4_clk_mux[] = {
2458 HSCK4_MARK,
2459};
2460
2461static const unsigned int hscif4_ctrl_pins[] = {
2462
2463 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2464};
2465
2466static const unsigned int hscif4_ctrl_mux[] = {
2467 HRTS4_N_MARK, HCTS4_N_MARK,
2468};
2469
2470static const unsigned int hscif4_data_b_pins[] = {
2471
2472 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2473};
2474
2475static const unsigned int hscif4_data_b_mux[] = {
2476 HRX4_B_MARK, HTX4_B_MARK,
2477};
2478
2479
2480static const unsigned int i2c0_pins[] = {
2481
2482 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2483};
2484
2485static const unsigned int i2c0_mux[] = {
2486 SCL0_MARK, SDA0_MARK,
2487};
2488
2489static const unsigned int i2c1_a_pins[] = {
2490
2491 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2492};
2493
2494static const unsigned int i2c1_a_mux[] = {
2495 SDA1_A_MARK, SCL1_A_MARK,
2496};
2497
2498static const unsigned int i2c1_b_pins[] = {
2499
2500 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2501};
2502
2503static const unsigned int i2c1_b_mux[] = {
2504 SDA1_B_MARK, SCL1_B_MARK,
2505};
2506
2507static const unsigned int i2c2_a_pins[] = {
2508
2509 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2510};
2511
2512static const unsigned int i2c2_a_mux[] = {
2513 SDA2_A_MARK, SCL2_A_MARK,
2514};
2515
2516static const unsigned int i2c2_b_pins[] = {
2517
2518 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2519};
2520
2521static const unsigned int i2c2_b_mux[] = {
2522 SDA2_B_MARK, SCL2_B_MARK,
2523};
2524
2525static const unsigned int i2c3_pins[] = {
2526
2527 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2528};
2529
2530static const unsigned int i2c3_mux[] = {
2531 SCL3_MARK, SDA3_MARK,
2532};
2533
2534static const unsigned int i2c5_pins[] = {
2535
2536 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2537};
2538
2539static const unsigned int i2c5_mux[] = {
2540 SCL5_MARK, SDA5_MARK,
2541};
2542
2543static const unsigned int i2c6_a_pins[] = {
2544
2545 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2546};
2547
2548static const unsigned int i2c6_a_mux[] = {
2549 SDA6_A_MARK, SCL6_A_MARK,
2550};
2551
2552static const unsigned int i2c6_b_pins[] = {
2553
2554 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2555};
2556
2557static const unsigned int i2c6_b_mux[] = {
2558 SDA6_B_MARK, SCL6_B_MARK,
2559};
2560
2561static const unsigned int i2c6_c_pins[] = {
2562
2563 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2564};
2565
2566static const unsigned int i2c6_c_mux[] = {
2567 SDA6_C_MARK, SCL6_C_MARK,
2568};
2569
2570
2571static const unsigned int intc_ex_irq0_pins[] = {
2572
2573 RCAR_GP_PIN(2, 0),
2574};
2575static const unsigned int intc_ex_irq0_mux[] = {
2576 IRQ0_MARK,
2577};
2578static const unsigned int intc_ex_irq1_pins[] = {
2579
2580 RCAR_GP_PIN(2, 1),
2581};
2582static const unsigned int intc_ex_irq1_mux[] = {
2583 IRQ1_MARK,
2584};
2585static const unsigned int intc_ex_irq2_pins[] = {
2586
2587 RCAR_GP_PIN(2, 2),
2588};
2589static const unsigned int intc_ex_irq2_mux[] = {
2590 IRQ2_MARK,
2591};
2592static const unsigned int intc_ex_irq3_pins[] = {
2593
2594 RCAR_GP_PIN(2, 3),
2595};
2596static const unsigned int intc_ex_irq3_mux[] = {
2597 IRQ3_MARK,
2598};
2599static const unsigned int intc_ex_irq4_pins[] = {
2600
2601 RCAR_GP_PIN(2, 4),
2602};
2603static const unsigned int intc_ex_irq4_mux[] = {
2604 IRQ4_MARK,
2605};
2606static const unsigned int intc_ex_irq5_pins[] = {
2607
2608 RCAR_GP_PIN(2, 5),
2609};
2610static const unsigned int intc_ex_irq5_mux[] = {
2611 IRQ5_MARK,
2612};
2613
2614
2615static const unsigned int msiof0_clk_pins[] = {
2616
2617 RCAR_GP_PIN(5, 17),
2618};
2619static const unsigned int msiof0_clk_mux[] = {
2620 MSIOF0_SCK_MARK,
2621};
2622static const unsigned int msiof0_sync_pins[] = {
2623
2624 RCAR_GP_PIN(5, 18),
2625};
2626static const unsigned int msiof0_sync_mux[] = {
2627 MSIOF0_SYNC_MARK,
2628};
2629static const unsigned int msiof0_ss1_pins[] = {
2630
2631 RCAR_GP_PIN(5, 19),
2632};
2633static const unsigned int msiof0_ss1_mux[] = {
2634 MSIOF0_SS1_MARK,
2635};
2636static const unsigned int msiof0_ss2_pins[] = {
2637
2638 RCAR_GP_PIN(5, 21),
2639};
2640static const unsigned int msiof0_ss2_mux[] = {
2641 MSIOF0_SS2_MARK,
2642};
2643static const unsigned int msiof0_txd_pins[] = {
2644
2645 RCAR_GP_PIN(5, 20),
2646};
2647static const unsigned int msiof0_txd_mux[] = {
2648 MSIOF0_TXD_MARK,
2649};
2650static const unsigned int msiof0_rxd_pins[] = {
2651
2652 RCAR_GP_PIN(5, 22),
2653};
2654static const unsigned int msiof0_rxd_mux[] = {
2655 MSIOF0_RXD_MARK,
2656};
2657
2658static const unsigned int msiof1_clk_a_pins[] = {
2659
2660 RCAR_GP_PIN(6, 8),
2661};
2662static const unsigned int msiof1_clk_a_mux[] = {
2663 MSIOF1_SCK_A_MARK,
2664};
2665static const unsigned int msiof1_sync_a_pins[] = {
2666
2667 RCAR_GP_PIN(6, 9),
2668};
2669static const unsigned int msiof1_sync_a_mux[] = {
2670 MSIOF1_SYNC_A_MARK,
2671};
2672static const unsigned int msiof1_ss1_a_pins[] = {
2673
2674 RCAR_GP_PIN(6, 5),
2675};
2676static const unsigned int msiof1_ss1_a_mux[] = {
2677 MSIOF1_SS1_A_MARK,
2678};
2679static const unsigned int msiof1_ss2_a_pins[] = {
2680
2681 RCAR_GP_PIN(6, 6),
2682};
2683static const unsigned int msiof1_ss2_a_mux[] = {
2684 MSIOF1_SS2_A_MARK,
2685};
2686static const unsigned int msiof1_txd_a_pins[] = {
2687
2688 RCAR_GP_PIN(6, 7),
2689};
2690static const unsigned int msiof1_txd_a_mux[] = {
2691 MSIOF1_TXD_A_MARK,
2692};
2693static const unsigned int msiof1_rxd_a_pins[] = {
2694
2695 RCAR_GP_PIN(6, 10),
2696};
2697static const unsigned int msiof1_rxd_a_mux[] = {
2698 MSIOF1_RXD_A_MARK,
2699};
2700static const unsigned int msiof1_clk_b_pins[] = {
2701
2702 RCAR_GP_PIN(5, 9),
2703};
2704static const unsigned int msiof1_clk_b_mux[] = {
2705 MSIOF1_SCK_B_MARK,
2706};
2707static const unsigned int msiof1_sync_b_pins[] = {
2708
2709 RCAR_GP_PIN(5, 3),
2710};
2711static const unsigned int msiof1_sync_b_mux[] = {
2712 MSIOF1_SYNC_B_MARK,
2713};
2714static const unsigned int msiof1_ss1_b_pins[] = {
2715
2716 RCAR_GP_PIN(5, 4),
2717};
2718static const unsigned int msiof1_ss1_b_mux[] = {
2719 MSIOF1_SS1_B_MARK,
2720};
2721static const unsigned int msiof1_ss2_b_pins[] = {
2722
2723 RCAR_GP_PIN(5, 0),
2724};
2725static const unsigned int msiof1_ss2_b_mux[] = {
2726 MSIOF1_SS2_B_MARK,
2727};
2728static const unsigned int msiof1_txd_b_pins[] = {
2729
2730 RCAR_GP_PIN(5, 8),
2731};
2732static const unsigned int msiof1_txd_b_mux[] = {
2733 MSIOF1_TXD_B_MARK,
2734};
2735static const unsigned int msiof1_rxd_b_pins[] = {
2736
2737 RCAR_GP_PIN(5, 7),
2738};
2739static const unsigned int msiof1_rxd_b_mux[] = {
2740 MSIOF1_RXD_B_MARK,
2741};
2742static const unsigned int msiof1_clk_c_pins[] = {
2743
2744 RCAR_GP_PIN(6, 17),
2745};
2746static const unsigned int msiof1_clk_c_mux[] = {
2747 MSIOF1_SCK_C_MARK,
2748};
2749static const unsigned int msiof1_sync_c_pins[] = {
2750
2751 RCAR_GP_PIN(6, 18),
2752};
2753static const unsigned int msiof1_sync_c_mux[] = {
2754 MSIOF1_SYNC_C_MARK,
2755};
2756static const unsigned int msiof1_ss1_c_pins[] = {
2757
2758 RCAR_GP_PIN(6, 21),
2759};
2760static const unsigned int msiof1_ss1_c_mux[] = {
2761 MSIOF1_SS1_C_MARK,
2762};
2763static const unsigned int msiof1_ss2_c_pins[] = {
2764
2765 RCAR_GP_PIN(6, 27),
2766};
2767static const unsigned int msiof1_ss2_c_mux[] = {
2768 MSIOF1_SS2_C_MARK,
2769};
2770static const unsigned int msiof1_txd_c_pins[] = {
2771
2772 RCAR_GP_PIN(6, 20),
2773};
2774static const unsigned int msiof1_txd_c_mux[] = {
2775 MSIOF1_TXD_C_MARK,
2776};
2777static const unsigned int msiof1_rxd_c_pins[] = {
2778
2779 RCAR_GP_PIN(6, 19),
2780};
2781static const unsigned int msiof1_rxd_c_mux[] = {
2782 MSIOF1_RXD_C_MARK,
2783};
2784static const unsigned int msiof1_clk_d_pins[] = {
2785
2786 RCAR_GP_PIN(5, 12),
2787};
2788static const unsigned int msiof1_clk_d_mux[] = {
2789 MSIOF1_SCK_D_MARK,
2790};
2791static const unsigned int msiof1_sync_d_pins[] = {
2792
2793 RCAR_GP_PIN(5, 15),
2794};
2795static const unsigned int msiof1_sync_d_mux[] = {
2796 MSIOF1_SYNC_D_MARK,
2797};
2798static const unsigned int msiof1_ss1_d_pins[] = {
2799
2800 RCAR_GP_PIN(5, 16),
2801};
2802static const unsigned int msiof1_ss1_d_mux[] = {
2803 MSIOF1_SS1_D_MARK,
2804};
2805static const unsigned int msiof1_ss2_d_pins[] = {
2806
2807 RCAR_GP_PIN(5, 21),
2808};
2809static const unsigned int msiof1_ss2_d_mux[] = {
2810 MSIOF1_SS2_D_MARK,
2811};
2812static const unsigned int msiof1_txd_d_pins[] = {
2813
2814 RCAR_GP_PIN(5, 14),
2815};
2816static const unsigned int msiof1_txd_d_mux[] = {
2817 MSIOF1_TXD_D_MARK,
2818};
2819static const unsigned int msiof1_rxd_d_pins[] = {
2820
2821 RCAR_GP_PIN(5, 13),
2822};
2823static const unsigned int msiof1_rxd_d_mux[] = {
2824 MSIOF1_RXD_D_MARK,
2825};
2826static const unsigned int msiof1_clk_e_pins[] = {
2827
2828 RCAR_GP_PIN(3, 0),
2829};
2830static const unsigned int msiof1_clk_e_mux[] = {
2831 MSIOF1_SCK_E_MARK,
2832};
2833static const unsigned int msiof1_sync_e_pins[] = {
2834
2835 RCAR_GP_PIN(3, 1),
2836};
2837static const unsigned int msiof1_sync_e_mux[] = {
2838 MSIOF1_SYNC_E_MARK,
2839};
2840static const unsigned int msiof1_ss1_e_pins[] = {
2841
2842 RCAR_GP_PIN(3, 4),
2843};
2844static const unsigned int msiof1_ss1_e_mux[] = {
2845 MSIOF1_SS1_E_MARK,
2846};
2847static const unsigned int msiof1_ss2_e_pins[] = {
2848
2849 RCAR_GP_PIN(3, 5),
2850};
2851static const unsigned int msiof1_ss2_e_mux[] = {
2852 MSIOF1_SS2_E_MARK,
2853};
2854static const unsigned int msiof1_txd_e_pins[] = {
2855
2856 RCAR_GP_PIN(3, 3),
2857};
2858static const unsigned int msiof1_txd_e_mux[] = {
2859 MSIOF1_TXD_E_MARK,
2860};
2861static const unsigned int msiof1_rxd_e_pins[] = {
2862
2863 RCAR_GP_PIN(3, 2),
2864};
2865static const unsigned int msiof1_rxd_e_mux[] = {
2866 MSIOF1_RXD_E_MARK,
2867};
2868static const unsigned int msiof1_clk_f_pins[] = {
2869
2870 RCAR_GP_PIN(5, 23),
2871};
2872static const unsigned int msiof1_clk_f_mux[] = {
2873 MSIOF1_SCK_F_MARK,
2874};
2875static const unsigned int msiof1_sync_f_pins[] = {
2876
2877 RCAR_GP_PIN(5, 24),
2878};
2879static const unsigned int msiof1_sync_f_mux[] = {
2880 MSIOF1_SYNC_F_MARK,
2881};
2882static const unsigned int msiof1_ss1_f_pins[] = {
2883
2884 RCAR_GP_PIN(6, 1),
2885};
2886static const unsigned int msiof1_ss1_f_mux[] = {
2887 MSIOF1_SS1_F_MARK,
2888};
2889static const unsigned int msiof1_ss2_f_pins[] = {
2890
2891 RCAR_GP_PIN(6, 2),
2892};
2893static const unsigned int msiof1_ss2_f_mux[] = {
2894 MSIOF1_SS2_F_MARK,
2895};
2896static const unsigned int msiof1_txd_f_pins[] = {
2897
2898 RCAR_GP_PIN(6, 0),
2899};
2900static const unsigned int msiof1_txd_f_mux[] = {
2901 MSIOF1_TXD_F_MARK,
2902};
2903static const unsigned int msiof1_rxd_f_pins[] = {
2904
2905 RCAR_GP_PIN(5, 25),
2906};
2907static const unsigned int msiof1_rxd_f_mux[] = {
2908 MSIOF1_RXD_F_MARK,
2909};
2910static const unsigned int msiof1_clk_g_pins[] = {
2911
2912 RCAR_GP_PIN(3, 6),
2913};
2914static const unsigned int msiof1_clk_g_mux[] = {
2915 MSIOF1_SCK_G_MARK,
2916};
2917static const unsigned int msiof1_sync_g_pins[] = {
2918
2919 RCAR_GP_PIN(3, 7),
2920};
2921static const unsigned int msiof1_sync_g_mux[] = {
2922 MSIOF1_SYNC_G_MARK,
2923};
2924static const unsigned int msiof1_ss1_g_pins[] = {
2925
2926 RCAR_GP_PIN(3, 10),
2927};
2928static const unsigned int msiof1_ss1_g_mux[] = {
2929 MSIOF1_SS1_G_MARK,
2930};
2931static const unsigned int msiof1_ss2_g_pins[] = {
2932
2933 RCAR_GP_PIN(3, 11),
2934};
2935static const unsigned int msiof1_ss2_g_mux[] = {
2936 MSIOF1_SS2_G_MARK,
2937};
2938static const unsigned int msiof1_txd_g_pins[] = {
2939
2940 RCAR_GP_PIN(3, 9),
2941};
2942static const unsigned int msiof1_txd_g_mux[] = {
2943 MSIOF1_TXD_G_MARK,
2944};
2945static const unsigned int msiof1_rxd_g_pins[] = {
2946
2947 RCAR_GP_PIN(3, 8),
2948};
2949static const unsigned int msiof1_rxd_g_mux[] = {
2950 MSIOF1_RXD_G_MARK,
2951};
2952
2953static const unsigned int msiof2_clk_a_pins[] = {
2954
2955 RCAR_GP_PIN(1, 9),
2956};
2957static const unsigned int msiof2_clk_a_mux[] = {
2958 MSIOF2_SCK_A_MARK,
2959};
2960static const unsigned int msiof2_sync_a_pins[] = {
2961
2962 RCAR_GP_PIN(1, 8),
2963};
2964static const unsigned int msiof2_sync_a_mux[] = {
2965 MSIOF2_SYNC_A_MARK,
2966};
2967static const unsigned int msiof2_ss1_a_pins[] = {
2968
2969 RCAR_GP_PIN(1, 6),
2970};
2971static const unsigned int msiof2_ss1_a_mux[] = {
2972 MSIOF2_SS1_A_MARK,
2973};
2974static const unsigned int msiof2_ss2_a_pins[] = {
2975
2976 RCAR_GP_PIN(1, 7),
2977};
2978static const unsigned int msiof2_ss2_a_mux[] = {
2979 MSIOF2_SS2_A_MARK,
2980};
2981static const unsigned int msiof2_txd_a_pins[] = {
2982
2983 RCAR_GP_PIN(1, 11),
2984};
2985static const unsigned int msiof2_txd_a_mux[] = {
2986 MSIOF2_TXD_A_MARK,
2987};
2988static const unsigned int msiof2_rxd_a_pins[] = {
2989
2990 RCAR_GP_PIN(1, 10),
2991};
2992static const unsigned int msiof2_rxd_a_mux[] = {
2993 MSIOF2_RXD_A_MARK,
2994};
2995static const unsigned int msiof2_clk_b_pins[] = {
2996
2997 RCAR_GP_PIN(0, 4),
2998};
2999static const unsigned int msiof2_clk_b_mux[] = {
3000 MSIOF2_SCK_B_MARK,
3001};
3002static const unsigned int msiof2_sync_b_pins[] = {
3003
3004 RCAR_GP_PIN(0, 5),
3005};
3006static const unsigned int msiof2_sync_b_mux[] = {
3007 MSIOF2_SYNC_B_MARK,
3008};
3009static const unsigned int msiof2_ss1_b_pins[] = {
3010
3011 RCAR_GP_PIN(0, 0),
3012};
3013static const unsigned int msiof2_ss1_b_mux[] = {
3014 MSIOF2_SS1_B_MARK,
3015};
3016static const unsigned int msiof2_ss2_b_pins[] = {
3017
3018 RCAR_GP_PIN(0, 1),
3019};
3020static const unsigned int msiof2_ss2_b_mux[] = {
3021 MSIOF2_SS2_B_MARK,
3022};
3023static const unsigned int msiof2_txd_b_pins[] = {
3024
3025 RCAR_GP_PIN(0, 7),
3026};
3027static const unsigned int msiof2_txd_b_mux[] = {
3028 MSIOF2_TXD_B_MARK,
3029};
3030static const unsigned int msiof2_rxd_b_pins[] = {
3031
3032 RCAR_GP_PIN(0, 6),
3033};
3034static const unsigned int msiof2_rxd_b_mux[] = {
3035 MSIOF2_RXD_B_MARK,
3036};
3037static const unsigned int msiof2_clk_c_pins[] = {
3038
3039 RCAR_GP_PIN(2, 12),
3040};
3041static const unsigned int msiof2_clk_c_mux[] = {
3042 MSIOF2_SCK_C_MARK,
3043};
3044static const unsigned int msiof2_sync_c_pins[] = {
3045
3046 RCAR_GP_PIN(2, 11),
3047};
3048static const unsigned int msiof2_sync_c_mux[] = {
3049 MSIOF2_SYNC_C_MARK,
3050};
3051static const unsigned int msiof2_ss1_c_pins[] = {
3052
3053 RCAR_GP_PIN(2, 10),
3054};
3055static const unsigned int msiof2_ss1_c_mux[] = {
3056 MSIOF2_SS1_C_MARK,
3057};
3058static const unsigned int msiof2_ss2_c_pins[] = {
3059
3060 RCAR_GP_PIN(2, 9),
3061};
3062static const unsigned int msiof2_ss2_c_mux[] = {
3063 MSIOF2_SS2_C_MARK,
3064};
3065static const unsigned int msiof2_txd_c_pins[] = {
3066
3067 RCAR_GP_PIN(2, 14),
3068};
3069static const unsigned int msiof2_txd_c_mux[] = {
3070 MSIOF2_TXD_C_MARK,
3071};
3072static const unsigned int msiof2_rxd_c_pins[] = {
3073
3074 RCAR_GP_PIN(2, 13),
3075};
3076static const unsigned int msiof2_rxd_c_mux[] = {
3077 MSIOF2_RXD_C_MARK,
3078};
3079static const unsigned int msiof2_clk_d_pins[] = {
3080
3081 RCAR_GP_PIN(0, 8),
3082};
3083static const unsigned int msiof2_clk_d_mux[] = {
3084 MSIOF2_SCK_D_MARK,
3085};
3086static const unsigned int msiof2_sync_d_pins[] = {
3087
3088 RCAR_GP_PIN(0, 9),
3089};
3090static const unsigned int msiof2_sync_d_mux[] = {
3091 MSIOF2_SYNC_D_MARK,
3092};
3093static const unsigned int msiof2_ss1_d_pins[] = {
3094
3095 RCAR_GP_PIN(0, 12),
3096};
3097static const unsigned int msiof2_ss1_d_mux[] = {
3098 MSIOF2_SS1_D_MARK,
3099};
3100static const unsigned int msiof2_ss2_d_pins[] = {
3101
3102 RCAR_GP_PIN(0, 13),
3103};
3104static const unsigned int msiof2_ss2_d_mux[] = {
3105 MSIOF2_SS2_D_MARK,
3106};
3107static const unsigned int msiof2_txd_d_pins[] = {
3108
3109 RCAR_GP_PIN(0, 11),
3110};
3111static const unsigned int msiof2_txd_d_mux[] = {
3112 MSIOF2_TXD_D_MARK,
3113};
3114static const unsigned int msiof2_rxd_d_pins[] = {
3115
3116 RCAR_GP_PIN(0, 10),
3117};
3118static const unsigned int msiof2_rxd_d_mux[] = {
3119 MSIOF2_RXD_D_MARK,
3120};
3121
3122static const unsigned int msiof3_clk_a_pins[] = {
3123
3124 RCAR_GP_PIN(0, 0),
3125};
3126static const unsigned int msiof3_clk_a_mux[] = {
3127 MSIOF3_SCK_A_MARK,
3128};
3129static const unsigned int msiof3_sync_a_pins[] = {
3130
3131 RCAR_GP_PIN(0, 1),
3132};
3133static const unsigned int msiof3_sync_a_mux[] = {
3134 MSIOF3_SYNC_A_MARK,
3135};
3136static const unsigned int msiof3_ss1_a_pins[] = {
3137
3138 RCAR_GP_PIN(0, 14),
3139};
3140static const unsigned int msiof3_ss1_a_mux[] = {
3141 MSIOF3_SS1_A_MARK,
3142};
3143static const unsigned int msiof3_ss2_a_pins[] = {
3144
3145 RCAR_GP_PIN(0, 15),
3146};
3147static const unsigned int msiof3_ss2_a_mux[] = {
3148 MSIOF3_SS2_A_MARK,
3149};
3150static const unsigned int msiof3_txd_a_pins[] = {
3151
3152 RCAR_GP_PIN(0, 3),
3153};
3154static const unsigned int msiof3_txd_a_mux[] = {
3155 MSIOF3_TXD_A_MARK,
3156};
3157static const unsigned int msiof3_rxd_a_pins[] = {
3158
3159 RCAR_GP_PIN(0, 2),
3160};
3161static const unsigned int msiof3_rxd_a_mux[] = {
3162 MSIOF3_RXD_A_MARK,
3163};
3164static const unsigned int msiof3_clk_b_pins[] = {
3165
3166 RCAR_GP_PIN(1, 2),
3167};
3168static const unsigned int msiof3_clk_b_mux[] = {
3169 MSIOF3_SCK_B_MARK,
3170};
3171static const unsigned int msiof3_sync_b_pins[] = {
3172
3173 RCAR_GP_PIN(1, 0),
3174};
3175static const unsigned int msiof3_sync_b_mux[] = {
3176 MSIOF3_SYNC_B_MARK,
3177};
3178static const unsigned int msiof3_ss1_b_pins[] = {
3179
3180 RCAR_GP_PIN(1, 4),
3181};
3182static const unsigned int msiof3_ss1_b_mux[] = {
3183 MSIOF3_SS1_B_MARK,
3184};
3185static const unsigned int msiof3_ss2_b_pins[] = {
3186
3187 RCAR_GP_PIN(1, 5),
3188};
3189static const unsigned int msiof3_ss2_b_mux[] = {
3190 MSIOF3_SS2_B_MARK,
3191};
3192static const unsigned int msiof3_txd_b_pins[] = {
3193
3194 RCAR_GP_PIN(1, 1),
3195};
3196static const unsigned int msiof3_txd_b_mux[] = {
3197 MSIOF3_TXD_B_MARK,
3198};
3199static const unsigned int msiof3_rxd_b_pins[] = {
3200
3201 RCAR_GP_PIN(1, 3),
3202};
3203static const unsigned int msiof3_rxd_b_mux[] = {
3204 MSIOF3_RXD_B_MARK,
3205};
3206static const unsigned int msiof3_clk_c_pins[] = {
3207
3208 RCAR_GP_PIN(1, 12),
3209};
3210static const unsigned int msiof3_clk_c_mux[] = {
3211 MSIOF3_SCK_C_MARK,
3212};
3213static const unsigned int msiof3_sync_c_pins[] = {
3214
3215 RCAR_GP_PIN(1, 13),
3216};
3217static const unsigned int msiof3_sync_c_mux[] = {
3218 MSIOF3_SYNC_C_MARK,
3219};
3220static const unsigned int msiof3_txd_c_pins[] = {
3221
3222 RCAR_GP_PIN(1, 15),
3223};
3224static const unsigned int msiof3_txd_c_mux[] = {
3225 MSIOF3_TXD_C_MARK,
3226};
3227static const unsigned int msiof3_rxd_c_pins[] = {
3228
3229 RCAR_GP_PIN(1, 14),
3230};
3231static const unsigned int msiof3_rxd_c_mux[] = {
3232 MSIOF3_RXD_C_MARK,
3233};
3234static const unsigned int msiof3_clk_d_pins[] = {
3235
3236 RCAR_GP_PIN(1, 22),
3237};
3238static const unsigned int msiof3_clk_d_mux[] = {
3239 MSIOF3_SCK_D_MARK,
3240};
3241static const unsigned int msiof3_sync_d_pins[] = {
3242
3243 RCAR_GP_PIN(1, 23),
3244};
3245static const unsigned int msiof3_sync_d_mux[] = {
3246 MSIOF3_SYNC_D_MARK,
3247};
3248static const unsigned int msiof3_ss1_d_pins[] = {
3249
3250 RCAR_GP_PIN(1, 26),
3251};
3252static const unsigned int msiof3_ss1_d_mux[] = {
3253 MSIOF3_SS1_D_MARK,
3254};
3255static const unsigned int msiof3_txd_d_pins[] = {
3256
3257 RCAR_GP_PIN(1, 25),
3258};
3259static const unsigned int msiof3_txd_d_mux[] = {
3260 MSIOF3_TXD_D_MARK,
3261};
3262static const unsigned int msiof3_rxd_d_pins[] = {
3263
3264 RCAR_GP_PIN(1, 24),
3265};
3266static const unsigned int msiof3_rxd_d_mux[] = {
3267 MSIOF3_RXD_D_MARK,
3268};
3269static const unsigned int msiof3_clk_e_pins[] = {
3270
3271 RCAR_GP_PIN(2, 3),
3272};
3273static const unsigned int msiof3_clk_e_mux[] = {
3274 MSIOF3_SCK_E_MARK,
3275};
3276static const unsigned int msiof3_sync_e_pins[] = {
3277
3278 RCAR_GP_PIN(2, 2),
3279};
3280static const unsigned int msiof3_sync_e_mux[] = {
3281 MSIOF3_SYNC_E_MARK,
3282};
3283static const unsigned int msiof3_ss1_e_pins[] = {
3284
3285 RCAR_GP_PIN(2, 1),
3286};
3287static const unsigned int msiof3_ss1_e_mux[] = {
3288 MSIOF3_SS1_E_MARK,
3289};
3290static const unsigned int msiof3_ss2_e_pins[] = {
3291
3292 RCAR_GP_PIN(2, 0),
3293};
3294static const unsigned int msiof3_ss2_e_mux[] = {
3295 MSIOF3_SS2_E_MARK,
3296};
3297static const unsigned int msiof3_txd_e_pins[] = {
3298
3299 RCAR_GP_PIN(2, 5),
3300};
3301static const unsigned int msiof3_txd_e_mux[] = {
3302 MSIOF3_TXD_E_MARK,
3303};
3304static const unsigned int msiof3_rxd_e_pins[] = {
3305
3306 RCAR_GP_PIN(2, 4),
3307};
3308static const unsigned int msiof3_rxd_e_mux[] = {
3309 MSIOF3_RXD_E_MARK,
3310};
3311
3312
3313static const unsigned int pwm0_pins[] = {
3314
3315 RCAR_GP_PIN(2, 6),
3316};
3317static const unsigned int pwm0_mux[] = {
3318 PWM0_MARK,
3319};
3320
3321static const unsigned int pwm1_a_pins[] = {
3322
3323 RCAR_GP_PIN(2, 7),
3324};
3325static const unsigned int pwm1_a_mux[] = {
3326 PWM1_A_MARK,
3327};
3328static const unsigned int pwm1_b_pins[] = {
3329
3330 RCAR_GP_PIN(1, 8),
3331};
3332static const unsigned int pwm1_b_mux[] = {
3333 PWM1_B_MARK,
3334};
3335
3336static const unsigned int pwm2_a_pins[] = {
3337
3338 RCAR_GP_PIN(2, 8),
3339};
3340static const unsigned int pwm2_a_mux[] = {
3341 PWM2_A_MARK,
3342};
3343static const unsigned int pwm2_b_pins[] = {
3344
3345 RCAR_GP_PIN(1, 11),
3346};
3347static const unsigned int pwm2_b_mux[] = {
3348 PWM2_B_MARK,
3349};
3350
3351static const unsigned int pwm3_a_pins[] = {
3352
3353 RCAR_GP_PIN(1, 0),
3354};
3355static const unsigned int pwm3_a_mux[] = {
3356 PWM3_A_MARK,
3357};
3358static const unsigned int pwm3_b_pins[] = {
3359
3360 RCAR_GP_PIN(2, 2),
3361};
3362static const unsigned int pwm3_b_mux[] = {
3363 PWM3_B_MARK,
3364};
3365
3366static const unsigned int pwm4_a_pins[] = {
3367
3368 RCAR_GP_PIN(1, 1),
3369};
3370static const unsigned int pwm4_a_mux[] = {
3371 PWM4_A_MARK,
3372};
3373static const unsigned int pwm4_b_pins[] = {
3374
3375 RCAR_GP_PIN(2, 3),
3376};
3377static const unsigned int pwm4_b_mux[] = {
3378 PWM4_B_MARK,
3379};
3380
3381static const unsigned int pwm5_a_pins[] = {
3382
3383 RCAR_GP_PIN(1, 2),
3384};
3385static const unsigned int pwm5_a_mux[] = {
3386 PWM5_A_MARK,
3387};
3388static const unsigned int pwm5_b_pins[] = {
3389
3390 RCAR_GP_PIN(2, 4),
3391};
3392static const unsigned int pwm5_b_mux[] = {
3393 PWM5_B_MARK,
3394};
3395
3396static const unsigned int pwm6_a_pins[] = {
3397
3398 RCAR_GP_PIN(1, 3),
3399};
3400static const unsigned int pwm6_a_mux[] = {
3401 PWM6_A_MARK,
3402};
3403static const unsigned int pwm6_b_pins[] = {
3404
3405 RCAR_GP_PIN(2, 5),
3406};
3407static const unsigned int pwm6_b_mux[] = {
3408 PWM6_B_MARK,
3409};
3410
3411
3412static const unsigned int qspi0_ctrl_pins[] = {
3413
3414 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3415};
3416static const unsigned int qspi0_ctrl_mux[] = {
3417 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3418};
3419static const unsigned int qspi0_data2_pins[] = {
3420
3421 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3422};
3423static const unsigned int qspi0_data2_mux[] = {
3424 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3425};
3426static const unsigned int qspi0_data4_pins[] = {
3427
3428 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3429
3430 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3431};
3432static const unsigned int qspi0_data4_mux[] = {
3433 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3434 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3435};
3436
3437static const unsigned int qspi1_ctrl_pins[] = {
3438
3439 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3440};
3441static const unsigned int qspi1_ctrl_mux[] = {
3442 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3443};
3444static const unsigned int qspi1_data2_pins[] = {
3445
3446 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3447};
3448static const unsigned int qspi1_data2_mux[] = {
3449 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3450};
3451static const unsigned int qspi1_data4_pins[] = {
3452
3453 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3454
3455 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3456};
3457static const unsigned int qspi1_data4_mux[] = {
3458 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3459 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3460};
3461
3462
3463static const unsigned int sata0_devslp_a_pins[] = {
3464
3465 RCAR_GP_PIN(6, 16),
3466};
3467
3468static const unsigned int sata0_devslp_a_mux[] = {
3469 SATA_DEVSLP_A_MARK,
3470};
3471
3472static const unsigned int sata0_devslp_b_pins[] = {
3473
3474 RCAR_GP_PIN(4, 6),
3475};
3476
3477static const unsigned int sata0_devslp_b_mux[] = {
3478 SATA_DEVSLP_B_MARK,
3479};
3480
3481
3482static const unsigned int scif0_data_pins[] = {
3483
3484 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3485};
3486static const unsigned int scif0_data_mux[] = {
3487 RX0_MARK, TX0_MARK,
3488};
3489static const unsigned int scif0_clk_pins[] = {
3490
3491 RCAR_GP_PIN(5, 0),
3492};
3493static const unsigned int scif0_clk_mux[] = {
3494 SCK0_MARK,
3495};
3496static const unsigned int scif0_ctrl_pins[] = {
3497
3498 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3499};
3500static const unsigned int scif0_ctrl_mux[] = {
3501 RTS0_N_MARK, CTS0_N_MARK,
3502};
3503
3504static const unsigned int scif1_data_a_pins[] = {
3505
3506 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3507};
3508static const unsigned int scif1_data_a_mux[] = {
3509 RX1_A_MARK, TX1_A_MARK,
3510};
3511static const unsigned int scif1_clk_pins[] = {
3512
3513 RCAR_GP_PIN(6, 21),
3514};
3515static const unsigned int scif1_clk_mux[] = {
3516 SCK1_MARK,
3517};
3518static const unsigned int scif1_ctrl_pins[] = {
3519
3520 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3521};
3522static const unsigned int scif1_ctrl_mux[] = {
3523 RTS1_N_MARK, CTS1_N_MARK,
3524};
3525static const unsigned int scif1_data_b_pins[] = {
3526
3527 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3528};
3529static const unsigned int scif1_data_b_mux[] = {
3530 RX1_B_MARK, TX1_B_MARK,
3531};
3532
3533static const unsigned int scif2_data_a_pins[] = {
3534
3535 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3536};
3537static const unsigned int scif2_data_a_mux[] = {
3538 RX2_A_MARK, TX2_A_MARK,
3539};
3540static const unsigned int scif2_clk_pins[] = {
3541
3542 RCAR_GP_PIN(5, 9),
3543};
3544static const unsigned int scif2_clk_mux[] = {
3545 SCK2_MARK,
3546};
3547static const unsigned int scif2_data_b_pins[] = {
3548
3549 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3550};
3551static const unsigned int scif2_data_b_mux[] = {
3552 RX2_B_MARK, TX2_B_MARK,
3553};
3554
3555static const unsigned int scif3_data_a_pins[] = {
3556
3557 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3558};
3559static const unsigned int scif3_data_a_mux[] = {
3560 RX3_A_MARK, TX3_A_MARK,
3561};
3562static const unsigned int scif3_clk_pins[] = {
3563
3564 RCAR_GP_PIN(1, 22),
3565};
3566static const unsigned int scif3_clk_mux[] = {
3567 SCK3_MARK,
3568};
3569static const unsigned int scif3_ctrl_pins[] = {
3570
3571 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3572};
3573static const unsigned int scif3_ctrl_mux[] = {
3574 RTS3_N_MARK, CTS3_N_MARK,
3575};
3576static const unsigned int scif3_data_b_pins[] = {
3577
3578 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3579};
3580static const unsigned int scif3_data_b_mux[] = {
3581 RX3_B_MARK, TX3_B_MARK,
3582};
3583
3584static const unsigned int scif4_data_a_pins[] = {
3585
3586 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3587};
3588static const unsigned int scif4_data_a_mux[] = {
3589 RX4_A_MARK, TX4_A_MARK,
3590};
3591static const unsigned int scif4_clk_a_pins[] = {
3592
3593 RCAR_GP_PIN(2, 10),
3594};
3595static const unsigned int scif4_clk_a_mux[] = {
3596 SCK4_A_MARK,
3597};
3598static const unsigned int scif4_ctrl_a_pins[] = {
3599
3600 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3601};
3602static const unsigned int scif4_ctrl_a_mux[] = {
3603 RTS4_N_A_MARK, CTS4_N_A_MARK,
3604};
3605static const unsigned int scif4_data_b_pins[] = {
3606
3607 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3608};
3609static const unsigned int scif4_data_b_mux[] = {
3610 RX4_B_MARK, TX4_B_MARK,
3611};
3612static const unsigned int scif4_clk_b_pins[] = {
3613
3614 RCAR_GP_PIN(1, 5),
3615};
3616static const unsigned int scif4_clk_b_mux[] = {
3617 SCK4_B_MARK,
3618};
3619static const unsigned int scif4_ctrl_b_pins[] = {
3620
3621 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3622};
3623static const unsigned int scif4_ctrl_b_mux[] = {
3624 RTS4_N_B_MARK, CTS4_N_B_MARK,
3625};
3626static const unsigned int scif4_data_c_pins[] = {
3627
3628 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3629};
3630static const unsigned int scif4_data_c_mux[] = {
3631 RX4_C_MARK, TX4_C_MARK,
3632};
3633static const unsigned int scif4_clk_c_pins[] = {
3634
3635 RCAR_GP_PIN(0, 8),
3636};
3637static const unsigned int scif4_clk_c_mux[] = {
3638 SCK4_C_MARK,
3639};
3640static const unsigned int scif4_ctrl_c_pins[] = {
3641
3642 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3643};
3644static const unsigned int scif4_ctrl_c_mux[] = {
3645 RTS4_N_C_MARK, CTS4_N_C_MARK,
3646};
3647
3648static const unsigned int scif5_data_a_pins[] = {
3649
3650 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3651};
3652static const unsigned int scif5_data_a_mux[] = {
3653 RX5_A_MARK, TX5_A_MARK,
3654};
3655static const unsigned int scif5_clk_a_pins[] = {
3656
3657 RCAR_GP_PIN(6, 21),
3658};
3659static const unsigned int scif5_clk_a_mux[] = {
3660 SCK5_A_MARK,
3661};
3662static const unsigned int scif5_data_b_pins[] = {
3663
3664 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3665};
3666static const unsigned int scif5_data_b_mux[] = {
3667 RX5_B_MARK, TX5_B_MARK,
3668};
3669static const unsigned int scif5_clk_b_pins[] = {
3670
3671 RCAR_GP_PIN(5, 0),
3672};
3673static const unsigned int scif5_clk_b_mux[] = {
3674 SCK5_B_MARK,
3675};
3676
3677static const unsigned int scif_clk_a_pins[] = {
3678
3679 RCAR_GP_PIN(6, 23),
3680};
3681static const unsigned int scif_clk_a_mux[] = {
3682 SCIF_CLK_A_MARK,
3683};
3684static const unsigned int scif_clk_b_pins[] = {
3685
3686 RCAR_GP_PIN(5, 9),
3687};
3688static const unsigned int scif_clk_b_mux[] = {
3689 SCIF_CLK_B_MARK,
3690};
3691
3692
3693static const unsigned int sdhi0_data1_pins[] = {
3694
3695 RCAR_GP_PIN(3, 2),
3696};
3697
3698static const unsigned int sdhi0_data1_mux[] = {
3699 SD0_DAT0_MARK,
3700};
3701
3702static const unsigned int sdhi0_data4_pins[] = {
3703
3704 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3705 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3706};
3707
3708static const unsigned int sdhi0_data4_mux[] = {
3709 SD0_DAT0_MARK, SD0_DAT1_MARK,
3710 SD0_DAT2_MARK, SD0_DAT3_MARK,
3711};
3712
3713static const unsigned int sdhi0_ctrl_pins[] = {
3714
3715 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3716};
3717
3718static const unsigned int sdhi0_ctrl_mux[] = {
3719 SD0_CLK_MARK, SD0_CMD_MARK,
3720};
3721
3722static const unsigned int sdhi0_cd_pins[] = {
3723
3724 RCAR_GP_PIN(3, 12),
3725};
3726
3727static const unsigned int sdhi0_cd_mux[] = {
3728 SD0_CD_MARK,
3729};
3730
3731static const unsigned int sdhi0_wp_pins[] = {
3732
3733 RCAR_GP_PIN(3, 13),
3734};
3735
3736static const unsigned int sdhi0_wp_mux[] = {
3737 SD0_WP_MARK,
3738};
3739
3740
3741static const unsigned int sdhi1_data1_pins[] = {
3742
3743 RCAR_GP_PIN(3, 8),
3744};
3745
3746static const unsigned int sdhi1_data1_mux[] = {
3747 SD1_DAT0_MARK,
3748};
3749
3750static const unsigned int sdhi1_data4_pins[] = {
3751
3752 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3753 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3754};
3755
3756static const unsigned int sdhi1_data4_mux[] = {
3757 SD1_DAT0_MARK, SD1_DAT1_MARK,
3758 SD1_DAT2_MARK, SD1_DAT3_MARK,
3759};
3760
3761static const unsigned int sdhi1_ctrl_pins[] = {
3762
3763 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3764};
3765
3766static const unsigned int sdhi1_ctrl_mux[] = {
3767 SD1_CLK_MARK, SD1_CMD_MARK,
3768};
3769
3770static const unsigned int sdhi1_cd_pins[] = {
3771
3772 RCAR_GP_PIN(3, 14),
3773};
3774
3775static const unsigned int sdhi1_cd_mux[] = {
3776 SD1_CD_MARK,
3777};
3778
3779static const unsigned int sdhi1_wp_pins[] = {
3780
3781 RCAR_GP_PIN(3, 15),
3782};
3783
3784static const unsigned int sdhi1_wp_mux[] = {
3785 SD1_WP_MARK,
3786};
3787
3788
3789static const unsigned int sdhi2_data1_pins[] = {
3790
3791 RCAR_GP_PIN(4, 2),
3792};
3793
3794static const unsigned int sdhi2_data1_mux[] = {
3795 SD2_DAT0_MARK,
3796};
3797
3798static const unsigned int sdhi2_data4_pins[] = {
3799
3800 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3801 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3802};
3803
3804static const unsigned int sdhi2_data4_mux[] = {
3805 SD2_DAT0_MARK, SD2_DAT1_MARK,
3806 SD2_DAT2_MARK, SD2_DAT3_MARK,
3807};
3808
3809static const unsigned int sdhi2_data8_pins[] = {
3810
3811 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3812 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3813 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3814 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3815};
3816
3817static const unsigned int sdhi2_data8_mux[] = {
3818 SD2_DAT0_MARK, SD2_DAT1_MARK,
3819 SD2_DAT2_MARK, SD2_DAT3_MARK,
3820 SD2_DAT4_MARK, SD2_DAT5_MARK,
3821 SD2_DAT6_MARK, SD2_DAT7_MARK,
3822};
3823
3824static const unsigned int sdhi2_ctrl_pins[] = {
3825
3826 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3827};
3828
3829static const unsigned int sdhi2_ctrl_mux[] = {
3830 SD2_CLK_MARK, SD2_CMD_MARK,
3831};
3832
3833static const unsigned int sdhi2_cd_a_pins[] = {
3834
3835 RCAR_GP_PIN(4, 13),
3836};
3837
3838static const unsigned int sdhi2_cd_a_mux[] = {
3839 SD2_CD_A_MARK,
3840};
3841
3842static const unsigned int sdhi2_cd_b_pins[] = {
3843
3844 RCAR_GP_PIN(5, 10),
3845};
3846
3847static const unsigned int sdhi2_cd_b_mux[] = {
3848 SD2_CD_B_MARK,
3849};
3850
3851static const unsigned int sdhi2_wp_a_pins[] = {
3852
3853 RCAR_GP_PIN(4, 14),
3854};
3855
3856static const unsigned int sdhi2_wp_a_mux[] = {
3857 SD2_WP_A_MARK,
3858};
3859
3860static const unsigned int sdhi2_wp_b_pins[] = {
3861
3862 RCAR_GP_PIN(5, 11),
3863};
3864
3865static const unsigned int sdhi2_wp_b_mux[] = {
3866 SD2_WP_B_MARK,
3867};
3868
3869static const unsigned int sdhi2_ds_pins[] = {
3870
3871 RCAR_GP_PIN(4, 6),
3872};
3873
3874static const unsigned int sdhi2_ds_mux[] = {
3875 SD2_DS_MARK,
3876};
3877
3878
3879static const unsigned int sdhi3_data1_pins[] = {
3880
3881 RCAR_GP_PIN(4, 9),
3882};
3883
3884static const unsigned int sdhi3_data1_mux[] = {
3885 SD3_DAT0_MARK,
3886};
3887
3888static const unsigned int sdhi3_data4_pins[] = {
3889
3890 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3891 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3892};
3893
3894static const unsigned int sdhi3_data4_mux[] = {
3895 SD3_DAT0_MARK, SD3_DAT1_MARK,
3896 SD3_DAT2_MARK, SD3_DAT3_MARK,
3897};
3898
3899static const unsigned int sdhi3_data8_pins[] = {
3900
3901 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3902 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3903 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3904 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3905};
3906
3907static const unsigned int sdhi3_data8_mux[] = {
3908 SD3_DAT0_MARK, SD3_DAT1_MARK,
3909 SD3_DAT2_MARK, SD3_DAT3_MARK,
3910 SD3_DAT4_MARK, SD3_DAT5_MARK,
3911 SD3_DAT6_MARK, SD3_DAT7_MARK,
3912};
3913
3914static const unsigned int sdhi3_ctrl_pins[] = {
3915
3916 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3917};
3918
3919static const unsigned int sdhi3_ctrl_mux[] = {
3920 SD3_CLK_MARK, SD3_CMD_MARK,
3921};
3922
3923static const unsigned int sdhi3_cd_pins[] = {
3924
3925 RCAR_GP_PIN(4, 15),
3926};
3927
3928static const unsigned int sdhi3_cd_mux[] = {
3929 SD3_CD_MARK,
3930};
3931
3932static const unsigned int sdhi3_wp_pins[] = {
3933
3934 RCAR_GP_PIN(4, 16),
3935};
3936
3937static const unsigned int sdhi3_wp_mux[] = {
3938 SD3_WP_MARK,
3939};
3940
3941static const unsigned int sdhi3_ds_pins[] = {
3942
3943 RCAR_GP_PIN(4, 17),
3944};
3945
3946static const unsigned int sdhi3_ds_mux[] = {
3947 SD3_DS_MARK,
3948};
3949
3950
3951static const unsigned int ssi0_data_pins[] = {
3952
3953 RCAR_GP_PIN(6, 2),
3954};
3955static const unsigned int ssi0_data_mux[] = {
3956 SSI_SDATA0_MARK,
3957};
3958static const unsigned int ssi01239_ctrl_pins[] = {
3959
3960 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3961};
3962static const unsigned int ssi01239_ctrl_mux[] = {
3963 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3964};
3965static const unsigned int ssi1_data_a_pins[] = {
3966
3967 RCAR_GP_PIN(6, 3),
3968};
3969static const unsigned int ssi1_data_a_mux[] = {
3970 SSI_SDATA1_A_MARK,
3971};
3972static const unsigned int ssi1_data_b_pins[] = {
3973
3974 RCAR_GP_PIN(5, 12),
3975};
3976static const unsigned int ssi1_data_b_mux[] = {
3977 SSI_SDATA1_B_MARK,
3978};
3979static const unsigned int ssi1_ctrl_a_pins[] = {
3980
3981 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3982};
3983static const unsigned int ssi1_ctrl_a_mux[] = {
3984 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3985};
3986static const unsigned int ssi1_ctrl_b_pins[] = {
3987
3988 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3989};
3990static const unsigned int ssi1_ctrl_b_mux[] = {
3991 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3992};
3993static const unsigned int ssi2_data_a_pins[] = {
3994
3995 RCAR_GP_PIN(6, 4),
3996};
3997static const unsigned int ssi2_data_a_mux[] = {
3998 SSI_SDATA2_A_MARK,
3999};
4000static const unsigned int ssi2_data_b_pins[] = {
4001
4002 RCAR_GP_PIN(5, 13),
4003};
4004static const unsigned int ssi2_data_b_mux[] = {
4005 SSI_SDATA2_B_MARK,
4006};
4007static const unsigned int ssi2_ctrl_a_pins[] = {
4008
4009 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
4010};
4011static const unsigned int ssi2_ctrl_a_mux[] = {
4012 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
4013};
4014static const unsigned int ssi2_ctrl_b_pins[] = {
4015
4016 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4017};
4018static const unsigned int ssi2_ctrl_b_mux[] = {
4019 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
4020};
4021static const unsigned int ssi3_data_pins[] = {
4022
4023 RCAR_GP_PIN(6, 7),
4024};
4025static const unsigned int ssi3_data_mux[] = {
4026 SSI_SDATA3_MARK,
4027};
4028static const unsigned int ssi349_ctrl_pins[] = {
4029
4030 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
4031};
4032static const unsigned int ssi349_ctrl_mux[] = {
4033 SSI_SCK349_MARK, SSI_WS349_MARK,
4034};
4035static const unsigned int ssi4_data_pins[] = {
4036
4037 RCAR_GP_PIN(6, 10),
4038};
4039static const unsigned int ssi4_data_mux[] = {
4040 SSI_SDATA4_MARK,
4041};
4042static const unsigned int ssi4_ctrl_pins[] = {
4043
4044 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
4045};
4046static const unsigned int ssi4_ctrl_mux[] = {
4047 SSI_SCK4_MARK, SSI_WS4_MARK,
4048};
4049static const unsigned int ssi5_data_pins[] = {
4050
4051 RCAR_GP_PIN(6, 13),
4052};
4053static const unsigned int ssi5_data_mux[] = {
4054 SSI_SDATA5_MARK,
4055};
4056static const unsigned int ssi5_ctrl_pins[] = {
4057
4058 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
4059};
4060static const unsigned int ssi5_ctrl_mux[] = {
4061 SSI_SCK5_MARK, SSI_WS5_MARK,
4062};
4063static const unsigned int ssi6_data_pins[] = {
4064
4065 RCAR_GP_PIN(6, 16),
4066};
4067static const unsigned int ssi6_data_mux[] = {
4068 SSI_SDATA6_MARK,
4069};
4070static const unsigned int ssi6_ctrl_pins[] = {
4071
4072 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
4073};
4074static const unsigned int ssi6_ctrl_mux[] = {
4075 SSI_SCK6_MARK, SSI_WS6_MARK,
4076};
4077static const unsigned int ssi7_data_pins[] = {
4078
4079 RCAR_GP_PIN(6, 19),
4080};
4081static const unsigned int ssi7_data_mux[] = {
4082 SSI_SDATA7_MARK,
4083};
4084static const unsigned int ssi78_ctrl_pins[] = {
4085
4086 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
4087};
4088static const unsigned int ssi78_ctrl_mux[] = {
4089 SSI_SCK78_MARK, SSI_WS78_MARK,
4090};
4091static const unsigned int ssi8_data_pins[] = {
4092
4093 RCAR_GP_PIN(6, 20),
4094};
4095static const unsigned int ssi8_data_mux[] = {
4096 SSI_SDATA8_MARK,
4097};
4098static const unsigned int ssi9_data_a_pins[] = {
4099
4100 RCAR_GP_PIN(6, 21),
4101};
4102static const unsigned int ssi9_data_a_mux[] = {
4103 SSI_SDATA9_A_MARK,
4104};
4105static const unsigned int ssi9_data_b_pins[] = {
4106
4107 RCAR_GP_PIN(5, 14),
4108};
4109static const unsigned int ssi9_data_b_mux[] = {
4110 SSI_SDATA9_B_MARK,
4111};
4112static const unsigned int ssi9_ctrl_a_pins[] = {
4113
4114 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
4115};
4116static const unsigned int ssi9_ctrl_a_mux[] = {
4117 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
4118};
4119static const unsigned int ssi9_ctrl_b_pins[] = {
4120
4121 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
4122};
4123static const unsigned int ssi9_ctrl_b_mux[] = {
4124 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4125};
4126
4127
4128static const unsigned int tmu_tclk1_a_pins[] = {
4129
4130 RCAR_GP_PIN(6, 23),
4131};
4132
4133static const unsigned int tmu_tclk1_a_mux[] = {
4134 TCLK1_A_MARK,
4135};
4136
4137static const unsigned int tmu_tclk1_b_pins[] = {
4138
4139 RCAR_GP_PIN(5, 19),
4140};
4141
4142static const unsigned int tmu_tclk1_b_mux[] = {
4143 TCLK1_B_MARK,
4144};
4145
4146static const unsigned int tmu_tclk2_a_pins[] = {
4147
4148 RCAR_GP_PIN(6, 19),
4149};
4150
4151static const unsigned int tmu_tclk2_a_mux[] = {
4152 TCLK2_A_MARK,
4153};
4154
4155static const unsigned int tmu_tclk2_b_pins[] = {
4156
4157 RCAR_GP_PIN(6, 28),
4158};
4159
4160static const unsigned int tmu_tclk2_b_mux[] = {
4161 TCLK2_B_MARK,
4162};
4163
4164
4165static const unsigned int tpu_to0_pins[] = {
4166
4167 RCAR_GP_PIN(6, 28),
4168};
4169static const unsigned int tpu_to0_mux[] = {
4170 TPU0TO0_MARK,
4171};
4172static const unsigned int tpu_to1_pins[] = {
4173
4174 RCAR_GP_PIN(6, 29),
4175};
4176static const unsigned int tpu_to1_mux[] = {
4177 TPU0TO1_MARK,
4178};
4179static const unsigned int tpu_to2_pins[] = {
4180
4181 RCAR_GP_PIN(6, 30),
4182};
4183static const unsigned int tpu_to2_mux[] = {
4184 TPU0TO2_MARK,
4185};
4186static const unsigned int tpu_to3_pins[] = {
4187
4188 RCAR_GP_PIN(6, 31),
4189};
4190static const unsigned int tpu_to3_mux[] = {
4191 TPU0TO3_MARK,
4192};
4193
4194
4195static const unsigned int usb0_pins[] = {
4196
4197 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4198};
4199
4200static const unsigned int usb0_mux[] = {
4201 USB0_PWEN_MARK, USB0_OVC_MARK,
4202};
4203
4204
4205static const unsigned int usb1_pins[] = {
4206
4207 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4208};
4209
4210static const unsigned int usb1_mux[] = {
4211 USB1_PWEN_MARK, USB1_OVC_MARK,
4212};
4213
4214
4215static const unsigned int usb30_pins[] = {
4216
4217 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4218};
4219
4220static const unsigned int usb30_mux[] = {
4221 USB30_PWEN_MARK, USB30_OVC_MARK,
4222};
4223
4224
4225static const unsigned int vin4_data18_a_pins[] = {
4226 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4227 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4228 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4229 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4230 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4231 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4232 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4233 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4234 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4235};
4236
4237static const unsigned int vin4_data18_a_mux[] = {
4238 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4239 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4240 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4241 VI4_DATA10_MARK, VI4_DATA11_MARK,
4242 VI4_DATA12_MARK, VI4_DATA13_MARK,
4243 VI4_DATA14_MARK, VI4_DATA15_MARK,
4244 VI4_DATA18_MARK, VI4_DATA19_MARK,
4245 VI4_DATA20_MARK, VI4_DATA21_MARK,
4246 VI4_DATA22_MARK, VI4_DATA23_MARK,
4247};
4248
4249static const union vin_data vin4_data_a_pins = {
4250 .data24 = {
4251 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4252 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4253 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4254 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4255 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4256 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4257 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4258 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4259 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4260 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4261 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4262 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4263 },
4264};
4265
4266static const union vin_data vin4_data_a_mux = {
4267 .data24 = {
4268 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4269 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4270 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4271 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4272 VI4_DATA8_MARK, VI4_DATA9_MARK,
4273 VI4_DATA10_MARK, VI4_DATA11_MARK,
4274 VI4_DATA12_MARK, VI4_DATA13_MARK,
4275 VI4_DATA14_MARK, VI4_DATA15_MARK,
4276 VI4_DATA16_MARK, VI4_DATA17_MARK,
4277 VI4_DATA18_MARK, VI4_DATA19_MARK,
4278 VI4_DATA20_MARK, VI4_DATA21_MARK,
4279 VI4_DATA22_MARK, VI4_DATA23_MARK,
4280 },
4281};
4282
4283static const unsigned int vin4_data18_b_pins[] = {
4284 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4285 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4286 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4287 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4288 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4289 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4290 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4291 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4292 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4293};
4294
4295static const unsigned int vin4_data18_b_mux[] = {
4296 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4297 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4298 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4299 VI4_DATA10_MARK, VI4_DATA11_MARK,
4300 VI4_DATA12_MARK, VI4_DATA13_MARK,
4301 VI4_DATA14_MARK, VI4_DATA15_MARK,
4302 VI4_DATA18_MARK, VI4_DATA19_MARK,
4303 VI4_DATA20_MARK, VI4_DATA21_MARK,
4304 VI4_DATA22_MARK, VI4_DATA23_MARK,
4305};
4306
4307static const union vin_data vin4_data_b_pins = {
4308 .data24 = {
4309 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4310 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4311 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4312 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4313 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4314 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4315 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4316 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4317 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4318 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4319 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4320 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4321 },
4322};
4323
4324static const union vin_data vin4_data_b_mux = {
4325 .data24 = {
4326 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4327 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4328 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4329 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4330 VI4_DATA8_MARK, VI4_DATA9_MARK,
4331 VI4_DATA10_MARK, VI4_DATA11_MARK,
4332 VI4_DATA12_MARK, VI4_DATA13_MARK,
4333 VI4_DATA14_MARK, VI4_DATA15_MARK,
4334 VI4_DATA16_MARK, VI4_DATA17_MARK,
4335 VI4_DATA18_MARK, VI4_DATA19_MARK,
4336 VI4_DATA20_MARK, VI4_DATA21_MARK,
4337 VI4_DATA22_MARK, VI4_DATA23_MARK,
4338 },
4339};
4340
4341static const unsigned int vin4_sync_pins[] = {
4342
4343 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
4344};
4345
4346static const unsigned int vin4_sync_mux[] = {
4347 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4348};
4349
4350static const unsigned int vin4_field_pins[] = {
4351 RCAR_GP_PIN(1, 16),
4352};
4353
4354static const unsigned int vin4_field_mux[] = {
4355 VI4_FIELD_MARK,
4356};
4357
4358static const unsigned int vin4_clkenb_pins[] = {
4359 RCAR_GP_PIN(1, 19),
4360};
4361
4362static const unsigned int vin4_clkenb_mux[] = {
4363 VI4_CLKENB_MARK,
4364};
4365
4366static const unsigned int vin4_clk_pins[] = {
4367 RCAR_GP_PIN(1, 27),
4368};
4369
4370static const unsigned int vin4_clk_mux[] = {
4371 VI4_CLK_MARK,
4372};
4373
4374
4375static const union vin_data16 vin5_data_pins = {
4376 .data16 = {
4377 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4378 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4379 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4380 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4381 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4382 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4383 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4384 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4385 },
4386};
4387
4388static const union vin_data16 vin5_data_mux = {
4389 .data16 = {
4390 VI5_DATA0_MARK, VI5_DATA1_MARK,
4391 VI5_DATA2_MARK, VI5_DATA3_MARK,
4392 VI5_DATA4_MARK, VI5_DATA5_MARK,
4393 VI5_DATA6_MARK, VI5_DATA7_MARK,
4394 VI5_DATA8_MARK, VI5_DATA9_MARK,
4395 VI5_DATA10_MARK, VI5_DATA11_MARK,
4396 VI5_DATA12_MARK, VI5_DATA13_MARK,
4397 VI5_DATA14_MARK, VI5_DATA15_MARK,
4398 },
4399};
4400
4401static const unsigned int vin5_sync_pins[] = {
4402
4403 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
4404};
4405
4406static const unsigned int vin5_sync_mux[] = {
4407 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4408};
4409
4410static const unsigned int vin5_field_pins[] = {
4411 RCAR_GP_PIN(1, 11),
4412};
4413
4414static const unsigned int vin5_field_mux[] = {
4415 VI5_FIELD_MARK,
4416};
4417
4418static const unsigned int vin5_clkenb_pins[] = {
4419 RCAR_GP_PIN(1, 20),
4420};
4421
4422static const unsigned int vin5_clkenb_mux[] = {
4423 VI5_CLKENB_MARK,
4424};
4425
4426static const unsigned int vin5_clk_pins[] = {
4427 RCAR_GP_PIN(1, 21),
4428};
4429
4430static const unsigned int vin5_clk_mux[] = {
4431 VI5_CLK_MARK,
4432};
4433
4434static const struct {
4435 struct sh_pfc_pin_group common[324];
4436#ifdef CONFIG_PINCTRL_PFC_R8A77965
4437 struct sh_pfc_pin_group automotive[30];
4438#endif
4439} pinmux_groups = {
4440 .common = {
4441 SH_PFC_PIN_GROUP(audio_clk_a_a),
4442 SH_PFC_PIN_GROUP(audio_clk_a_b),
4443 SH_PFC_PIN_GROUP(audio_clk_a_c),
4444 SH_PFC_PIN_GROUP(audio_clk_b_a),
4445 SH_PFC_PIN_GROUP(audio_clk_b_b),
4446 SH_PFC_PIN_GROUP(audio_clk_c_a),
4447 SH_PFC_PIN_GROUP(audio_clk_c_b),
4448 SH_PFC_PIN_GROUP(audio_clkout_a),
4449 SH_PFC_PIN_GROUP(audio_clkout_b),
4450 SH_PFC_PIN_GROUP(audio_clkout_c),
4451 SH_PFC_PIN_GROUP(audio_clkout_d),
4452 SH_PFC_PIN_GROUP(audio_clkout1_a),
4453 SH_PFC_PIN_GROUP(audio_clkout1_b),
4454 SH_PFC_PIN_GROUP(audio_clkout2_a),
4455 SH_PFC_PIN_GROUP(audio_clkout2_b),
4456 SH_PFC_PIN_GROUP(audio_clkout3_a),
4457 SH_PFC_PIN_GROUP(audio_clkout3_b),
4458 SH_PFC_PIN_GROUP(avb_link),
4459 SH_PFC_PIN_GROUP(avb_magic),
4460 SH_PFC_PIN_GROUP(avb_phy_int),
4461 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),
4462 SH_PFC_PIN_GROUP(avb_mdio),
4463 SH_PFC_PIN_GROUP(avb_mii),
4464 SH_PFC_PIN_GROUP(avb_avtp_pps),
4465 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4466 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4467 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4468 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4469 SH_PFC_PIN_GROUP(can0_data_a),
4470 SH_PFC_PIN_GROUP(can0_data_b),
4471 SH_PFC_PIN_GROUP(can1_data),
4472 SH_PFC_PIN_GROUP(can_clk),
4473 SH_PFC_PIN_GROUP(canfd0_data_a),
4474 SH_PFC_PIN_GROUP(canfd0_data_b),
4475 SH_PFC_PIN_GROUP(canfd1_data),
4476 SH_PFC_PIN_GROUP(du_rgb666),
4477 SH_PFC_PIN_GROUP(du_rgb888),
4478 SH_PFC_PIN_GROUP(du_clk_out_0),
4479 SH_PFC_PIN_GROUP(du_clk_out_1),
4480 SH_PFC_PIN_GROUP(du_sync),
4481 SH_PFC_PIN_GROUP(du_oddf),
4482 SH_PFC_PIN_GROUP(du_cde),
4483 SH_PFC_PIN_GROUP(du_disp),
4484 SH_PFC_PIN_GROUP(hscif0_data),
4485 SH_PFC_PIN_GROUP(hscif0_clk),
4486 SH_PFC_PIN_GROUP(hscif0_ctrl),
4487 SH_PFC_PIN_GROUP(hscif1_data_a),
4488 SH_PFC_PIN_GROUP(hscif1_clk_a),
4489 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4490 SH_PFC_PIN_GROUP(hscif1_data_b),
4491 SH_PFC_PIN_GROUP(hscif1_clk_b),
4492 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4493 SH_PFC_PIN_GROUP(hscif2_data_a),
4494 SH_PFC_PIN_GROUP(hscif2_clk_a),
4495 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4496 SH_PFC_PIN_GROUP(hscif2_data_b),
4497 SH_PFC_PIN_GROUP(hscif2_clk_b),
4498 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4499 SH_PFC_PIN_GROUP(hscif2_data_c),
4500 SH_PFC_PIN_GROUP(hscif2_clk_c),
4501 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4502 SH_PFC_PIN_GROUP(hscif3_data_a),
4503 SH_PFC_PIN_GROUP(hscif3_clk),
4504 SH_PFC_PIN_GROUP(hscif3_ctrl),
4505 SH_PFC_PIN_GROUP(hscif3_data_b),
4506 SH_PFC_PIN_GROUP(hscif3_data_c),
4507 SH_PFC_PIN_GROUP(hscif3_data_d),
4508 SH_PFC_PIN_GROUP(hscif4_data_a),
4509 SH_PFC_PIN_GROUP(hscif4_clk),
4510 SH_PFC_PIN_GROUP(hscif4_ctrl),
4511 SH_PFC_PIN_GROUP(hscif4_data_b),
4512 SH_PFC_PIN_GROUP(i2c0),
4513 SH_PFC_PIN_GROUP(i2c1_a),
4514 SH_PFC_PIN_GROUP(i2c1_b),
4515 SH_PFC_PIN_GROUP(i2c2_a),
4516 SH_PFC_PIN_GROUP(i2c2_b),
4517 SH_PFC_PIN_GROUP(i2c3),
4518 SH_PFC_PIN_GROUP(i2c5),
4519 SH_PFC_PIN_GROUP(i2c6_a),
4520 SH_PFC_PIN_GROUP(i2c6_b),
4521 SH_PFC_PIN_GROUP(i2c6_c),
4522 SH_PFC_PIN_GROUP(intc_ex_irq0),
4523 SH_PFC_PIN_GROUP(intc_ex_irq1),
4524 SH_PFC_PIN_GROUP(intc_ex_irq2),
4525 SH_PFC_PIN_GROUP(intc_ex_irq3),
4526 SH_PFC_PIN_GROUP(intc_ex_irq4),
4527 SH_PFC_PIN_GROUP(intc_ex_irq5),
4528 SH_PFC_PIN_GROUP(msiof0_clk),
4529 SH_PFC_PIN_GROUP(msiof0_sync),
4530 SH_PFC_PIN_GROUP(msiof0_ss1),
4531 SH_PFC_PIN_GROUP(msiof0_ss2),
4532 SH_PFC_PIN_GROUP(msiof0_txd),
4533 SH_PFC_PIN_GROUP(msiof0_rxd),
4534 SH_PFC_PIN_GROUP(msiof1_clk_a),
4535 SH_PFC_PIN_GROUP(msiof1_sync_a),
4536 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4537 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4538 SH_PFC_PIN_GROUP(msiof1_txd_a),
4539 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4540 SH_PFC_PIN_GROUP(msiof1_clk_b),
4541 SH_PFC_PIN_GROUP(msiof1_sync_b),
4542 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4543 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4544 SH_PFC_PIN_GROUP(msiof1_txd_b),
4545 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4546 SH_PFC_PIN_GROUP(msiof1_clk_c),
4547 SH_PFC_PIN_GROUP(msiof1_sync_c),
4548 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4549 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4550 SH_PFC_PIN_GROUP(msiof1_txd_c),
4551 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4552 SH_PFC_PIN_GROUP(msiof1_clk_d),
4553 SH_PFC_PIN_GROUP(msiof1_sync_d),
4554 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4555 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4556 SH_PFC_PIN_GROUP(msiof1_txd_d),
4557 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4558 SH_PFC_PIN_GROUP(msiof1_clk_e),
4559 SH_PFC_PIN_GROUP(msiof1_sync_e),
4560 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4561 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4562 SH_PFC_PIN_GROUP(msiof1_txd_e),
4563 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4564 SH_PFC_PIN_GROUP(msiof1_clk_f),
4565 SH_PFC_PIN_GROUP(msiof1_sync_f),
4566 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4567 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4568 SH_PFC_PIN_GROUP(msiof1_txd_f),
4569 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4570 SH_PFC_PIN_GROUP(msiof1_clk_g),
4571 SH_PFC_PIN_GROUP(msiof1_sync_g),
4572 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4573 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4574 SH_PFC_PIN_GROUP(msiof1_txd_g),
4575 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4576 SH_PFC_PIN_GROUP(msiof2_clk_a),
4577 SH_PFC_PIN_GROUP(msiof2_sync_a),
4578 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4579 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4580 SH_PFC_PIN_GROUP(msiof2_txd_a),
4581 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4582 SH_PFC_PIN_GROUP(msiof2_clk_b),
4583 SH_PFC_PIN_GROUP(msiof2_sync_b),
4584 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4585 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4586 SH_PFC_PIN_GROUP(msiof2_txd_b),
4587 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4588 SH_PFC_PIN_GROUP(msiof2_clk_c),
4589 SH_PFC_PIN_GROUP(msiof2_sync_c),
4590 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4591 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4592 SH_PFC_PIN_GROUP(msiof2_txd_c),
4593 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4594 SH_PFC_PIN_GROUP(msiof2_clk_d),
4595 SH_PFC_PIN_GROUP(msiof2_sync_d),
4596 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4597 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4598 SH_PFC_PIN_GROUP(msiof2_txd_d),
4599 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4600 SH_PFC_PIN_GROUP(msiof3_clk_a),
4601 SH_PFC_PIN_GROUP(msiof3_sync_a),
4602 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4603 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4604 SH_PFC_PIN_GROUP(msiof3_txd_a),
4605 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4606 SH_PFC_PIN_GROUP(msiof3_clk_b),
4607 SH_PFC_PIN_GROUP(msiof3_sync_b),
4608 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4609 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4610 SH_PFC_PIN_GROUP(msiof3_txd_b),
4611 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4612 SH_PFC_PIN_GROUP(msiof3_clk_c),
4613 SH_PFC_PIN_GROUP(msiof3_sync_c),
4614 SH_PFC_PIN_GROUP(msiof3_txd_c),
4615 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4616 SH_PFC_PIN_GROUP(msiof3_clk_d),
4617 SH_PFC_PIN_GROUP(msiof3_sync_d),
4618 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4619 SH_PFC_PIN_GROUP(msiof3_txd_d),
4620 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4621 SH_PFC_PIN_GROUP(msiof3_clk_e),
4622 SH_PFC_PIN_GROUP(msiof3_sync_e),
4623 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4624 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4625 SH_PFC_PIN_GROUP(msiof3_txd_e),
4626 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4627 SH_PFC_PIN_GROUP(pwm0),
4628 SH_PFC_PIN_GROUP(pwm1_a),
4629 SH_PFC_PIN_GROUP(pwm1_b),
4630 SH_PFC_PIN_GROUP(pwm2_a),
4631 SH_PFC_PIN_GROUP(pwm2_b),
4632 SH_PFC_PIN_GROUP(pwm3_a),
4633 SH_PFC_PIN_GROUP(pwm3_b),
4634 SH_PFC_PIN_GROUP(pwm4_a),
4635 SH_PFC_PIN_GROUP(pwm4_b),
4636 SH_PFC_PIN_GROUP(pwm5_a),
4637 SH_PFC_PIN_GROUP(pwm5_b),
4638 SH_PFC_PIN_GROUP(pwm6_a),
4639 SH_PFC_PIN_GROUP(pwm6_b),
4640 SH_PFC_PIN_GROUP(qspi0_ctrl),
4641 SH_PFC_PIN_GROUP(qspi0_data2),
4642 SH_PFC_PIN_GROUP(qspi0_data4),
4643 SH_PFC_PIN_GROUP(qspi1_ctrl),
4644 SH_PFC_PIN_GROUP(qspi1_data2),
4645 SH_PFC_PIN_GROUP(qspi1_data4),
4646 SH_PFC_PIN_GROUP(sata0_devslp_a),
4647 SH_PFC_PIN_GROUP(sata0_devslp_b),
4648 SH_PFC_PIN_GROUP(scif0_data),
4649 SH_PFC_PIN_GROUP(scif0_clk),
4650 SH_PFC_PIN_GROUP(scif0_ctrl),
4651 SH_PFC_PIN_GROUP(scif1_data_a),
4652 SH_PFC_PIN_GROUP(scif1_clk),
4653 SH_PFC_PIN_GROUP(scif1_ctrl),
4654 SH_PFC_PIN_GROUP(scif1_data_b),
4655 SH_PFC_PIN_GROUP(scif2_data_a),
4656 SH_PFC_PIN_GROUP(scif2_clk),
4657 SH_PFC_PIN_GROUP(scif2_data_b),
4658 SH_PFC_PIN_GROUP(scif3_data_a),
4659 SH_PFC_PIN_GROUP(scif3_clk),
4660 SH_PFC_PIN_GROUP(scif3_ctrl),
4661 SH_PFC_PIN_GROUP(scif3_data_b),
4662 SH_PFC_PIN_GROUP(scif4_data_a),
4663 SH_PFC_PIN_GROUP(scif4_clk_a),
4664 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4665 SH_PFC_PIN_GROUP(scif4_data_b),
4666 SH_PFC_PIN_GROUP(scif4_clk_b),
4667 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4668 SH_PFC_PIN_GROUP(scif4_data_c),
4669 SH_PFC_PIN_GROUP(scif4_clk_c),
4670 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4671 SH_PFC_PIN_GROUP(scif5_data_a),
4672 SH_PFC_PIN_GROUP(scif5_clk_a),
4673 SH_PFC_PIN_GROUP(scif5_data_b),
4674 SH_PFC_PIN_GROUP(scif5_clk_b),
4675 SH_PFC_PIN_GROUP(scif_clk_a),
4676 SH_PFC_PIN_GROUP(scif_clk_b),
4677 SH_PFC_PIN_GROUP(sdhi0_data1),
4678 SH_PFC_PIN_GROUP(sdhi0_data4),
4679 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4680 SH_PFC_PIN_GROUP(sdhi0_cd),
4681 SH_PFC_PIN_GROUP(sdhi0_wp),
4682 SH_PFC_PIN_GROUP(sdhi1_data1),
4683 SH_PFC_PIN_GROUP(sdhi1_data4),
4684 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4685 SH_PFC_PIN_GROUP(sdhi1_cd),
4686 SH_PFC_PIN_GROUP(sdhi1_wp),
4687 SH_PFC_PIN_GROUP(sdhi2_data1),
4688 SH_PFC_PIN_GROUP(sdhi2_data4),
4689 SH_PFC_PIN_GROUP(sdhi2_data8),
4690 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4691 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4692 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4693 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4694 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4695 SH_PFC_PIN_GROUP(sdhi2_ds),
4696 SH_PFC_PIN_GROUP(sdhi3_data1),
4697 SH_PFC_PIN_GROUP(sdhi3_data4),
4698 SH_PFC_PIN_GROUP(sdhi3_data8),
4699 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4700 SH_PFC_PIN_GROUP(sdhi3_cd),
4701 SH_PFC_PIN_GROUP(sdhi3_wp),
4702 SH_PFC_PIN_GROUP(sdhi3_ds),
4703 SH_PFC_PIN_GROUP(ssi0_data),
4704 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4705 SH_PFC_PIN_GROUP(ssi1_data_a),
4706 SH_PFC_PIN_GROUP(ssi1_data_b),
4707 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4708 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4709 SH_PFC_PIN_GROUP(ssi2_data_a),
4710 SH_PFC_PIN_GROUP(ssi2_data_b),
4711 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4712 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4713 SH_PFC_PIN_GROUP(ssi3_data),
4714 SH_PFC_PIN_GROUP(ssi349_ctrl),
4715 SH_PFC_PIN_GROUP(ssi4_data),
4716 SH_PFC_PIN_GROUP(ssi4_ctrl),
4717 SH_PFC_PIN_GROUP(ssi5_data),
4718 SH_PFC_PIN_GROUP(ssi5_ctrl),
4719 SH_PFC_PIN_GROUP(ssi6_data),
4720 SH_PFC_PIN_GROUP(ssi6_ctrl),
4721 SH_PFC_PIN_GROUP(ssi7_data),
4722 SH_PFC_PIN_GROUP(ssi78_ctrl),
4723 SH_PFC_PIN_GROUP(ssi8_data),
4724 SH_PFC_PIN_GROUP(ssi9_data_a),
4725 SH_PFC_PIN_GROUP(ssi9_data_b),
4726 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4727 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4728 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4729 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4730 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4731 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4732 SH_PFC_PIN_GROUP(tpu_to0),
4733 SH_PFC_PIN_GROUP(tpu_to1),
4734 SH_PFC_PIN_GROUP(tpu_to2),
4735 SH_PFC_PIN_GROUP(tpu_to3),
4736 SH_PFC_PIN_GROUP(usb0),
4737 SH_PFC_PIN_GROUP(usb1),
4738 SH_PFC_PIN_GROUP(usb30),
4739 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4740 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4741 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4742 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4743 SH_PFC_PIN_GROUP(vin4_data18_a),
4744 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4745 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4746 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4747 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4748 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4749 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4750 SH_PFC_PIN_GROUP(vin4_data18_b),
4751 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4752 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4753 SH_PFC_PIN_GROUP(vin4_sync),
4754 SH_PFC_PIN_GROUP(vin4_field),
4755 SH_PFC_PIN_GROUP(vin4_clkenb),
4756 SH_PFC_PIN_GROUP(vin4_clk),
4757 VIN_DATA_PIN_GROUP(vin5_data, 8),
4758 VIN_DATA_PIN_GROUP(vin5_data, 10),
4759 VIN_DATA_PIN_GROUP(vin5_data, 12),
4760 VIN_DATA_PIN_GROUP(vin5_data, 16),
4761 SH_PFC_PIN_GROUP(vin5_sync),
4762 SH_PFC_PIN_GROUP(vin5_field),
4763 SH_PFC_PIN_GROUP(vin5_clkenb),
4764 SH_PFC_PIN_GROUP(vin5_clk),
4765 },
4766#ifdef CONFIG_PINCTRL_PFC_R8A77965
4767 .automotive = {
4768 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4769 SH_PFC_PIN_GROUP(drif0_data0_a),
4770 SH_PFC_PIN_GROUP(drif0_data1_a),
4771 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4772 SH_PFC_PIN_GROUP(drif0_data0_b),
4773 SH_PFC_PIN_GROUP(drif0_data1_b),
4774 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4775 SH_PFC_PIN_GROUP(drif0_data0_c),
4776 SH_PFC_PIN_GROUP(drif0_data1_c),
4777 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4778 SH_PFC_PIN_GROUP(drif1_data0_a),
4779 SH_PFC_PIN_GROUP(drif1_data1_a),
4780 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4781 SH_PFC_PIN_GROUP(drif1_data0_b),
4782 SH_PFC_PIN_GROUP(drif1_data1_b),
4783 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4784 SH_PFC_PIN_GROUP(drif1_data0_c),
4785 SH_PFC_PIN_GROUP(drif1_data1_c),
4786 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4787 SH_PFC_PIN_GROUP(drif2_data0_a),
4788 SH_PFC_PIN_GROUP(drif2_data1_a),
4789 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4790 SH_PFC_PIN_GROUP(drif2_data0_b),
4791 SH_PFC_PIN_GROUP(drif2_data1_b),
4792 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4793 SH_PFC_PIN_GROUP(drif3_data0_a),
4794 SH_PFC_PIN_GROUP(drif3_data1_a),
4795 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4796 SH_PFC_PIN_GROUP(drif3_data0_b),
4797 SH_PFC_PIN_GROUP(drif3_data1_b),
4798 }
4799#endif
4800};
4801
4802static const char * const audio_clk_groups[] = {
4803 "audio_clk_a_a",
4804 "audio_clk_a_b",
4805 "audio_clk_a_c",
4806 "audio_clk_b_a",
4807 "audio_clk_b_b",
4808 "audio_clk_c_a",
4809 "audio_clk_c_b",
4810 "audio_clkout_a",
4811 "audio_clkout_b",
4812 "audio_clkout_c",
4813 "audio_clkout_d",
4814 "audio_clkout1_a",
4815 "audio_clkout1_b",
4816 "audio_clkout2_a",
4817 "audio_clkout2_b",
4818 "audio_clkout3_a",
4819 "audio_clkout3_b",
4820};
4821
4822static const char * const avb_groups[] = {
4823 "avb_link",
4824 "avb_magic",
4825 "avb_phy_int",
4826 "avb_mdc",
4827 "avb_mdio",
4828 "avb_mii",
4829 "avb_avtp_pps",
4830 "avb_avtp_match_a",
4831 "avb_avtp_capture_a",
4832 "avb_avtp_match_b",
4833 "avb_avtp_capture_b",
4834};
4835
4836static const char * const can0_groups[] = {
4837 "can0_data_a",
4838 "can0_data_b",
4839};
4840
4841static const char * const can1_groups[] = {
4842 "can1_data",
4843};
4844
4845static const char * const can_clk_groups[] = {
4846 "can_clk",
4847};
4848
4849static const char * const canfd0_groups[] = {
4850 "canfd0_data_a",
4851 "canfd0_data_b",
4852};
4853
4854static const char * const canfd1_groups[] = {
4855 "canfd1_data",
4856};
4857
4858#ifdef CONFIG_PINCTRL_PFC_R8A77965
4859static const char * const drif0_groups[] = {
4860 "drif0_ctrl_a",
4861 "drif0_data0_a",
4862 "drif0_data1_a",
4863 "drif0_ctrl_b",
4864 "drif0_data0_b",
4865 "drif0_data1_b",
4866 "drif0_ctrl_c",
4867 "drif0_data0_c",
4868 "drif0_data1_c",
4869};
4870
4871static const char * const drif1_groups[] = {
4872 "drif1_ctrl_a",
4873 "drif1_data0_a",
4874 "drif1_data1_a",
4875 "drif1_ctrl_b",
4876 "drif1_data0_b",
4877 "drif1_data1_b",
4878 "drif1_ctrl_c",
4879 "drif1_data0_c",
4880 "drif1_data1_c",
4881};
4882
4883static const char * const drif2_groups[] = {
4884 "drif2_ctrl_a",
4885 "drif2_data0_a",
4886 "drif2_data1_a",
4887 "drif2_ctrl_b",
4888 "drif2_data0_b",
4889 "drif2_data1_b",
4890};
4891
4892static const char * const drif3_groups[] = {
4893 "drif3_ctrl_a",
4894 "drif3_data0_a",
4895 "drif3_data1_a",
4896 "drif3_ctrl_b",
4897 "drif3_data0_b",
4898 "drif3_data1_b",
4899};
4900#endif
4901
4902static const char * const du_groups[] = {
4903 "du_rgb666",
4904 "du_rgb888",
4905 "du_clk_out_0",
4906 "du_clk_out_1",
4907 "du_sync",
4908 "du_oddf",
4909 "du_cde",
4910 "du_disp",
4911};
4912
4913static const char * const hscif0_groups[] = {
4914 "hscif0_data",
4915 "hscif0_clk",
4916 "hscif0_ctrl",
4917};
4918
4919static const char * const hscif1_groups[] = {
4920 "hscif1_data_a",
4921 "hscif1_clk_a",
4922 "hscif1_ctrl_a",
4923 "hscif1_data_b",
4924 "hscif1_clk_b",
4925 "hscif1_ctrl_b",
4926};
4927
4928static const char * const hscif2_groups[] = {
4929 "hscif2_data_a",
4930 "hscif2_clk_a",
4931 "hscif2_ctrl_a",
4932 "hscif2_data_b",
4933 "hscif2_clk_b",
4934 "hscif2_ctrl_b",
4935 "hscif2_data_c",
4936 "hscif2_clk_c",
4937 "hscif2_ctrl_c",
4938};
4939
4940static const char * const hscif3_groups[] = {
4941 "hscif3_data_a",
4942 "hscif3_clk",
4943 "hscif3_ctrl",
4944 "hscif3_data_b",
4945 "hscif3_data_c",
4946 "hscif3_data_d",
4947};
4948
4949static const char * const hscif4_groups[] = {
4950 "hscif4_data_a",
4951 "hscif4_clk",
4952 "hscif4_ctrl",
4953 "hscif4_data_b",
4954};
4955
4956static const char * const i2c0_groups[] = {
4957 "i2c0",
4958};
4959
4960static const char * const i2c1_groups[] = {
4961 "i2c1_a",
4962 "i2c1_b",
4963};
4964
4965static const char * const i2c2_groups[] = {
4966 "i2c2_a",
4967 "i2c2_b",
4968};
4969
4970static const char * const i2c3_groups[] = {
4971 "i2c3",
4972};
4973
4974static const char * const i2c5_groups[] = {
4975 "i2c5",
4976};
4977
4978static const char * const i2c6_groups[] = {
4979 "i2c6_a",
4980 "i2c6_b",
4981 "i2c6_c",
4982};
4983
4984static const char * const intc_ex_groups[] = {
4985 "intc_ex_irq0",
4986 "intc_ex_irq1",
4987 "intc_ex_irq2",
4988 "intc_ex_irq3",
4989 "intc_ex_irq4",
4990 "intc_ex_irq5",
4991};
4992
4993static const char * const msiof0_groups[] = {
4994 "msiof0_clk",
4995 "msiof0_sync",
4996 "msiof0_ss1",
4997 "msiof0_ss2",
4998 "msiof0_txd",
4999 "msiof0_rxd",
5000};
5001
5002static const char * const msiof1_groups[] = {
5003 "msiof1_clk_a",
5004 "msiof1_sync_a",
5005 "msiof1_ss1_a",
5006 "msiof1_ss2_a",
5007 "msiof1_txd_a",
5008 "msiof1_rxd_a",
5009 "msiof1_clk_b",
5010 "msiof1_sync_b",
5011 "msiof1_ss1_b",
5012 "msiof1_ss2_b",
5013 "msiof1_txd_b",
5014 "msiof1_rxd_b",
5015 "msiof1_clk_c",
5016 "msiof1_sync_c",
5017 "msiof1_ss1_c",
5018 "msiof1_ss2_c",
5019 "msiof1_txd_c",
5020 "msiof1_rxd_c",
5021 "msiof1_clk_d",
5022 "msiof1_sync_d",
5023 "msiof1_ss1_d",
5024 "msiof1_ss2_d",
5025 "msiof1_txd_d",
5026 "msiof1_rxd_d",
5027 "msiof1_clk_e",
5028 "msiof1_sync_e",
5029 "msiof1_ss1_e",
5030 "msiof1_ss2_e",
5031 "msiof1_txd_e",
5032 "msiof1_rxd_e",
5033 "msiof1_clk_f",
5034 "msiof1_sync_f",
5035 "msiof1_ss1_f",
5036 "msiof1_ss2_f",
5037 "msiof1_txd_f",
5038 "msiof1_rxd_f",
5039 "msiof1_clk_g",
5040 "msiof1_sync_g",
5041 "msiof1_ss1_g",
5042 "msiof1_ss2_g",
5043 "msiof1_txd_g",
5044 "msiof1_rxd_g",
5045};
5046
5047static const char * const msiof2_groups[] = {
5048 "msiof2_clk_a",
5049 "msiof2_sync_a",
5050 "msiof2_ss1_a",
5051 "msiof2_ss2_a",
5052 "msiof2_txd_a",
5053 "msiof2_rxd_a",
5054 "msiof2_clk_b",
5055 "msiof2_sync_b",
5056 "msiof2_ss1_b",
5057 "msiof2_ss2_b",
5058 "msiof2_txd_b",
5059 "msiof2_rxd_b",
5060 "msiof2_clk_c",
5061 "msiof2_sync_c",
5062 "msiof2_ss1_c",
5063 "msiof2_ss2_c",
5064 "msiof2_txd_c",
5065 "msiof2_rxd_c",
5066 "msiof2_clk_d",
5067 "msiof2_sync_d",
5068 "msiof2_ss1_d",
5069 "msiof2_ss2_d",
5070 "msiof2_txd_d",
5071 "msiof2_rxd_d",
5072};
5073
5074static const char * const msiof3_groups[] = {
5075 "msiof3_clk_a",
5076 "msiof3_sync_a",
5077 "msiof3_ss1_a",
5078 "msiof3_ss2_a",
5079 "msiof3_txd_a",
5080 "msiof3_rxd_a",
5081 "msiof3_clk_b",
5082 "msiof3_sync_b",
5083 "msiof3_ss1_b",
5084 "msiof3_ss2_b",
5085 "msiof3_txd_b",
5086 "msiof3_rxd_b",
5087 "msiof3_clk_c",
5088 "msiof3_sync_c",
5089 "msiof3_txd_c",
5090 "msiof3_rxd_c",
5091 "msiof3_clk_d",
5092 "msiof3_sync_d",
5093 "msiof3_ss1_d",
5094 "msiof3_txd_d",
5095 "msiof3_rxd_d",
5096 "msiof3_clk_e",
5097 "msiof3_sync_e",
5098 "msiof3_ss1_e",
5099 "msiof3_ss2_e",
5100 "msiof3_txd_e",
5101 "msiof3_rxd_e",
5102};
5103
5104static const char * const pwm0_groups[] = {
5105 "pwm0",
5106};
5107
5108static const char * const pwm1_groups[] = {
5109 "pwm1_a",
5110 "pwm1_b",
5111};
5112
5113static const char * const pwm2_groups[] = {
5114 "pwm2_a",
5115 "pwm2_b",
5116};
5117
5118static const char * const pwm3_groups[] = {
5119 "pwm3_a",
5120 "pwm3_b",
5121};
5122
5123static const char * const pwm4_groups[] = {
5124 "pwm4_a",
5125 "pwm4_b",
5126};
5127
5128static const char * const pwm5_groups[] = {
5129 "pwm5_a",
5130 "pwm5_b",
5131};
5132
5133static const char * const pwm6_groups[] = {
5134 "pwm6_a",
5135 "pwm6_b",
5136};
5137
5138static const char * const qspi0_groups[] = {
5139 "qspi0_ctrl",
5140 "qspi0_data2",
5141 "qspi0_data4",
5142};
5143
5144static const char * const qspi1_groups[] = {
5145 "qspi1_ctrl",
5146 "qspi1_data2",
5147 "qspi1_data4",
5148};
5149
5150static const char * const sata0_groups[] = {
5151 "sata0_devslp_a",
5152 "sata0_devslp_b",
5153};
5154
5155static const char * const scif0_groups[] = {
5156 "scif0_data",
5157 "scif0_clk",
5158 "scif0_ctrl",
5159};
5160
5161static const char * const scif1_groups[] = {
5162 "scif1_data_a",
5163 "scif1_clk",
5164 "scif1_ctrl",
5165 "scif1_data_b",
5166};
5167static const char * const scif2_groups[] = {
5168 "scif2_data_a",
5169 "scif2_clk",
5170 "scif2_data_b",
5171};
5172
5173static const char * const scif3_groups[] = {
5174 "scif3_data_a",
5175 "scif3_clk",
5176 "scif3_ctrl",
5177 "scif3_data_b",
5178};
5179
5180static const char * const scif4_groups[] = {
5181 "scif4_data_a",
5182 "scif4_clk_a",
5183 "scif4_ctrl_a",
5184 "scif4_data_b",
5185 "scif4_clk_b",
5186 "scif4_ctrl_b",
5187 "scif4_data_c",
5188 "scif4_clk_c",
5189 "scif4_ctrl_c",
5190};
5191
5192static const char * const scif5_groups[] = {
5193 "scif5_data_a",
5194 "scif5_clk_a",
5195 "scif5_data_b",
5196 "scif5_clk_b",
5197};
5198
5199static const char * const scif_clk_groups[] = {
5200 "scif_clk_a",
5201 "scif_clk_b",
5202};
5203
5204static const char * const sdhi0_groups[] = {
5205 "sdhi0_data1",
5206 "sdhi0_data4",
5207 "sdhi0_ctrl",
5208 "sdhi0_cd",
5209 "sdhi0_wp",
5210};
5211
5212static const char * const sdhi1_groups[] = {
5213 "sdhi1_data1",
5214 "sdhi1_data4",
5215 "sdhi1_ctrl",
5216 "sdhi1_cd",
5217 "sdhi1_wp",
5218};
5219
5220static const char * const sdhi2_groups[] = {
5221 "sdhi2_data1",
5222 "sdhi2_data4",
5223 "sdhi2_data8",
5224 "sdhi2_ctrl",
5225 "sdhi2_cd_a",
5226 "sdhi2_wp_a",
5227 "sdhi2_cd_b",
5228 "sdhi2_wp_b",
5229 "sdhi2_ds",
5230};
5231
5232static const char * const sdhi3_groups[] = {
5233 "sdhi3_data1",
5234 "sdhi3_data4",
5235 "sdhi3_data8",
5236 "sdhi3_ctrl",
5237 "sdhi3_cd",
5238 "sdhi3_wp",
5239 "sdhi3_ds",
5240};
5241
5242static const char * const ssi_groups[] = {
5243 "ssi0_data",
5244 "ssi01239_ctrl",
5245 "ssi1_data_a",
5246 "ssi1_data_b",
5247 "ssi1_ctrl_a",
5248 "ssi1_ctrl_b",
5249 "ssi2_data_a",
5250 "ssi2_data_b",
5251 "ssi2_ctrl_a",
5252 "ssi2_ctrl_b",
5253 "ssi3_data",
5254 "ssi349_ctrl",
5255 "ssi4_data",
5256 "ssi4_ctrl",
5257 "ssi5_data",
5258 "ssi5_ctrl",
5259 "ssi6_data",
5260 "ssi6_ctrl",
5261 "ssi7_data",
5262 "ssi78_ctrl",
5263 "ssi8_data",
5264 "ssi9_data_a",
5265 "ssi9_data_b",
5266 "ssi9_ctrl_a",
5267 "ssi9_ctrl_b",
5268};
5269
5270static const char * const tmu_groups[] = {
5271 "tmu_tclk1_a",
5272 "tmu_tclk1_b",
5273 "tmu_tclk2_a",
5274 "tmu_tclk2_b",
5275};
5276
5277static const char * const tpu_groups[] = {
5278 "tpu_to0",
5279 "tpu_to1",
5280 "tpu_to2",
5281 "tpu_to3",
5282};
5283
5284static const char * const usb0_groups[] = {
5285 "usb0",
5286};
5287
5288static const char * const usb1_groups[] = {
5289 "usb1",
5290};
5291
5292static const char * const usb30_groups[] = {
5293 "usb30",
5294};
5295
5296static const char * const vin4_groups[] = {
5297 "vin4_data8_a",
5298 "vin4_data10_a",
5299 "vin4_data12_a",
5300 "vin4_data16_a",
5301 "vin4_data18_a",
5302 "vin4_data20_a",
5303 "vin4_data24_a",
5304 "vin4_data8_b",
5305 "vin4_data10_b",
5306 "vin4_data12_b",
5307 "vin4_data16_b",
5308 "vin4_data18_b",
5309 "vin4_data20_b",
5310 "vin4_data24_b",
5311 "vin4_sync",
5312 "vin4_field",
5313 "vin4_clkenb",
5314 "vin4_clk",
5315};
5316
5317static const char * const vin5_groups[] = {
5318 "vin5_data8",
5319 "vin5_data10",
5320 "vin5_data12",
5321 "vin5_data16",
5322 "vin5_sync",
5323 "vin5_field",
5324 "vin5_clkenb",
5325 "vin5_clk",
5326};
5327
5328static const struct {
5329 struct sh_pfc_function common[53];
5330#ifdef CONFIG_PINCTRL_PFC_R8A77965
5331 struct sh_pfc_function automotive[4];
5332#endif
5333} pinmux_functions = {
5334 .common = {
5335 SH_PFC_FUNCTION(audio_clk),
5336 SH_PFC_FUNCTION(avb),
5337 SH_PFC_FUNCTION(can0),
5338 SH_PFC_FUNCTION(can1),
5339 SH_PFC_FUNCTION(can_clk),
5340 SH_PFC_FUNCTION(canfd0),
5341 SH_PFC_FUNCTION(canfd1),
5342 SH_PFC_FUNCTION(du),
5343 SH_PFC_FUNCTION(hscif0),
5344 SH_PFC_FUNCTION(hscif1),
5345 SH_PFC_FUNCTION(hscif2),
5346 SH_PFC_FUNCTION(hscif3),
5347 SH_PFC_FUNCTION(hscif4),
5348 SH_PFC_FUNCTION(i2c0),
5349 SH_PFC_FUNCTION(i2c1),
5350 SH_PFC_FUNCTION(i2c2),
5351 SH_PFC_FUNCTION(i2c3),
5352 SH_PFC_FUNCTION(i2c5),
5353 SH_PFC_FUNCTION(i2c6),
5354 SH_PFC_FUNCTION(intc_ex),
5355 SH_PFC_FUNCTION(msiof0),
5356 SH_PFC_FUNCTION(msiof1),
5357 SH_PFC_FUNCTION(msiof2),
5358 SH_PFC_FUNCTION(msiof3),
5359 SH_PFC_FUNCTION(pwm0),
5360 SH_PFC_FUNCTION(pwm1),
5361 SH_PFC_FUNCTION(pwm2),
5362 SH_PFC_FUNCTION(pwm3),
5363 SH_PFC_FUNCTION(pwm4),
5364 SH_PFC_FUNCTION(pwm5),
5365 SH_PFC_FUNCTION(pwm6),
5366 SH_PFC_FUNCTION(qspi0),
5367 SH_PFC_FUNCTION(qspi1),
5368 SH_PFC_FUNCTION(sata0),
5369 SH_PFC_FUNCTION(scif0),
5370 SH_PFC_FUNCTION(scif1),
5371 SH_PFC_FUNCTION(scif2),
5372 SH_PFC_FUNCTION(scif3),
5373 SH_PFC_FUNCTION(scif4),
5374 SH_PFC_FUNCTION(scif5),
5375 SH_PFC_FUNCTION(scif_clk),
5376 SH_PFC_FUNCTION(sdhi0),
5377 SH_PFC_FUNCTION(sdhi1),
5378 SH_PFC_FUNCTION(sdhi2),
5379 SH_PFC_FUNCTION(sdhi3),
5380 SH_PFC_FUNCTION(ssi),
5381 SH_PFC_FUNCTION(tmu),
5382 SH_PFC_FUNCTION(tpu),
5383 SH_PFC_FUNCTION(usb0),
5384 SH_PFC_FUNCTION(usb1),
5385 SH_PFC_FUNCTION(usb30),
5386 SH_PFC_FUNCTION(vin4),
5387 SH_PFC_FUNCTION(vin5),
5388 },
5389#ifdef CONFIG_PINCTRL_PFC_R8A77965
5390 .automotive = {
5391 SH_PFC_FUNCTION(drif0),
5392 SH_PFC_FUNCTION(drif1),
5393 SH_PFC_FUNCTION(drif2),
5394 SH_PFC_FUNCTION(drif3),
5395 }
5396#endif
5397};
5398
5399static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5400#define F_(x, y) FN_##y
5401#define FM(x) FN_##x
5402 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5403 0, 0,
5404 0, 0,
5405 0, 0,
5406 0, 0,
5407 0, 0,
5408 0, 0,
5409 0, 0,
5410 0, 0,
5411 0, 0,
5412 0, 0,
5413 0, 0,
5414 0, 0,
5415 0, 0,
5416 0, 0,
5417 0, 0,
5418 0, 0,
5419 GP_0_15_FN, GPSR0_15,
5420 GP_0_14_FN, GPSR0_14,
5421 GP_0_13_FN, GPSR0_13,
5422 GP_0_12_FN, GPSR0_12,
5423 GP_0_11_FN, GPSR0_11,
5424 GP_0_10_FN, GPSR0_10,
5425 GP_0_9_FN, GPSR0_9,
5426 GP_0_8_FN, GPSR0_8,
5427 GP_0_7_FN, GPSR0_7,
5428 GP_0_6_FN, GPSR0_6,
5429 GP_0_5_FN, GPSR0_5,
5430 GP_0_4_FN, GPSR0_4,
5431 GP_0_3_FN, GPSR0_3,
5432 GP_0_2_FN, GPSR0_2,
5433 GP_0_1_FN, GPSR0_1,
5434 GP_0_0_FN, GPSR0_0, ))
5435 },
5436 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5437 0, 0,
5438 0, 0,
5439 0, 0,
5440 GP_1_28_FN, GPSR1_28,
5441 GP_1_27_FN, GPSR1_27,
5442 GP_1_26_FN, GPSR1_26,
5443 GP_1_25_FN, GPSR1_25,
5444 GP_1_24_FN, GPSR1_24,
5445 GP_1_23_FN, GPSR1_23,
5446 GP_1_22_FN, GPSR1_22,
5447 GP_1_21_FN, GPSR1_21,
5448 GP_1_20_FN, GPSR1_20,
5449 GP_1_19_FN, GPSR1_19,
5450 GP_1_18_FN, GPSR1_18,
5451 GP_1_17_FN, GPSR1_17,
5452 GP_1_16_FN, GPSR1_16,
5453 GP_1_15_FN, GPSR1_15,
5454 GP_1_14_FN, GPSR1_14,
5455 GP_1_13_FN, GPSR1_13,
5456 GP_1_12_FN, GPSR1_12,
5457 GP_1_11_FN, GPSR1_11,
5458 GP_1_10_FN, GPSR1_10,
5459 GP_1_9_FN, GPSR1_9,
5460 GP_1_8_FN, GPSR1_8,
5461 GP_1_7_FN, GPSR1_7,
5462 GP_1_6_FN, GPSR1_6,
5463 GP_1_5_FN, GPSR1_5,
5464 GP_1_4_FN, GPSR1_4,
5465 GP_1_3_FN, GPSR1_3,
5466 GP_1_2_FN, GPSR1_2,
5467 GP_1_1_FN, GPSR1_1,
5468 GP_1_0_FN, GPSR1_0, ))
5469 },
5470 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5471 0, 0,
5472 0, 0,
5473 0, 0,
5474 0, 0,
5475 0, 0,
5476 0, 0,
5477 0, 0,
5478 0, 0,
5479 0, 0,
5480 0, 0,
5481 0, 0,
5482 0, 0,
5483 0, 0,
5484 0, 0,
5485 0, 0,
5486 0, 0,
5487 0, 0,
5488 GP_2_14_FN, GPSR2_14,
5489 GP_2_13_FN, GPSR2_13,
5490 GP_2_12_FN, GPSR2_12,
5491 GP_2_11_FN, GPSR2_11,
5492 GP_2_10_FN, GPSR2_10,
5493 GP_2_9_FN, GPSR2_9,
5494 GP_2_8_FN, GPSR2_8,
5495 GP_2_7_FN, GPSR2_7,
5496 GP_2_6_FN, GPSR2_6,
5497 GP_2_5_FN, GPSR2_5,
5498 GP_2_4_FN, GPSR2_4,
5499 GP_2_3_FN, GPSR2_3,
5500 GP_2_2_FN, GPSR2_2,
5501 GP_2_1_FN, GPSR2_1,
5502 GP_2_0_FN, GPSR2_0, ))
5503 },
5504 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5505 0, 0,
5506 0, 0,
5507 0, 0,
5508 0, 0,
5509 0, 0,
5510 0, 0,
5511 0, 0,
5512 0, 0,
5513 0, 0,
5514 0, 0,
5515 0, 0,
5516 0, 0,
5517 0, 0,
5518 0, 0,
5519 0, 0,
5520 0, 0,
5521 GP_3_15_FN, GPSR3_15,
5522 GP_3_14_FN, GPSR3_14,
5523 GP_3_13_FN, GPSR3_13,
5524 GP_3_12_FN, GPSR3_12,
5525 GP_3_11_FN, GPSR3_11,
5526 GP_3_10_FN, GPSR3_10,
5527 GP_3_9_FN, GPSR3_9,
5528 GP_3_8_FN, GPSR3_8,
5529 GP_3_7_FN, GPSR3_7,
5530 GP_3_6_FN, GPSR3_6,
5531 GP_3_5_FN, GPSR3_5,
5532 GP_3_4_FN, GPSR3_4,
5533 GP_3_3_FN, GPSR3_3,
5534 GP_3_2_FN, GPSR3_2,
5535 GP_3_1_FN, GPSR3_1,
5536 GP_3_0_FN, GPSR3_0, ))
5537 },
5538 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5539 0, 0,
5540 0, 0,
5541 0, 0,
5542 0, 0,
5543 0, 0,
5544 0, 0,
5545 0, 0,
5546 0, 0,
5547 0, 0,
5548 0, 0,
5549 0, 0,
5550 0, 0,
5551 0, 0,
5552 0, 0,
5553 GP_4_17_FN, GPSR4_17,
5554 GP_4_16_FN, GPSR4_16,
5555 GP_4_15_FN, GPSR4_15,
5556 GP_4_14_FN, GPSR4_14,
5557 GP_4_13_FN, GPSR4_13,
5558 GP_4_12_FN, GPSR4_12,
5559 GP_4_11_FN, GPSR4_11,
5560 GP_4_10_FN, GPSR4_10,
5561 GP_4_9_FN, GPSR4_9,
5562 GP_4_8_FN, GPSR4_8,
5563 GP_4_7_FN, GPSR4_7,
5564 GP_4_6_FN, GPSR4_6,
5565 GP_4_5_FN, GPSR4_5,
5566 GP_4_4_FN, GPSR4_4,
5567 GP_4_3_FN, GPSR4_3,
5568 GP_4_2_FN, GPSR4_2,
5569 GP_4_1_FN, GPSR4_1,
5570 GP_4_0_FN, GPSR4_0, ))
5571 },
5572 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5573 0, 0,
5574 0, 0,
5575 0, 0,
5576 0, 0,
5577 0, 0,
5578 0, 0,
5579 GP_5_25_FN, GPSR5_25,
5580 GP_5_24_FN, GPSR5_24,
5581 GP_5_23_FN, GPSR5_23,
5582 GP_5_22_FN, GPSR5_22,
5583 GP_5_21_FN, GPSR5_21,
5584 GP_5_20_FN, GPSR5_20,
5585 GP_5_19_FN, GPSR5_19,
5586 GP_5_18_FN, GPSR5_18,
5587 GP_5_17_FN, GPSR5_17,
5588 GP_5_16_FN, GPSR5_16,
5589 GP_5_15_FN, GPSR5_15,
5590 GP_5_14_FN, GPSR5_14,
5591 GP_5_13_FN, GPSR5_13,
5592 GP_5_12_FN, GPSR5_12,
5593 GP_5_11_FN, GPSR5_11,
5594 GP_5_10_FN, GPSR5_10,
5595 GP_5_9_FN, GPSR5_9,
5596 GP_5_8_FN, GPSR5_8,
5597 GP_5_7_FN, GPSR5_7,
5598 GP_5_6_FN, GPSR5_6,
5599 GP_5_5_FN, GPSR5_5,
5600 GP_5_4_FN, GPSR5_4,
5601 GP_5_3_FN, GPSR5_3,
5602 GP_5_2_FN, GPSR5_2,
5603 GP_5_1_FN, GPSR5_1,
5604 GP_5_0_FN, GPSR5_0, ))
5605 },
5606 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5607 GP_6_31_FN, GPSR6_31,
5608 GP_6_30_FN, GPSR6_30,
5609 GP_6_29_FN, GPSR6_29,
5610 GP_6_28_FN, GPSR6_28,
5611 GP_6_27_FN, GPSR6_27,
5612 GP_6_26_FN, GPSR6_26,
5613 GP_6_25_FN, GPSR6_25,
5614 GP_6_24_FN, GPSR6_24,
5615 GP_6_23_FN, GPSR6_23,
5616 GP_6_22_FN, GPSR6_22,
5617 GP_6_21_FN, GPSR6_21,
5618 GP_6_20_FN, GPSR6_20,
5619 GP_6_19_FN, GPSR6_19,
5620 GP_6_18_FN, GPSR6_18,
5621 GP_6_17_FN, GPSR6_17,
5622 GP_6_16_FN, GPSR6_16,
5623 GP_6_15_FN, GPSR6_15,
5624 GP_6_14_FN, GPSR6_14,
5625 GP_6_13_FN, GPSR6_13,
5626 GP_6_12_FN, GPSR6_12,
5627 GP_6_11_FN, GPSR6_11,
5628 GP_6_10_FN, GPSR6_10,
5629 GP_6_9_FN, GPSR6_9,
5630 GP_6_8_FN, GPSR6_8,
5631 GP_6_7_FN, GPSR6_7,
5632 GP_6_6_FN, GPSR6_6,
5633 GP_6_5_FN, GPSR6_5,
5634 GP_6_4_FN, GPSR6_4,
5635 GP_6_3_FN, GPSR6_3,
5636 GP_6_2_FN, GPSR6_2,
5637 GP_6_1_FN, GPSR6_1,
5638 GP_6_0_FN, GPSR6_0, ))
5639 },
5640 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5641 0, 0,
5642 0, 0,
5643 0, 0,
5644 0, 0,
5645 0, 0,
5646 0, 0,
5647 0, 0,
5648 0, 0,
5649 0, 0,
5650 0, 0,
5651 0, 0,
5652 0, 0,
5653 0, 0,
5654 0, 0,
5655 0, 0,
5656 0, 0,
5657 0, 0,
5658 0, 0,
5659 0, 0,
5660 0, 0,
5661 0, 0,
5662 0, 0,
5663 0, 0,
5664 0, 0,
5665 0, 0,
5666 0, 0,
5667 0, 0,
5668 0, 0,
5669 GP_7_3_FN, GPSR7_3,
5670 GP_7_2_FN, GPSR7_2,
5671 GP_7_1_FN, GPSR7_1,
5672 GP_7_0_FN, GPSR7_0, ))
5673 },
5674#undef F_
5675#undef FM
5676
5677#define F_(x, y) x,
5678#define FM(x) FN_##x,
5679 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5680 IP0_31_28
5681 IP0_27_24
5682 IP0_23_20
5683 IP0_19_16
5684 IP0_15_12
5685 IP0_11_8
5686 IP0_7_4
5687 IP0_3_0 ))
5688 },
5689 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5690 IP1_31_28
5691 IP1_27_24
5692 IP1_23_20
5693 IP1_19_16
5694 IP1_15_12
5695 IP1_11_8
5696 IP1_7_4
5697 IP1_3_0 ))
5698 },
5699 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5700 IP2_31_28
5701 IP2_27_24
5702 IP2_23_20
5703 IP2_19_16
5704 IP2_15_12
5705 IP2_11_8
5706 IP2_7_4
5707 IP2_3_0 ))
5708 },
5709 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5710 IP3_31_28
5711 IP3_27_24
5712 IP3_23_20
5713 IP3_19_16
5714 IP3_15_12
5715 IP3_11_8
5716 IP3_7_4
5717 IP3_3_0 ))
5718 },
5719 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5720 IP4_31_28
5721 IP4_27_24
5722 IP4_23_20
5723 IP4_19_16
5724 IP4_15_12
5725 IP4_11_8
5726 IP4_7_4
5727 IP4_3_0 ))
5728 },
5729 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5730 IP5_31_28
5731 IP5_27_24
5732 IP5_23_20
5733 IP5_19_16
5734 IP5_15_12
5735 IP5_11_8
5736 IP5_7_4
5737 IP5_3_0 ))
5738 },
5739 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5740 IP6_31_28
5741 IP6_27_24
5742 IP6_23_20
5743 IP6_19_16
5744 IP6_15_12
5745 IP6_11_8
5746 IP6_7_4
5747 IP6_3_0 ))
5748 },
5749 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5750 IP7_31_28
5751 IP7_27_24
5752 IP7_23_20
5753 IP7_19_16
5754 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5755 IP7_11_8
5756 IP7_7_4
5757 IP7_3_0 ))
5758 },
5759 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5760 IP8_31_28
5761 IP8_27_24
5762 IP8_23_20
5763 IP8_19_16
5764 IP8_15_12
5765 IP8_11_8
5766 IP8_7_4
5767 IP8_3_0 ))
5768 },
5769 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5770 IP9_31_28
5771 IP9_27_24
5772 IP9_23_20
5773 IP9_19_16
5774 IP9_15_12
5775 IP9_11_8
5776 IP9_7_4
5777 IP9_3_0 ))
5778 },
5779 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5780 IP10_31_28
5781 IP10_27_24
5782 IP10_23_20
5783 IP10_19_16
5784 IP10_15_12
5785 IP10_11_8
5786 IP10_7_4
5787 IP10_3_0 ))
5788 },
5789 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5790 IP11_31_28
5791 IP11_27_24
5792 IP11_23_20
5793 IP11_19_16
5794 IP11_15_12
5795 IP11_11_8
5796 IP11_7_4
5797 IP11_3_0 ))
5798 },
5799 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5800 IP12_31_28
5801 IP12_27_24
5802 IP12_23_20
5803 IP12_19_16
5804 IP12_15_12
5805 IP12_11_8
5806 IP12_7_4
5807 IP12_3_0 ))
5808 },
5809 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5810 IP13_31_28
5811 IP13_27_24
5812 IP13_23_20
5813 IP13_19_16
5814 IP13_15_12
5815 IP13_11_8
5816 IP13_7_4
5817 IP13_3_0 ))
5818 },
5819 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5820 IP14_31_28
5821 IP14_27_24
5822 IP14_23_20
5823 IP14_19_16
5824 IP14_15_12
5825 IP14_11_8
5826 IP14_7_4
5827 IP14_3_0 ))
5828 },
5829 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5830 IP15_31_28
5831 IP15_27_24
5832 IP15_23_20
5833 IP15_19_16
5834 IP15_15_12
5835 IP15_11_8
5836 IP15_7_4
5837 IP15_3_0 ))
5838 },
5839 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5840 IP16_31_28
5841 IP16_27_24
5842 IP16_23_20
5843 IP16_19_16
5844 IP16_15_12
5845 IP16_11_8
5846 IP16_7_4
5847 IP16_3_0 ))
5848 },
5849 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5850 IP17_31_28
5851 IP17_27_24
5852 IP17_23_20
5853 IP17_19_16
5854 IP17_15_12
5855 IP17_11_8
5856 IP17_7_4
5857 IP17_3_0 ))
5858 },
5859 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
5860 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5861 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5862 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5863 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5864 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5865 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5866 IP18_7_4
5867 IP18_3_0 ))
5868 },
5869#undef F_
5870#undef FM
5871
5872#define F_(x, y) x,
5873#define FM(x) FN_##x,
5874 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5875 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5876 1, 1, 1, 2, 2, 1, 2, 3),
5877 GROUP(
5878 MOD_SEL0_31_30_29
5879 MOD_SEL0_28_27
5880 MOD_SEL0_26_25_24
5881 MOD_SEL0_23
5882 MOD_SEL0_22
5883 MOD_SEL0_21
5884 MOD_SEL0_20
5885 MOD_SEL0_19
5886 MOD_SEL0_18_17
5887 MOD_SEL0_16
5888 0, 0,
5889 MOD_SEL0_14_13
5890 MOD_SEL0_12
5891 MOD_SEL0_11
5892 MOD_SEL0_10
5893 MOD_SEL0_9_8
5894 MOD_SEL0_7_6
5895 MOD_SEL0_5
5896 MOD_SEL0_4_3
5897
5898 0, 0, 0, 0, 0, 0, 0, 0 ))
5899 },
5900 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5901 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5902 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5903 GROUP(
5904 MOD_SEL1_31_30
5905 MOD_SEL1_29_28_27
5906 MOD_SEL1_26
5907 MOD_SEL1_25_24
5908 MOD_SEL1_23_22_21
5909 MOD_SEL1_20
5910 MOD_SEL1_19
5911 MOD_SEL1_18_17
5912 MOD_SEL1_16
5913 MOD_SEL1_15_14
5914 MOD_SEL1_13
5915 MOD_SEL1_12
5916 MOD_SEL1_11
5917 MOD_SEL1_10
5918 MOD_SEL1_9
5919 0, 0, 0, 0,
5920 MOD_SEL1_6
5921 MOD_SEL1_5
5922 MOD_SEL1_4
5923 MOD_SEL1_3
5924 MOD_SEL1_2
5925 MOD_SEL1_1
5926 MOD_SEL1_0 ))
5927 },
5928 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5929 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5930 1, 4, 4, 4, 3, 1),
5931 GROUP(
5932 MOD_SEL2_31
5933 MOD_SEL2_30
5934 MOD_SEL2_29
5935 MOD_SEL2_28_27
5936 MOD_SEL2_26
5937 MOD_SEL2_25_24_23
5938 MOD_SEL2_22
5939 MOD_SEL2_21
5940 MOD_SEL2_20
5941 MOD_SEL2_19
5942 MOD_SEL2_18
5943 MOD_SEL2_17
5944
5945 0, 0,
5946
5947 0, 0, 0, 0, 0, 0, 0, 0,
5948 0, 0, 0, 0, 0, 0, 0, 0,
5949
5950 0, 0, 0, 0, 0, 0, 0, 0,
5951 0, 0, 0, 0, 0, 0, 0, 0,
5952
5953 0, 0, 0, 0, 0, 0, 0, 0,
5954 0, 0, 0, 0, 0, 0, 0, 0,
5955
5956 0, 0, 0, 0, 0, 0, 0, 0,
5957 MOD_SEL2_0 ))
5958 },
5959 { },
5960};
5961
5962static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5963 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5964 { PIN_QSPI0_SPCLK, 28, 2 },
5965 { PIN_QSPI0_MOSI_IO0, 24, 2 },
5966 { PIN_QSPI0_MISO_IO1, 20, 2 },
5967 { PIN_QSPI0_IO2, 16, 2 },
5968 { PIN_QSPI0_IO3, 12, 2 },
5969 { PIN_QSPI0_SSL, 8, 2 },
5970 { PIN_QSPI1_SPCLK, 4, 2 },
5971 { PIN_QSPI1_MOSI_IO0, 0, 2 },
5972 } },
5973 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5974 { PIN_QSPI1_MISO_IO1, 28, 2 },
5975 { PIN_QSPI1_IO2, 24, 2 },
5976 { PIN_QSPI1_IO3, 20, 2 },
5977 { PIN_QSPI1_SSL, 16, 2 },
5978 { PIN_RPC_INT_N, 12, 2 },
5979 { PIN_RPC_WP_N, 8, 2 },
5980 { PIN_RPC_RESET_N, 4, 2 },
5981 { PIN_AVB_RX_CTL, 0, 3 },
5982 } },
5983 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5984 { PIN_AVB_RXC, 28, 3 },
5985 { PIN_AVB_RD0, 24, 3 },
5986 { PIN_AVB_RD1, 20, 3 },
5987 { PIN_AVB_RD2, 16, 3 },
5988 { PIN_AVB_RD3, 12, 3 },
5989 { PIN_AVB_TX_CTL, 8, 3 },
5990 { PIN_AVB_TXC, 4, 3 },
5991 { PIN_AVB_TD0, 0, 3 },
5992 } },
5993 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5994 { PIN_AVB_TD1, 28, 3 },
5995 { PIN_AVB_TD2, 24, 3 },
5996 { PIN_AVB_TD3, 20, 3 },
5997 { PIN_AVB_TXCREFCLK, 16, 3 },
5998 { PIN_AVB_MDIO, 12, 3 },
5999 { RCAR_GP_PIN(2, 9), 8, 3 },
6000 { RCAR_GP_PIN(2, 10), 4, 3 },
6001 { RCAR_GP_PIN(2, 11), 0, 3 },
6002 } },
6003 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
6004 { RCAR_GP_PIN(2, 12), 28, 3 },
6005 { RCAR_GP_PIN(2, 13), 24, 3 },
6006 { RCAR_GP_PIN(2, 14), 20, 3 },
6007 { RCAR_GP_PIN(2, 0), 16, 3 },
6008 { RCAR_GP_PIN(2, 1), 12, 3 },
6009 { RCAR_GP_PIN(2, 2), 8, 3 },
6010 { RCAR_GP_PIN(2, 3), 4, 3 },
6011 { RCAR_GP_PIN(2, 4), 0, 3 },
6012 } },
6013 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
6014 { RCAR_GP_PIN(2, 5), 28, 3 },
6015 { RCAR_GP_PIN(2, 6), 24, 3 },
6016 { RCAR_GP_PIN(2, 7), 20, 3 },
6017 { RCAR_GP_PIN(2, 8), 16, 3 },
6018 { RCAR_GP_PIN(1, 0), 12, 3 },
6019 { RCAR_GP_PIN(1, 1), 8, 3 },
6020 { RCAR_GP_PIN(1, 2), 4, 3 },
6021 { RCAR_GP_PIN(1, 3), 0, 3 },
6022 } },
6023 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
6024 { RCAR_GP_PIN(1, 4), 28, 3 },
6025 { RCAR_GP_PIN(1, 5), 24, 3 },
6026 { RCAR_GP_PIN(1, 6), 20, 3 },
6027 { RCAR_GP_PIN(1, 7), 16, 3 },
6028 { RCAR_GP_PIN(1, 8), 12, 3 },
6029 { RCAR_GP_PIN(1, 9), 8, 3 },
6030 { RCAR_GP_PIN(1, 10), 4, 3 },
6031 { RCAR_GP_PIN(1, 11), 0, 3 },
6032 } },
6033 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
6034 { RCAR_GP_PIN(1, 12), 28, 3 },
6035 { RCAR_GP_PIN(1, 13), 24, 3 },
6036 { RCAR_GP_PIN(1, 14), 20, 3 },
6037 { RCAR_GP_PIN(1, 15), 16, 3 },
6038 { RCAR_GP_PIN(1, 16), 12, 3 },
6039 { RCAR_GP_PIN(1, 17), 8, 3 },
6040 { RCAR_GP_PIN(1, 18), 4, 3 },
6041 { RCAR_GP_PIN(1, 19), 0, 3 },
6042 } },
6043 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
6044 { RCAR_GP_PIN(1, 28), 28, 3 },
6045 { RCAR_GP_PIN(1, 20), 24, 3 },
6046 { RCAR_GP_PIN(1, 21), 20, 3 },
6047 { RCAR_GP_PIN(1, 22), 16, 3 },
6048 { RCAR_GP_PIN(1, 23), 12, 3 },
6049 { RCAR_GP_PIN(1, 24), 8, 3 },
6050 { RCAR_GP_PIN(1, 25), 4, 3 },
6051 { RCAR_GP_PIN(1, 26), 0, 3 },
6052 } },
6053 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
6054 { RCAR_GP_PIN(1, 27), 28, 3 },
6055 { PIN_PRESETOUT_N, 24, 3 },
6056 { RCAR_GP_PIN(0, 0), 20, 3 },
6057 { RCAR_GP_PIN(0, 1), 16, 3 },
6058 { RCAR_GP_PIN(0, 2), 12, 3 },
6059 { RCAR_GP_PIN(0, 3), 8, 3 },
6060 { RCAR_GP_PIN(0, 4), 4, 3 },
6061 { RCAR_GP_PIN(0, 5), 0, 3 },
6062 } },
6063 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
6064 { RCAR_GP_PIN(0, 6), 28, 3 },
6065 { RCAR_GP_PIN(0, 7), 24, 3 },
6066 { RCAR_GP_PIN(0, 8), 20, 3 },
6067 { RCAR_GP_PIN(0, 9), 16, 3 },
6068 { RCAR_GP_PIN(0, 10), 12, 3 },
6069 { RCAR_GP_PIN(0, 11), 8, 3 },
6070 { RCAR_GP_PIN(0, 12), 4, 3 },
6071 { RCAR_GP_PIN(0, 13), 0, 3 },
6072 } },
6073 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
6074 { RCAR_GP_PIN(0, 14), 28, 3 },
6075 { RCAR_GP_PIN(0, 15), 24, 3 },
6076 { RCAR_GP_PIN(7, 0), 20, 3 },
6077 { RCAR_GP_PIN(7, 1), 16, 3 },
6078 { RCAR_GP_PIN(7, 2), 12, 3 },
6079 { RCAR_GP_PIN(7, 3), 8, 3 },
6080 { PIN_DU_DOTCLKIN0, 4, 2 },
6081 { PIN_DU_DOTCLKIN1, 0, 2 },
6082 } },
6083 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
6084 { PIN_DU_DOTCLKIN3, 24, 2 },
6085 { PIN_FSCLKST, 20, 2 },
6086 { PIN_TMS, 4, 2 },
6087 } },
6088 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
6089 { PIN_TDO, 28, 2 },
6090 { PIN_ASEBRK, 24, 2 },
6091 { RCAR_GP_PIN(3, 0), 20, 3 },
6092 { RCAR_GP_PIN(3, 1), 16, 3 },
6093 { RCAR_GP_PIN(3, 2), 12, 3 },
6094 { RCAR_GP_PIN(3, 3), 8, 3 },
6095 { RCAR_GP_PIN(3, 4), 4, 3 },
6096 { RCAR_GP_PIN(3, 5), 0, 3 },
6097 } },
6098 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
6099 { RCAR_GP_PIN(3, 6), 28, 3 },
6100 { RCAR_GP_PIN(3, 7), 24, 3 },
6101 { RCAR_GP_PIN(3, 8), 20, 3 },
6102 { RCAR_GP_PIN(3, 9), 16, 3 },
6103 { RCAR_GP_PIN(3, 10), 12, 3 },
6104 { RCAR_GP_PIN(3, 11), 8, 3 },
6105 { RCAR_GP_PIN(4, 0), 4, 3 },
6106 { RCAR_GP_PIN(4, 1), 0, 3 },
6107 } },
6108 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
6109 { RCAR_GP_PIN(4, 2), 28, 3 },
6110 { RCAR_GP_PIN(4, 3), 24, 3 },
6111 { RCAR_GP_PIN(4, 4), 20, 3 },
6112 { RCAR_GP_PIN(4, 5), 16, 3 },
6113 { RCAR_GP_PIN(4, 6), 12, 3 },
6114 { RCAR_GP_PIN(4, 7), 8, 3 },
6115 { RCAR_GP_PIN(4, 8), 4, 3 },
6116 { RCAR_GP_PIN(4, 9), 0, 3 },
6117 } },
6118 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
6119 { RCAR_GP_PIN(4, 10), 28, 3 },
6120 { RCAR_GP_PIN(4, 11), 24, 3 },
6121 { RCAR_GP_PIN(4, 12), 20, 3 },
6122 { RCAR_GP_PIN(4, 13), 16, 3 },
6123 { RCAR_GP_PIN(4, 14), 12, 3 },
6124 { RCAR_GP_PIN(4, 15), 8, 3 },
6125 { RCAR_GP_PIN(4, 16), 4, 3 },
6126 { RCAR_GP_PIN(4, 17), 0, 3 },
6127 } },
6128 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
6129 { RCAR_GP_PIN(3, 12), 28, 3 },
6130 { RCAR_GP_PIN(3, 13), 24, 3 },
6131 { RCAR_GP_PIN(3, 14), 20, 3 },
6132 { RCAR_GP_PIN(3, 15), 16, 3 },
6133 { RCAR_GP_PIN(5, 0), 12, 3 },
6134 { RCAR_GP_PIN(5, 1), 8, 3 },
6135 { RCAR_GP_PIN(5, 2), 4, 3 },
6136 { RCAR_GP_PIN(5, 3), 0, 3 },
6137 } },
6138 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
6139 { RCAR_GP_PIN(5, 4), 28, 3 },
6140 { RCAR_GP_PIN(5, 5), 24, 3 },
6141 { RCAR_GP_PIN(5, 6), 20, 3 },
6142 { RCAR_GP_PIN(5, 7), 16, 3 },
6143 { RCAR_GP_PIN(5, 8), 12, 3 },
6144 { RCAR_GP_PIN(5, 9), 8, 3 },
6145 { RCAR_GP_PIN(5, 10), 4, 3 },
6146 { RCAR_GP_PIN(5, 11), 0, 3 },
6147 } },
6148 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
6149 { RCAR_GP_PIN(5, 12), 28, 3 },
6150 { RCAR_GP_PIN(5, 13), 24, 3 },
6151 { RCAR_GP_PIN(5, 14), 20, 3 },
6152 { RCAR_GP_PIN(5, 15), 16, 3 },
6153 { RCAR_GP_PIN(5, 16), 12, 3 },
6154 { RCAR_GP_PIN(5, 17), 8, 3 },
6155 { RCAR_GP_PIN(5, 18), 4, 3 },
6156 { RCAR_GP_PIN(5, 19), 0, 3 },
6157 } },
6158 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
6159 { RCAR_GP_PIN(5, 20), 28, 3 },
6160 { RCAR_GP_PIN(5, 21), 24, 3 },
6161 { RCAR_GP_PIN(5, 22), 20, 3 },
6162 { RCAR_GP_PIN(5, 23), 16, 3 },
6163 { RCAR_GP_PIN(5, 24), 12, 3 },
6164 { RCAR_GP_PIN(5, 25), 8, 3 },
6165 { PIN_MLB_REF, 4, 3 },
6166 { RCAR_GP_PIN(6, 0), 0, 3 },
6167 } },
6168 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
6169 { RCAR_GP_PIN(6, 1), 28, 3 },
6170 { RCAR_GP_PIN(6, 2), 24, 3 },
6171 { RCAR_GP_PIN(6, 3), 20, 3 },
6172 { RCAR_GP_PIN(6, 4), 16, 3 },
6173 { RCAR_GP_PIN(6, 5), 12, 3 },
6174 { RCAR_GP_PIN(6, 6), 8, 3 },
6175 { RCAR_GP_PIN(6, 7), 4, 3 },
6176 { RCAR_GP_PIN(6, 8), 0, 3 },
6177 } },
6178 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
6179 { RCAR_GP_PIN(6, 9), 28, 3 },
6180 { RCAR_GP_PIN(6, 10), 24, 3 },
6181 { RCAR_GP_PIN(6, 11), 20, 3 },
6182 { RCAR_GP_PIN(6, 12), 16, 3 },
6183 { RCAR_GP_PIN(6, 13), 12, 3 },
6184 { RCAR_GP_PIN(6, 14), 8, 3 },
6185 { RCAR_GP_PIN(6, 15), 4, 3 },
6186 { RCAR_GP_PIN(6, 16), 0, 3 },
6187 } },
6188 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
6189 { RCAR_GP_PIN(6, 17), 28, 3 },
6190 { RCAR_GP_PIN(6, 18), 24, 3 },
6191 { RCAR_GP_PIN(6, 19), 20, 3 },
6192 { RCAR_GP_PIN(6, 20), 16, 3 },
6193 { RCAR_GP_PIN(6, 21), 12, 3 },
6194 { RCAR_GP_PIN(6, 22), 8, 3 },
6195 { RCAR_GP_PIN(6, 23), 4, 3 },
6196 { RCAR_GP_PIN(6, 24), 0, 3 },
6197 } },
6198 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
6199 { RCAR_GP_PIN(6, 25), 28, 3 },
6200 { RCAR_GP_PIN(6, 26), 24, 3 },
6201 { RCAR_GP_PIN(6, 27), 20, 3 },
6202 { RCAR_GP_PIN(6, 28), 16, 3 },
6203 { RCAR_GP_PIN(6, 29), 12, 3 },
6204 { RCAR_GP_PIN(6, 30), 8, 3 },
6205 { RCAR_GP_PIN(6, 31), 4, 3 },
6206 } },
6207 { },
6208};
6209
6210enum ioctrl_regs {
6211 POCCTRL,
6212 TDSELCTRL,
6213};
6214
6215static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
6216 [POCCTRL] = { 0xe6060380, },
6217 [TDSELCTRL] = { 0xe60603c0, },
6218 { },
6219};
6220
6221static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6222{
6223 int bit = -EINVAL;
6224
6225 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
6226
6227 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
6228 bit = pin & 0x1f;
6229
6230 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
6231 bit = (pin & 0x1f) + 12;
6232
6233 return bit;
6234}
6235
6236static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6237 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
6238 [ 0] = PIN_QSPI0_SPCLK,
6239 [ 1] = PIN_QSPI0_MOSI_IO0,
6240 [ 2] = PIN_QSPI0_MISO_IO1,
6241 [ 3] = PIN_QSPI0_IO2,
6242 [ 4] = PIN_QSPI0_IO3,
6243 [ 5] = PIN_QSPI0_SSL,
6244 [ 6] = PIN_QSPI1_SPCLK,
6245 [ 7] = PIN_QSPI1_MOSI_IO0,
6246 [ 8] = PIN_QSPI1_MISO_IO1,
6247 [ 9] = PIN_QSPI1_IO2,
6248 [10] = PIN_QSPI1_IO3,
6249 [11] = PIN_QSPI1_SSL,
6250 [12] = PIN_RPC_INT_N,
6251 [13] = PIN_RPC_WP_N,
6252 [14] = PIN_RPC_RESET_N,
6253 [15] = PIN_AVB_RX_CTL,
6254 [16] = PIN_AVB_RXC,
6255 [17] = PIN_AVB_RD0,
6256 [18] = PIN_AVB_RD1,
6257 [19] = PIN_AVB_RD2,
6258 [20] = PIN_AVB_RD3,
6259 [21] = PIN_AVB_TX_CTL,
6260 [22] = PIN_AVB_TXC,
6261 [23] = PIN_AVB_TD0,
6262 [24] = PIN_AVB_TD1,
6263 [25] = PIN_AVB_TD2,
6264 [26] = PIN_AVB_TD3,
6265 [27] = PIN_AVB_TXCREFCLK,
6266 [28] = PIN_AVB_MDIO,
6267 [29] = RCAR_GP_PIN(2, 9),
6268 [30] = RCAR_GP_PIN(2, 10),
6269 [31] = RCAR_GP_PIN(2, 11),
6270 } },
6271 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6272 [ 0] = RCAR_GP_PIN(2, 12),
6273 [ 1] = RCAR_GP_PIN(2, 13),
6274 [ 2] = RCAR_GP_PIN(2, 14),
6275 [ 3] = RCAR_GP_PIN(2, 0),
6276 [ 4] = RCAR_GP_PIN(2, 1),
6277 [ 5] = RCAR_GP_PIN(2, 2),
6278 [ 6] = RCAR_GP_PIN(2, 3),
6279 [ 7] = RCAR_GP_PIN(2, 4),
6280 [ 8] = RCAR_GP_PIN(2, 5),
6281 [ 9] = RCAR_GP_PIN(2, 6),
6282 [10] = RCAR_GP_PIN(2, 7),
6283 [11] = RCAR_GP_PIN(2, 8),
6284 [12] = RCAR_GP_PIN(1, 0),
6285 [13] = RCAR_GP_PIN(1, 1),
6286 [14] = RCAR_GP_PIN(1, 2),
6287 [15] = RCAR_GP_PIN(1, 3),
6288 [16] = RCAR_GP_PIN(1, 4),
6289 [17] = RCAR_GP_PIN(1, 5),
6290 [18] = RCAR_GP_PIN(1, 6),
6291 [19] = RCAR_GP_PIN(1, 7),
6292 [20] = RCAR_GP_PIN(1, 8),
6293 [21] = RCAR_GP_PIN(1, 9),
6294 [22] = RCAR_GP_PIN(1, 10),
6295 [23] = RCAR_GP_PIN(1, 11),
6296 [24] = RCAR_GP_PIN(1, 12),
6297 [25] = RCAR_GP_PIN(1, 13),
6298 [26] = RCAR_GP_PIN(1, 14),
6299 [27] = RCAR_GP_PIN(1, 15),
6300 [28] = RCAR_GP_PIN(1, 16),
6301 [29] = RCAR_GP_PIN(1, 17),
6302 [30] = RCAR_GP_PIN(1, 18),
6303 [31] = RCAR_GP_PIN(1, 19),
6304 } },
6305 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6306 [ 0] = RCAR_GP_PIN(1, 28),
6307 [ 1] = RCAR_GP_PIN(1, 20),
6308 [ 2] = RCAR_GP_PIN(1, 21),
6309 [ 3] = RCAR_GP_PIN(1, 22),
6310 [ 4] = RCAR_GP_PIN(1, 23),
6311 [ 5] = RCAR_GP_PIN(1, 24),
6312 [ 6] = RCAR_GP_PIN(1, 25),
6313 [ 7] = RCAR_GP_PIN(1, 26),
6314 [ 8] = RCAR_GP_PIN(1, 27),
6315 [ 9] = PIN_PRESETOUT_N,
6316 [10] = RCAR_GP_PIN(0, 0),
6317 [11] = RCAR_GP_PIN(0, 1),
6318 [12] = RCAR_GP_PIN(0, 2),
6319 [13] = RCAR_GP_PIN(0, 3),
6320 [14] = RCAR_GP_PIN(0, 4),
6321 [15] = RCAR_GP_PIN(0, 5),
6322 [16] = RCAR_GP_PIN(0, 6),
6323 [17] = RCAR_GP_PIN(0, 7),
6324 [18] = RCAR_GP_PIN(0, 8),
6325 [19] = RCAR_GP_PIN(0, 9),
6326 [20] = RCAR_GP_PIN(0, 10),
6327 [21] = RCAR_GP_PIN(0, 11),
6328 [22] = RCAR_GP_PIN(0, 12),
6329 [23] = RCAR_GP_PIN(0, 13),
6330 [24] = RCAR_GP_PIN(0, 14),
6331 [25] = RCAR_GP_PIN(0, 15),
6332 [26] = RCAR_GP_PIN(7, 0),
6333 [27] = RCAR_GP_PIN(7, 1),
6334 [28] = RCAR_GP_PIN(7, 2),
6335 [29] = RCAR_GP_PIN(7, 3),
6336 [30] = PIN_DU_DOTCLKIN0,
6337 [31] = PIN_DU_DOTCLKIN1,
6338 } },
6339 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6340 [ 0] = SH_PFC_PIN_NONE,
6341 [ 1] = PIN_DU_DOTCLKIN3,
6342 [ 2] = PIN_FSCLKST,
6343 [ 3] = PIN_EXTALR,
6344 [ 4] = PIN_TRST_N,
6345 [ 5] = PIN_TCK,
6346 [ 6] = PIN_TMS,
6347 [ 7] = PIN_TDI,
6348 [ 8] = SH_PFC_PIN_NONE,
6349 [ 9] = PIN_ASEBRK,
6350 [10] = RCAR_GP_PIN(3, 0),
6351 [11] = RCAR_GP_PIN(3, 1),
6352 [12] = RCAR_GP_PIN(3, 2),
6353 [13] = RCAR_GP_PIN(3, 3),
6354 [14] = RCAR_GP_PIN(3, 4),
6355 [15] = RCAR_GP_PIN(3, 5),
6356 [16] = RCAR_GP_PIN(3, 6),
6357 [17] = RCAR_GP_PIN(3, 7),
6358 [18] = RCAR_GP_PIN(3, 8),
6359 [19] = RCAR_GP_PIN(3, 9),
6360 [20] = RCAR_GP_PIN(3, 10),
6361 [21] = RCAR_GP_PIN(3, 11),
6362 [22] = RCAR_GP_PIN(4, 0),
6363 [23] = RCAR_GP_PIN(4, 1),
6364 [24] = RCAR_GP_PIN(4, 2),
6365 [25] = RCAR_GP_PIN(4, 3),
6366 [26] = RCAR_GP_PIN(4, 4),
6367 [27] = RCAR_GP_PIN(4, 5),
6368 [28] = RCAR_GP_PIN(4, 6),
6369 [29] = RCAR_GP_PIN(4, 7),
6370 [30] = RCAR_GP_PIN(4, 8),
6371 [31] = RCAR_GP_PIN(4, 9),
6372 } },
6373 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6374 [ 0] = RCAR_GP_PIN(4, 10),
6375 [ 1] = RCAR_GP_PIN(4, 11),
6376 [ 2] = RCAR_GP_PIN(4, 12),
6377 [ 3] = RCAR_GP_PIN(4, 13),
6378 [ 4] = RCAR_GP_PIN(4, 14),
6379 [ 5] = RCAR_GP_PIN(4, 15),
6380 [ 6] = RCAR_GP_PIN(4, 16),
6381 [ 7] = RCAR_GP_PIN(4, 17),
6382 [ 8] = RCAR_GP_PIN(3, 12),
6383 [ 9] = RCAR_GP_PIN(3, 13),
6384 [10] = RCAR_GP_PIN(3, 14),
6385 [11] = RCAR_GP_PIN(3, 15),
6386 [12] = RCAR_GP_PIN(5, 0),
6387 [13] = RCAR_GP_PIN(5, 1),
6388 [14] = RCAR_GP_PIN(5, 2),
6389 [15] = RCAR_GP_PIN(5, 3),
6390 [16] = RCAR_GP_PIN(5, 4),
6391 [17] = RCAR_GP_PIN(5, 5),
6392 [18] = RCAR_GP_PIN(5, 6),
6393 [19] = RCAR_GP_PIN(5, 7),
6394 [20] = RCAR_GP_PIN(5, 8),
6395 [21] = RCAR_GP_PIN(5, 9),
6396 [22] = RCAR_GP_PIN(5, 10),
6397 [23] = RCAR_GP_PIN(5, 11),
6398 [24] = RCAR_GP_PIN(5, 12),
6399 [25] = RCAR_GP_PIN(5, 13),
6400 [26] = RCAR_GP_PIN(5, 14),
6401 [27] = RCAR_GP_PIN(5, 15),
6402 [28] = RCAR_GP_PIN(5, 16),
6403 [29] = RCAR_GP_PIN(5, 17),
6404 [30] = RCAR_GP_PIN(5, 18),
6405 [31] = RCAR_GP_PIN(5, 19),
6406 } },
6407 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6408 [ 0] = RCAR_GP_PIN(5, 20),
6409 [ 1] = RCAR_GP_PIN(5, 21),
6410 [ 2] = RCAR_GP_PIN(5, 22),
6411 [ 3] = RCAR_GP_PIN(5, 23),
6412 [ 4] = RCAR_GP_PIN(5, 24),
6413 [ 5] = RCAR_GP_PIN(5, 25),
6414 [ 6] = PIN_MLB_REF,
6415 [ 7] = RCAR_GP_PIN(6, 0),
6416 [ 8] = RCAR_GP_PIN(6, 1),
6417 [ 9] = RCAR_GP_PIN(6, 2),
6418 [10] = RCAR_GP_PIN(6, 3),
6419 [11] = RCAR_GP_PIN(6, 4),
6420 [12] = RCAR_GP_PIN(6, 5),
6421 [13] = RCAR_GP_PIN(6, 6),
6422 [14] = RCAR_GP_PIN(6, 7),
6423 [15] = RCAR_GP_PIN(6, 8),
6424 [16] = RCAR_GP_PIN(6, 9),
6425 [17] = RCAR_GP_PIN(6, 10),
6426 [18] = RCAR_GP_PIN(6, 11),
6427 [19] = RCAR_GP_PIN(6, 12),
6428 [20] = RCAR_GP_PIN(6, 13),
6429 [21] = RCAR_GP_PIN(6, 14),
6430 [22] = RCAR_GP_PIN(6, 15),
6431 [23] = RCAR_GP_PIN(6, 16),
6432 [24] = RCAR_GP_PIN(6, 17),
6433 [25] = RCAR_GP_PIN(6, 18),
6434 [26] = RCAR_GP_PIN(6, 19),
6435 [27] = RCAR_GP_PIN(6, 20),
6436 [28] = RCAR_GP_PIN(6, 21),
6437 [29] = RCAR_GP_PIN(6, 22),
6438 [30] = RCAR_GP_PIN(6, 23),
6439 [31] = RCAR_GP_PIN(6, 24),
6440 } },
6441 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6442 [ 0] = RCAR_GP_PIN(6, 25),
6443 [ 1] = RCAR_GP_PIN(6, 26),
6444 [ 2] = RCAR_GP_PIN(6, 27),
6445 [ 3] = RCAR_GP_PIN(6, 28),
6446 [ 4] = RCAR_GP_PIN(6, 29),
6447 [ 5] = RCAR_GP_PIN(6, 30),
6448 [ 6] = RCAR_GP_PIN(6, 31),
6449 [ 7] = SH_PFC_PIN_NONE,
6450 [ 8] = SH_PFC_PIN_NONE,
6451 [ 9] = SH_PFC_PIN_NONE,
6452 [10] = SH_PFC_PIN_NONE,
6453 [11] = SH_PFC_PIN_NONE,
6454 [12] = SH_PFC_PIN_NONE,
6455 [13] = SH_PFC_PIN_NONE,
6456 [14] = SH_PFC_PIN_NONE,
6457 [15] = SH_PFC_PIN_NONE,
6458 [16] = SH_PFC_PIN_NONE,
6459 [17] = SH_PFC_PIN_NONE,
6460 [18] = SH_PFC_PIN_NONE,
6461 [19] = SH_PFC_PIN_NONE,
6462 [20] = SH_PFC_PIN_NONE,
6463 [21] = SH_PFC_PIN_NONE,
6464 [22] = SH_PFC_PIN_NONE,
6465 [23] = SH_PFC_PIN_NONE,
6466 [24] = SH_PFC_PIN_NONE,
6467 [25] = SH_PFC_PIN_NONE,
6468 [26] = SH_PFC_PIN_NONE,
6469 [27] = SH_PFC_PIN_NONE,
6470 [28] = SH_PFC_PIN_NONE,
6471 [29] = SH_PFC_PIN_NONE,
6472 [30] = SH_PFC_PIN_NONE,
6473 [31] = SH_PFC_PIN_NONE,
6474 } },
6475 { },
6476};
6477
6478static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
6479 .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
6480 .get_bias = rcar_pinmux_get_bias,
6481 .set_bias = rcar_pinmux_set_bias,
6482};
6483
6484#ifdef CONFIG_PINCTRL_PFC_R8A774B1
6485const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
6486 .name = "r8a774b1_pfc",
6487 .ops = &r8a77965_pinmux_ops,
6488 .unlock_reg = 0xe6060000,
6489
6490 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6491
6492 .pins = pinmux_pins,
6493 .nr_pins = ARRAY_SIZE(pinmux_pins),
6494 .groups = pinmux_groups.common,
6495 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6496 .functions = pinmux_functions.common,
6497 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6498
6499 .cfg_regs = pinmux_config_regs,
6500 .drive_regs = pinmux_drive_regs,
6501 .bias_regs = pinmux_bias_regs,
6502 .ioctrl_regs = pinmux_ioctrl_regs,
6503
6504 .pinmux_data = pinmux_data,
6505 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6506};
6507#endif
6508
6509#ifdef CONFIG_PINCTRL_PFC_R8A77965
6510const struct sh_pfc_soc_info r8a77965_pinmux_info = {
6511 .name = "r8a77965_pfc",
6512 .ops = &r8a77965_pinmux_ops,
6513 .unlock_reg = 0xe6060000,
6514
6515 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6516
6517 .pins = pinmux_pins,
6518 .nr_pins = ARRAY_SIZE(pinmux_pins),
6519 .groups = pinmux_groups.common,
6520 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6521 ARRAY_SIZE(pinmux_groups.automotive),
6522 .functions = pinmux_functions.common,
6523 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6524 ARRAY_SIZE(pinmux_functions.automotive),
6525
6526 .cfg_regs = pinmux_config_regs,
6527 .drive_regs = pinmux_drive_regs,
6528 .bias_regs = pinmux_bias_regs,
6529 .ioctrl_regs = pinmux_ioctrl_regs,
6530
6531 .pinmux_data = pinmux_data,
6532 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6533};
6534#endif
6535
