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39#include <linux/clk.h>
40#include <linux/err.h>
41#include <linux/io.h>
42#include <linux/module.h>
43#include <linux/of.h>
44#include <linux/of_device.h>
45#include <linux/pwm.h>
46#include <linux/platform_device.h>
47#include <linux/pinctrl/consumer.h>
48#include <linux/slab.h>
49#include <linux/reset.h>
50
51#define PWM_ENABLE (1 << 31)
52#define PWM_DUTY_WIDTH 8
53#define PWM_DUTY_SHIFT 16
54#define PWM_SCALE_WIDTH 13
55#define PWM_SCALE_SHIFT 0
56
57struct tegra_pwm_soc {
58 unsigned int num_channels;
59
60
61 unsigned long max_frequency;
62};
63
64struct tegra_pwm_chip {
65 struct pwm_chip chip;
66 struct device *dev;
67
68 struct clk *clk;
69 struct reset_control*rst;
70
71 unsigned long clk_rate;
72 unsigned long min_period_ns;
73
74 void __iomem *regs;
75
76 const struct tegra_pwm_soc *soc;
77};
78
79static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
80{
81 return container_of(chip, struct tegra_pwm_chip, chip);
82}
83
84static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
85{
86 return readl(chip->regs + (num << 4));
87}
88
89static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
90 unsigned long val)
91{
92 writel(val, chip->regs + (num << 4));
93}
94
95static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
96 int duty_ns, int period_ns)
97{
98 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
99 unsigned long long c = duty_ns, hz;
100 unsigned long rate, required_clk_rate;
101 u32 val = 0;
102 int err;
103
104
105
106
107
108
109 c *= (1 << PWM_DUTY_WIDTH);
110 c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
111
112 val = (u32)c << PWM_DUTY_SHIFT;
113
114
115
116
117 if (period_ns < pc->min_period_ns)
118 return -EINVAL;
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133 if (pc->soc->num_channels == 1) {
134
135
136
137
138
139
140
141
142
143
144
145 required_clk_rate =
146 (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;
147
148 err = clk_set_rate(pc->clk, required_clk_rate);
149 if (err < 0)
150 return -EINVAL;
151
152
153 pc->clk_rate = clk_get_rate(pc->clk);
154 }
155
156 rate = pc->clk_rate >> PWM_DUTY_WIDTH;
157
158
159 hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns);
160 rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz);
161
162
163
164
165
166
167 if (rate > 0)
168 rate--;
169
170
171
172
173
174 if (rate >> PWM_SCALE_WIDTH)
175 return -EINVAL;
176
177 val |= rate << PWM_SCALE_SHIFT;
178
179
180
181
182
183 if (!pwm_is_enabled(pwm)) {
184 err = clk_prepare_enable(pc->clk);
185 if (err < 0)
186 return err;
187 } else
188 val |= PWM_ENABLE;
189
190 pwm_writel(pc, pwm->hwpwm, val);
191
192
193
194
195 if (!pwm_is_enabled(pwm))
196 clk_disable_unprepare(pc->clk);
197
198 return 0;
199}
200
201static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
202{
203 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
204 int rc = 0;
205 u32 val;
206
207 rc = clk_prepare_enable(pc->clk);
208 if (rc < 0)
209 return rc;
210
211 val = pwm_readl(pc, pwm->hwpwm);
212 val |= PWM_ENABLE;
213 pwm_writel(pc, pwm->hwpwm, val);
214
215 return 0;
216}
217
218static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
219{
220 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
221 u32 val;
222
223 val = pwm_readl(pc, pwm->hwpwm);
224 val &= ~PWM_ENABLE;
225 pwm_writel(pc, pwm->hwpwm, val);
226
227 clk_disable_unprepare(pc->clk);
228}
229
230static const struct pwm_ops tegra_pwm_ops = {
231 .config = tegra_pwm_config,
232 .enable = tegra_pwm_enable,
233 .disable = tegra_pwm_disable,
234 .owner = THIS_MODULE,
235};
236
237static int tegra_pwm_probe(struct platform_device *pdev)
238{
239 struct tegra_pwm_chip *pwm;
240 int ret;
241
242 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
243 if (!pwm)
244 return -ENOMEM;
245
246 pwm->soc = of_device_get_match_data(&pdev->dev);
247 pwm->dev = &pdev->dev;
248
249 pwm->regs = devm_platform_ioremap_resource(pdev, 0);
250 if (IS_ERR(pwm->regs))
251 return PTR_ERR(pwm->regs);
252
253 platform_set_drvdata(pdev, pwm);
254
255 pwm->clk = devm_clk_get(&pdev->dev, NULL);
256 if (IS_ERR(pwm->clk))
257 return PTR_ERR(pwm->clk);
258
259
260 ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency);
261 if (ret < 0) {
262 dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
263 return ret;
264 }
265
266
267
268
269
270
271 pwm->clk_rate = clk_get_rate(pwm->clk);
272
273
274 pwm->min_period_ns =
275 (NSEC_PER_SEC / (pwm->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;
276
277 pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
278 if (IS_ERR(pwm->rst)) {
279 ret = PTR_ERR(pwm->rst);
280 dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
281 return ret;
282 }
283
284 reset_control_deassert(pwm->rst);
285
286 pwm->chip.dev = &pdev->dev;
287 pwm->chip.ops = &tegra_pwm_ops;
288 pwm->chip.base = -1;
289 pwm->chip.npwm = pwm->soc->num_channels;
290
291 ret = pwmchip_add(&pwm->chip);
292 if (ret < 0) {
293 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
294 reset_control_assert(pwm->rst);
295 return ret;
296 }
297
298 return 0;
299}
300
301static int tegra_pwm_remove(struct platform_device *pdev)
302{
303 struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
304 unsigned int i;
305 int err;
306
307 if (WARN_ON(!pc))
308 return -ENODEV;
309
310 err = clk_prepare_enable(pc->clk);
311 if (err < 0)
312 return err;
313
314 for (i = 0; i < pc->chip.npwm; i++) {
315 struct pwm_device *pwm = &pc->chip.pwms[i];
316
317 if (!pwm_is_enabled(pwm))
318 if (clk_prepare_enable(pc->clk) < 0)
319 continue;
320
321 pwm_writel(pc, i, 0);
322
323 clk_disable_unprepare(pc->clk);
324 }
325
326 reset_control_assert(pc->rst);
327 clk_disable_unprepare(pc->clk);
328
329 return pwmchip_remove(&pc->chip);
330}
331
332#ifdef CONFIG_PM_SLEEP
333static int tegra_pwm_suspend(struct device *dev)
334{
335 return pinctrl_pm_select_sleep_state(dev);
336}
337
338static int tegra_pwm_resume(struct device *dev)
339{
340 return pinctrl_pm_select_default_state(dev);
341}
342#endif
343
344static const struct tegra_pwm_soc tegra20_pwm_soc = {
345 .num_channels = 4,
346 .max_frequency = 48000000UL,
347};
348
349static const struct tegra_pwm_soc tegra186_pwm_soc = {
350 .num_channels = 1,
351 .max_frequency = 102000000UL,
352};
353
354static const struct tegra_pwm_soc tegra194_pwm_soc = {
355 .num_channels = 1,
356 .max_frequency = 408000000UL,
357};
358
359static const struct of_device_id tegra_pwm_of_match[] = {
360 { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
361 { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
362 { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
363 { }
364};
365MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
366
367static const struct dev_pm_ops tegra_pwm_pm_ops = {
368 SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume)
369};
370
371static struct platform_driver tegra_pwm_driver = {
372 .driver = {
373 .name = "tegra-pwm",
374 .of_match_table = tegra_pwm_of_match,
375 .pm = &tegra_pwm_pm_ops,
376 },
377 .probe = tegra_pwm_probe,
378 .remove = tegra_pwm_remove,
379};
380
381module_platform_driver(tegra_pwm_driver);
382
383MODULE_LICENSE("GPL");
384MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>");
385MODULE_DESCRIPTION("Tegra PWM controller driver");
386MODULE_ALIAS("platform:tegra-pwm");
387