1/******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2020 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23#include <uapi/scsi/fc/fc_els.h> 24 25/* Macros to deal with bit fields. Each bit field must have 3 #defines 26 * associated with it (_SHIFT, _MASK, and _WORD). 27 * EG. For a bit field that is in the 7th bit of the "field4" field of a 28 * structure and is 2 bits in size the following #defines must exist: 29 * struct temp { 30 * uint32_t field1; 31 * uint32_t field2; 32 * uint32_t field3; 33 * uint32_t field4; 34 * #define example_bit_field_SHIFT 7 35 * #define example_bit_field_MASK 0x03 36 * #define example_bit_field_WORD field4 37 * uint32_t field5; 38 * }; 39 * Then the macros below may be used to get or set the value of that field. 40 * EG. To get the value of the bit field from the above example: 41 * struct temp t1; 42 * value = bf_get(example_bit_field, &t1); 43 * And then to set that bit field: 44 * bf_set(example_bit_field, &t1, 2); 45 * Or clear that bit field: 46 * bf_set(example_bit_field, &t1, 0); 47 */ 48#define bf_get_be32(name, ptr) \ 49 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 50#define bf_get_le32(name, ptr) \ 51 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 52#define bf_get(name, ptr) \ 53 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 54#define bf_set_le32(name, ptr, value) \ 55 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 56 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 57 ~(name##_MASK << name##_SHIFT))))) 58#define bf_set(name, ptr, value) \ 59 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 60 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 61 62struct dma_address { 63 uint32_t addr_lo; 64 uint32_t addr_hi; 65}; 66 67struct lpfc_sli_intf { 68 uint32_t word0; 69#define lpfc_sli_intf_valid_SHIFT 29 70#define lpfc_sli_intf_valid_MASK 0x00000007 71#define lpfc_sli_intf_valid_WORD word0 72#define LPFC_SLI_INTF_VALID 6 73#define lpfc_sli_intf_sli_hint2_SHIFT 24 74#define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 75#define lpfc_sli_intf_sli_hint2_WORD word0 76#define LPFC_SLI_INTF_SLI_HINT2_NONE 0 77#define lpfc_sli_intf_sli_hint1_SHIFT 16 78#define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 79#define lpfc_sli_intf_sli_hint1_WORD word0 80#define LPFC_SLI_INTF_SLI_HINT1_NONE 0 81#define LPFC_SLI_INTF_SLI_HINT1_1 1 82#define LPFC_SLI_INTF_SLI_HINT1_2 2 83#define lpfc_sli_intf_if_type_SHIFT 12 84#define lpfc_sli_intf_if_type_MASK 0x0000000F 85#define lpfc_sli_intf_if_type_WORD word0 86#define LPFC_SLI_INTF_IF_TYPE_0 0 87#define LPFC_SLI_INTF_IF_TYPE_1 1 88#define LPFC_SLI_INTF_IF_TYPE_2 2 89#define LPFC_SLI_INTF_IF_TYPE_6 6 90#define lpfc_sli_intf_sli_family_SHIFT 8 91#define lpfc_sli_intf_sli_family_MASK 0x0000000F 92#define lpfc_sli_intf_sli_family_WORD word0 93#define LPFC_SLI_INTF_FAMILY_BE2 0x0 94#define LPFC_SLI_INTF_FAMILY_BE3 0x1 95#define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 96#define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 97#define lpfc_sli_intf_slirev_SHIFT 4 98#define lpfc_sli_intf_slirev_MASK 0x0000000F 99#define lpfc_sli_intf_slirev_WORD word0 100#define LPFC_SLI_INTF_REV_SLI3 3 101#define LPFC_SLI_INTF_REV_SLI4 4 102#define lpfc_sli_intf_func_type_SHIFT 0 103#define lpfc_sli_intf_func_type_MASK 0x00000001 104#define lpfc_sli_intf_func_type_WORD word0 105#define LPFC_SLI_INTF_IF_TYPE_PHYS 0 106#define LPFC_SLI_INTF_IF_TYPE_VIRT 1 107}; 108 109#define LPFC_SLI4_MBX_EMBED true 110#define LPFC_SLI4_MBX_NEMBED false 111 112#define LPFC_SLI4_MB_WORD_COUNT 64 113#define LPFC_MAX_MQ_PAGE 8 114#define LPFC_MAX_WQ_PAGE_V0 4 115#define LPFC_MAX_WQ_PAGE 8 116#define LPFC_MAX_RQ_PAGE 8 117#define LPFC_MAX_CQ_PAGE 4 118#define LPFC_MAX_EQ_PAGE 8 119 120#define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 121#define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 122#define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 123 124/* Define SLI4 Alignment requirements. */ 125#define LPFC_ALIGN_16_BYTE 16 126#define LPFC_ALIGN_64_BYTE 64 127 128/* Define SLI4 specific definitions. */ 129#define LPFC_MQ_CQE_BYTE_OFFSET 256 130#define LPFC_MBX_CMD_HDR_LENGTH 16 131#define LPFC_MBX_ERROR_RANGE 0x4000 132#define LPFC_BMBX_BIT1_ADDR_HI 0x2 133#define LPFC_BMBX_BIT1_ADDR_LO 0 134#define LPFC_RPI_HDR_COUNT 64 135#define LPFC_HDR_TEMPLATE_SIZE 4096 136#define LPFC_RPI_ALLOC_ERROR 0xFFFF 137#define LPFC_FCF_RECORD_WD_CNT 132 138#define LPFC_ENTIRE_FCF_DATABASE 0 139#define LPFC_DFLT_FCF_INDEX 0 140 141/* Virtual function numbers */ 142#define LPFC_VF0 0 143#define LPFC_VF1 1 144#define LPFC_VF2 2 145#define LPFC_VF3 3 146#define LPFC_VF4 4 147#define LPFC_VF5 5 148#define LPFC_VF6 6 149#define LPFC_VF7 7 150#define LPFC_VF8 8 151#define LPFC_VF9 9 152#define LPFC_VF10 10 153#define LPFC_VF11 11 154#define LPFC_VF12 12 155#define LPFC_VF13 13 156#define LPFC_VF14 14 157#define LPFC_VF15 15 158#define LPFC_VF16 16 159#define LPFC_VF17 17 160#define LPFC_VF18 18 161#define LPFC_VF19 19 162#define LPFC_VF20 20 163#define LPFC_VF21 21 164#define LPFC_VF22 22 165#define LPFC_VF23 23 166#define LPFC_VF24 24 167#define LPFC_VF25 25 168#define LPFC_VF26 26 169#define LPFC_VF27 27 170#define LPFC_VF28 28 171#define LPFC_VF29 29 172#define LPFC_VF30 30 173#define LPFC_VF31 31 174 175/* PCI function numbers */ 176#define LPFC_PCI_FUNC0 0 177#define LPFC_PCI_FUNC1 1 178#define LPFC_PCI_FUNC2 2 179#define LPFC_PCI_FUNC3 3 180#define LPFC_PCI_FUNC4 4 181 182/* SLI4 interface type-2 PDEV_CTL register */ 183#define LPFC_CTL_PDEV_CTL_OFFSET 0x414 184#define LPFC_CTL_PDEV_CTL_DRST 0x00000001 185#define LPFC_CTL_PDEV_CTL_FRST 0x00000002 186#define LPFC_CTL_PDEV_CTL_DD 0x00000004 187#define LPFC_CTL_PDEV_CTL_LC 0x00000008 188#define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 189#define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 190#define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 191#define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000 192 193#define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 194 195/* Active interrupt test count */ 196#define LPFC_ACT_INTR_CNT 4 197 198/* Algrithmns for scheduling FCP commands to WQs */ 199#define LPFC_FCP_SCHED_BY_HDWQ 0 200#define LPFC_FCP_SCHED_BY_CPU 1 201 202/* Algrithmns for NameServer Query after RSCN */ 203#define LPFC_NS_QUERY_GID_FT 0 204#define LPFC_NS_QUERY_GID_PT 1 205 206/* Delay Multiplier constant */ 207#define LPFC_DMULT_CONST 651042 208#define LPFC_DMULT_MAX 1023 209 210/* Configuration of Interrupts / sec for entire HBA port */ 211#define LPFC_MIN_IMAX 5000 212#define LPFC_MAX_IMAX 5000000 213#define LPFC_DEF_IMAX 0 214 215#define LPFC_MAX_AUTO_EQ_DELAY 120 216#define LPFC_EQ_DELAY_STEP 15 217#define LPFC_EQD_ISR_TRIGGER 20000 218/* 1s intervals */ 219#define LPFC_EQ_DELAY_MSECS 1000 220 221#define LPFC_MIN_CPU_MAP 0 222#define LPFC_MAX_CPU_MAP 1 223#define LPFC_HBA_CPU_MAP 1 224 225/* PORT_CAPABILITIES constants. */ 226#define LPFC_MAX_SUPPORTED_PAGES 8 227 228struct ulp_bde64 { 229 union ULP_BDE_TUS { 230 uint32_t w; 231 struct { 232#ifdef __BIG_ENDIAN_BITFIELD 233 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 234 VALUE !! */ 235 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 236#else /* __LITTLE_ENDIAN_BITFIELD */ 237 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 238 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 239 VALUE !! */ 240#endif 241#define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 242#define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 243#define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 244#define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 245#define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 246#define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 247#define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 248 } f; 249 } tus; 250 uint32_t addrLow; 251 uint32_t addrHigh; 252}; 253 254/* Maximun size of immediate data that can fit into a 128 byte WQE */ 255#define LPFC_MAX_BDE_IMM_SIZE 64 256 257struct lpfc_sli4_flags { 258 uint32_t word0; 259#define lpfc_idx_rsrc_rdy_SHIFT 0 260#define lpfc_idx_rsrc_rdy_MASK 0x00000001 261#define lpfc_idx_rsrc_rdy_WORD word0 262#define LPFC_IDX_RSRC_RDY 1 263#define lpfc_rpi_rsrc_rdy_SHIFT 1 264#define lpfc_rpi_rsrc_rdy_MASK 0x00000001 265#define lpfc_rpi_rsrc_rdy_WORD word0 266#define LPFC_RPI_RSRC_RDY 1 267#define lpfc_vpi_rsrc_rdy_SHIFT 2 268#define lpfc_vpi_rsrc_rdy_MASK 0x00000001 269#define lpfc_vpi_rsrc_rdy_WORD word0 270#define LPFC_VPI_RSRC_RDY 1 271#define lpfc_vfi_rsrc_rdy_SHIFT 3 272#define lpfc_vfi_rsrc_rdy_MASK 0x00000001 273#define lpfc_vfi_rsrc_rdy_WORD word0 274#define LPFC_VFI_RSRC_RDY 1 275}; 276 277struct sli4_bls_rsp { 278 uint32_t word0_rsvd; /* Word0 must be reserved */ 279 uint32_t word1; 280#define lpfc_abts_orig_SHIFT 0 281#define lpfc_abts_orig_MASK 0x00000001 282#define lpfc_abts_orig_WORD word1 283#define LPFC_ABTS_UNSOL_RSP 1 284#define LPFC_ABTS_UNSOL_INT 0 285 uint32_t word2; 286#define lpfc_abts_rxid_SHIFT 0 287#define lpfc_abts_rxid_MASK 0x0000FFFF 288#define lpfc_abts_rxid_WORD word2 289#define lpfc_abts_oxid_SHIFT 16 290#define lpfc_abts_oxid_MASK 0x0000FFFF 291#define lpfc_abts_oxid_WORD word2 292 uint32_t word3; 293#define lpfc_vndr_code_SHIFT 0 294#define lpfc_vndr_code_MASK 0x000000FF 295#define lpfc_vndr_code_WORD word3 296#define lpfc_rsn_expln_SHIFT 8 297#define lpfc_rsn_expln_MASK 0x000000FF 298#define lpfc_rsn_expln_WORD word3 299#define lpfc_rsn_code_SHIFT 16 300#define lpfc_rsn_code_MASK 0x000000FF 301#define lpfc_rsn_code_WORD word3 302 303 uint32_t word4; 304 uint32_t word5_rsvd; /* Word5 must be reserved */ 305}; 306 307/* event queue entry structure */ 308struct lpfc_eqe { 309 uint32_t word0; 310#define lpfc_eqe_resource_id_SHIFT 16 311#define lpfc_eqe_resource_id_MASK 0x0000FFFF 312#define lpfc_eqe_resource_id_WORD word0 313#define lpfc_eqe_minor_code_SHIFT 4 314#define lpfc_eqe_minor_code_MASK 0x00000FFF 315#define lpfc_eqe_minor_code_WORD word0 316#define lpfc_eqe_major_code_SHIFT 1 317#define lpfc_eqe_major_code_MASK 0x00000007 318#define lpfc_eqe_major_code_WORD word0 319#define lpfc_eqe_valid_SHIFT 0 320#define lpfc_eqe_valid_MASK 0x00000001 321#define lpfc_eqe_valid_WORD word0 322}; 323 324/* completion queue entry structure (common fields for all cqe types) */ 325struct lpfc_cqe { 326 uint32_t reserved0; 327 uint32_t reserved1; 328 uint32_t reserved2; 329 uint32_t word3; 330#define lpfc_cqe_valid_SHIFT 31 331#define lpfc_cqe_valid_MASK 0x00000001 332#define lpfc_cqe_valid_WORD word3 333#define lpfc_cqe_code_SHIFT 16 334#define lpfc_cqe_code_MASK 0x000000FF 335#define lpfc_cqe_code_WORD word3 336}; 337 338/* Completion Queue Entry Status Codes */ 339#define CQE_STATUS_SUCCESS 0x0 340#define CQE_STATUS_FCP_RSP_FAILURE 0x1 341#define CQE_STATUS_REMOTE_STOP 0x2 342#define CQE_STATUS_LOCAL_REJECT 0x3 343#define CQE_STATUS_NPORT_RJT 0x4 344#define CQE_STATUS_FABRIC_RJT 0x5 345#define CQE_STATUS_NPORT_BSY 0x6 346#define CQE_STATUS_FABRIC_BSY 0x7 347#define CQE_STATUS_INTERMED_RSP 0x8 348#define CQE_STATUS_LS_RJT 0x9 349#define CQE_STATUS_CMD_REJECT 0xb 350#define CQE_STATUS_FCP_TGT_LENCHECK 0xc 351#define CQE_STATUS_NEED_BUFF_ENTRY 0xf 352#define CQE_STATUS_DI_ERROR 0x16 353 354/* Used when mapping CQE status to IOCB */ 355#define LPFC_IOCB_STATUS_MASK 0xf 356 357/* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 358#define CQE_HW_STATUS_NO_ERR 0x0 359#define CQE_HW_STATUS_UNDERRUN 0x1 360#define CQE_HW_STATUS_OVERRUN 0x2 361 362/* Completion Queue Entry Codes */ 363#define CQE_CODE_COMPL_WQE 0x1 364#define CQE_CODE_RELEASE_WQE 0x2 365#define CQE_CODE_RECEIVE 0x4 366#define CQE_CODE_XRI_ABORTED 0x5 367#define CQE_CODE_RECEIVE_V1 0x9 368#define CQE_CODE_NVME_ERSP 0xd 369 370/* 371 * Define mask value for xri_aborted and wcqe completed CQE extended status. 372 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 373 */ 374#define WCQE_PARAM_MASK 0x1FF 375 376/* completion queue entry for wqe completions */ 377struct lpfc_wcqe_complete { 378 uint32_t word0; 379#define lpfc_wcqe_c_request_tag_SHIFT 16 380#define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 381#define lpfc_wcqe_c_request_tag_WORD word0 382#define lpfc_wcqe_c_status_SHIFT 8 383#define lpfc_wcqe_c_status_MASK 0x000000FF 384#define lpfc_wcqe_c_status_WORD word0 385#define lpfc_wcqe_c_hw_status_SHIFT 0 386#define lpfc_wcqe_c_hw_status_MASK 0x000000FF 387#define lpfc_wcqe_c_hw_status_WORD word0 388#define lpfc_wcqe_c_ersp0_SHIFT 0 389#define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF 390#define lpfc_wcqe_c_ersp0_WORD word0 391 uint32_t total_data_placed; 392 uint32_t parameter; 393#define lpfc_wcqe_c_bg_edir_SHIFT 5 394#define lpfc_wcqe_c_bg_edir_MASK 0x00000001 395#define lpfc_wcqe_c_bg_edir_WORD parameter 396#define lpfc_wcqe_c_bg_tdpv_SHIFT 3 397#define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 398#define lpfc_wcqe_c_bg_tdpv_WORD parameter 399#define lpfc_wcqe_c_bg_re_SHIFT 2 400#define lpfc_wcqe_c_bg_re_MASK 0x00000001 401#define lpfc_wcqe_c_bg_re_WORD parameter 402#define lpfc_wcqe_c_bg_ae_SHIFT 1 403#define lpfc_wcqe_c_bg_ae_MASK 0x00000001 404#define lpfc_wcqe_c_bg_ae_WORD parameter 405#define lpfc_wcqe_c_bg_ge_SHIFT 0 406#define lpfc_wcqe_c_bg_ge_MASK 0x00000001 407#define lpfc_wcqe_c_bg_ge_WORD parameter 408 uint32_t word3; 409#define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 410#define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 411#define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 412#define lpfc_wcqe_c_xb_SHIFT 28 413#define lpfc_wcqe_c_xb_MASK 0x00000001 414#define lpfc_wcqe_c_xb_WORD word3 415#define lpfc_wcqe_c_pv_SHIFT 27 416#define lpfc_wcqe_c_pv_MASK 0x00000001 417#define lpfc_wcqe_c_pv_WORD word3 418#define lpfc_wcqe_c_priority_SHIFT 24 419#define lpfc_wcqe_c_priority_MASK 0x00000007 420#define lpfc_wcqe_c_priority_WORD word3 421#define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 422#define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 423#define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 424#define lpfc_wcqe_c_sqhead_SHIFT 0 425#define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF 426#define lpfc_wcqe_c_sqhead_WORD word3 427}; 428 429/* completion queue entry for wqe release */ 430struct lpfc_wcqe_release { 431 uint32_t reserved0; 432 uint32_t reserved1; 433 uint32_t word2; 434#define lpfc_wcqe_r_wq_id_SHIFT 16 435#define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 436#define lpfc_wcqe_r_wq_id_WORD word2 437#define lpfc_wcqe_r_wqe_index_SHIFT 0 438#define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 439#define lpfc_wcqe_r_wqe_index_WORD word2 440 uint32_t word3; 441#define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 442#define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 443#define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 444#define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 445#define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 446#define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 447}; 448 449struct sli4_wcqe_xri_aborted { 450 uint32_t word0; 451#define lpfc_wcqe_xa_status_SHIFT 8 452#define lpfc_wcqe_xa_status_MASK 0x000000FF 453#define lpfc_wcqe_xa_status_WORD word0 454 uint32_t parameter; 455 uint32_t word2; 456#define lpfc_wcqe_xa_remote_xid_SHIFT 16 457#define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 458#define lpfc_wcqe_xa_remote_xid_WORD word2 459#define lpfc_wcqe_xa_xri_SHIFT 0 460#define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 461#define lpfc_wcqe_xa_xri_WORD word2 462 uint32_t word3; 463#define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 464#define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 465#define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 466#define lpfc_wcqe_xa_ia_SHIFT 30 467#define lpfc_wcqe_xa_ia_MASK 0x00000001 468#define lpfc_wcqe_xa_ia_WORD word3 469#define CQE_XRI_ABORTED_IA_REMOTE 0 470#define CQE_XRI_ABORTED_IA_LOCAL 1 471#define lpfc_wcqe_xa_br_SHIFT 29 472#define lpfc_wcqe_xa_br_MASK 0x00000001 473#define lpfc_wcqe_xa_br_WORD word3 474#define CQE_XRI_ABORTED_BR_BA_ACC 0 475#define CQE_XRI_ABORTED_BR_BA_RJT 1 476#define lpfc_wcqe_xa_eo_SHIFT 28 477#define lpfc_wcqe_xa_eo_MASK 0x00000001 478#define lpfc_wcqe_xa_eo_WORD word3 479#define CQE_XRI_ABORTED_EO_REMOTE 0 480#define CQE_XRI_ABORTED_EO_LOCAL 1 481#define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 482#define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 483#define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 484}; 485 486/* completion queue entry structure for rqe completion */ 487struct lpfc_rcqe { 488 uint32_t word0; 489#define lpfc_rcqe_bindex_SHIFT 16 490#define lpfc_rcqe_bindex_MASK 0x0000FFF 491#define lpfc_rcqe_bindex_WORD word0 492#define lpfc_rcqe_status_SHIFT 8 493#define lpfc_rcqe_status_MASK 0x000000FF 494#define lpfc_rcqe_status_WORD word0 495#define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 496#define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 497#define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 498#define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 499 uint32_t word1; 500#define lpfc_rcqe_fcf_id_v1_SHIFT 0 501#define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 502#define lpfc_rcqe_fcf_id_v1_WORD word1 503 uint32_t word2; 504#define lpfc_rcqe_length_SHIFT 16 505#define lpfc_rcqe_length_MASK 0x0000FFFF 506#define lpfc_rcqe_length_WORD word2 507#define lpfc_rcqe_rq_id_SHIFT 6 508#define lpfc_rcqe_rq_id_MASK 0x000003FF 509#define lpfc_rcqe_rq_id_WORD word2 510#define lpfc_rcqe_fcf_id_SHIFT 0 511#define lpfc_rcqe_fcf_id_MASK 0x0000003F 512#define lpfc_rcqe_fcf_id_WORD word2 513#define lpfc_rcqe_rq_id_v1_SHIFT 0 514#define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 515#define lpfc_rcqe_rq_id_v1_WORD word2 516 uint32_t word3; 517#define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 518#define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 519#define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 520#define lpfc_rcqe_port_SHIFT 30 521#define lpfc_rcqe_port_MASK 0x00000001 522#define lpfc_rcqe_port_WORD word3 523#define lpfc_rcqe_hdr_length_SHIFT 24 524#define lpfc_rcqe_hdr_length_MASK 0x0000001F 525#define lpfc_rcqe_hdr_length_WORD word3 526#define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 527#define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 528#define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 529#define lpfc_rcqe_eof_SHIFT 8 530#define lpfc_rcqe_eof_MASK 0x000000FF 531#define lpfc_rcqe_eof_WORD word3 532#define FCOE_EOFn 0x41 533#define FCOE_EOFt 0x42 534#define FCOE_EOFni 0x49 535#define FCOE_EOFa 0x50 536#define lpfc_rcqe_sof_SHIFT 0 537#define lpfc_rcqe_sof_MASK 0x000000FF 538#define lpfc_rcqe_sof_WORD word3 539#define FCOE_SOFi2 0x2d 540#define FCOE_SOFi3 0x2e 541#define FCOE_SOFn2 0x35 542#define FCOE_SOFn3 0x36 543}; 544 545struct lpfc_rqe { 546 uint32_t address_hi; 547 uint32_t address_lo; 548}; 549 550/* buffer descriptors */ 551struct lpfc_bde4 { 552 uint32_t addr_hi; 553 uint32_t addr_lo; 554 uint32_t word2; 555#define lpfc_bde4_last_SHIFT 31 556#define lpfc_bde4_last_MASK 0x00000001 557#define lpfc_bde4_last_WORD word2 558#define lpfc_bde4_sge_offset_SHIFT 0 559#define lpfc_bde4_sge_offset_MASK 0x000003FF 560#define lpfc_bde4_sge_offset_WORD word2 561 uint32_t word3; 562#define lpfc_bde4_length_SHIFT 0 563#define lpfc_bde4_length_MASK 0x000000FF 564#define lpfc_bde4_length_WORD word3 565}; 566 567struct lpfc_register { 568 uint32_t word0; 569}; 570 571#define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000 572#define LPFC_PORT_SEM_MASK 0xF000 573/* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 574#define LPFC_UERR_STATUS_HI 0x00A4 575#define LPFC_UERR_STATUS_LO 0x00A0 576#define LPFC_UE_MASK_HI 0x00AC 577#define LPFC_UE_MASK_LO 0x00A8 578 579/* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 580#define LPFC_SLI_INTF 0x0058 581#define LPFC_SLI_ASIC_VER 0x009C 582 583#define LPFC_CTL_PORT_SEM_OFFSET 0x400 584#define lpfc_port_smphr_perr_SHIFT 31 585#define lpfc_port_smphr_perr_MASK 0x1 586#define lpfc_port_smphr_perr_WORD word0 587#define lpfc_port_smphr_sfi_SHIFT 30 588#define lpfc_port_smphr_sfi_MASK 0x1 589#define lpfc_port_smphr_sfi_WORD word0 590#define lpfc_port_smphr_nip_SHIFT 29 591#define lpfc_port_smphr_nip_MASK 0x1 592#define lpfc_port_smphr_nip_WORD word0 593#define lpfc_port_smphr_ipc_SHIFT 28 594#define lpfc_port_smphr_ipc_MASK 0x1 595#define lpfc_port_smphr_ipc_WORD word0 596#define lpfc_port_smphr_scr1_SHIFT 27 597#define lpfc_port_smphr_scr1_MASK 0x1 598#define lpfc_port_smphr_scr1_WORD word0 599#define lpfc_port_smphr_scr2_SHIFT 26 600#define lpfc_port_smphr_scr2_MASK 0x1 601#define lpfc_port_smphr_scr2_WORD word0 602#define lpfc_port_smphr_host_scratch_SHIFT 16 603#define lpfc_port_smphr_host_scratch_MASK 0xFF 604#define lpfc_port_smphr_host_scratch_WORD word0 605#define lpfc_port_smphr_port_status_SHIFT 0 606#define lpfc_port_smphr_port_status_MASK 0xFFFF 607#define lpfc_port_smphr_port_status_WORD word0 608 609#define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 610#define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 611#define LPFC_POST_STAGE_HOST_RDY 0x0002 612#define LPFC_POST_STAGE_BE_RESET 0x0003 613#define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 614#define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 615#define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 616#define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 617#define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 618#define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 619#define LPFC_POST_STAGE_DDR_TEST_START 0x0400 620#define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 621#define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 622#define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 623#define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 624#define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 625#define LPFC_POST_STAGE_ARMFW_START 0x0800 626#define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 627#define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 628#define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 629#define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 630#define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 631#define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 632#define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 633#define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 634#define LPFC_POST_STAGE_PARSE_XML 0x0B04 635#define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 636#define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 637#define LPFC_POST_STAGE_RC_DONE 0x0B07 638#define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 639#define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 640#define LPFC_POST_STAGE_PORT_READY 0xC000 641#define LPFC_POST_STAGE_PORT_UE 0xF000 642 643#define LPFC_CTL_PORT_STA_OFFSET 0x404 644#define lpfc_sliport_status_err_SHIFT 31 645#define lpfc_sliport_status_err_MASK 0x1 646#define lpfc_sliport_status_err_WORD word0 647#define lpfc_sliport_status_end_SHIFT 30 648#define lpfc_sliport_status_end_MASK 0x1 649#define lpfc_sliport_status_end_WORD word0 650#define lpfc_sliport_status_oti_SHIFT 29 651#define lpfc_sliport_status_oti_MASK 0x1 652#define lpfc_sliport_status_oti_WORD word0 653#define lpfc_sliport_status_dip_SHIFT 25 654#define lpfc_sliport_status_dip_MASK 0x1 655#define lpfc_sliport_status_dip_WORD word0 656#define lpfc_sliport_status_rn_SHIFT 24 657#define lpfc_sliport_status_rn_MASK 0x1 658#define lpfc_sliport_status_rn_WORD word0 659#define lpfc_sliport_status_rdy_SHIFT 23 660#define lpfc_sliport_status_rdy_MASK 0x1 661#define lpfc_sliport_status_rdy_WORD word0 662#define MAX_IF_TYPE_2_RESETS 6 663 664#define LPFC_CTL_PORT_CTL_OFFSET 0x408 665#define lpfc_sliport_ctrl_end_SHIFT 30 666#define lpfc_sliport_ctrl_end_MASK 0x1 667#define lpfc_sliport_ctrl_end_WORD word0 668#define LPFC_SLIPORT_LITTLE_ENDIAN 0 669#define LPFC_SLIPORT_BIG_ENDIAN 1 670#define lpfc_sliport_ctrl_ip_SHIFT 27 671#define lpfc_sliport_ctrl_ip_MASK 0x1 672#define lpfc_sliport_ctrl_ip_WORD word0 673#define LPFC_SLIPORT_INIT_PORT 1 674 675#define LPFC_CTL_PORT_ER1_OFFSET 0x40C 676#define LPFC_CTL_PORT_ER2_OFFSET 0x410 677 678#define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418 679#define lpfc_sliport_eqdelay_delay_SHIFT 16 680#define lpfc_sliport_eqdelay_delay_MASK 0xffff 681#define lpfc_sliport_eqdelay_delay_WORD word0 682#define lpfc_sliport_eqdelay_id_SHIFT 0 683#define lpfc_sliport_eqdelay_id_MASK 0xfff 684#define lpfc_sliport_eqdelay_id_WORD word0 685#define LPFC_SEC_TO_USEC 1000000 686 687/* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 688 * reside in BAR 2. 689 */ 690#define LPFC_SLIPORT_IF0_SMPHR 0x00AC 691 692#define LPFC_IMR_MASK_ALL 0xFFFFFFFF 693#define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 694 695#define LPFC_HST_ISR0 0x0C18 696#define LPFC_HST_ISR1 0x0C1C 697#define LPFC_HST_ISR2 0x0C20 698#define LPFC_HST_ISR3 0x0C24 699#define LPFC_HST_ISR4 0x0C28 700 701#define LPFC_HST_IMR0 0x0C48 702#define LPFC_HST_IMR1 0x0C4C 703#define LPFC_HST_IMR2 0x0C50 704#define LPFC_HST_IMR3 0x0C54 705#define LPFC_HST_IMR4 0x0C58 706 707#define LPFC_HST_ISCR0 0x0C78 708#define LPFC_HST_ISCR1 0x0C7C 709#define LPFC_HST_ISCR2 0x0C80 710#define LPFC_HST_ISCR3 0x0C84 711#define LPFC_HST_ISCR4 0x0C88 712 713#define LPFC_SLI4_INTR0 BIT0 714#define LPFC_SLI4_INTR1 BIT1 715#define LPFC_SLI4_INTR2 BIT2 716#define LPFC_SLI4_INTR3 BIT3 717#define LPFC_SLI4_INTR4 BIT4 718#define LPFC_SLI4_INTR5 BIT5 719#define LPFC_SLI4_INTR6 BIT6 720#define LPFC_SLI4_INTR7 BIT7 721#define LPFC_SLI4_INTR8 BIT8 722#define LPFC_SLI4_INTR9 BIT9 723#define LPFC_SLI4_INTR10 BIT10 724#define LPFC_SLI4_INTR11 BIT11 725#define LPFC_SLI4_INTR12 BIT12 726#define LPFC_SLI4_INTR13 BIT13 727#define LPFC_SLI4_INTR14 BIT14 728#define LPFC_SLI4_INTR15 BIT15 729#define LPFC_SLI4_INTR16 BIT16 730#define LPFC_SLI4_INTR17 BIT17 731#define LPFC_SLI4_INTR18 BIT18 732#define LPFC_SLI4_INTR19 BIT19 733#define LPFC_SLI4_INTR20 BIT20 734#define LPFC_SLI4_INTR21 BIT21 735#define LPFC_SLI4_INTR22 BIT22 736#define LPFC_SLI4_INTR23 BIT23 737#define LPFC_SLI4_INTR24 BIT24 738#define LPFC_SLI4_INTR25 BIT25 739#define LPFC_SLI4_INTR26 BIT26 740#define LPFC_SLI4_INTR27 BIT27 741#define LPFC_SLI4_INTR28 BIT28 742#define LPFC_SLI4_INTR29 BIT29 743#define LPFC_SLI4_INTR30 BIT30 744#define LPFC_SLI4_INTR31 BIT31 745 746/* 747 * The Doorbell registers defined here exist in different BAR 748 * register sets depending on the UCNA Port's reported if_type 749 * value. For UCNA ports running SLI4 and if_type 0, they reside in 750 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 751 * BAR0. For FC ports running SLI4 and if_type 6, they reside in 752 * BAR2. The offsets and base address are different, so the driver 753 * has to compute the register addresses accordingly 754 */ 755#define LPFC_ULP0_RQ_DOORBELL 0x00A0 756#define LPFC_ULP1_RQ_DOORBELL 0x00C0 757#define LPFC_IF6_RQ_DOORBELL 0x0080 758#define lpfc_rq_db_list_fm_num_posted_SHIFT 24 759#define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 760#define lpfc_rq_db_list_fm_num_posted_WORD word0 761#define lpfc_rq_db_list_fm_index_SHIFT 16 762#define lpfc_rq_db_list_fm_index_MASK 0x00FF 763#define lpfc_rq_db_list_fm_index_WORD word0 764#define lpfc_rq_db_list_fm_id_SHIFT 0 765#define lpfc_rq_db_list_fm_id_MASK 0xFFFF 766#define lpfc_rq_db_list_fm_id_WORD word0 767#define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 768#define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 769#define lpfc_rq_db_ring_fm_num_posted_WORD word0 770#define lpfc_rq_db_ring_fm_id_SHIFT 0 771#define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 772#define lpfc_rq_db_ring_fm_id_WORD word0 773 774#define LPFC_ULP0_WQ_DOORBELL 0x0040 775#define LPFC_ULP1_WQ_DOORBELL 0x0060 776#define lpfc_wq_db_list_fm_num_posted_SHIFT 24 777#define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 778#define lpfc_wq_db_list_fm_num_posted_WORD word0 779#define lpfc_wq_db_list_fm_index_SHIFT 16 780#define lpfc_wq_db_list_fm_index_MASK 0x00FF 781#define lpfc_wq_db_list_fm_index_WORD word0 782#define lpfc_wq_db_list_fm_id_SHIFT 0 783#define lpfc_wq_db_list_fm_id_MASK 0xFFFF 784#define lpfc_wq_db_list_fm_id_WORD word0 785#define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 786#define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 787#define lpfc_wq_db_ring_fm_num_posted_WORD word0 788#define lpfc_wq_db_ring_fm_id_SHIFT 0 789#define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 790#define lpfc_wq_db_ring_fm_id_WORD word0 791 792#define LPFC_IF6_WQ_DOORBELL 0x0040 793#define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24 794#define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF 795#define lpfc_if6_wq_db_list_fm_num_posted_WORD word0 796#define lpfc_if6_wq_db_list_fm_dpp_SHIFT 23 797#define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001 798#define lpfc_if6_wq_db_list_fm_dpp_WORD word0 799#define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT 16 800#define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F 801#define lpfc_if6_wq_db_list_fm_dpp_id_WORD word0 802#define lpfc_if6_wq_db_list_fm_id_SHIFT 0 803#define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF 804#define lpfc_if6_wq_db_list_fm_id_WORD word0 805 806#define LPFC_EQCQ_DOORBELL 0x0120 807#define lpfc_eqcq_doorbell_se_SHIFT 31 808#define lpfc_eqcq_doorbell_se_MASK 0x0001 809#define lpfc_eqcq_doorbell_se_WORD word0 810#define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 811#define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 812#define lpfc_eqcq_doorbell_arm_SHIFT 29 813#define lpfc_eqcq_doorbell_arm_MASK 0x0001 814#define lpfc_eqcq_doorbell_arm_WORD word0 815#define lpfc_eqcq_doorbell_num_released_SHIFT 16 816#define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 817#define lpfc_eqcq_doorbell_num_released_WORD word0 818#define lpfc_eqcq_doorbell_qt_SHIFT 10 819#define lpfc_eqcq_doorbell_qt_MASK 0x0001 820#define lpfc_eqcq_doorbell_qt_WORD word0 821#define LPFC_QUEUE_TYPE_COMPLETION 0 822#define LPFC_QUEUE_TYPE_EVENT 1 823#define lpfc_eqcq_doorbell_eqci_SHIFT 9 824#define lpfc_eqcq_doorbell_eqci_MASK 0x0001 825#define lpfc_eqcq_doorbell_eqci_WORD word0 826#define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 827#define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 828#define lpfc_eqcq_doorbell_cqid_lo_WORD word0 829#define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 830#define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 831#define lpfc_eqcq_doorbell_cqid_hi_WORD word0 832#define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 833#define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 834#define lpfc_eqcq_doorbell_eqid_lo_WORD word0 835#define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 836#define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 837#define lpfc_eqcq_doorbell_eqid_hi_WORD word0 838#define LPFC_CQID_HI_FIELD_SHIFT 10 839#define LPFC_EQID_HI_FIELD_SHIFT 9 840 841#define LPFC_IF6_CQ_DOORBELL 0x00C0 842#define lpfc_if6_cq_doorbell_se_SHIFT 31 843#define lpfc_if6_cq_doorbell_se_MASK 0x0001 844#define lpfc_if6_cq_doorbell_se_WORD word0 845#define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0 846#define LPFC_IF6_CQ_SOLICIT_ENABLE_ON 1 847#define lpfc_if6_cq_doorbell_arm_SHIFT 29 848#define lpfc_if6_cq_doorbell_arm_MASK 0x0001 849#define lpfc_if6_cq_doorbell_arm_WORD word0 850#define lpfc_if6_cq_doorbell_num_released_SHIFT 16 851#define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF 852#define lpfc_if6_cq_doorbell_num_released_WORD word0 853#define lpfc_if6_cq_doorbell_cqid_SHIFT 0 854#define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF 855#define lpfc_if6_cq_doorbell_cqid_WORD word0 856 857#define LPFC_IF6_EQ_DOORBELL 0x0120 858#define lpfc_if6_eq_doorbell_io_SHIFT 31 859#define lpfc_if6_eq_doorbell_io_MASK 0x0001 860#define lpfc_if6_eq_doorbell_io_WORD word0 861#define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0 862#define LPFC_IF6_EQ_INTR_OVERRIDE_ON 1 863#define lpfc_if6_eq_doorbell_arm_SHIFT 29 864#define lpfc_if6_eq_doorbell_arm_MASK 0x0001 865#define lpfc_if6_eq_doorbell_arm_WORD word0 866#define lpfc_if6_eq_doorbell_num_released_SHIFT 16 867#define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF 868#define lpfc_if6_eq_doorbell_num_released_WORD word0 869#define lpfc_if6_eq_doorbell_eqid_SHIFT 0 870#define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF 871#define lpfc_if6_eq_doorbell_eqid_WORD word0 872 873#define LPFC_BMBX 0x0160 874#define lpfc_bmbx_addr_SHIFT 2 875#define lpfc_bmbx_addr_MASK 0x3FFFFFFF 876#define lpfc_bmbx_addr_WORD word0 877#define lpfc_bmbx_hi_SHIFT 1 878#define lpfc_bmbx_hi_MASK 0x0001 879#define lpfc_bmbx_hi_WORD word0 880#define lpfc_bmbx_rdy_SHIFT 0 881#define lpfc_bmbx_rdy_MASK 0x0001 882#define lpfc_bmbx_rdy_WORD word0 883 884#define LPFC_MQ_DOORBELL 0x0140 885#define LPFC_IF6_MQ_DOORBELL 0x0160 886#define lpfc_mq_doorbell_num_posted_SHIFT 16 887#define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 888#define lpfc_mq_doorbell_num_posted_WORD word0 889#define lpfc_mq_doorbell_id_SHIFT 0 890#define lpfc_mq_doorbell_id_MASK 0xFFFF 891#define lpfc_mq_doorbell_id_WORD word0 892 893struct lpfc_sli4_cfg_mhdr { 894 uint32_t word1; 895#define lpfc_mbox_hdr_emb_SHIFT 0 896#define lpfc_mbox_hdr_emb_MASK 0x00000001 897#define lpfc_mbox_hdr_emb_WORD word1 898#define lpfc_mbox_hdr_sge_cnt_SHIFT 3 899#define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 900#define lpfc_mbox_hdr_sge_cnt_WORD word1 901 uint32_t payload_length; 902 uint32_t tag_lo; 903 uint32_t tag_hi; 904 uint32_t reserved5; 905}; 906 907union lpfc_sli4_cfg_shdr { 908 struct { 909 uint32_t word6; 910#define lpfc_mbox_hdr_opcode_SHIFT 0 911#define lpfc_mbox_hdr_opcode_MASK 0x000000FF 912#define lpfc_mbox_hdr_opcode_WORD word6 913#define lpfc_mbox_hdr_subsystem_SHIFT 8 914#define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 915#define lpfc_mbox_hdr_subsystem_WORD word6 916#define lpfc_mbox_hdr_port_number_SHIFT 16 917#define lpfc_mbox_hdr_port_number_MASK 0x000000FF 918#define lpfc_mbox_hdr_port_number_WORD word6 919#define lpfc_mbox_hdr_domain_SHIFT 24 920#define lpfc_mbox_hdr_domain_MASK 0x000000FF 921#define lpfc_mbox_hdr_domain_WORD word6 922 uint32_t timeout; 923 uint32_t request_length; 924 uint32_t word9; 925#define lpfc_mbox_hdr_version_SHIFT 0 926#define lpfc_mbox_hdr_version_MASK 0x000000FF 927#define lpfc_mbox_hdr_version_WORD word9 928#define lpfc_mbox_hdr_pf_num_SHIFT 16 929#define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 930#define lpfc_mbox_hdr_pf_num_WORD word9 931#define lpfc_mbox_hdr_vh_num_SHIFT 24 932#define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 933#define lpfc_mbox_hdr_vh_num_WORD word9 934#define LPFC_Q_CREATE_VERSION_2 2 935#define LPFC_Q_CREATE_VERSION_1 1 936#define LPFC_Q_CREATE_VERSION_0 0 937#define LPFC_OPCODE_VERSION_0 0 938#define LPFC_OPCODE_VERSION_1 1 939 } request; 940 struct { 941 uint32_t word6; 942#define lpfc_mbox_hdr_opcode_SHIFT 0 943#define lpfc_mbox_hdr_opcode_MASK 0x000000FF 944#define lpfc_mbox_hdr_opcode_WORD word6 945#define lpfc_mbox_hdr_subsystem_SHIFT 8 946#define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 947#define lpfc_mbox_hdr_subsystem_WORD word6 948#define lpfc_mbox_hdr_domain_SHIFT 24 949#define lpfc_mbox_hdr_domain_MASK 0x000000FF 950#define lpfc_mbox_hdr_domain_WORD word6 951 uint32_t word7; 952#define lpfc_mbox_hdr_status_SHIFT 0 953#define lpfc_mbox_hdr_status_MASK 0x000000FF 954#define lpfc_mbox_hdr_status_WORD word7 955#define lpfc_mbox_hdr_add_status_SHIFT 8 956#define lpfc_mbox_hdr_add_status_MASK 0x000000FF 957#define lpfc_mbox_hdr_add_status_WORD word7 958 uint32_t response_length; 959 uint32_t actual_response_length; 960 } response; 961}; 962 963/* Mailbox Header structures. 964 * struct mbox_header is defined for first generation SLI4_CFG mailbox 965 * calls deployed for BE-based ports. 966 * 967 * struct sli4_mbox_header is defined for second generation SLI4 968 * ports that don't deploy the SLI4_CFG mechanism. 969 */ 970struct mbox_header { 971 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 972 union lpfc_sli4_cfg_shdr cfg_shdr; 973}; 974 975#define LPFC_EXTENT_LOCAL 0 976#define LPFC_TIMEOUT_DEFAULT 0 977#define LPFC_EXTENT_VERSION_DEFAULT 0 978 979/* Subsystem Definitions */ 980#define LPFC_MBOX_SUBSYSTEM_NA 0x0 981#define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 982#define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB 983#define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 984 985/* Device Specific Definitions */ 986 987/* The HOST ENDIAN defines are in Big Endian format. */ 988#define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 989#define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 990 991/* Common Opcodes */ 992#define LPFC_MBOX_OPCODE_NA 0x00 993#define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 994#define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 995#define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 996#define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 997#define LPFC_MBOX_OPCODE_NOP 0x21 998#define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 999#define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 1000#define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36
1001#define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 1002#define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 1003#define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 1004#define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 1005#define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 1006#define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45 1007#define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46 1008#define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 1009#define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 1010#define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 1011#define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D 1012#define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 1013#define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 1014#define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 1015#define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 1016#define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 1017#define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 1018#define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 1019#define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 1020#define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 1021#define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 1022#define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 1023#define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 1024#define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 1025#define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 1026#define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 1027#define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 1028#define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 1029#define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 1030#define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF 1031 1032/* FCoE Opcodes */ 1033#define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 1034#define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 1035#define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 1036#define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 1037#define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 1038#define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 1039#define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 1040#define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 1041#define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 1042#define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 1043#define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 1044#define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D 1045#define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 1046#define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 1047#define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 1048#define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE 0x42 1049 1050/* Low level Opcodes */ 1051#define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37 1052 1053/* Mailbox command structures */ 1054struct eq_context { 1055 uint32_t word0; 1056#define lpfc_eq_context_size_SHIFT 31 1057#define lpfc_eq_context_size_MASK 0x00000001 1058#define lpfc_eq_context_size_WORD word0 1059#define LPFC_EQE_SIZE_4 0x0 1060#define LPFC_EQE_SIZE_16 0x1 1061#define lpfc_eq_context_valid_SHIFT 29 1062#define lpfc_eq_context_valid_MASK 0x00000001 1063#define lpfc_eq_context_valid_WORD word0 1064#define lpfc_eq_context_autovalid_SHIFT 28 1065#define lpfc_eq_context_autovalid_MASK 0x00000001 1066#define lpfc_eq_context_autovalid_WORD word0 1067 uint32_t word1; 1068#define lpfc_eq_context_count_SHIFT 26 1069#define lpfc_eq_context_count_MASK 0x00000003 1070#define lpfc_eq_context_count_WORD word1 1071#define LPFC_EQ_CNT_256 0x0 1072#define LPFC_EQ_CNT_512 0x1 1073#define LPFC_EQ_CNT_1024 0x2 1074#define LPFC_EQ_CNT_2048 0x3 1075#define LPFC_EQ_CNT_4096 0x4 1076 uint32_t word2; 1077#define lpfc_eq_context_delay_multi_SHIFT 13 1078#define lpfc_eq_context_delay_multi_MASK 0x000003FF 1079#define lpfc_eq_context_delay_multi_WORD word2 1080 uint32_t reserved3; 1081}; 1082 1083struct eq_delay_info { 1084 uint32_t eq_id; 1085 uint32_t phase; 1086 uint32_t delay_multi; 1087}; 1088#define LPFC_MAX_EQ_DELAY_EQID_CNT 8 1089 1090struct sgl_page_pairs { 1091 uint32_t sgl_pg0_addr_lo; 1092 uint32_t sgl_pg0_addr_hi; 1093 uint32_t sgl_pg1_addr_lo; 1094 uint32_t sgl_pg1_addr_hi; 1095}; 1096 1097struct lpfc_mbx_post_sgl_pages { 1098 struct mbox_header header; 1099 uint32_t word0; 1100#define lpfc_post_sgl_pages_xri_SHIFT 0 1101#define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1102#define lpfc_post_sgl_pages_xri_WORD word0 1103#define lpfc_post_sgl_pages_xricnt_SHIFT 16 1104#define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1105#define lpfc_post_sgl_pages_xricnt_WORD word0 1106 struct sgl_page_pairs sgl_pg_pairs[1]; 1107}; 1108 1109/* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1110struct lpfc_mbx_post_uembed_sgl_page1 { 1111 union lpfc_sli4_cfg_shdr cfg_shdr; 1112 uint32_t word0; 1113 struct sgl_page_pairs sgl_pg_pairs; 1114}; 1115 1116struct lpfc_mbx_sge { 1117 uint32_t pa_lo; 1118 uint32_t pa_hi; 1119 uint32_t length; 1120}; 1121 1122struct lpfc_mbx_nembed_cmd { 1123 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1124#define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1125 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1126}; 1127 1128struct lpfc_mbx_nembed_sge_virt { 1129 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1130}; 1131 1132struct lpfc_mbx_eq_create { 1133 struct mbox_header header; 1134 union { 1135 struct { 1136 uint32_t word0; 1137#define lpfc_mbx_eq_create_num_pages_SHIFT 0 1138#define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1139#define lpfc_mbx_eq_create_num_pages_WORD word0 1140 struct eq_context context; 1141 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1142 } request; 1143 struct { 1144 uint32_t word0; 1145#define lpfc_mbx_eq_create_q_id_SHIFT 0 1146#define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1147#define lpfc_mbx_eq_create_q_id_WORD word0 1148 } response; 1149 } u; 1150}; 1151 1152struct lpfc_mbx_modify_eq_delay { 1153 struct mbox_header header; 1154 union { 1155 struct { 1156 uint32_t num_eq; 1157 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT]; 1158 } request; 1159 struct { 1160 uint32_t word0; 1161 } response; 1162 } u; 1163}; 1164 1165struct lpfc_mbx_eq_destroy { 1166 struct mbox_header header; 1167 union { 1168 struct { 1169 uint32_t word0; 1170#define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1171#define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1172#define lpfc_mbx_eq_destroy_q_id_WORD word0 1173 } request; 1174 struct { 1175 uint32_t word0; 1176 } response; 1177 } u; 1178}; 1179 1180struct lpfc_mbx_nop { 1181 struct mbox_header header; 1182 uint32_t context[2]; 1183}; 1184 1185 1186 1187struct lpfc_mbx_set_ras_fwlog { 1188 struct mbox_header header; 1189 union { 1190 struct { 1191 uint32_t word4; 1192#define lpfc_fwlog_enable_SHIFT 0 1193#define lpfc_fwlog_enable_MASK 0x00000001 1194#define lpfc_fwlog_enable_WORD word4 1195#define lpfc_fwlog_loglvl_SHIFT 8 1196#define lpfc_fwlog_loglvl_MASK 0x0000000F 1197#define lpfc_fwlog_loglvl_WORD word4 1198#define lpfc_fwlog_ra_SHIFT 15 1199#define lpfc_fwlog_ra_WORD 0x00000008 1200#define lpfc_fwlog_buffcnt_SHIFT 16 1201#define lpfc_fwlog_buffcnt_MASK 0x000000FF 1202#define lpfc_fwlog_buffcnt_WORD word4 1203#define lpfc_fwlog_buffsz_SHIFT 24 1204#define lpfc_fwlog_buffsz_MASK 0x000000FF 1205#define lpfc_fwlog_buffsz_WORD word4 1206 uint32_t word5; 1207#define lpfc_fwlog_acqe_SHIFT 0 1208#define lpfc_fwlog_acqe_MASK 0x0000FFFF 1209#define lpfc_fwlog_acqe_WORD word5 1210#define lpfc_fwlog_cqid_SHIFT 16 1211#define lpfc_fwlog_cqid_MASK 0x0000FFFF 1212#define lpfc_fwlog_cqid_WORD word5 1213#define LPFC_MAX_FWLOG_PAGE 16 1214 struct dma_address lwpd; 1215 struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE]; 1216 } request; 1217 struct { 1218 uint32_t word0; 1219 } response; 1220 } u; 1221}; 1222 1223 1224struct cq_context { 1225 uint32_t word0; 1226#define lpfc_cq_context_event_SHIFT 31 1227#define lpfc_cq_context_event_MASK 0x00000001 1228#define lpfc_cq_context_event_WORD word0 1229#define lpfc_cq_context_valid_SHIFT 29 1230#define lpfc_cq_context_valid_MASK 0x00000001 1231#define lpfc_cq_context_valid_WORD word0 1232#define lpfc_cq_context_count_SHIFT 27 1233#define lpfc_cq_context_count_MASK 0x00000003 1234#define lpfc_cq_context_count_WORD word0 1235#define LPFC_CQ_CNT_256 0x0 1236#define LPFC_CQ_CNT_512 0x1 1237#define LPFC_CQ_CNT_1024 0x2 1238#define LPFC_CQ_CNT_WORD7 0x3 1239#define lpfc_cq_context_autovalid_SHIFT 15 1240#define lpfc_cq_context_autovalid_MASK 0x00000001 1241#define lpfc_cq_context_autovalid_WORD word0 1242 uint32_t word1; 1243#define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1244#define lpfc_cq_eq_id_MASK 0x000000FF 1245#define lpfc_cq_eq_id_WORD word1 1246#define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1247#define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1248#define lpfc_cq_eq_id_2_WORD word1 1249 uint32_t lpfc_cq_context_count; /* Version 2 Only */ 1250 uint32_t reserved1; 1251}; 1252 1253struct lpfc_mbx_cq_create { 1254 struct mbox_header header; 1255 union { 1256 struct { 1257 uint32_t word0; 1258#define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1259#define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1260#define lpfc_mbx_cq_create_page_size_WORD word0 1261#define lpfc_mbx_cq_create_num_pages_SHIFT 0 1262#define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1263#define lpfc_mbx_cq_create_num_pages_WORD word0 1264 struct cq_context context; 1265 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1266 } request; 1267 struct { 1268 uint32_t word0; 1269#define lpfc_mbx_cq_create_q_id_SHIFT 0 1270#define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1271#define lpfc_mbx_cq_create_q_id_WORD word0 1272 } response; 1273 } u; 1274}; 1275 1276struct lpfc_mbx_cq_create_set { 1277 union lpfc_sli4_cfg_shdr cfg_shdr; 1278 union { 1279 struct { 1280 uint32_t word0; 1281#define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */ 1282#define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF 1283#define lpfc_mbx_cq_create_set_page_size_WORD word0 1284#define lpfc_mbx_cq_create_set_num_pages_SHIFT 0 1285#define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF 1286#define lpfc_mbx_cq_create_set_num_pages_WORD word0 1287 uint32_t word1; 1288#define lpfc_mbx_cq_create_set_evt_SHIFT 31 1289#define lpfc_mbx_cq_create_set_evt_MASK 0x00000001 1290#define lpfc_mbx_cq_create_set_evt_WORD word1 1291#define lpfc_mbx_cq_create_set_valid_SHIFT 29 1292#define lpfc_mbx_cq_create_set_valid_MASK 0x00000001 1293#define lpfc_mbx_cq_create_set_valid_WORD word1 1294#define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT 27 1295#define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003 1296#define lpfc_mbx_cq_create_set_cqe_cnt_WORD word1 1297#define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25 1298#define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003 1299#define lpfc_mbx_cq_create_set_cqe_size_WORD word1 1300#define lpfc_mbx_cq_create_set_autovalid_SHIFT 15 1301#define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001 1302#define lpfc_mbx_cq_create_set_autovalid_WORD word1 1303#define lpfc_mbx_cq_create_set_nodelay_SHIFT 14 1304#define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001 1305#define lpfc_mbx_cq_create_set_nodelay_WORD word1 1306#define lpfc_mbx_cq_create_set_clswm_SHIFT 12 1307#define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003 1308#define lpfc_mbx_cq_create_set_clswm_WORD word1 1309 uint32_t word2; 1310#define lpfc_mbx_cq_create_set_arm_SHIFT 31 1311#define lpfc_mbx_cq_create_set_arm_MASK 0x00000001 1312#define lpfc_mbx_cq_create_set_arm_WORD word2 1313#define lpfc_mbx_cq_create_set_cq_cnt_SHIFT 16 1314#define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF 1315#define lpfc_mbx_cq_create_set_cq_cnt_WORD word2 1316#define lpfc_mbx_cq_create_set_num_cq_SHIFT 0 1317#define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF 1318#define lpfc_mbx_cq_create_set_num_cq_WORD word2 1319 uint32_t word3; 1320#define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16 1321#define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF 1322#define lpfc_mbx_cq_create_set_eq_id1_WORD word3 1323#define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0 1324#define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF 1325#define lpfc_mbx_cq_create_set_eq_id0_WORD word3 1326 uint32_t word4; 1327#define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16 1328#define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF 1329#define lpfc_mbx_cq_create_set_eq_id3_WORD word4 1330#define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0 1331#define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF 1332#define lpfc_mbx_cq_create_set_eq_id2_WORD word4 1333 uint32_t word5; 1334#define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16 1335#define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF 1336#define lpfc_mbx_cq_create_set_eq_id5_WORD word5 1337#define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0 1338#define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF 1339#define lpfc_mbx_cq_create_set_eq_id4_WORD word5 1340 uint32_t word6; 1341#define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16 1342#define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF 1343#define lpfc_mbx_cq_create_set_eq_id7_WORD word6 1344#define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0 1345#define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF 1346#define lpfc_mbx_cq_create_set_eq_id6_WORD word6 1347 uint32_t word7; 1348#define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16 1349#define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF 1350#define lpfc_mbx_cq_create_set_eq_id9_WORD word7 1351#define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0 1352#define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF 1353#define lpfc_mbx_cq_create_set_eq_id8_WORD word7 1354 uint32_t word8; 1355#define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16 1356#define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF 1357#define lpfc_mbx_cq_create_set_eq_id11_WORD word8 1358#define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0 1359#define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF 1360#define lpfc_mbx_cq_create_set_eq_id10_WORD word8 1361 uint32_t word9; 1362#define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16 1363#define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF 1364#define lpfc_mbx_cq_create_set_eq_id13_WORD word9 1365#define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0 1366#define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF 1367#define lpfc_mbx_cq_create_set_eq_id12_WORD word9 1368 uint32_t word10; 1369#define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16 1370#define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF 1371#define lpfc_mbx_cq_create_set_eq_id15_WORD word10 1372#define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0 1373#define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF 1374#define lpfc_mbx_cq_create_set_eq_id14_WORD word10 1375 struct dma_address page[1]; 1376 } request; 1377 struct { 1378 uint32_t word0; 1379#define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16 1380#define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF 1381#define lpfc_mbx_cq_create_set_num_alloc_WORD word0 1382#define lpfc_mbx_cq_create_set_base_id_SHIFT 0 1383#define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF 1384#define lpfc_mbx_cq_create_set_base_id_WORD word0 1385 } response; 1386 } u; 1387}; 1388 1389struct lpfc_mbx_cq_destroy { 1390 struct mbox_header header; 1391 union { 1392 struct { 1393 uint32_t word0; 1394#define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1395#define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1396#define lpfc_mbx_cq_destroy_q_id_WORD word0 1397 } request; 1398 struct { 1399 uint32_t word0; 1400 } response; 1401 } u; 1402}; 1403 1404struct wq_context { 1405 uint32_t reserved0; 1406 uint32_t reserved1; 1407 uint32_t reserved2; 1408 uint32_t reserved3; 1409}; 1410 1411struct lpfc_mbx_wq_create { 1412 struct mbox_header header; 1413 union { 1414 struct { /* Version 0 Request */ 1415 uint32_t word0; 1416#define lpfc_mbx_wq_create_num_pages_SHIFT 0 1417#define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1418#define lpfc_mbx_wq_create_num_pages_WORD word0 1419#define lpfc_mbx_wq_create_dua_SHIFT 8 1420#define lpfc_mbx_wq_create_dua_MASK 0x00000001 1421#define lpfc_mbx_wq_create_dua_WORD word0 1422#define lpfc_mbx_wq_create_cq_id_SHIFT 16 1423#define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1424#define lpfc_mbx_wq_create_cq_id_WORD word0 1425 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1426 uint32_t word9; 1427#define lpfc_mbx_wq_create_bua_SHIFT 0 1428#define lpfc_mbx_wq_create_bua_MASK 0x00000001 1429#define lpfc_mbx_wq_create_bua_WORD word9 1430#define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1431#define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1432#define lpfc_mbx_wq_create_ulp_num_WORD word9 1433 } request; 1434 struct { /* Version 1 Request */ 1435 uint32_t word0; /* Word 0 is the same as in v0 */ 1436 uint32_t word1; 1437#define lpfc_mbx_wq_create_page_size_SHIFT 0 1438#define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1439#define lpfc_mbx_wq_create_page_size_WORD word1 1440#define LPFC_WQ_PAGE_SIZE_4096 0x1 1441#define lpfc_mbx_wq_create_dpp_req_SHIFT 15 1442#define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001 1443#define lpfc_mbx_wq_create_dpp_req_WORD word1 1444#define lpfc_mbx_wq_create_doe_SHIFT 14 1445#define lpfc_mbx_wq_create_doe_MASK 0x00000001 1446#define lpfc_mbx_wq_create_doe_WORD word1 1447#define lpfc_mbx_wq_create_toe_SHIFT 13 1448#define lpfc_mbx_wq_create_toe_MASK 0x00000001 1449#define lpfc_mbx_wq_create_toe_WORD word1 1450#define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1451#define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1452#define lpfc_mbx_wq_create_wqe_size_WORD word1 1453#define LPFC_WQ_WQE_SIZE_64 0x5 1454#define LPFC_WQ_WQE_SIZE_128 0x6 1455#define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1456#define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1457#define lpfc_mbx_wq_create_wqe_count_WORD word1 1458 uint32_t word2; 1459 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1460 } request_1; 1461 struct { 1462 uint32_t word0; 1463#define lpfc_mbx_wq_create_q_id_SHIFT 0 1464#define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1465#define lpfc_mbx_wq_create_q_id_WORD word0 1466 uint32_t doorbell_offset; 1467 uint32_t word2; 1468#define lpfc_mbx_wq_create_bar_set_SHIFT 0 1469#define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1470#define lpfc_mbx_wq_create_bar_set_WORD word2 1471#define WQ_PCI_BAR_0_AND_1 0x00 1472#define WQ_PCI_BAR_2_AND_3 0x01 1473#define WQ_PCI_BAR_4_AND_5 0x02 1474#define lpfc_mbx_wq_create_db_format_SHIFT 16 1475#define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1476#define lpfc_mbx_wq_create_db_format_WORD word2 1477 } response; 1478 struct { 1479 uint32_t word0; 1480#define lpfc_mbx_wq_create_dpp_rsp_SHIFT 31 1481#define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001 1482#define lpfc_mbx_wq_create_dpp_rsp_WORD word0 1483#define lpfc_mbx_wq_create_v1_q_id_SHIFT 0 1484#define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF 1485#define lpfc_mbx_wq_create_v1_q_id_WORD word0 1486 uint32_t word1; 1487#define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0 1488#define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F 1489#define lpfc_mbx_wq_create_v1_bar_set_WORD word1 1490 uint32_t doorbell_offset; 1491 uint32_t word3; 1492#define lpfc_mbx_wq_create_dpp_id_SHIFT 16 1493#define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F 1494#define lpfc_mbx_wq_create_dpp_id_WORD word3 1495#define lpfc_mbx_wq_create_dpp_bar_SHIFT 0 1496#define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F 1497#define lpfc_mbx_wq_create_dpp_bar_WORD word3 1498 uint32_t dpp_offset; 1499 } response_1; 1500 } u; 1501}; 1502 1503struct lpfc_mbx_wq_destroy { 1504 struct mbox_header header; 1505 union { 1506 struct { 1507 uint32_t word0; 1508#define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1509#define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1510#define lpfc_mbx_wq_destroy_q_id_WORD word0 1511 } request; 1512 struct { 1513 uint32_t word0; 1514 } response; 1515 } u; 1516}; 1517 1518#define LPFC_HDR_BUF_SIZE 128 1519#define LPFC_DATA_BUF_SIZE 2048 1520#define LPFC_NVMET_DATA_BUF_SIZE 128 1521struct rq_context { 1522 uint32_t word0; 1523#define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1524#define lpfc_rq_context_rqe_count_MASK 0x0000000F 1525#define lpfc_rq_context_rqe_count_WORD word0 1526#define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1527#define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1528#define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1529#define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1530#define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */ 1531#define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1532#define lpfc_rq_context_rqe_count_1_WORD word0 1533#define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */ 1534#define lpfc_rq_context_rqe_size_MASK 0x0000000F 1535#define lpfc_rq_context_rqe_size_WORD word0 1536#define LPFC_RQE_SIZE_8 2 1537#define LPFC_RQE_SIZE_16 3 1538#define LPFC_RQE_SIZE_32 4 1539#define LPFC_RQE_SIZE_64 5 1540#define LPFC_RQE_SIZE_128 6 1541#define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1542#define lpfc_rq_context_page_size_MASK 0x000000FF 1543#define lpfc_rq_context_page_size_WORD word0 1544#define LPFC_RQ_PAGE_SIZE_4096 0x1 1545 uint32_t word1; 1546#define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */ 1547#define lpfc_rq_context_data_size_MASK 0x0000FFFF 1548#define lpfc_rq_context_data_size_WORD word1 1549#define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */ 1550#define lpfc_rq_context_hdr_size_MASK 0x0000FFFF 1551#define lpfc_rq_context_hdr_size_WORD word1 1552 uint32_t word2; 1553#define lpfc_rq_context_cq_id_SHIFT 16 1554#define lpfc_rq_context_cq_id_MASK 0x000003FF 1555#define lpfc_rq_context_cq_id_WORD word2 1556#define lpfc_rq_context_buf_size_SHIFT 0 1557#define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1558#define lpfc_rq_context_buf_size_WORD word2 1559#define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */ 1560#define lpfc_rq_context_base_cq_MASK 0x0000FFFF 1561#define lpfc_rq_context_base_cq_WORD word2 1562 uint32_t buffer_size; /* Version 1 Only */ 1563}; 1564 1565struct lpfc_mbx_rq_create { 1566 struct mbox_header header; 1567 union { 1568 struct { 1569 uint32_t word0; 1570#define lpfc_mbx_rq_create_num_pages_SHIFT 0 1571#define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1572#define lpfc_mbx_rq_create_num_pages_WORD word0 1573#define lpfc_mbx_rq_create_dua_SHIFT 16 1574#define lpfc_mbx_rq_create_dua_MASK 0x00000001 1575#define lpfc_mbx_rq_create_dua_WORD word0 1576#define lpfc_mbx_rq_create_bqu_SHIFT 17 1577#define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1578#define lpfc_mbx_rq_create_bqu_WORD word0 1579#define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1580#define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1581#define lpfc_mbx_rq_create_ulp_num_WORD word0 1582 struct rq_context context; 1583 struct dma_address page[LPFC_MAX_RQ_PAGE]; 1584 } request; 1585 struct { 1586 uint32_t word0; 1587#define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1588#define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1589#define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1590#define lpfc_mbx_rq_create_q_id_SHIFT 0 1591#define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1592#define lpfc_mbx_rq_create_q_id_WORD word0 1593 uint32_t doorbell_offset; 1594 uint32_t word2; 1595#define lpfc_mbx_rq_create_bar_set_SHIFT 0 1596#define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1597#define lpfc_mbx_rq_create_bar_set_WORD word2 1598#define lpfc_mbx_rq_create_db_format_SHIFT 16 1599#define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1600#define lpfc_mbx_rq_create_db_format_WORD word2 1601 } response; 1602 } u; 1603}; 1604 1605struct lpfc_mbx_rq_create_v2 { 1606 union lpfc_sli4_cfg_shdr cfg_shdr; 1607 union { 1608 struct { 1609 uint32_t word0; 1610#define lpfc_mbx_rq_create_num_pages_SHIFT 0 1611#define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1612#define lpfc_mbx_rq_create_num_pages_WORD word0 1613#define lpfc_mbx_rq_create_rq_cnt_SHIFT 16 1614#define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF 1615#define lpfc_mbx_rq_create_rq_cnt_WORD word0 1616#define lpfc_mbx_rq_create_dua_SHIFT 16 1617#define lpfc_mbx_rq_create_dua_MASK 0x00000001 1618#define lpfc_mbx_rq_create_dua_WORD word0 1619#define lpfc_mbx_rq_create_bqu_SHIFT 17 1620#define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1621#define lpfc_mbx_rq_create_bqu_WORD word0 1622#define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1623#define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1624#define lpfc_mbx_rq_create_ulp_num_WORD word0 1625#define lpfc_mbx_rq_create_dim_SHIFT 29 1626#define lpfc_mbx_rq_create_dim_MASK 0x00000001 1627#define lpfc_mbx_rq_create_dim_WORD word0 1628#define lpfc_mbx_rq_create_dfd_SHIFT 30 1629#define lpfc_mbx_rq_create_dfd_MASK 0x00000001 1630#define lpfc_mbx_rq_create_dfd_WORD word0 1631#define lpfc_mbx_rq_create_dnb_SHIFT 31 1632#define lpfc_mbx_rq_create_dnb_MASK 0x00000001 1633#define lpfc_mbx_rq_create_dnb_WORD word0 1634 struct rq_context context; 1635 struct dma_address page[1]; 1636 } request; 1637 struct { 1638 uint32_t word0; 1639#define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1640#define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1641#define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1642#define lpfc_mbx_rq_create_q_id_SHIFT 0 1643#define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1644#define lpfc_mbx_rq_create_q_id_WORD word0 1645 uint32_t doorbell_offset; 1646 uint32_t word2; 1647#define lpfc_mbx_rq_create_bar_set_SHIFT 0 1648#define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1649#define lpfc_mbx_rq_create_bar_set_WORD word2 1650#define lpfc_mbx_rq_create_db_format_SHIFT 16 1651#define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1652#define lpfc_mbx_rq_create_db_format_WORD word2 1653 } response; 1654 } u; 1655}; 1656 1657struct lpfc_mbx_rq_destroy { 1658 struct mbox_header header; 1659 union { 1660 struct { 1661 uint32_t word0; 1662#define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1663#define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1664#define lpfc_mbx_rq_destroy_q_id_WORD word0 1665 } request; 1666 struct { 1667 uint32_t word0; 1668 } response; 1669 } u; 1670}; 1671 1672struct mq_context { 1673 uint32_t word0; 1674#define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1675#define lpfc_mq_context_cq_id_MASK 0x000003FF 1676#define lpfc_mq_context_cq_id_WORD word0 1677#define lpfc_mq_context_ring_size_SHIFT 16 1678#define lpfc_mq_context_ring_size_MASK 0x0000000F 1679#define lpfc_mq_context_ring_size_WORD word0 1680#define LPFC_MQ_RING_SIZE_16 0x5 1681#define LPFC_MQ_RING_SIZE_32 0x6 1682#define LPFC_MQ_RING_SIZE_64 0x7 1683#define LPFC_MQ_RING_SIZE_128 0x8 1684 uint32_t word1; 1685#define lpfc_mq_context_valid_SHIFT 31 1686#define lpfc_mq_context_valid_MASK 0x00000001 1687#define lpfc_mq_context_valid_WORD word1 1688 uint32_t reserved2; 1689 uint32_t reserved3; 1690}; 1691 1692struct lpfc_mbx_mq_create { 1693 struct mbox_header header; 1694 union { 1695 struct { 1696 uint32_t word0; 1697#define lpfc_mbx_mq_create_num_pages_SHIFT 0 1698#define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1699#define lpfc_mbx_mq_create_num_pages_WORD word0 1700 struct mq_context context; 1701 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1702 } request; 1703 struct { 1704 uint32_t word0; 1705#define lpfc_mbx_mq_create_q_id_SHIFT 0 1706#define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1707#define lpfc_mbx_mq_create_q_id_WORD word0 1708 } response; 1709 } u; 1710}; 1711 1712struct lpfc_mbx_mq_create_ext { 1713 struct mbox_header header; 1714 union { 1715 struct { 1716 uint32_t word0; 1717#define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1718#define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1719#define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1720#define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1721#define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1722#define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1723 uint32_t async_evt_bmap; 1724#define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1725#define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1726#define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1727#define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1728#define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1729#define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1730#define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1731#define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1732#define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1733#define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1734#define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1735#define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1736#define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1737#define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1738#define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1739#define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1740#define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1741#define LPFC_EVT_CODE_FC_NO_LINK 0x0 1742#define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1743#define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1744#define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1745#define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1746#define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1747#define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1748#define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1749#define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1750#define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1751 struct mq_context context; 1752 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1753 } request; 1754 struct { 1755 uint32_t word0; 1756#define lpfc_mbx_mq_create_q_id_SHIFT 0 1757#define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1758#define lpfc_mbx_mq_create_q_id_WORD word0 1759 } response; 1760 } u; 1761#define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1762#define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1763#define LPFC_ASYNC_EVENT_GROUP5 0x20 1764}; 1765 1766struct lpfc_mbx_mq_destroy { 1767 struct mbox_header header; 1768 union { 1769 struct { 1770 uint32_t word0; 1771#define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1772#define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1773#define lpfc_mbx_mq_destroy_q_id_WORD word0 1774 } request; 1775 struct { 1776 uint32_t word0; 1777 } response; 1778 } u; 1779}; 1780 1781/* Start Gen 2 SLI4 Mailbox definitions: */ 1782 1783/* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1784#define LPFC_RSC_TYPE_FCOE_VFI 0x20 1785#define LPFC_RSC_TYPE_FCOE_VPI 0x21 1786#define LPFC_RSC_TYPE_FCOE_RPI 0x22 1787#define LPFC_RSC_TYPE_FCOE_XRI 0x23 1788 1789struct lpfc_mbx_get_rsrc_extent_info { 1790 struct mbox_header header; 1791 union { 1792 struct { 1793 uint32_t word4; 1794#define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1795#define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1796#define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1797 } req; 1798 struct { 1799 uint32_t word4; 1800#define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1801#define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1802#define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1803#define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1804#define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1805#define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1806 } rsp; 1807 } u; 1808}; 1809 1810struct lpfc_mbx_query_fw_config { 1811 struct mbox_header header; 1812 struct { 1813 uint32_t config_number; 1814#define LPFC_FC_FCOE 0x00000007 1815 uint32_t asic_revision; 1816 uint32_t physical_port; 1817 uint32_t function_mode; 1818#define LPFC_FCOE_INI_MODE 0x00000040 1819#define LPFC_FCOE_TGT_MODE 0x00000080 1820#define LPFC_DUA_MODE 0x00000800 1821 uint32_t ulp0_mode; 1822#define LPFC_ULP_FCOE_INIT_MODE 0x00000040 1823#define LPFC_ULP_FCOE_TGT_MODE 0x00000080 1824 uint32_t ulp0_nap_words[12]; 1825 uint32_t ulp1_mode; 1826 uint32_t ulp1_nap_words[12]; 1827 uint32_t function_capabilities; 1828 uint32_t cqid_base; 1829 uint32_t cqid_tot; 1830 uint32_t eqid_base; 1831 uint32_t eqid_tot; 1832 uint32_t ulp0_nap2_words[2]; 1833 uint32_t ulp1_nap2_words[2]; 1834 } rsp; 1835}; 1836 1837struct lpfc_mbx_set_beacon_config { 1838 struct mbox_header header; 1839 uint32_t word4; 1840#define lpfc_mbx_set_beacon_port_num_SHIFT 0 1841#define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F 1842#define lpfc_mbx_set_beacon_port_num_WORD word4 1843#define lpfc_mbx_set_beacon_port_type_SHIFT 6 1844#define lpfc_mbx_set_beacon_port_type_MASK 0x00000003 1845#define lpfc_mbx_set_beacon_port_type_WORD word4 1846#define lpfc_mbx_set_beacon_state_SHIFT 8 1847#define lpfc_mbx_set_beacon_state_MASK 0x000000FF 1848#define lpfc_mbx_set_beacon_state_WORD word4 1849#define lpfc_mbx_set_beacon_duration_SHIFT 16 1850#define lpfc_mbx_set_beacon_duration_MASK 0x000000FF 1851#define lpfc_mbx_set_beacon_duration_WORD word4 1852 1853/* COMMON_SET_BEACON_CONFIG_V1 */ 1854#define lpfc_mbx_set_beacon_duration_v1_SHIFT 16 1855#define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF 1856#define lpfc_mbx_set_beacon_duration_v1_WORD word4 1857 uint32_t word5; /* RESERVED */ 1858}; 1859 1860struct lpfc_id_range { 1861 uint32_t word5; 1862#define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1863#define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1864#define lpfc_mbx_rsrc_id_word4_0_WORD word5 1865#define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1866#define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1867#define lpfc_mbx_rsrc_id_word4_1_WORD word5 1868}; 1869 1870struct lpfc_mbx_set_link_diag_state { 1871 struct mbox_header header; 1872 union { 1873 struct { 1874 uint32_t word0; 1875#define lpfc_mbx_set_diag_state_diag_SHIFT 0 1876#define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1877#define lpfc_mbx_set_diag_state_diag_WORD word0 1878#define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1879#define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1880#define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1881#define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1882#define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1883#define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1884#define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1885#define lpfc_mbx_set_diag_state_link_num_WORD word0 1886#define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1887#define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1888#define lpfc_mbx_set_diag_state_link_type_WORD word0 1889 } req; 1890 struct { 1891 uint32_t word0; 1892 } rsp; 1893 } u; 1894}; 1895 1896struct lpfc_mbx_set_link_diag_loopback { 1897 struct mbox_header header; 1898 union { 1899 struct { 1900 uint32_t word0; 1901#define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1902#define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1903#define lpfc_mbx_set_diag_lpbk_type_WORD word0 1904#define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1905#define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1906#define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1907#define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED 0x3 1908#define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1909#define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1910#define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1911#define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1912#define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1913#define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1914 } req; 1915 struct { 1916 uint32_t word0; 1917 } rsp; 1918 } u; 1919}; 1920 1921struct lpfc_mbx_run_link_diag_test { 1922 struct mbox_header header; 1923 union { 1924 struct { 1925 uint32_t word0; 1926#define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1927#define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1928#define lpfc_mbx_run_diag_test_link_num_WORD word0 1929#define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1930#define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1931#define lpfc_mbx_run_diag_test_link_type_WORD word0 1932 uint32_t word1; 1933#define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1934#define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1935#define lpfc_mbx_run_diag_test_test_id_WORD word1 1936#define lpfc_mbx_run_diag_test_loops_SHIFT 16 1937#define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1938#define lpfc_mbx_run_diag_test_loops_WORD word1 1939 uint32_t word2; 1940#define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1941#define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1942#define lpfc_mbx_run_diag_test_test_ver_WORD word2 1943#define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1944#define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1945#define lpfc_mbx_run_diag_test_err_act_WORD word2 1946 } req; 1947 struct { 1948 uint32_t word0; 1949 } rsp; 1950 } u; 1951}; 1952 1953/* 1954 * struct lpfc_mbx_alloc_rsrc_extents: 1955 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1956 * 6 words of header + 4 words of shared subcommand header + 1957 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1958 * 1959 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1960 * for extents payload. 1961 * 1962 * 212/2 (bytes per extent) = 106 extents. 1963 * 106/2 (extents per word) = 53 words. 1964 * lpfc_id_range id is statically size to 53. 1965 * 1966 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1967 * extent ranges. For ALLOC, the type and cnt are required. 1968 * For GET_ALLOCATED, only the type is required. 1969 */ 1970struct lpfc_mbx_alloc_rsrc_extents { 1971 struct mbox_header header; 1972 union { 1973 struct { 1974 uint32_t word4; 1975#define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1976#define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1977#define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1978#define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1979#define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1980#define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1981 } req; 1982 struct { 1983 uint32_t word4; 1984#define lpfc_mbx_rsrc_cnt_SHIFT 0 1985#define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1986#define lpfc_mbx_rsrc_cnt_WORD word4 1987 struct lpfc_id_range id[53]; 1988 } rsp; 1989 } u; 1990}; 1991 1992/* 1993 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 1994 * structure shares the same SHIFT/MASK/WORD defines provided in the 1995 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 1996 * the structures defined above. This non-embedded structure provides for the 1997 * maximum number of extents supported by the port. 1998 */ 1999struct lpfc_mbx_nembed_rsrc_extent { 2000 union lpfc_sli4_cfg_shdr cfg_shdr;
2001 uint32_t word4; 2002 struct lpfc_id_range id; 2003}; 2004 2005struct lpfc_mbx_dealloc_rsrc_extents { 2006 struct mbox_header header; 2007 struct { 2008 uint32_t word4; 2009#define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 2010#define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 2011#define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 2012 } req; 2013 2014}; 2015 2016/* Start SLI4 FCoE specific mbox structures. */ 2017 2018struct lpfc_mbx_post_hdr_tmpl { 2019 struct mbox_header header; 2020 uint32_t word10; 2021#define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 2022#define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 2023#define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 2024#define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 2025#define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 2026#define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 2027 uint32_t rpi_paddr_lo; 2028 uint32_t rpi_paddr_hi; 2029}; 2030 2031struct sli4_sge { /* SLI-4 */ 2032 uint32_t addr_hi; 2033 uint32_t addr_lo; 2034 2035 uint32_t word2; 2036#define lpfc_sli4_sge_offset_SHIFT 0 2037#define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 2038#define lpfc_sli4_sge_offset_WORD word2 2039#define lpfc_sli4_sge_type_SHIFT 27 2040#define lpfc_sli4_sge_type_MASK 0x0000000F 2041#define lpfc_sli4_sge_type_WORD word2 2042#define LPFC_SGE_TYPE_DATA 0x0 2043#define LPFC_SGE_TYPE_DIF 0x4 2044#define LPFC_SGE_TYPE_LSP 0x5 2045#define LPFC_SGE_TYPE_PEDIF 0x6 2046#define LPFC_SGE_TYPE_PESEED 0x7 2047#define LPFC_SGE_TYPE_DISEED 0x8 2048#define LPFC_SGE_TYPE_ENC 0x9 2049#define LPFC_SGE_TYPE_ATM 0xA 2050#define LPFC_SGE_TYPE_SKIP 0xC 2051#define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2052#define lpfc_sli4_sge_last_MASK 0x00000001 2053#define lpfc_sli4_sge_last_WORD word2 2054 uint32_t sge_len; 2055}; 2056 2057struct sli4_hybrid_sgl { 2058 struct list_head list_node; 2059 struct sli4_sge *dma_sgl; 2060 dma_addr_t dma_phys_sgl; 2061}; 2062 2063struct fcp_cmd_rsp_buf { 2064 struct list_head list_node; 2065 2066 /* for storing cmd/rsp dma alloc'ed virt_addr */ 2067 struct fcp_cmnd *fcp_cmnd; 2068 struct fcp_rsp *fcp_rsp; 2069 2070 /* for storing this cmd/rsp's dma mapped phys addr from per CPU pool */ 2071 dma_addr_t fcp_cmd_rsp_dma_handle; 2072}; 2073 2074struct sli4_sge_diseed { /* SLI-4 */ 2075 uint32_t ref_tag; 2076 uint32_t ref_tag_tran; 2077 2078 uint32_t word2; 2079#define lpfc_sli4_sge_dif_apptran_SHIFT 0 2080#define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 2081#define lpfc_sli4_sge_dif_apptran_WORD word2 2082#define lpfc_sli4_sge_dif_af_SHIFT 24 2083#define lpfc_sli4_sge_dif_af_MASK 0x00000001 2084#define lpfc_sli4_sge_dif_af_WORD word2 2085#define lpfc_sli4_sge_dif_na_SHIFT 25 2086#define lpfc_sli4_sge_dif_na_MASK 0x00000001 2087#define lpfc_sli4_sge_dif_na_WORD word2 2088#define lpfc_sli4_sge_dif_hi_SHIFT 26 2089#define lpfc_sli4_sge_dif_hi_MASK 0x00000001 2090#define lpfc_sli4_sge_dif_hi_WORD word2 2091#define lpfc_sli4_sge_dif_type_SHIFT 27 2092#define lpfc_sli4_sge_dif_type_MASK 0x0000000F 2093#define lpfc_sli4_sge_dif_type_WORD word2 2094#define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2095#define lpfc_sli4_sge_dif_last_MASK 0x00000001 2096#define lpfc_sli4_sge_dif_last_WORD word2 2097 uint32_t word3; 2098#define lpfc_sli4_sge_dif_apptag_SHIFT 0 2099#define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 2100#define lpfc_sli4_sge_dif_apptag_WORD word3 2101#define lpfc_sli4_sge_dif_bs_SHIFT 16 2102#define lpfc_sli4_sge_dif_bs_MASK 0x00000007 2103#define lpfc_sli4_sge_dif_bs_WORD word3 2104#define lpfc_sli4_sge_dif_ai_SHIFT 19 2105#define lpfc_sli4_sge_dif_ai_MASK 0x00000001 2106#define lpfc_sli4_sge_dif_ai_WORD word3 2107#define lpfc_sli4_sge_dif_me_SHIFT 20 2108#define lpfc_sli4_sge_dif_me_MASK 0x00000001 2109#define lpfc_sli4_sge_dif_me_WORD word3 2110#define lpfc_sli4_sge_dif_re_SHIFT 21 2111#define lpfc_sli4_sge_dif_re_MASK 0x00000001 2112#define lpfc_sli4_sge_dif_re_WORD word3 2113#define lpfc_sli4_sge_dif_ce_SHIFT 22 2114#define lpfc_sli4_sge_dif_ce_MASK 0x00000001 2115#define lpfc_sli4_sge_dif_ce_WORD word3 2116#define lpfc_sli4_sge_dif_nr_SHIFT 23 2117#define lpfc_sli4_sge_dif_nr_MASK 0x00000001 2118#define lpfc_sli4_sge_dif_nr_WORD word3 2119#define lpfc_sli4_sge_dif_oprx_SHIFT 24 2120#define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 2121#define lpfc_sli4_sge_dif_oprx_WORD word3 2122#define lpfc_sli4_sge_dif_optx_SHIFT 28 2123#define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 2124#define lpfc_sli4_sge_dif_optx_WORD word3 2125/* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 2126}; 2127 2128struct fcf_record { 2129 uint32_t max_rcv_size; 2130 uint32_t fka_adv_period; 2131 uint32_t fip_priority; 2132 uint32_t word3; 2133#define lpfc_fcf_record_mac_0_SHIFT 0 2134#define lpfc_fcf_record_mac_0_MASK 0x000000FF 2135#define lpfc_fcf_record_mac_0_WORD word3 2136#define lpfc_fcf_record_mac_1_SHIFT 8 2137#define lpfc_fcf_record_mac_1_MASK 0x000000FF 2138#define lpfc_fcf_record_mac_1_WORD word3 2139#define lpfc_fcf_record_mac_2_SHIFT 16 2140#define lpfc_fcf_record_mac_2_MASK 0x000000FF 2141#define lpfc_fcf_record_mac_2_WORD word3 2142#define lpfc_fcf_record_mac_3_SHIFT 24 2143#define lpfc_fcf_record_mac_3_MASK 0x000000FF 2144#define lpfc_fcf_record_mac_3_WORD word3 2145 uint32_t word4; 2146#define lpfc_fcf_record_mac_4_SHIFT 0 2147#define lpfc_fcf_record_mac_4_MASK 0x000000FF 2148#define lpfc_fcf_record_mac_4_WORD word4 2149#define lpfc_fcf_record_mac_5_SHIFT 8 2150#define lpfc_fcf_record_mac_5_MASK 0x000000FF 2151#define lpfc_fcf_record_mac_5_WORD word4 2152#define lpfc_fcf_record_fcf_avail_SHIFT 16 2153#define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 2154#define lpfc_fcf_record_fcf_avail_WORD word4 2155#define lpfc_fcf_record_mac_addr_prov_SHIFT 24 2156#define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 2157#define lpfc_fcf_record_mac_addr_prov_WORD word4 2158#define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 2159#define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 2160 uint32_t word5; 2161#define lpfc_fcf_record_fab_name_0_SHIFT 0 2162#define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 2163#define lpfc_fcf_record_fab_name_0_WORD word5 2164#define lpfc_fcf_record_fab_name_1_SHIFT 8 2165#define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 2166#define lpfc_fcf_record_fab_name_1_WORD word5 2167#define lpfc_fcf_record_fab_name_2_SHIFT 16 2168#define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 2169#define lpfc_fcf_record_fab_name_2_WORD word5 2170#define lpfc_fcf_record_fab_name_3_SHIFT 24 2171#define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 2172#define lpfc_fcf_record_fab_name_3_WORD word5 2173 uint32_t word6; 2174#define lpfc_fcf_record_fab_name_4_SHIFT 0 2175#define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 2176#define lpfc_fcf_record_fab_name_4_WORD word6 2177#define lpfc_fcf_record_fab_name_5_SHIFT 8 2178#define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 2179#define lpfc_fcf_record_fab_name_5_WORD word6 2180#define lpfc_fcf_record_fab_name_6_SHIFT 16 2181#define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 2182#define lpfc_fcf_record_fab_name_6_WORD word6 2183#define lpfc_fcf_record_fab_name_7_SHIFT 24 2184#define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 2185#define lpfc_fcf_record_fab_name_7_WORD word6 2186 uint32_t word7; 2187#define lpfc_fcf_record_fc_map_0_SHIFT 0 2188#define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 2189#define lpfc_fcf_record_fc_map_0_WORD word7 2190#define lpfc_fcf_record_fc_map_1_SHIFT 8 2191#define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 2192#define lpfc_fcf_record_fc_map_1_WORD word7 2193#define lpfc_fcf_record_fc_map_2_SHIFT 16 2194#define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 2195#define lpfc_fcf_record_fc_map_2_WORD word7 2196#define lpfc_fcf_record_fcf_valid_SHIFT 24 2197#define lpfc_fcf_record_fcf_valid_MASK 0x00000001 2198#define lpfc_fcf_record_fcf_valid_WORD word7 2199#define lpfc_fcf_record_fcf_fc_SHIFT 25 2200#define lpfc_fcf_record_fcf_fc_MASK 0x00000001 2201#define lpfc_fcf_record_fcf_fc_WORD word7 2202#define lpfc_fcf_record_fcf_sol_SHIFT 31 2203#define lpfc_fcf_record_fcf_sol_MASK 0x00000001 2204#define lpfc_fcf_record_fcf_sol_WORD word7 2205 uint32_t word8; 2206#define lpfc_fcf_record_fcf_index_SHIFT 0 2207#define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 2208#define lpfc_fcf_record_fcf_index_WORD word8 2209#define lpfc_fcf_record_fcf_state_SHIFT 16 2210#define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 2211#define lpfc_fcf_record_fcf_state_WORD word8 2212 uint8_t vlan_bitmap[512]; 2213 uint32_t word137; 2214#define lpfc_fcf_record_switch_name_0_SHIFT 0 2215#define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 2216#define lpfc_fcf_record_switch_name_0_WORD word137 2217#define lpfc_fcf_record_switch_name_1_SHIFT 8 2218#define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 2219#define lpfc_fcf_record_switch_name_1_WORD word137 2220#define lpfc_fcf_record_switch_name_2_SHIFT 16 2221#define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 2222#define lpfc_fcf_record_switch_name_2_WORD word137 2223#define lpfc_fcf_record_switch_name_3_SHIFT 24 2224#define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 2225#define lpfc_fcf_record_switch_name_3_WORD word137 2226 uint32_t word138; 2227#define lpfc_fcf_record_switch_name_4_SHIFT 0 2228#define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 2229#define lpfc_fcf_record_switch_name_4_WORD word138 2230#define lpfc_fcf_record_switch_name_5_SHIFT 8 2231#define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 2232#define lpfc_fcf_record_switch_name_5_WORD word138 2233#define lpfc_fcf_record_switch_name_6_SHIFT 16 2234#define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 2235#define lpfc_fcf_record_switch_name_6_WORD word138 2236#define lpfc_fcf_record_switch_name_7_SHIFT 24 2237#define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 2238#define lpfc_fcf_record_switch_name_7_WORD word138 2239}; 2240 2241struct lpfc_mbx_read_fcf_tbl { 2242 union lpfc_sli4_cfg_shdr cfg_shdr; 2243 union { 2244 struct { 2245 uint32_t word10; 2246#define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 2247#define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 2248#define lpfc_mbx_read_fcf_tbl_indx_WORD word10 2249 } request; 2250 struct { 2251 uint32_t eventag; 2252 } response; 2253 } u; 2254 uint32_t word11; 2255#define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 2256#define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 2257#define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 2258}; 2259 2260struct lpfc_mbx_add_fcf_tbl_entry { 2261 union lpfc_sli4_cfg_shdr cfg_shdr; 2262 uint32_t word10; 2263#define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 2264#define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 2265#define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 2266 struct lpfc_mbx_sge fcf_sge; 2267}; 2268 2269struct lpfc_mbx_del_fcf_tbl_entry { 2270 struct mbox_header header; 2271 uint32_t word10; 2272#define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 2273#define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 2274#define lpfc_mbx_del_fcf_tbl_count_WORD word10 2275#define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 2276#define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 2277#define lpfc_mbx_del_fcf_tbl_index_WORD word10 2278}; 2279 2280struct lpfc_mbx_redisc_fcf_tbl { 2281 struct mbox_header header; 2282 uint32_t word10; 2283#define lpfc_mbx_redisc_fcf_count_SHIFT 0 2284#define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 2285#define lpfc_mbx_redisc_fcf_count_WORD word10 2286 uint32_t resvd; 2287 uint32_t word12; 2288#define lpfc_mbx_redisc_fcf_index_SHIFT 0 2289#define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 2290#define lpfc_mbx_redisc_fcf_index_WORD word12 2291}; 2292 2293/* Status field for embedded SLI_CONFIG mailbox command */ 2294#define STATUS_SUCCESS 0x0 2295#define STATUS_FAILED 0x1 2296#define STATUS_ILLEGAL_REQUEST 0x2 2297#define STATUS_ILLEGAL_FIELD 0x3 2298#define STATUS_INSUFFICIENT_BUFFER 0x4 2299#define STATUS_UNAUTHORIZED_REQUEST 0x5 2300#define STATUS_FLASHROM_SAVE_FAILED 0x17 2301#define STATUS_FLASHROM_RESTORE_FAILED 0x18 2302#define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 2303#define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 2304#define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 2305#define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 2306#define STATUS_ASSERT_FAILED 0x1e 2307#define STATUS_INVALID_SESSION 0x1f 2308#define STATUS_INVALID_CONNECTION 0x20 2309#define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 2310#define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 2311#define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 2312#define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 2313#define STATUS_FLASHROM_READ_FAILED 0x27 2314#define STATUS_POLL_IOCTL_TIMEOUT 0x28 2315#define STATUS_ERROR_ACITMAIN 0x2a 2316#define STATUS_REBOOT_REQUIRED 0x2c 2317#define STATUS_FCF_IN_USE 0x3a 2318#define STATUS_FCF_TABLE_EMPTY 0x43 2319 2320/* 2321 * Additional status field for embedded SLI_CONFIG mailbox 2322 * command. 2323 */ 2324#define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67 2325#define ADD_STATUS_FW_NOT_SUPPORTED 0xEB 2326#define ADD_STATUS_INVALID_REQUEST 0x4B 2327#define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED 0x58 2328 2329struct lpfc_mbx_sli4_config { 2330 struct mbox_header header; 2331}; 2332 2333struct lpfc_mbx_init_vfi { 2334 uint32_t word1; 2335#define lpfc_init_vfi_vr_SHIFT 31 2336#define lpfc_init_vfi_vr_MASK 0x00000001 2337#define lpfc_init_vfi_vr_WORD word1 2338#define lpfc_init_vfi_vt_SHIFT 30 2339#define lpfc_init_vfi_vt_MASK 0x00000001 2340#define lpfc_init_vfi_vt_WORD word1 2341#define lpfc_init_vfi_vf_SHIFT 29 2342#define lpfc_init_vfi_vf_MASK 0x00000001 2343#define lpfc_init_vfi_vf_WORD word1 2344#define lpfc_init_vfi_vp_SHIFT 28 2345#define lpfc_init_vfi_vp_MASK 0x00000001 2346#define lpfc_init_vfi_vp_WORD word1 2347#define lpfc_init_vfi_vfi_SHIFT 0 2348#define lpfc_init_vfi_vfi_MASK 0x0000FFFF 2349#define lpfc_init_vfi_vfi_WORD word1 2350 uint32_t word2; 2351#define lpfc_init_vfi_vpi_SHIFT 16 2352#define lpfc_init_vfi_vpi_MASK 0x0000FFFF 2353#define lpfc_init_vfi_vpi_WORD word2 2354#define lpfc_init_vfi_fcfi_SHIFT 0 2355#define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 2356#define lpfc_init_vfi_fcfi_WORD word2 2357 uint32_t word3; 2358#define lpfc_init_vfi_pri_SHIFT 13 2359#define lpfc_init_vfi_pri_MASK 0x00000007 2360#define lpfc_init_vfi_pri_WORD word3 2361#define lpfc_init_vfi_vf_id_SHIFT 1 2362#define lpfc_init_vfi_vf_id_MASK 0x00000FFF 2363#define lpfc_init_vfi_vf_id_WORD word3 2364 uint32_t word4; 2365#define lpfc_init_vfi_hop_count_SHIFT 24 2366#define lpfc_init_vfi_hop_count_MASK 0x000000FF 2367#define lpfc_init_vfi_hop_count_WORD word4 2368}; 2369#define MBX_VFI_IN_USE 0x9F02 2370 2371 2372struct lpfc_mbx_reg_vfi { 2373 uint32_t word1; 2374#define lpfc_reg_vfi_upd_SHIFT 29 2375#define lpfc_reg_vfi_upd_MASK 0x00000001 2376#define lpfc_reg_vfi_upd_WORD word1 2377#define lpfc_reg_vfi_vp_SHIFT 28 2378#define lpfc_reg_vfi_vp_MASK 0x00000001 2379#define lpfc_reg_vfi_vp_WORD word1 2380#define lpfc_reg_vfi_vfi_SHIFT 0 2381#define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 2382#define lpfc_reg_vfi_vfi_WORD word1 2383 uint32_t word2; 2384#define lpfc_reg_vfi_vpi_SHIFT 16 2385#define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 2386#define lpfc_reg_vfi_vpi_WORD word2 2387#define lpfc_reg_vfi_fcfi_SHIFT 0 2388#define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 2389#define lpfc_reg_vfi_fcfi_WORD word2 2390 uint32_t wwn[2]; 2391 struct ulp_bde64 bde; 2392 uint32_t e_d_tov; 2393 uint32_t r_a_tov; 2394 uint32_t word10; 2395#define lpfc_reg_vfi_nport_id_SHIFT 0 2396#define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 2397#define lpfc_reg_vfi_nport_id_WORD word10 2398#define lpfc_reg_vfi_bbcr_SHIFT 27 2399#define lpfc_reg_vfi_bbcr_MASK 0x00000001 2400#define lpfc_reg_vfi_bbcr_WORD word10 2401#define lpfc_reg_vfi_bbscn_SHIFT 28 2402#define lpfc_reg_vfi_bbscn_MASK 0x0000000F 2403#define lpfc_reg_vfi_bbscn_WORD word10 2404}; 2405 2406struct lpfc_mbx_init_vpi { 2407 uint32_t word1; 2408#define lpfc_init_vpi_vfi_SHIFT 16 2409#define lpfc_init_vpi_vfi_MASK 0x0000FFFF 2410#define lpfc_init_vpi_vfi_WORD word1 2411#define lpfc_init_vpi_vpi_SHIFT 0 2412#define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2413#define lpfc_init_vpi_vpi_WORD word1 2414}; 2415 2416struct lpfc_mbx_read_vpi { 2417 uint32_t word1_rsvd; 2418 uint32_t word2; 2419#define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2420#define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2421#define lpfc_mbx_read_vpi_vnportid_WORD word2 2422 uint32_t word3_rsvd; 2423 uint32_t word4; 2424#define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2425#define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2426#define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2427#define lpfc_mbx_read_vpi_pb_SHIFT 15 2428#define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2429#define lpfc_mbx_read_vpi_pb_WORD word4 2430#define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2431#define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2432#define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2433#define lpfc_mbx_read_vpi_ns_SHIFT 30 2434#define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2435#define lpfc_mbx_read_vpi_ns_WORD word4 2436#define lpfc_mbx_read_vpi_hl_SHIFT 31 2437#define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2438#define lpfc_mbx_read_vpi_hl_WORD word4 2439 uint32_t word5_rsvd; 2440 uint32_t word6; 2441#define lpfc_mbx_read_vpi_vpi_SHIFT 0 2442#define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2443#define lpfc_mbx_read_vpi_vpi_WORD word6 2444 uint32_t word7; 2445#define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2446#define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2447#define lpfc_mbx_read_vpi_mac_0_WORD word7 2448#define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2449#define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2450#define lpfc_mbx_read_vpi_mac_1_WORD word7 2451#define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2452#define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2453#define lpfc_mbx_read_vpi_mac_2_WORD word7 2454#define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2455#define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2456#define lpfc_mbx_read_vpi_mac_3_WORD word7 2457 uint32_t word8; 2458#define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2459#define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2460#define lpfc_mbx_read_vpi_mac_4_WORD word8 2461#define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2462#define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2463#define lpfc_mbx_read_vpi_mac_5_WORD word8 2464#define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2465#define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2466#define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2467#define lpfc_mbx_read_vpi_vv_SHIFT 28 2468#define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2469#define lpfc_mbx_read_vpi_vv_WORD word8 2470}; 2471 2472struct lpfc_mbx_unreg_vfi { 2473 uint32_t word1_rsvd; 2474 uint32_t word2; 2475#define lpfc_unreg_vfi_vfi_SHIFT 0 2476#define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2477#define lpfc_unreg_vfi_vfi_WORD word2 2478}; 2479 2480struct lpfc_mbx_resume_rpi { 2481 uint32_t word1; 2482#define lpfc_resume_rpi_index_SHIFT 0 2483#define lpfc_resume_rpi_index_MASK 0x0000FFFF 2484#define lpfc_resume_rpi_index_WORD word1 2485#define lpfc_resume_rpi_ii_SHIFT 30 2486#define lpfc_resume_rpi_ii_MASK 0x00000003 2487#define lpfc_resume_rpi_ii_WORD word1 2488#define RESUME_INDEX_RPI 0 2489#define RESUME_INDEX_VPI 1 2490#define RESUME_INDEX_VFI 2 2491#define RESUME_INDEX_FCFI 3 2492 uint32_t event_tag; 2493}; 2494 2495#define REG_FCF_INVALID_QID 0xFFFF 2496struct lpfc_mbx_reg_fcfi { 2497 uint32_t word1; 2498#define lpfc_reg_fcfi_info_index_SHIFT 0 2499#define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2500#define lpfc_reg_fcfi_info_index_WORD word1 2501#define lpfc_reg_fcfi_fcfi_SHIFT 16 2502#define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2503#define lpfc_reg_fcfi_fcfi_WORD word1 2504 uint32_t word2; 2505#define lpfc_reg_fcfi_rq_id1_SHIFT 0 2506#define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2507#define lpfc_reg_fcfi_rq_id1_WORD word2 2508#define lpfc_reg_fcfi_rq_id0_SHIFT 16 2509#define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2510#define lpfc_reg_fcfi_rq_id0_WORD word2 2511 uint32_t word3; 2512#define lpfc_reg_fcfi_rq_id3_SHIFT 0 2513#define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2514#define lpfc_reg_fcfi_rq_id3_WORD word3 2515#define lpfc_reg_fcfi_rq_id2_SHIFT 16 2516#define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2517#define lpfc_reg_fcfi_rq_id2_WORD word3 2518 uint32_t word4; 2519#define lpfc_reg_fcfi_type_match0_SHIFT 24 2520#define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2521#define lpfc_reg_fcfi_type_match0_WORD word4 2522#define lpfc_reg_fcfi_type_mask0_SHIFT 16 2523#define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2524#define lpfc_reg_fcfi_type_mask0_WORD word4 2525#define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2526#define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2527#define lpfc_reg_fcfi_rctl_match0_WORD word4 2528#define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2529#define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2530#define lpfc_reg_fcfi_rctl_mask0_WORD word4 2531 uint32_t word5; 2532#define lpfc_reg_fcfi_type_match1_SHIFT 24 2533#define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2534#define lpfc_reg_fcfi_type_match1_WORD word5 2535#define lpfc_reg_fcfi_type_mask1_SHIFT 16 2536#define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2537#define lpfc_reg_fcfi_type_mask1_WORD word5 2538#define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2539#define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2540#define lpfc_reg_fcfi_rctl_match1_WORD word5 2541#define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2542#define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2543#define lpfc_reg_fcfi_rctl_mask1_WORD word5 2544 uint32_t word6; 2545#define lpfc_reg_fcfi_type_match2_SHIFT 24 2546#define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2547#define lpfc_reg_fcfi_type_match2_WORD word6 2548#define lpfc_reg_fcfi_type_mask2_SHIFT 16 2549#define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2550#define lpfc_reg_fcfi_type_mask2_WORD word6 2551#define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2552#define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2553#define lpfc_reg_fcfi_rctl_match2_WORD word6 2554#define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2555#define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2556#define lpfc_reg_fcfi_rctl_mask2_WORD word6 2557 uint32_t word7; 2558#define lpfc_reg_fcfi_type_match3_SHIFT 24 2559#define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2560#define lpfc_reg_fcfi_type_match3_WORD word7 2561#define lpfc_reg_fcfi_type_mask3_SHIFT 16 2562#define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2563#define lpfc_reg_fcfi_type_mask3_WORD word7 2564#define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2565#define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2566#define lpfc_reg_fcfi_rctl_match3_WORD word7 2567#define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2568#define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2569#define lpfc_reg_fcfi_rctl_mask3_WORD word7 2570 uint32_t word8; 2571#define lpfc_reg_fcfi_mam_SHIFT 13 2572#define lpfc_reg_fcfi_mam_MASK 0x00000003 2573#define lpfc_reg_fcfi_mam_WORD word8 2574#define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2575#define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2576#define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2577#define lpfc_reg_fcfi_vv_SHIFT 12 2578#define lpfc_reg_fcfi_vv_MASK 0x00000001 2579#define lpfc_reg_fcfi_vv_WORD word8 2580#define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2581#define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2582#define lpfc_reg_fcfi_vlan_tag_WORD word8 2583}; 2584 2585struct lpfc_mbx_reg_fcfi_mrq { 2586 uint32_t word1; 2587#define lpfc_reg_fcfi_mrq_info_index_SHIFT 0 2588#define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF 2589#define lpfc_reg_fcfi_mrq_info_index_WORD word1 2590#define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16 2591#define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF 2592#define lpfc_reg_fcfi_mrq_fcfi_WORD word1 2593 uint32_t word2; 2594#define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0 2595#define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF 2596#define lpfc_reg_fcfi_mrq_rq_id1_WORD word2 2597#define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16 2598#define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF 2599#define lpfc_reg_fcfi_mrq_rq_id0_WORD word2 2600 uint32_t word3; 2601#define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0 2602#define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF 2603#define lpfc_reg_fcfi_mrq_rq_id3_WORD word3 2604#define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16 2605#define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF 2606#define lpfc_reg_fcfi_mrq_rq_id2_WORD word3 2607 uint32_t word4; 2608#define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24 2609#define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF 2610#define lpfc_reg_fcfi_mrq_type_match0_WORD word4 2611#define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16 2612#define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF 2613#define lpfc_reg_fcfi_mrq_type_mask0_WORD word4 2614#define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8 2615#define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF 2616#define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4 2617#define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0 2618#define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF 2619#define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4 2620 uint32_t word5; 2621#define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24 2622#define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF 2623#define lpfc_reg_fcfi_mrq_type_match1_WORD word5 2624#define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16 2625#define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF 2626#define lpfc_reg_fcfi_mrq_type_mask1_WORD word5 2627#define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8 2628#define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF 2629#define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5 2630#define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0 2631#define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF 2632#define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5 2633 uint32_t word6; 2634#define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24 2635#define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF 2636#define lpfc_reg_fcfi_mrq_type_match2_WORD word6 2637#define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16 2638#define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF 2639#define lpfc_reg_fcfi_mrq_type_mask2_WORD word6 2640#define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8 2641#define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF 2642#define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6 2643#define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0 2644#define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF 2645#define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6 2646 uint32_t word7; 2647#define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24 2648#define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF 2649#define lpfc_reg_fcfi_mrq_type_match3_WORD word7 2650#define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16 2651#define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF 2652#define lpfc_reg_fcfi_mrq_type_mask3_WORD word7 2653#define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8 2654#define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF 2655#define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7 2656#define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0 2657#define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF 2658#define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7 2659 uint32_t word8; 2660#define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31 2661#define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001 2662#define lpfc_reg_fcfi_mrq_ptc7_WORD word8 2663#define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30 2664#define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001 2665#define lpfc_reg_fcfi_mrq_ptc6_WORD word8 2666#define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29 2667#define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001 2668#define lpfc_reg_fcfi_mrq_ptc5_WORD word8 2669#define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28 2670#define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001 2671#define lpfc_reg_fcfi_mrq_ptc4_WORD word8 2672#define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27 2673#define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001 2674#define lpfc_reg_fcfi_mrq_ptc3_WORD word8 2675#define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26 2676#define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001 2677#define lpfc_reg_fcfi_mrq_ptc2_WORD word8 2678#define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25 2679#define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001 2680#define lpfc_reg_fcfi_mrq_ptc1_WORD word8 2681#define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24 2682#define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001 2683#define lpfc_reg_fcfi_mrq_ptc0_WORD word8 2684#define lpfc_reg_fcfi_mrq_pt7_SHIFT 23 2685#define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001 2686#define lpfc_reg_fcfi_mrq_pt7_WORD word8 2687#define lpfc_reg_fcfi_mrq_pt6_SHIFT 22 2688#define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001 2689#define lpfc_reg_fcfi_mrq_pt6_WORD word8 2690#define lpfc_reg_fcfi_mrq_pt5_SHIFT 21 2691#define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001 2692#define lpfc_reg_fcfi_mrq_pt5_WORD word8 2693#define lpfc_reg_fcfi_mrq_pt4_SHIFT 20 2694#define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001 2695#define lpfc_reg_fcfi_mrq_pt4_WORD word8 2696#define lpfc_reg_fcfi_mrq_pt3_SHIFT 19 2697#define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001 2698#define lpfc_reg_fcfi_mrq_pt3_WORD word8 2699#define lpfc_reg_fcfi_mrq_pt2_SHIFT 18 2700#define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001 2701#define lpfc_reg_fcfi_mrq_pt2_WORD word8 2702#define lpfc_reg_fcfi_mrq_pt1_SHIFT 17 2703#define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001 2704#define lpfc_reg_fcfi_mrq_pt1_WORD word8 2705#define lpfc_reg_fcfi_mrq_pt0_SHIFT 16 2706#define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001 2707#define lpfc_reg_fcfi_mrq_pt0_WORD word8 2708#define lpfc_reg_fcfi_mrq_xmv_SHIFT 15 2709#define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001 2710#define lpfc_reg_fcfi_mrq_xmv_WORD word8 2711#define lpfc_reg_fcfi_mrq_mode_SHIFT 13 2712#define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001 2713#define lpfc_reg_fcfi_mrq_mode_WORD word8 2714#define lpfc_reg_fcfi_mrq_vv_SHIFT 12 2715#define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001 2716#define lpfc_reg_fcfi_mrq_vv_WORD word8 2717#define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0 2718#define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF 2719#define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8 2720 uint32_t word9; 2721#define lpfc_reg_fcfi_mrq_policy_SHIFT 12 2722#define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F 2723#define lpfc_reg_fcfi_mrq_policy_WORD word9 2724#define lpfc_reg_fcfi_mrq_filter_SHIFT 8 2725#define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F 2726#define lpfc_reg_fcfi_mrq_filter_WORD word9 2727#define lpfc_reg_fcfi_mrq_npairs_SHIFT 0 2728#define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF 2729#define lpfc_reg_fcfi_mrq_npairs_WORD word9 2730 uint32_t word10; 2731 uint32_t word11; 2732 uint32_t word12; 2733 uint32_t word13; 2734 uint32_t word14; 2735 uint32_t word15; 2736 uint32_t word16; 2737}; 2738 2739struct lpfc_mbx_unreg_fcfi { 2740 uint32_t word1_rsv; 2741 uint32_t word2; 2742#define lpfc_unreg_fcfi_SHIFT 0 2743#define lpfc_unreg_fcfi_MASK 0x0000FFFF 2744#define lpfc_unreg_fcfi_WORD word2 2745}; 2746 2747struct lpfc_mbx_read_rev { 2748 uint32_t word1; 2749#define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2750#define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2751#define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2752#define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2753#define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2754#define lpfc_mbx_rd_rev_fcoe_WORD word1 2755#define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2756#define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2757#define lpfc_mbx_rd_rev_cee_ver_WORD word1 2758#define LPFC_PREDCBX_CEE_MODE 0 2759#define LPFC_DCBX_CEE_MODE 1 2760#define lpfc_mbx_rd_rev_vpd_SHIFT 29 2761#define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2762#define lpfc_mbx_rd_rev_vpd_WORD word1 2763 uint32_t first_hw_rev; 2764#define LPFC_G7_ASIC_1 0xd 2765 uint32_t second_hw_rev; 2766 uint32_t word4_rsvd; 2767 uint32_t third_hw_rev; 2768 uint32_t word6; 2769#define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2770#define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2771#define lpfc_mbx_rd_rev_fcph_low_WORD word6 2772#define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2773#define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2774#define lpfc_mbx_rd_rev_fcph_high_WORD word6 2775#define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2776#define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2777#define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2778#define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2779#define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2780#define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2781 uint32_t word7_rsvd; 2782 uint32_t fw_id_rev; 2783 uint8_t fw_name[16]; 2784 uint32_t ulp_fw_id_rev; 2785 uint8_t ulp_fw_name[16]; 2786 uint32_t word18_47_rsvd[30]; 2787 uint32_t word48; 2788#define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2789#define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2790#define lpfc_mbx_rd_rev_avail_len_WORD word48 2791 uint32_t vpd_paddr_low; 2792 uint32_t vpd_paddr_high; 2793 uint32_t avail_vpd_len; 2794 uint32_t rsvd_52_63[12]; 2795}; 2796 2797struct lpfc_mbx_read_config { 2798 uint32_t word1; 2799#define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2800#define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2801#define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2802 uint32_t word2; 2803#define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2804#define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2805#define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2806#define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2807#define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2808#define lpfc_mbx_rd_conf_lnk_type_WORD word2 2809#define LPFC_LNK_TYPE_GE 0 2810#define LPFC_LNK_TYPE_FC 1 2811#define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2812#define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2813#define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2814#define lpfc_mbx_rd_conf_trunk_SHIFT 12 2815#define lpfc_mbx_rd_conf_trunk_MASK 0x0000000F 2816#define lpfc_mbx_rd_conf_trunk_WORD word2 2817#define lpfc_mbx_rd_conf_pt_SHIFT 20 2818#define lpfc_mbx_rd_conf_pt_MASK 0x00000003 2819#define lpfc_mbx_rd_conf_pt_WORD word2 2820#define lpfc_mbx_rd_conf_tf_SHIFT 22 2821#define lpfc_mbx_rd_conf_tf_MASK 0x00000001 2822#define lpfc_mbx_rd_conf_tf_WORD word2 2823#define lpfc_mbx_rd_conf_ptv_SHIFT 23 2824#define lpfc_mbx_rd_conf_ptv_MASK 0x00000001 2825#define lpfc_mbx_rd_conf_ptv_WORD word2 2826#define lpfc_mbx_rd_conf_topology_SHIFT 24 2827#define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2828#define lpfc_mbx_rd_conf_topology_WORD word2 2829 uint32_t rsvd_3; 2830 uint32_t word4; 2831#define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2832#define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2833#define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2834 uint32_t rsvd_5; 2835 uint32_t word6; 2836#define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2837#define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2838#define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2839#define lpfc_mbx_rd_conf_link_speed_SHIFT 16 2840#define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF 2841#define lpfc_mbx_rd_conf_link_speed_WORD word6 2842 uint32_t rsvd_7; 2843 uint32_t word8; 2844#define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0 2845#define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F 2846#define lpfc_mbx_rd_conf_bbscn_min_WORD word8 2847#define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4 2848#define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F 2849#define lpfc_mbx_rd_conf_bbscn_max_WORD word8 2850#define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8 2851#define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F 2852#define lpfc_mbx_rd_conf_bbscn_def_WORD word8 2853 uint32_t word9; 2854#define lpfc_mbx_rd_conf_lmt_SHIFT 0 2855#define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2856#define lpfc_mbx_rd_conf_lmt_WORD word9 2857 uint32_t rsvd_10; 2858 uint32_t rsvd_11; 2859 uint32_t word12; 2860#define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2861#define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2862#define lpfc_mbx_rd_conf_xri_base_WORD word12 2863#define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2864#define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2865#define lpfc_mbx_rd_conf_xri_count_WORD word12 2866 uint32_t word13; 2867#define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2868#define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2869#define lpfc_mbx_rd_conf_rpi_base_WORD word13 2870#define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2871#define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2872#define lpfc_mbx_rd_conf_rpi_count_WORD word13 2873 uint32_t word14; 2874#define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2875#define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2876#define lpfc_mbx_rd_conf_vpi_base_WORD word14 2877#define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2878#define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2879#define lpfc_mbx_rd_conf_vpi_count_WORD word14 2880 uint32_t word15; 2881#define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2882#define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2883#define lpfc_mbx_rd_conf_vfi_base_WORD word15 2884#define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2885#define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2886#define lpfc_mbx_rd_conf_vfi_count_WORD word15 2887 uint32_t word16; 2888#define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2889#define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2890#define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2891 uint32_t word17; 2892#define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2893#define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2894#define lpfc_mbx_rd_conf_rq_count_WORD word17 2895#define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2896#define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2897#define lpfc_mbx_rd_conf_eq_count_WORD word17 2898 uint32_t word18; 2899#define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2900#define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2901#define lpfc_mbx_rd_conf_wq_count_WORD word18 2902#define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2903#define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2904#define lpfc_mbx_rd_conf_cq_count_WORD word18 2905}; 2906 2907struct lpfc_mbx_request_features { 2908 uint32_t word1; 2909#define lpfc_mbx_rq_ftr_qry_SHIFT 0 2910#define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2911#define lpfc_mbx_rq_ftr_qry_WORD word1 2912 uint32_t word2; 2913#define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2914#define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2915#define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2916#define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2917#define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2918#define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2919#define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2920#define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2921#define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2922#define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2923#define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2924#define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2925#define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2926#define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2927#define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2928#define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2929#define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2930#define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2931#define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2932#define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2933#define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2934#define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2935#define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2936#define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2937#define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9 2938#define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001 2939#define lpfc_mbx_rq_ftr_rq_iaar_WORD word2 2940#define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2941#define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2942#define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2943#define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16 2944#define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001 2945#define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2 2946 uint32_t word3; 2947#define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2948#define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2949#define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2950#define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2951#define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2952#define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2953#define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2954#define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2955#define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2956#define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2957#define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2958#define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2959#define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2960#define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2961#define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2962#define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2963#define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2964#define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2965#define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2966#define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2967#define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2968#define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2969#define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2970#define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2971#define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2972#define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2973#define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2974#define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16 2975#define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001 2976#define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3 2977}; 2978 2979struct lpfc_mbx_supp_pages { 2980 uint32_t word1; 2981#define qs_SHIFT 0 2982#define qs_MASK 0x00000001 2983#define qs_WORD word1 2984#define wr_SHIFT 1 2985#define wr_MASK 0x00000001 2986#define wr_WORD word1 2987#define pf_SHIFT 8 2988#define pf_MASK 0x000000ff 2989#define pf_WORD word1 2990#define cpn_SHIFT 16 2991#define cpn_MASK 0x000000ff 2992#define cpn_WORD word1 2993 uint32_t word2; 2994#define list_offset_SHIFT 0 2995#define list_offset_MASK 0x000000ff 2996#define list_offset_WORD word2 2997#define next_offset_SHIFT 8 2998#define next_offset_MASK 0x000000ff 2999#define next_offset_WORD word2 3000#define elem_cnt_SHIFT 16
3001#define elem_cnt_MASK 0x000000ff 3002#define elem_cnt_WORD word2 3003 uint32_t word3; 3004#define pn_0_SHIFT 24 3005#define pn_0_MASK 0x000000ff 3006#define pn_0_WORD word3 3007#define pn_1_SHIFT 16 3008#define pn_1_MASK 0x000000ff 3009#define pn_1_WORD word3 3010#define pn_2_SHIFT 8 3011#define pn_2_MASK 0x000000ff 3012#define pn_2_WORD word3 3013#define pn_3_SHIFT 0 3014#define pn_3_MASK 0x000000ff 3015#define pn_3_WORD word3 3016 uint32_t word4; 3017#define pn_4_SHIFT 24 3018#define pn_4_MASK 0x000000ff 3019#define pn_4_WORD word4 3020#define pn_5_SHIFT 16 3021#define pn_5_MASK 0x000000ff 3022#define pn_5_WORD word4 3023#define pn_6_SHIFT 8 3024#define pn_6_MASK 0x000000ff 3025#define pn_6_WORD word4 3026#define pn_7_SHIFT 0 3027#define pn_7_MASK 0x000000ff 3028#define pn_7_WORD word4 3029 uint32_t rsvd[27]; 3030#define LPFC_SUPP_PAGES 0 3031#define LPFC_BLOCK_GUARD_PROFILES 1 3032#define LPFC_SLI4_PARAMETERS 2 3033}; 3034 3035struct lpfc_mbx_memory_dump_type3 { 3036 uint32_t word1; 3037#define lpfc_mbx_memory_dump_type3_type_SHIFT 0 3038#define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f 3039#define lpfc_mbx_memory_dump_type3_type_WORD word1 3040#define lpfc_mbx_memory_dump_type3_link_SHIFT 24 3041#define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff 3042#define lpfc_mbx_memory_dump_type3_link_WORD word1 3043 uint32_t word2; 3044#define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0 3045#define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff 3046#define lpfc_mbx_memory_dump_type3_page_no_WORD word2 3047#define lpfc_mbx_memory_dump_type3_offset_SHIFT 16 3048#define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff 3049#define lpfc_mbx_memory_dump_type3_offset_WORD word2 3050 uint32_t word3; 3051#define lpfc_mbx_memory_dump_type3_length_SHIFT 0 3052#define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff 3053#define lpfc_mbx_memory_dump_type3_length_WORD word3 3054 uint32_t addr_lo; 3055 uint32_t addr_hi; 3056 uint32_t return_len; 3057}; 3058 3059#define DMP_PAGE_A0 0xa0 3060#define DMP_PAGE_A2 0xa2 3061#define DMP_SFF_PAGE_A0_SIZE 256 3062#define DMP_SFF_PAGE_A2_SIZE 256 3063 3064#define SFP_WAVELENGTH_LC1310 1310 3065#define SFP_WAVELENGTH_LL1550 1550 3066 3067 3068/* 3069 * * SFF-8472 TABLE 3.4 3070 * */ 3071#define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */ 3072#define SFF_PG0_CONNECTOR_SC 0x01 /* SC */ 3073#define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */ 3074#define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */ 3075#define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */ 3076#define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */ 3077#define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */ 3078#define SFF_PG0_CONNECTOR_LC 0x07 /* LC */ 3079#define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */ 3080#define SFF_PG0_CONNECTOR_MU 0x09 /* MU */ 3081#define SFF_PG0_CONNECTOR_SF 0x0A /* SG */ 3082#define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */ 3083#define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */ 3084#define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */ 3085#define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */ 3086#define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */ 3087 3088/* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ 3089 3090#define SSF_IDENTIFIER 0 3091#define SSF_EXT_IDENTIFIER 1 3092#define SSF_CONNECTOR 2 3093#define SSF_TRANSCEIVER_CODE_B0 3 3094#define SSF_TRANSCEIVER_CODE_B1 4 3095#define SSF_TRANSCEIVER_CODE_B2 5 3096#define SSF_TRANSCEIVER_CODE_B3 6 3097#define SSF_TRANSCEIVER_CODE_B4 7 3098#define SSF_TRANSCEIVER_CODE_B5 8 3099#define SSF_TRANSCEIVER_CODE_B6 9 3100#define SSF_TRANSCEIVER_CODE_B7 10 3101#define SSF_ENCODING 11 3102#define SSF_BR_NOMINAL 12 3103#define SSF_RATE_IDENTIFIER 13 3104#define SSF_LENGTH_9UM_KM 14 3105#define SSF_LENGTH_9UM 15 3106#define SSF_LENGTH_50UM_OM2 16 3107#define SSF_LENGTH_62UM_OM1 17 3108#define SFF_LENGTH_COPPER 18 3109#define SSF_LENGTH_50UM_OM3 19 3110#define SSF_VENDOR_NAME 20 3111#define SSF_VENDOR_OUI 36 3112#define SSF_VENDOR_PN 40 3113#define SSF_VENDOR_REV 56 3114#define SSF_WAVELENGTH_B1 60 3115#define SSF_WAVELENGTH_B0 61 3116#define SSF_CC_BASE 63 3117#define SSF_OPTIONS_B1 64 3118#define SSF_OPTIONS_B0 65 3119#define SSF_BR_MAX 66 3120#define SSF_BR_MIN 67 3121#define SSF_VENDOR_SN 68 3122#define SSF_DATE_CODE 84 3123#define SSF_MONITORING_TYPEDIAGNOSTIC 92 3124#define SSF_ENHANCED_OPTIONS 93 3125#define SFF_8472_COMPLIANCE 94 3126#define SSF_CC_EXT 95 3127#define SSF_A0_VENDOR_SPECIFIC 96 3128 3129/* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ 3130 3131#define SSF_TEMP_HIGH_ALARM 0 3132#define SSF_TEMP_LOW_ALARM 2 3133#define SSF_TEMP_HIGH_WARNING 4 3134#define SSF_TEMP_LOW_WARNING 6 3135#define SSF_VOLTAGE_HIGH_ALARM 8 3136#define SSF_VOLTAGE_LOW_ALARM 10 3137#define SSF_VOLTAGE_HIGH_WARNING 12 3138#define SSF_VOLTAGE_LOW_WARNING 14 3139#define SSF_BIAS_HIGH_ALARM 16 3140#define SSF_BIAS_LOW_ALARM 18 3141#define SSF_BIAS_HIGH_WARNING 20 3142#define SSF_BIAS_LOW_WARNING 22 3143#define SSF_TXPOWER_HIGH_ALARM 24 3144#define SSF_TXPOWER_LOW_ALARM 26 3145#define SSF_TXPOWER_HIGH_WARNING 28 3146#define SSF_TXPOWER_LOW_WARNING 30 3147#define SSF_RXPOWER_HIGH_ALARM 32 3148#define SSF_RXPOWER_LOW_ALARM 34 3149#define SSF_RXPOWER_HIGH_WARNING 36 3150#define SSF_RXPOWER_LOW_WARNING 38 3151#define SSF_EXT_CAL_CONSTANTS 56 3152#define SSF_CC_DMI 95 3153#define SFF_TEMPERATURE_B1 96 3154#define SFF_TEMPERATURE_B0 97 3155#define SFF_VCC_B1 98 3156#define SFF_VCC_B0 99 3157#define SFF_TX_BIAS_CURRENT_B1 100 3158#define SFF_TX_BIAS_CURRENT_B0 101 3159#define SFF_TXPOWER_B1 102 3160#define SFF_TXPOWER_B0 103 3161#define SFF_RXPOWER_B1 104 3162#define SFF_RXPOWER_B0 105 3163#define SSF_STATUS_CONTROL 110 3164#define SSF_ALARM_FLAGS 112 3165#define SSF_WARNING_FLAGS 116 3166#define SSF_EXT_TATUS_CONTROL_B1 118 3167#define SSF_EXT_TATUS_CONTROL_B0 119 3168#define SSF_A2_VENDOR_SPECIFIC 120 3169#define SSF_USER_EEPROM 128 3170#define SSF_VENDOR_CONTROL 148 3171 3172 3173/* 3174 * Tranceiver codes Fibre Channel SFF-8472 3175 * Table 3.5. 3176 */ 3177 3178struct sff_trasnceiver_codes_byte0 { 3179 uint8_t inifiband:4; 3180 uint8_t teng_ethernet:4; 3181}; 3182 3183struct sff_trasnceiver_codes_byte1 { 3184 uint8_t sonet:6; 3185 uint8_t escon:2; 3186}; 3187 3188struct sff_trasnceiver_codes_byte2 { 3189 uint8_t soNet:8; 3190}; 3191 3192struct sff_trasnceiver_codes_byte3 { 3193 uint8_t ethernet:8; 3194}; 3195 3196struct sff_trasnceiver_codes_byte4 { 3197 uint8_t fc_el_lo:1; 3198 uint8_t fc_lw_laser:1; 3199 uint8_t fc_sw_laser:1; 3200 uint8_t fc_md_distance:1; 3201 uint8_t fc_lg_distance:1; 3202 uint8_t fc_int_distance:1; 3203 uint8_t fc_short_distance:1; 3204 uint8_t fc_vld_distance:1; 3205}; 3206 3207struct sff_trasnceiver_codes_byte5 { 3208 uint8_t reserved1:1; 3209 uint8_t reserved2:1; 3210 uint8_t fc_sfp_active:1; /* Active cable */ 3211 uint8_t fc_sfp_passive:1; /* Passive cable */ 3212 uint8_t fc_lw_laser:1; /* Longwave laser */ 3213 uint8_t fc_sw_laser_sl:1; 3214 uint8_t fc_sw_laser_sn:1; 3215 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */ 3216}; 3217 3218struct sff_trasnceiver_codes_byte6 { 3219 uint8_t fc_tm_sm:1; /* Single Mode */ 3220 uint8_t reserved:1; 3221 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */ 3222 uint8_t fc_tm_tv:1; /* Video Coax (TV) */ 3223 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */ 3224 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */ 3225 uint8_t fc_tm_tw:1; /* Twin Axial Pair */ 3226}; 3227 3228struct sff_trasnceiver_codes_byte7 { 3229 uint8_t fc_sp_100MB:1; /* 100 MB/sec */ 3230 uint8_t reserve:1; 3231 uint8_t fc_sp_200mb:1; /* 200 MB/sec */ 3232 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */ 3233 uint8_t fc_sp_400MB:1; /* 400 MB/sec */ 3234 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */ 3235 uint8_t fc_sp_800MB:1; /* 800 MB/sec */ 3236 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */ 3237}; 3238 3239/* User writable non-volatile memory, SFF-8472 Table 3.20 */ 3240struct user_eeprom { 3241 uint8_t vendor_name[16]; 3242 uint8_t vendor_oui[3]; 3243 uint8_t vendor_pn[816]; 3244 uint8_t vendor_rev[4]; 3245 uint8_t vendor_sn[16]; 3246 uint8_t datecode[6]; 3247 uint8_t lot_code[2]; 3248 uint8_t reserved191[57]; 3249}; 3250 3251struct lpfc_mbx_pc_sli4_params { 3252 uint32_t word1; 3253#define qs_SHIFT 0 3254#define qs_MASK 0x00000001 3255#define qs_WORD word1 3256#define wr_SHIFT 1 3257#define wr_MASK 0x00000001 3258#define wr_WORD word1 3259#define pf_SHIFT 8 3260#define pf_MASK 0x000000ff 3261#define pf_WORD word1 3262#define cpn_SHIFT 16 3263#define cpn_MASK 0x000000ff 3264#define cpn_WORD word1 3265 uint32_t word2; 3266#define if_type_SHIFT 0 3267#define if_type_MASK 0x00000007 3268#define if_type_WORD word2 3269#define sli_rev_SHIFT 4 3270#define sli_rev_MASK 0x0000000f 3271#define sli_rev_WORD word2 3272#define sli_family_SHIFT 8 3273#define sli_family_MASK 0x000000ff 3274#define sli_family_WORD word2 3275#define featurelevel_1_SHIFT 16 3276#define featurelevel_1_MASK 0x000000ff 3277#define featurelevel_1_WORD word2 3278#define featurelevel_2_SHIFT 24 3279#define featurelevel_2_MASK 0x0000001f 3280#define featurelevel_2_WORD word2 3281 uint32_t word3; 3282#define fcoe_SHIFT 0 3283#define fcoe_MASK 0x00000001 3284#define fcoe_WORD word3 3285#define fc_SHIFT 1 3286#define fc_MASK 0x00000001 3287#define fc_WORD word3 3288#define nic_SHIFT 2 3289#define nic_MASK 0x00000001 3290#define nic_WORD word3 3291#define iscsi_SHIFT 3 3292#define iscsi_MASK 0x00000001 3293#define iscsi_WORD word3 3294#define rdma_SHIFT 4 3295#define rdma_MASK 0x00000001 3296#define rdma_WORD word3 3297 uint32_t sge_supp_len; 3298#define SLI4_PAGE_SIZE 4096 3299 uint32_t word5; 3300#define if_page_sz_SHIFT 0 3301#define if_page_sz_MASK 0x0000ffff 3302#define if_page_sz_WORD word5 3303#define loopbk_scope_SHIFT 24 3304#define loopbk_scope_MASK 0x0000000f 3305#define loopbk_scope_WORD word5 3306#define rq_db_window_SHIFT 28 3307#define rq_db_window_MASK 0x0000000f 3308#define rq_db_window_WORD word5 3309 uint32_t word6; 3310#define eq_pages_SHIFT 0 3311#define eq_pages_MASK 0x0000000f 3312#define eq_pages_WORD word6 3313#define eqe_size_SHIFT 8 3314#define eqe_size_MASK 0x000000ff 3315#define eqe_size_WORD word6 3316 uint32_t word7; 3317#define cq_pages_SHIFT 0 3318#define cq_pages_MASK 0x0000000f 3319#define cq_pages_WORD word7 3320#define cqe_size_SHIFT 8 3321#define cqe_size_MASK 0x000000ff 3322#define cqe_size_WORD word7 3323 uint32_t word8; 3324#define mq_pages_SHIFT 0 3325#define mq_pages_MASK 0x0000000f 3326#define mq_pages_WORD word8 3327#define mqe_size_SHIFT 8 3328#define mqe_size_MASK 0x000000ff 3329#define mqe_size_WORD word8 3330#define mq_elem_cnt_SHIFT 16 3331#define mq_elem_cnt_MASK 0x000000ff 3332#define mq_elem_cnt_WORD word8 3333 uint32_t word9; 3334#define wq_pages_SHIFT 0 3335#define wq_pages_MASK 0x0000ffff 3336#define wq_pages_WORD word9 3337#define wqe_size_SHIFT 8 3338#define wqe_size_MASK 0x000000ff 3339#define wqe_size_WORD word9 3340 uint32_t word10; 3341#define rq_pages_SHIFT 0 3342#define rq_pages_MASK 0x0000ffff 3343#define rq_pages_WORD word10 3344#define rqe_size_SHIFT 8 3345#define rqe_size_MASK 0x000000ff 3346#define rqe_size_WORD word10 3347 uint32_t word11; 3348#define hdr_pages_SHIFT 0 3349#define hdr_pages_MASK 0x0000000f 3350#define hdr_pages_WORD word11 3351#define hdr_size_SHIFT 8 3352#define hdr_size_MASK 0x0000000f 3353#define hdr_size_WORD word11 3354#define hdr_pp_align_SHIFT 16 3355#define hdr_pp_align_MASK 0x0000ffff 3356#define hdr_pp_align_WORD word11 3357 uint32_t word12; 3358#define sgl_pages_SHIFT 0 3359#define sgl_pages_MASK 0x0000000f 3360#define sgl_pages_WORD word12 3361#define sgl_pp_align_SHIFT 16 3362#define sgl_pp_align_MASK 0x0000ffff 3363#define sgl_pp_align_WORD word12 3364 uint32_t rsvd_13_63[51]; 3365}; 3366#define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 3367 &(~((SLI4_PAGE_SIZE)-1))) 3368 3369struct lpfc_sli4_parameters { 3370 uint32_t word0; 3371#define cfg_prot_type_SHIFT 0 3372#define cfg_prot_type_MASK 0x000000FF 3373#define cfg_prot_type_WORD word0 3374 uint32_t word1; 3375#define cfg_ft_SHIFT 0 3376#define cfg_ft_MASK 0x00000001 3377#define cfg_ft_WORD word1 3378#define cfg_sli_rev_SHIFT 4 3379#define cfg_sli_rev_MASK 0x0000000f 3380#define cfg_sli_rev_WORD word1 3381#define cfg_sli_family_SHIFT 8 3382#define cfg_sli_family_MASK 0x0000000f 3383#define cfg_sli_family_WORD word1 3384#define cfg_if_type_SHIFT 12 3385#define cfg_if_type_MASK 0x0000000f 3386#define cfg_if_type_WORD word1 3387#define cfg_sli_hint_1_SHIFT 16 3388#define cfg_sli_hint_1_MASK 0x000000ff 3389#define cfg_sli_hint_1_WORD word1 3390#define cfg_sli_hint_2_SHIFT 24 3391#define cfg_sli_hint_2_MASK 0x0000001f 3392#define cfg_sli_hint_2_WORD word1 3393 uint32_t word2; 3394#define cfg_eqav_SHIFT 31 3395#define cfg_eqav_MASK 0x00000001 3396#define cfg_eqav_WORD word2 3397 uint32_t word3; 3398 uint32_t word4; 3399#define cfg_cqv_SHIFT 14 3400#define cfg_cqv_MASK 0x00000003 3401#define cfg_cqv_WORD word4 3402#define cfg_cqpsize_SHIFT 16 3403#define cfg_cqpsize_MASK 0x000000ff 3404#define cfg_cqpsize_WORD word4 3405#define cfg_cqav_SHIFT 31 3406#define cfg_cqav_MASK 0x00000001 3407#define cfg_cqav_WORD word4 3408 uint32_t word5; 3409 uint32_t word6; 3410#define cfg_mqv_SHIFT 14 3411#define cfg_mqv_MASK 0x00000003 3412#define cfg_mqv_WORD word6 3413 uint32_t word7; 3414 uint32_t word8; 3415#define cfg_wqpcnt_SHIFT 0 3416#define cfg_wqpcnt_MASK 0x0000000f 3417#define cfg_wqpcnt_WORD word8 3418#define cfg_wqsize_SHIFT 8 3419#define cfg_wqsize_MASK 0x0000000f 3420#define cfg_wqsize_WORD word8 3421#define cfg_wqv_SHIFT 14 3422#define cfg_wqv_MASK 0x00000003 3423#define cfg_wqv_WORD word8 3424#define cfg_wqpsize_SHIFT 16 3425#define cfg_wqpsize_MASK 0x000000ff 3426#define cfg_wqpsize_WORD word8 3427 uint32_t word9; 3428 uint32_t word10; 3429#define cfg_rqv_SHIFT 14 3430#define cfg_rqv_MASK 0x00000003 3431#define cfg_rqv_WORD word10 3432 uint32_t word11; 3433#define cfg_rq_db_window_SHIFT 28 3434#define cfg_rq_db_window_MASK 0x0000000f 3435#define cfg_rq_db_window_WORD word11 3436 uint32_t word12; 3437#define cfg_fcoe_SHIFT 0 3438#define cfg_fcoe_MASK 0x00000001 3439#define cfg_fcoe_WORD word12 3440#define cfg_ext_SHIFT 1 3441#define cfg_ext_MASK 0x00000001 3442#define cfg_ext_WORD word12 3443#define cfg_hdrr_SHIFT 2 3444#define cfg_hdrr_MASK 0x00000001 3445#define cfg_hdrr_WORD word12 3446#define cfg_phwq_SHIFT 15 3447#define cfg_phwq_MASK 0x00000001 3448#define cfg_phwq_WORD word12 3449#define cfg_oas_SHIFT 25 3450#define cfg_oas_MASK 0x00000001 3451#define cfg_oas_WORD word12 3452#define cfg_loopbk_scope_SHIFT 28 3453#define cfg_loopbk_scope_MASK 0x0000000f 3454#define cfg_loopbk_scope_WORD word12 3455 uint32_t sge_supp_len; 3456 uint32_t word14; 3457#define cfg_sgl_page_cnt_SHIFT 0 3458#define cfg_sgl_page_cnt_MASK 0x0000000f 3459#define cfg_sgl_page_cnt_WORD word14 3460#define cfg_sgl_page_size_SHIFT 8 3461#define cfg_sgl_page_size_MASK 0x000000ff 3462#define cfg_sgl_page_size_WORD word14 3463#define cfg_sgl_pp_align_SHIFT 16 3464#define cfg_sgl_pp_align_MASK 0x000000ff 3465#define cfg_sgl_pp_align_WORD word14 3466 uint32_t word15; 3467 uint32_t word16; 3468 uint32_t word17; 3469 uint32_t word18; 3470 uint32_t word19; 3471#define cfg_ext_embed_cb_SHIFT 0 3472#define cfg_ext_embed_cb_MASK 0x00000001 3473#define cfg_ext_embed_cb_WORD word19 3474#define cfg_mds_diags_SHIFT 1 3475#define cfg_mds_diags_MASK 0x00000001 3476#define cfg_mds_diags_WORD word19 3477#define cfg_nvme_SHIFT 3 3478#define cfg_nvme_MASK 0x00000001 3479#define cfg_nvme_WORD word19 3480#define cfg_xib_SHIFT 4 3481#define cfg_xib_MASK 0x00000001 3482#define cfg_xib_WORD word19 3483#define cfg_xpsgl_SHIFT 6 3484#define cfg_xpsgl_MASK 0x00000001 3485#define cfg_xpsgl_WORD word19 3486#define cfg_eqdr_SHIFT 8 3487#define cfg_eqdr_MASK 0x00000001 3488#define cfg_eqdr_WORD word19 3489#define cfg_nosr_SHIFT 9 3490#define cfg_nosr_MASK 0x00000001 3491#define cfg_nosr_WORD word19 3492 3493#define cfg_bv1s_SHIFT 10 3494#define cfg_bv1s_MASK 0x00000001 3495#define cfg_bv1s_WORD word19 3496#define cfg_pvl_SHIFT 13 3497#define cfg_pvl_MASK 0x00000001 3498#define cfg_pvl_WORD word19 3499 3500#define cfg_nsler_SHIFT 12 3501#define cfg_nsler_MASK 0x00000001 3502#define cfg_nsler_WORD word19 3503 3504 uint32_t word20; 3505#define cfg_max_tow_xri_SHIFT 0 3506#define cfg_max_tow_xri_MASK 0x0000ffff 3507#define cfg_max_tow_xri_WORD word20 3508 3509 uint32_t word21; 3510#define cfg_mib_bde_cnt_SHIFT 16 3511#define cfg_mib_bde_cnt_MASK 0x000000ff 3512#define cfg_mib_bde_cnt_WORD word21 3513#define cfg_mi_ver_SHIFT 0 3514#define cfg_mi_ver_MASK 0x0000ffff 3515#define cfg_mi_ver_WORD word21 3516 uint32_t mib_size; 3517 uint32_t word23; /* RESERVED */ 3518 3519 uint32_t word24; 3520#define cfg_frag_field_offset_SHIFT 0 3521#define cfg_frag_field_offset_MASK 0x0000ffff 3522#define cfg_frag_field_offset_WORD word24 3523 3524#define cfg_frag_field_size_SHIFT 16 3525#define cfg_frag_field_size_MASK 0x0000ffff 3526#define cfg_frag_field_size_WORD word24 3527 3528 uint32_t word25; 3529#define cfg_sgl_field_offset_SHIFT 0 3530#define cfg_sgl_field_offset_MASK 0x0000ffff 3531#define cfg_sgl_field_offset_WORD word25 3532 3533#define cfg_sgl_field_size_SHIFT 16 3534#define cfg_sgl_field_size_MASK 0x0000ffff 3535#define cfg_sgl_field_size_WORD word25 3536 3537 uint32_t word26; /* Chain SGE initial value LOW */ 3538 uint32_t word27; /* Chain SGE initial value HIGH */ 3539#define LPFC_NODELAY_MAX_IO 32 3540}; 3541 3542#define LPFC_SET_UE_RECOVERY 0x10 3543#define LPFC_SET_MDS_DIAGS 0x12 3544#define LPFC_SET_DUAL_DUMP 0x1e 3545struct lpfc_mbx_set_feature { 3546 struct mbox_header header; 3547 uint32_t feature; 3548 uint32_t param_len; 3549 uint32_t word6; 3550#define lpfc_mbx_set_feature_UER_SHIFT 0 3551#define lpfc_mbx_set_feature_UER_MASK 0x00000001 3552#define lpfc_mbx_set_feature_UER_WORD word6 3553#define lpfc_mbx_set_feature_mds_SHIFT 2 3554#define lpfc_mbx_set_feature_mds_MASK 0x00000001 3555#define lpfc_mbx_set_feature_mds_WORD word6 3556#define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1 3557#define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001 3558#define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6 3559#define lpfc_mbx_set_feature_dd_SHIFT 0 3560#define lpfc_mbx_set_feature_dd_MASK 0x00000001 3561#define lpfc_mbx_set_feature_dd_WORD word6 3562#define lpfc_mbx_set_feature_ddquery_SHIFT 1 3563#define lpfc_mbx_set_feature_ddquery_MASK 0x00000001 3564#define lpfc_mbx_set_feature_ddquery_WORD word6 3565#define LPFC_DISABLE_DUAL_DUMP 0 3566#define LPFC_ENABLE_DUAL_DUMP 1 3567#define LPFC_QUERY_OP_DUAL_DUMP 2 3568 uint32_t word7; 3569#define lpfc_mbx_set_feature_UERP_SHIFT 0 3570#define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff 3571#define lpfc_mbx_set_feature_UERP_WORD word7 3572#define lpfc_mbx_set_feature_UESR_SHIFT 16 3573#define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff 3574#define lpfc_mbx_set_feature_UESR_WORD word7 3575}; 3576 3577 3578#define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2 3579struct lpfc_mbx_set_host_data { 3580#define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48 3581 struct mbox_header header; 3582 uint32_t param_id; 3583 uint32_t param_len; 3584 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE]; 3585}; 3586 3587struct lpfc_mbx_set_trunk_mode { 3588 struct mbox_header header; 3589 uint32_t word0; 3590#define lpfc_mbx_set_trunk_mode_WORD word0 3591#define lpfc_mbx_set_trunk_mode_SHIFT 0 3592#define lpfc_mbx_set_trunk_mode_MASK 0xFF 3593 uint32_t word1; 3594 uint32_t word2; 3595}; 3596 3597struct lpfc_mbx_get_sli4_parameters { 3598 struct mbox_header header; 3599 struct lpfc_sli4_parameters sli4_parameters; 3600}; 3601 3602struct lpfc_rscr_desc_generic { 3603#define LPFC_RSRC_DESC_WSIZE 22 3604 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 3605}; 3606 3607struct lpfc_rsrc_desc_pcie { 3608 uint32_t word0; 3609#define lpfc_rsrc_desc_pcie_type_SHIFT 0 3610#define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 3611#define lpfc_rsrc_desc_pcie_type_WORD word0 3612#define LPFC_RSRC_DESC_TYPE_PCIE 0x40 3613#define lpfc_rsrc_desc_pcie_length_SHIFT 8 3614#define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 3615#define lpfc_rsrc_desc_pcie_length_WORD word0 3616 uint32_t word1; 3617#define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 3618#define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 3619#define lpfc_rsrc_desc_pcie_pfnum_WORD word1 3620 uint32_t reserved; 3621 uint32_t word3; 3622#define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 3623#define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 3624#define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 3625#define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 3626#define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 3627#define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 3628#define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 3629#define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 3630#define lpfc_rsrc_desc_pcie_pf_type_WORD word3 3631 uint32_t word4; 3632#define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 3633#define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 3634#define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 3635}; 3636 3637struct lpfc_rsrc_desc_fcfcoe { 3638 uint32_t word0; 3639#define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 3640#define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 3641#define lpfc_rsrc_desc_fcfcoe_type_WORD word0 3642#define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 3643#define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 3644#define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 3645#define lpfc_rsrc_desc_fcfcoe_length_WORD word0 3646#define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 3647#define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 3648#define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 3649 uint32_t word1; 3650#define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 3651#define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 3652#define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 3653#define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 3654#define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 3655#define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 3656 uint32_t word2; 3657#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 3658#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 3659#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 3660#define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 3661#define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 3662#define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 3663 uint32_t word3; 3664#define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 3665#define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 3666#define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 3667#define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 3668#define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 3669#define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 3670 uint32_t word4; 3671#define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 3672#define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 3673#define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 3674#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 3675#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 3676#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 3677 uint32_t word5; 3678#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 3679#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 3680#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 3681#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 3682#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 3683#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 3684 uint32_t word6; 3685 uint32_t word7; 3686 uint32_t word8; 3687 uint32_t word9; 3688 uint32_t word10; 3689 uint32_t word11; 3690 uint32_t word12; 3691 uint32_t word13; 3692#define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 3693#define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 3694#define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 3695#define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 3696#define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 3697#define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 3698#define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 3699#define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 3700#define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 3701#define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 3702#define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 3703#define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 3704#define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 3705#define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 3706#define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 3707/* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 3708 uint32_t bw_min; 3709 uint32_t bw_max; 3710 uint32_t iops_min; 3711 uint32_t iops_max; 3712 uint32_t reserved[4]; 3713}; 3714 3715struct lpfc_func_cfg { 3716#define LPFC_RSRC_DESC_MAX_NUM 2 3717 uint32_t rsrc_desc_count; 3718 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3719}; 3720 3721struct lpfc_mbx_get_func_cfg { 3722 struct mbox_header header; 3723#define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3724#define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3725#define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3726 struct lpfc_func_cfg func_cfg; 3727}; 3728 3729struct lpfc_prof_cfg { 3730#define LPFC_RSRC_DESC_MAX_NUM 2 3731 uint32_t rsrc_desc_count; 3732 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3733}; 3734 3735struct lpfc_mbx_get_prof_cfg { 3736 struct mbox_header header; 3737#define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3738#define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3739#define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3740 union { 3741 struct { 3742 uint32_t word10; 3743#define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 3744#define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 3745#define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 3746#define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 3747#define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 3748#define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 3749 } request; 3750 struct { 3751 struct lpfc_prof_cfg prof_cfg; 3752 } response; 3753 } u; 3754}; 3755 3756struct lpfc_controller_attribute { 3757 uint32_t version_string[8]; 3758 uint32_t manufacturer_name[8]; 3759 uint32_t supported_modes; 3760 uint32_t word17; 3761#define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 3762#define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 3763#define lpfc_cntl_attr_eprom_ver_lo_WORD word17 3764#define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 3765#define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 3766#define lpfc_cntl_attr_eprom_ver_hi_WORD word17 3767 uint32_t mbx_da_struct_ver; 3768 uint32_t ep_fw_da_struct_ver; 3769 uint32_t ncsi_ver_str[3]; 3770 uint32_t dflt_ext_timeout; 3771 uint32_t model_number[8]; 3772 uint32_t description[16]; 3773 uint32_t serial_number[8]; 3774 uint32_t ip_ver_str[8]; 3775 uint32_t fw_ver_str[8]; 3776 uint32_t bios_ver_str[8]; 3777 uint32_t redboot_ver_str[8]; 3778 uint32_t driver_ver_str[8]; 3779 uint32_t flash_fw_ver_str[8]; 3780 uint32_t functionality; 3781 uint32_t word105; 3782#define lpfc_cntl_attr_max_cbd_len_SHIFT 0 3783#define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 3784#define lpfc_cntl_attr_max_cbd_len_WORD word105 3785#define lpfc_cntl_attr_asic_rev_SHIFT 16 3786#define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 3787#define lpfc_cntl_attr_asic_rev_WORD word105 3788#define lpfc_cntl_attr_gen_guid0_SHIFT 24 3789#define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 3790#define lpfc_cntl_attr_gen_guid0_WORD word105 3791 uint32_t gen_guid1_12[3]; 3792 uint32_t word109; 3793#define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 3794#define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 3795#define lpfc_cntl_attr_gen_guid13_14_WORD word109 3796#define lpfc_cntl_attr_gen_guid15_SHIFT 16 3797#define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 3798#define lpfc_cntl_attr_gen_guid15_WORD word109 3799#define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 3800#define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 3801#define lpfc_cntl_attr_hba_port_cnt_WORD word109 3802 uint32_t word110; 3803#define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 3804#define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 3805#define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 3806#define lpfc_cntl_attr_multi_func_dev_SHIFT 24 3807#define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 3808#define lpfc_cntl_attr_multi_func_dev_WORD word110 3809 uint32_t word111; 3810#define lpfc_cntl_attr_cache_valid_SHIFT 0 3811#define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 3812#define lpfc_cntl_attr_cache_valid_WORD word111 3813#define lpfc_cntl_attr_hba_status_SHIFT 8 3814#define lpfc_cntl_attr_hba_status_MASK 0x000000ff 3815#define lpfc_cntl_attr_hba_status_WORD word111 3816#define lpfc_cntl_attr_max_domain_SHIFT 16 3817#define lpfc_cntl_attr_max_domain_MASK 0x000000ff 3818#define lpfc_cntl_attr_max_domain_WORD word111 3819#define lpfc_cntl_attr_lnk_numb_SHIFT 24 3820#define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 3821#define lpfc_cntl_attr_lnk_numb_WORD word111 3822#define lpfc_cntl_attr_lnk_type_SHIFT 30 3823#define lpfc_cntl_attr_lnk_type_MASK 0x00000003 3824#define lpfc_cntl_attr_lnk_type_WORD word111 3825 uint32_t fw_post_status; 3826 uint32_t hba_mtu[8]; 3827 uint32_t word121; 3828 uint32_t reserved1[3]; 3829 uint32_t word125; 3830#define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 3831#define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 3832#define lpfc_cntl_attr_pci_vendor_id_WORD word125 3833#define lpfc_cntl_attr_pci_device_id_SHIFT 16 3834#define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 3835#define lpfc_cntl_attr_pci_device_id_WORD word125 3836 uint32_t word126; 3837#define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 3838#define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 3839#define lpfc_cntl_attr_pci_subvdr_id_WORD word126 3840#define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 3841#define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 3842#define lpfc_cntl_attr_pci_subsys_id_WORD word126 3843 uint32_t word127; 3844#define lpfc_cntl_attr_pci_bus_num_SHIFT 0 3845#define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 3846#define lpfc_cntl_attr_pci_bus_num_WORD word127 3847#define lpfc_cntl_attr_pci_dev_num_SHIFT 8 3848#define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 3849#define lpfc_cntl_attr_pci_dev_num_WORD word127 3850#define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 3851#define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 3852#define lpfc_cntl_attr_pci_fnc_num_WORD word127 3853#define lpfc_cntl_attr_inf_type_SHIFT 24 3854#define lpfc_cntl_attr_inf_type_MASK 0x000000ff 3855#define lpfc_cntl_attr_inf_type_WORD word127 3856 uint32_t unique_id[2]; 3857 uint32_t word130; 3858#define lpfc_cntl_attr_num_netfil_SHIFT 0 3859#define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 3860#define lpfc_cntl_attr_num_netfil_WORD word130 3861 uint32_t reserved2[4]; 3862}; 3863 3864struct lpfc_mbx_get_cntl_attributes { 3865 union lpfc_sli4_cfg_shdr cfg_shdr; 3866 struct lpfc_controller_attribute cntl_attr; 3867}; 3868 3869struct lpfc_mbx_get_port_name { 3870 struct mbox_header header; 3871 union { 3872 struct { 3873 uint32_t word4; 3874#define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 3875#define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 3876#define lpfc_mbx_get_port_name_lnk_type_WORD word4 3877 } request; 3878 struct { 3879 uint32_t word4; 3880#define lpfc_mbx_get_port_name_name0_SHIFT 0 3881#define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 3882#define lpfc_mbx_get_port_name_name0_WORD word4 3883#define lpfc_mbx_get_port_name_name1_SHIFT 8 3884#define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 3885#define lpfc_mbx_get_port_name_name1_WORD word4 3886#define lpfc_mbx_get_port_name_name2_SHIFT 16 3887#define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 3888#define lpfc_mbx_get_port_name_name2_WORD word4 3889#define lpfc_mbx_get_port_name_name3_SHIFT 24 3890#define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 3891#define lpfc_mbx_get_port_name_name3_WORD word4 3892#define LPFC_LINK_NUMBER_0 0 3893#define LPFC_LINK_NUMBER_1 1 3894#define LPFC_LINK_NUMBER_2 2 3895#define LPFC_LINK_NUMBER_3 3 3896 } response; 3897 } u; 3898}; 3899 3900/* Mailbox Completion Queue Error Messages */ 3901#define MB_CQE_STATUS_SUCCESS 0x0 3902#define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 3903#define MB_CQE_STATUS_INVALID_PARAMETER 0x2 3904#define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 3905#define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 3906#define MB_CQE_STATUS_DMA_FAILED 0x5 3907 3908#define LPFC_MBX_WR_CONFIG_MAX_BDE 1 3909struct lpfc_mbx_wr_object { 3910 struct mbox_header header; 3911 union { 3912 struct { 3913 uint32_t word4; 3914#define lpfc_wr_object_eof_SHIFT 31 3915#define lpfc_wr_object_eof_MASK 0x00000001 3916#define lpfc_wr_object_eof_WORD word4 3917#define lpfc_wr_object_eas_SHIFT 29 3918#define lpfc_wr_object_eas_MASK 0x00000001 3919#define lpfc_wr_object_eas_WORD word4 3920#define lpfc_wr_object_write_length_SHIFT 0 3921#define lpfc_wr_object_write_length_MASK 0x00FFFFFF 3922#define lpfc_wr_object_write_length_WORD word4 3923 uint32_t write_offset; 3924 uint32_t object_name[26]; 3925 uint32_t bde_count; 3926 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 3927 } request; 3928 struct { 3929 uint32_t actual_write_length; 3930 uint32_t word5; 3931#define lpfc_wr_object_change_status_SHIFT 0 3932#define lpfc_wr_object_change_status_MASK 0x000000FF 3933#define lpfc_wr_object_change_status_WORD word5 3934#define LPFC_CHANGE_STATUS_NO_RESET_NEEDED 0x00 3935#define LPFC_CHANGE_STATUS_PHYS_DEV_RESET 0x01 3936#define LPFC_CHANGE_STATUS_FW_RESET 0x02 3937#define LPFC_CHANGE_STATUS_PORT_MIGRATION 0x04 3938#define LPFC_CHANGE_STATUS_PCI_RESET 0x05 3939#define lpfc_wr_object_csf_SHIFT 8 3940#define lpfc_wr_object_csf_MASK 0x00000001 3941#define lpfc_wr_object_csf_WORD word5 3942 } response; 3943 } u; 3944}; 3945 3946/* mailbox queue entry structure */ 3947struct lpfc_mqe { 3948 uint32_t word0; 3949#define lpfc_mqe_status_SHIFT 16 3950#define lpfc_mqe_status_MASK 0x0000FFFF 3951#define lpfc_mqe_status_WORD word0 3952#define lpfc_mqe_command_SHIFT 8 3953#define lpfc_mqe_command_MASK 0x000000FF 3954#define lpfc_mqe_command_WORD word0 3955 union { 3956 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 3957 /* sli4 mailbox commands */ 3958 struct lpfc_mbx_sli4_config sli4_config; 3959 struct lpfc_mbx_init_vfi init_vfi; 3960 struct lpfc_mbx_reg_vfi reg_vfi; 3961 struct lpfc_mbx_reg_vfi unreg_vfi; 3962 struct lpfc_mbx_init_vpi init_vpi; 3963 struct lpfc_mbx_resume_rpi resume_rpi; 3964 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 3965 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 3966 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 3967 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 3968 struct lpfc_mbx_reg_fcfi reg_fcfi; 3969 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq; 3970 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 3971 struct lpfc_mbx_mq_create mq_create; 3972 struct lpfc_mbx_mq_create_ext mq_create_ext; 3973 struct lpfc_mbx_eq_create eq_create; 3974 struct lpfc_mbx_modify_eq_delay eq_delay; 3975 struct lpfc_mbx_cq_create cq_create; 3976 struct lpfc_mbx_cq_create_set cq_create_set; 3977 struct lpfc_mbx_wq_create wq_create; 3978 struct lpfc_mbx_rq_create rq_create; 3979 struct lpfc_mbx_rq_create_v2 rq_create_v2; 3980 struct lpfc_mbx_mq_destroy mq_destroy; 3981 struct lpfc_mbx_eq_destroy eq_destroy; 3982 struct lpfc_mbx_cq_destroy cq_destroy; 3983 struct lpfc_mbx_wq_destroy wq_destroy; 3984 struct lpfc_mbx_rq_destroy rq_destroy; 3985 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3986 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3987 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 3988 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 3989 struct lpfc_mbx_nembed_cmd nembed_cmd; 3990 struct lpfc_mbx_read_rev read_rev; 3991 struct lpfc_mbx_read_vpi read_vpi; 3992 struct lpfc_mbx_read_config rd_config; 3993 struct lpfc_mbx_request_features req_ftrs; 3994 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 3995 struct lpfc_mbx_query_fw_config query_fw_cfg; 3996 struct lpfc_mbx_set_beacon_config beacon_config; 3997 struct lpfc_mbx_supp_pages supp_pages; 3998 struct lpfc_mbx_pc_sli4_params sli4_params; 3999 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 4000 struct lpfc_mbx_set_link_diag_state link_diag_state;
4001 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 4002 struct lpfc_mbx_run_link_diag_test link_diag_test; 4003 struct lpfc_mbx_get_func_cfg get_func_cfg; 4004 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 4005 struct lpfc_mbx_wr_object wr_object; 4006 struct lpfc_mbx_get_port_name get_port_name; 4007 struct lpfc_mbx_set_feature set_feature; 4008 struct lpfc_mbx_memory_dump_type3 mem_dump_type3; 4009 struct lpfc_mbx_set_host_data set_host_data; 4010 struct lpfc_mbx_set_trunk_mode set_trunk_mode; 4011 struct lpfc_mbx_nop nop; 4012 struct lpfc_mbx_set_ras_fwlog ras_fwlog; 4013 } un; 4014}; 4015 4016struct lpfc_mcqe { 4017 uint32_t word0; 4018#define lpfc_mcqe_status_SHIFT 0 4019#define lpfc_mcqe_status_MASK 0x0000FFFF 4020#define lpfc_mcqe_status_WORD word0 4021#define lpfc_mcqe_ext_status_SHIFT 16 4022#define lpfc_mcqe_ext_status_MASK 0x0000FFFF 4023#define lpfc_mcqe_ext_status_WORD word0 4024 uint32_t mcqe_tag0; 4025 uint32_t mcqe_tag1; 4026 uint32_t trailer; 4027#define lpfc_trailer_valid_SHIFT 31 4028#define lpfc_trailer_valid_MASK 0x00000001 4029#define lpfc_trailer_valid_WORD trailer 4030#define lpfc_trailer_async_SHIFT 30 4031#define lpfc_trailer_async_MASK 0x00000001 4032#define lpfc_trailer_async_WORD trailer 4033#define lpfc_trailer_hpi_SHIFT 29 4034#define lpfc_trailer_hpi_MASK 0x00000001 4035#define lpfc_trailer_hpi_WORD trailer 4036#define lpfc_trailer_completed_SHIFT 28 4037#define lpfc_trailer_completed_MASK 0x00000001 4038#define lpfc_trailer_completed_WORD trailer 4039#define lpfc_trailer_consumed_SHIFT 27 4040#define lpfc_trailer_consumed_MASK 0x00000001 4041#define lpfc_trailer_consumed_WORD trailer 4042#define lpfc_trailer_type_SHIFT 16 4043#define lpfc_trailer_type_MASK 0x000000FF 4044#define lpfc_trailer_type_WORD trailer 4045#define lpfc_trailer_code_SHIFT 8 4046#define lpfc_trailer_code_MASK 0x000000FF 4047#define lpfc_trailer_code_WORD trailer 4048#define LPFC_TRAILER_CODE_LINK 0x1 4049#define LPFC_TRAILER_CODE_FCOE 0x2 4050#define LPFC_TRAILER_CODE_DCBX 0x3 4051#define LPFC_TRAILER_CODE_GRP5 0x5 4052#define LPFC_TRAILER_CODE_FC 0x10 4053#define LPFC_TRAILER_CODE_SLI 0x11 4054}; 4055 4056struct lpfc_acqe_link { 4057 uint32_t word0; 4058#define lpfc_acqe_link_speed_SHIFT 24 4059#define lpfc_acqe_link_speed_MASK 0x000000FF 4060#define lpfc_acqe_link_speed_WORD word0 4061#define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 4062#define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 4063#define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 4064#define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 4065#define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 4066#define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5 4067#define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6 4068#define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7 4069#define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8 4070#define lpfc_acqe_link_duplex_SHIFT 16 4071#define lpfc_acqe_link_duplex_MASK 0x000000FF 4072#define lpfc_acqe_link_duplex_WORD word0 4073#define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 4074#define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 4075#define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 4076#define lpfc_acqe_link_status_SHIFT 8 4077#define lpfc_acqe_link_status_MASK 0x000000FF 4078#define lpfc_acqe_link_status_WORD word0 4079#define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 4080#define LPFC_ASYNC_LINK_STATUS_UP 0x1 4081#define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 4082#define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 4083#define lpfc_acqe_link_type_SHIFT 6 4084#define lpfc_acqe_link_type_MASK 0x00000003 4085#define lpfc_acqe_link_type_WORD word0 4086#define lpfc_acqe_link_number_SHIFT 0 4087#define lpfc_acqe_link_number_MASK 0x0000003F 4088#define lpfc_acqe_link_number_WORD word0 4089 uint32_t word1; 4090#define lpfc_acqe_link_fault_SHIFT 0 4091#define lpfc_acqe_link_fault_MASK 0x000000FF 4092#define lpfc_acqe_link_fault_WORD word1 4093#define LPFC_ASYNC_LINK_FAULT_NONE 0x0 4094#define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 4095#define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 4096#define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3 4097#define lpfc_acqe_logical_link_speed_SHIFT 16 4098#define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 4099#define lpfc_acqe_logical_link_speed_WORD word1 4100 uint32_t event_tag; 4101 uint32_t trailer; 4102#define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 4103#define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 4104}; 4105 4106struct lpfc_acqe_fip { 4107 uint32_t index; 4108 uint32_t word1; 4109#define lpfc_acqe_fip_fcf_count_SHIFT 0 4110#define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 4111#define lpfc_acqe_fip_fcf_count_WORD word1 4112#define lpfc_acqe_fip_event_type_SHIFT 16 4113#define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 4114#define lpfc_acqe_fip_event_type_WORD word1 4115 uint32_t event_tag; 4116 uint32_t trailer; 4117#define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 4118#define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 4119#define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 4120#define LPFC_FIP_EVENT_TYPE_CVL 0x4 4121#define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 4122}; 4123 4124struct lpfc_acqe_dcbx { 4125 uint32_t tlv_ttl; 4126 uint32_t reserved; 4127 uint32_t event_tag; 4128 uint32_t trailer; 4129}; 4130 4131struct lpfc_acqe_grp5 { 4132 uint32_t word0; 4133#define lpfc_acqe_grp5_type_SHIFT 6 4134#define lpfc_acqe_grp5_type_MASK 0x00000003 4135#define lpfc_acqe_grp5_type_WORD word0 4136#define lpfc_acqe_grp5_number_SHIFT 0 4137#define lpfc_acqe_grp5_number_MASK 0x0000003F 4138#define lpfc_acqe_grp5_number_WORD word0 4139 uint32_t word1; 4140#define lpfc_acqe_grp5_llink_spd_SHIFT 16 4141#define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 4142#define lpfc_acqe_grp5_llink_spd_WORD word1 4143 uint32_t event_tag; 4144 uint32_t trailer; 4145}; 4146 4147extern const char *const trunk_errmsg[]; 4148 4149struct lpfc_acqe_fc_la { 4150 uint32_t word0; 4151#define lpfc_acqe_fc_la_speed_SHIFT 24 4152#define lpfc_acqe_fc_la_speed_MASK 0x000000FF 4153#define lpfc_acqe_fc_la_speed_WORD word0 4154#define LPFC_FC_LA_SPEED_UNKNOWN 0x0 4155#define LPFC_FC_LA_SPEED_1G 0x1 4156#define LPFC_FC_LA_SPEED_2G 0x2 4157#define LPFC_FC_LA_SPEED_4G 0x4 4158#define LPFC_FC_LA_SPEED_8G 0x8 4159#define LPFC_FC_LA_SPEED_10G 0xA 4160#define LPFC_FC_LA_SPEED_16G 0x10 4161#define LPFC_FC_LA_SPEED_32G 0x20 4162#define LPFC_FC_LA_SPEED_64G 0x21 4163#define LPFC_FC_LA_SPEED_128G 0x22 4164#define LPFC_FC_LA_SPEED_256G 0x23 4165#define lpfc_acqe_fc_la_topology_SHIFT 16 4166#define lpfc_acqe_fc_la_topology_MASK 0x000000FF 4167#define lpfc_acqe_fc_la_topology_WORD word0 4168#define LPFC_FC_LA_TOP_UNKOWN 0x0 4169#define LPFC_FC_LA_TOP_P2P 0x1 4170#define LPFC_FC_LA_TOP_FCAL 0x2 4171#define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 4172#define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 4173#define lpfc_acqe_fc_la_att_type_SHIFT 8 4174#define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 4175#define lpfc_acqe_fc_la_att_type_WORD word0 4176#define LPFC_FC_LA_TYPE_LINK_UP 0x1 4177#define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 4178#define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 4179#define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4 4180#define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5 4181#define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6 4182#define LPFC_FC_LA_TYPE_TRUNKING_EVENT 0x7 4183#define lpfc_acqe_fc_la_port_type_SHIFT 6 4184#define lpfc_acqe_fc_la_port_type_MASK 0x00000003 4185#define lpfc_acqe_fc_la_port_type_WORD word0 4186#define LPFC_LINK_TYPE_ETHERNET 0x0 4187#define LPFC_LINK_TYPE_FC 0x1 4188#define lpfc_acqe_fc_la_port_number_SHIFT 0 4189#define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 4190#define lpfc_acqe_fc_la_port_number_WORD word0 4191 4192/* Attention Type is 0x07 (Trunking Event) word0 */ 4193#define lpfc_acqe_fc_la_trunk_link_status_port0_SHIFT 16 4194#define lpfc_acqe_fc_la_trunk_link_status_port0_MASK 0x0000001 4195#define lpfc_acqe_fc_la_trunk_link_status_port0_WORD word0 4196#define lpfc_acqe_fc_la_trunk_link_status_port1_SHIFT 17 4197#define lpfc_acqe_fc_la_trunk_link_status_port1_MASK 0x0000001 4198#define lpfc_acqe_fc_la_trunk_link_status_port1_WORD word0 4199#define lpfc_acqe_fc_la_trunk_link_status_port2_SHIFT 18 4200#define lpfc_acqe_fc_la_trunk_link_status_port2_MASK 0x0000001 4201#define lpfc_acqe_fc_la_trunk_link_status_port2_WORD word0 4202#define lpfc_acqe_fc_la_trunk_link_status_port3_SHIFT 19 4203#define lpfc_acqe_fc_la_trunk_link_status_port3_MASK 0x0000001 4204#define lpfc_acqe_fc_la_trunk_link_status_port3_WORD word0 4205#define lpfc_acqe_fc_la_trunk_config_port0_SHIFT 20 4206#define lpfc_acqe_fc_la_trunk_config_port0_MASK 0x0000001 4207#define lpfc_acqe_fc_la_trunk_config_port0_WORD word0 4208#define lpfc_acqe_fc_la_trunk_config_port1_SHIFT 21 4209#define lpfc_acqe_fc_la_trunk_config_port1_MASK 0x0000001 4210#define lpfc_acqe_fc_la_trunk_config_port1_WORD word0 4211#define lpfc_acqe_fc_la_trunk_config_port2_SHIFT 22 4212#define lpfc_acqe_fc_la_trunk_config_port2_MASK 0x0000001 4213#define lpfc_acqe_fc_la_trunk_config_port2_WORD word0 4214#define lpfc_acqe_fc_la_trunk_config_port3_SHIFT 23 4215#define lpfc_acqe_fc_la_trunk_config_port3_MASK 0x0000001 4216#define lpfc_acqe_fc_la_trunk_config_port3_WORD word0 4217 uint32_t word1; 4218#define lpfc_acqe_fc_la_llink_spd_SHIFT 16 4219#define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 4220#define lpfc_acqe_fc_la_llink_spd_WORD word1 4221#define lpfc_acqe_fc_la_fault_SHIFT 0 4222#define lpfc_acqe_fc_la_fault_MASK 0x000000FF 4223#define lpfc_acqe_fc_la_fault_WORD word1 4224#define lpfc_acqe_fc_la_trunk_fault_SHIFT 0 4225#define lpfc_acqe_fc_la_trunk_fault_MASK 0x0000000F 4226#define lpfc_acqe_fc_la_trunk_fault_WORD word1 4227#define lpfc_acqe_fc_la_trunk_linkmask_SHIFT 4 4228#define lpfc_acqe_fc_la_trunk_linkmask_MASK 0x000000F 4229#define lpfc_acqe_fc_la_trunk_linkmask_WORD word1 4230#define LPFC_FC_LA_FAULT_NONE 0x0 4231#define LPFC_FC_LA_FAULT_LOCAL 0x1 4232#define LPFC_FC_LA_FAULT_REMOTE 0x2 4233 uint32_t event_tag; 4234 uint32_t trailer; 4235#define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 4236#define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 4237}; 4238 4239struct lpfc_acqe_misconfigured_event { 4240 struct { 4241 uint32_t word0; 4242#define lpfc_sli_misconfigured_port0_state_SHIFT 0 4243#define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF 4244#define lpfc_sli_misconfigured_port0_state_WORD word0 4245#define lpfc_sli_misconfigured_port1_state_SHIFT 8 4246#define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF 4247#define lpfc_sli_misconfigured_port1_state_WORD word0 4248#define lpfc_sli_misconfigured_port2_state_SHIFT 16 4249#define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF 4250#define lpfc_sli_misconfigured_port2_state_WORD word0 4251#define lpfc_sli_misconfigured_port3_state_SHIFT 24 4252#define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF 4253#define lpfc_sli_misconfigured_port3_state_WORD word0 4254 uint32_t word1; 4255#define lpfc_sli_misconfigured_port0_op_SHIFT 0 4256#define lpfc_sli_misconfigured_port0_op_MASK 0x00000001 4257#define lpfc_sli_misconfigured_port0_op_WORD word1 4258#define lpfc_sli_misconfigured_port0_severity_SHIFT 1 4259#define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003 4260#define lpfc_sli_misconfigured_port0_severity_WORD word1 4261#define lpfc_sli_misconfigured_port1_op_SHIFT 8 4262#define lpfc_sli_misconfigured_port1_op_MASK 0x00000001 4263#define lpfc_sli_misconfigured_port1_op_WORD word1 4264#define lpfc_sli_misconfigured_port1_severity_SHIFT 9 4265#define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003 4266#define lpfc_sli_misconfigured_port1_severity_WORD word1 4267#define lpfc_sli_misconfigured_port2_op_SHIFT 16 4268#define lpfc_sli_misconfigured_port2_op_MASK 0x00000001 4269#define lpfc_sli_misconfigured_port2_op_WORD word1 4270#define lpfc_sli_misconfigured_port2_severity_SHIFT 17 4271#define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003 4272#define lpfc_sli_misconfigured_port2_severity_WORD word1 4273#define lpfc_sli_misconfigured_port3_op_SHIFT 24 4274#define lpfc_sli_misconfigured_port3_op_MASK 0x00000001 4275#define lpfc_sli_misconfigured_port3_op_WORD word1 4276#define lpfc_sli_misconfigured_port3_severity_SHIFT 25 4277#define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003 4278#define lpfc_sli_misconfigured_port3_severity_WORD word1 4279 } theEvent; 4280#define LPFC_SLI_EVENT_STATUS_VALID 0x00 4281#define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 4282#define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 4283#define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 4284#define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04 4285#define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05 4286}; 4287 4288struct lpfc_acqe_sli { 4289 uint32_t event_data1; 4290 uint32_t event_data2; 4291 uint32_t reserved; 4292 uint32_t trailer; 4293#define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 4294#define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 4295#define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 4296#define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 4297#define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 4298#define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 4299#define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA 4300#define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN 0xF 4301#define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE 0x10 4302}; 4303 4304/* 4305 * Define the bootstrap mailbox (bmbx) region used to communicate 4306 * mailbox command between the host and port. The mailbox consists 4307 * of a payload area of 256 bytes and a completion queue of length 4308 * 16 bytes. 4309 */ 4310struct lpfc_bmbx_create { 4311 struct lpfc_mqe mqe; 4312 struct lpfc_mcqe mcqe; 4313}; 4314 4315#define SGL_ALIGN_SZ 64 4316#define SGL_PAGE_SIZE 4096 4317/* align SGL addr on a size boundary - adjust address up */ 4318#define NO_XRI 0xffff 4319 4320struct wqe_common { 4321 uint32_t word6; 4322#define wqe_xri_tag_SHIFT 0 4323#define wqe_xri_tag_MASK 0x0000FFFF 4324#define wqe_xri_tag_WORD word6 4325#define wqe_ctxt_tag_SHIFT 16 4326#define wqe_ctxt_tag_MASK 0x0000FFFF 4327#define wqe_ctxt_tag_WORD word6 4328 uint32_t word7; 4329#define wqe_dif_SHIFT 0 4330#define wqe_dif_MASK 0x00000003 4331#define wqe_dif_WORD word7 4332#define LPFC_WQE_DIF_PASSTHRU 1 4333#define LPFC_WQE_DIF_STRIP 2 4334#define LPFC_WQE_DIF_INSERT 3 4335#define wqe_ct_SHIFT 2 4336#define wqe_ct_MASK 0x00000003 4337#define wqe_ct_WORD word7 4338#define wqe_status_SHIFT 4 4339#define wqe_status_MASK 0x0000000f 4340#define wqe_status_WORD word7 4341#define wqe_cmnd_SHIFT 8 4342#define wqe_cmnd_MASK 0x000000ff 4343#define wqe_cmnd_WORD word7 4344#define wqe_class_SHIFT 16 4345#define wqe_class_MASK 0x00000007 4346#define wqe_class_WORD word7 4347#define wqe_ar_SHIFT 19 4348#define wqe_ar_MASK 0x00000001 4349#define wqe_ar_WORD word7 4350#define wqe_ag_SHIFT wqe_ar_SHIFT 4351#define wqe_ag_MASK wqe_ar_MASK 4352#define wqe_ag_WORD wqe_ar_WORD 4353#define wqe_pu_SHIFT 20 4354#define wqe_pu_MASK 0x00000003 4355#define wqe_pu_WORD word7 4356#define wqe_erp_SHIFT 22 4357#define wqe_erp_MASK 0x00000001 4358#define wqe_erp_WORD word7 4359#define wqe_conf_SHIFT wqe_erp_SHIFT 4360#define wqe_conf_MASK wqe_erp_MASK 4361#define wqe_conf_WORD wqe_erp_WORD 4362#define wqe_lnk_SHIFT 23 4363#define wqe_lnk_MASK 0x00000001 4364#define wqe_lnk_WORD word7 4365#define wqe_tmo_SHIFT 24 4366#define wqe_tmo_MASK 0x000000ff 4367#define wqe_tmo_WORD word7 4368 uint32_t abort_tag; /* word 8 in WQE */ 4369 uint32_t word9; 4370#define wqe_reqtag_SHIFT 0 4371#define wqe_reqtag_MASK 0x0000FFFF 4372#define wqe_reqtag_WORD word9 4373#define wqe_temp_rpi_SHIFT 16 4374#define wqe_temp_rpi_MASK 0x0000FFFF 4375#define wqe_temp_rpi_WORD word9 4376#define wqe_rcvoxid_SHIFT 16 4377#define wqe_rcvoxid_MASK 0x0000FFFF 4378#define wqe_rcvoxid_WORD word9 4379#define wqe_sof_SHIFT 24 4380#define wqe_sof_MASK 0x000000FF 4381#define wqe_sof_WORD word9 4382#define wqe_eof_SHIFT 16 4383#define wqe_eof_MASK 0x000000FF 4384#define wqe_eof_WORD word9 4385 uint32_t word10; 4386#define wqe_ebde_cnt_SHIFT 0 4387#define wqe_ebde_cnt_MASK 0x0000000f 4388#define wqe_ebde_cnt_WORD word10 4389#define wqe_xchg_SHIFT 4 4390#define wqe_xchg_MASK 0x00000001 4391#define wqe_xchg_WORD word10 4392#define LPFC_SCSI_XCHG 0x0 4393#define LPFC_NVME_XCHG 0x1 4394#define wqe_oas_SHIFT 6 4395#define wqe_oas_MASK 0x00000001 4396#define wqe_oas_WORD word10 4397#define wqe_lenloc_SHIFT 7 4398#define wqe_lenloc_MASK 0x00000003 4399#define wqe_lenloc_WORD word10 4400#define LPFC_WQE_LENLOC_NONE 0 4401#define LPFC_WQE_LENLOC_WORD3 1 4402#define LPFC_WQE_LENLOC_WORD12 2 4403#define LPFC_WQE_LENLOC_WORD4 3 4404#define wqe_qosd_SHIFT 9 4405#define wqe_qosd_MASK 0x00000001 4406#define wqe_qosd_WORD word10 4407#define wqe_xbl_SHIFT 11 4408#define wqe_xbl_MASK 0x00000001 4409#define wqe_xbl_WORD word10 4410#define wqe_iod_SHIFT 13 4411#define wqe_iod_MASK 0x00000001 4412#define wqe_iod_WORD word10 4413#define LPFC_WQE_IOD_NONE 0 4414#define LPFC_WQE_IOD_WRITE 0 4415#define LPFC_WQE_IOD_READ 1 4416#define wqe_dbde_SHIFT 14 4417#define wqe_dbde_MASK 0x00000001 4418#define wqe_dbde_WORD word10 4419#define wqe_wqes_SHIFT 15 4420#define wqe_wqes_MASK 0x00000001 4421#define wqe_wqes_WORD word10 4422/* Note that this field overlaps above fields */ 4423#define wqe_wqid_SHIFT 1 4424#define wqe_wqid_MASK 0x00007fff 4425#define wqe_wqid_WORD word10 4426#define wqe_pri_SHIFT 16 4427#define wqe_pri_MASK 0x00000007 4428#define wqe_pri_WORD word10 4429#define wqe_pv_SHIFT 19 4430#define wqe_pv_MASK 0x00000001 4431#define wqe_pv_WORD word10 4432#define wqe_xc_SHIFT 21 4433#define wqe_xc_MASK 0x00000001 4434#define wqe_xc_WORD word10 4435#define wqe_sr_SHIFT 22 4436#define wqe_sr_MASK 0x00000001 4437#define wqe_sr_WORD word10 4438#define wqe_ccpe_SHIFT 23 4439#define wqe_ccpe_MASK 0x00000001 4440#define wqe_ccpe_WORD word10 4441#define wqe_ccp_SHIFT 24 4442#define wqe_ccp_MASK 0x000000ff 4443#define wqe_ccp_WORD word10 4444 uint32_t word11; 4445#define wqe_cmd_type_SHIFT 0 4446#define wqe_cmd_type_MASK 0x0000000f 4447#define wqe_cmd_type_WORD word11 4448#define wqe_els_id_SHIFT 4 4449#define wqe_els_id_MASK 0x00000003 4450#define wqe_els_id_WORD word11 4451#define LPFC_ELS_ID_FLOGI 3 4452#define LPFC_ELS_ID_FDISC 2 4453#define LPFC_ELS_ID_LOGO 1 4454#define LPFC_ELS_ID_DEFAULT 0 4455#define wqe_irsp_SHIFT 4 4456#define wqe_irsp_MASK 0x00000001 4457#define wqe_irsp_WORD word11 4458#define wqe_pbde_SHIFT 5 4459#define wqe_pbde_MASK 0x00000001 4460#define wqe_pbde_WORD word11 4461#define wqe_sup_SHIFT 6 4462#define wqe_sup_MASK 0x00000001 4463#define wqe_sup_WORD word11 4464#define wqe_wqec_SHIFT 7 4465#define wqe_wqec_MASK 0x00000001 4466#define wqe_wqec_WORD word11 4467#define wqe_irsplen_SHIFT 8 4468#define wqe_irsplen_MASK 0x0000000f 4469#define wqe_irsplen_WORD word11 4470#define wqe_cqid_SHIFT 16 4471#define wqe_cqid_MASK 0x0000ffff 4472#define wqe_cqid_WORD word11 4473#define LPFC_WQE_CQ_ID_DEFAULT 0xffff 4474}; 4475 4476struct wqe_did { 4477 uint32_t word5; 4478#define wqe_els_did_SHIFT 0 4479#define wqe_els_did_MASK 0x00FFFFFF 4480#define wqe_els_did_WORD word5 4481#define wqe_xmit_bls_pt_SHIFT 28 4482#define wqe_xmit_bls_pt_MASK 0x00000003 4483#define wqe_xmit_bls_pt_WORD word5 4484#define wqe_xmit_bls_ar_SHIFT 30 4485#define wqe_xmit_bls_ar_MASK 0x00000001 4486#define wqe_xmit_bls_ar_WORD word5 4487#define wqe_xmit_bls_xo_SHIFT 31 4488#define wqe_xmit_bls_xo_MASK 0x00000001 4489#define wqe_xmit_bls_xo_WORD word5 4490}; 4491 4492struct lpfc_wqe_generic{ 4493 struct ulp_bde64 bde; 4494 uint32_t word3; 4495 uint32_t word4; 4496 uint32_t word5; 4497 struct wqe_common wqe_com; 4498 uint32_t payload[4]; 4499}; 4500 4501struct els_request64_wqe { 4502 struct ulp_bde64 bde; 4503 uint32_t payload_len; 4504 uint32_t word4; 4505#define els_req64_sid_SHIFT 0 4506#define els_req64_sid_MASK 0x00FFFFFF 4507#define els_req64_sid_WORD word4 4508#define els_req64_sp_SHIFT 24 4509#define els_req64_sp_MASK 0x00000001 4510#define els_req64_sp_WORD word4 4511#define els_req64_vf_SHIFT 25 4512#define els_req64_vf_MASK 0x00000001 4513#define els_req64_vf_WORD word4 4514 struct wqe_did wqe_dest; 4515 struct wqe_common wqe_com; /* words 6-11 */ 4516 uint32_t word12; 4517#define els_req64_vfid_SHIFT 1 4518#define els_req64_vfid_MASK 0x00000FFF 4519#define els_req64_vfid_WORD word12 4520#define els_req64_pri_SHIFT 13 4521#define els_req64_pri_MASK 0x00000007 4522#define els_req64_pri_WORD word12 4523 uint32_t word13; 4524#define els_req64_hopcnt_SHIFT 24 4525#define els_req64_hopcnt_MASK 0x000000ff 4526#define els_req64_hopcnt_WORD word13 4527 uint32_t word14; 4528 uint32_t max_response_payload_len; 4529}; 4530 4531struct xmit_els_rsp64_wqe { 4532 struct ulp_bde64 bde; 4533 uint32_t response_payload_len; 4534 uint32_t word4; 4535#define els_rsp64_sid_SHIFT 0 4536#define els_rsp64_sid_MASK 0x00FFFFFF 4537#define els_rsp64_sid_WORD word4 4538#define els_rsp64_sp_SHIFT 24 4539#define els_rsp64_sp_MASK 0x00000001 4540#define els_rsp64_sp_WORD word4 4541 struct wqe_did wqe_dest; 4542 struct wqe_common wqe_com; /* words 6-11 */ 4543 uint32_t word12; 4544#define wqe_rsp_temp_rpi_SHIFT 0 4545#define wqe_rsp_temp_rpi_MASK 0x0000FFFF 4546#define wqe_rsp_temp_rpi_WORD word12 4547 uint32_t rsvd_13_15[3]; 4548}; 4549 4550struct xmit_bls_rsp64_wqe { 4551 uint32_t payload0; 4552/* Payload0 for BA_ACC */ 4553#define xmit_bls_rsp64_acc_seq_id_SHIFT 16 4554#define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 4555#define xmit_bls_rsp64_acc_seq_id_WORD payload0 4556#define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 4557#define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 4558#define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 4559/* Payload0 for BA_RJT */ 4560#define xmit_bls_rsp64_rjt_vspec_SHIFT 0 4561#define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 4562#define xmit_bls_rsp64_rjt_vspec_WORD payload0 4563#define xmit_bls_rsp64_rjt_expc_SHIFT 8 4564#define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 4565#define xmit_bls_rsp64_rjt_expc_WORD payload0 4566#define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 4567#define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 4568#define xmit_bls_rsp64_rjt_rsnc_WORD payload0 4569 uint32_t word1; 4570#define xmit_bls_rsp64_rxid_SHIFT 0 4571#define xmit_bls_rsp64_rxid_MASK 0x0000ffff 4572#define xmit_bls_rsp64_rxid_WORD word1 4573#define xmit_bls_rsp64_oxid_SHIFT 16 4574#define xmit_bls_rsp64_oxid_MASK 0x0000ffff 4575#define xmit_bls_rsp64_oxid_WORD word1 4576 uint32_t word2; 4577#define xmit_bls_rsp64_seqcnthi_SHIFT 0 4578#define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 4579#define xmit_bls_rsp64_seqcnthi_WORD word2 4580#define xmit_bls_rsp64_seqcntlo_SHIFT 16 4581#define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 4582#define xmit_bls_rsp64_seqcntlo_WORD word2 4583 uint32_t rsrvd3; 4584 uint32_t rsrvd4; 4585 struct wqe_did wqe_dest; 4586 struct wqe_common wqe_com; /* words 6-11 */ 4587 uint32_t word12; 4588#define xmit_bls_rsp64_temprpi_SHIFT 0 4589#define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 4590#define xmit_bls_rsp64_temprpi_WORD word12 4591 uint32_t rsvd_13_15[3]; 4592}; 4593 4594struct wqe_rctl_dfctl { 4595 uint32_t word5; 4596#define wqe_si_SHIFT 2 4597#define wqe_si_MASK 0x000000001 4598#define wqe_si_WORD word5 4599#define wqe_la_SHIFT 3 4600#define wqe_la_MASK 0x000000001 4601#define wqe_la_WORD word5 4602#define wqe_xo_SHIFT 6 4603#define wqe_xo_MASK 0x000000001 4604#define wqe_xo_WORD word5 4605#define wqe_ls_SHIFT 7 4606#define wqe_ls_MASK 0x000000001 4607#define wqe_ls_WORD word5 4608#define wqe_dfctl_SHIFT 8 4609#define wqe_dfctl_MASK 0x0000000ff 4610#define wqe_dfctl_WORD word5 4611#define wqe_type_SHIFT 16 4612#define wqe_type_MASK 0x0000000ff 4613#define wqe_type_WORD word5 4614#define wqe_rctl_SHIFT 24 4615#define wqe_rctl_MASK 0x0000000ff 4616#define wqe_rctl_WORD word5 4617}; 4618 4619struct xmit_seq64_wqe { 4620 struct ulp_bde64 bde; 4621 uint32_t rsvd3; 4622 uint32_t relative_offset; 4623 struct wqe_rctl_dfctl wge_ctl; 4624 struct wqe_common wqe_com; /* words 6-11 */ 4625 uint32_t xmit_len; 4626 uint32_t rsvd_12_15[3]; 4627}; 4628struct xmit_bcast64_wqe { 4629 struct ulp_bde64 bde; 4630 uint32_t seq_payload_len; 4631 uint32_t rsvd4; 4632 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4633 struct wqe_common wqe_com; /* words 6-11 */ 4634 uint32_t rsvd_12_15[4]; 4635}; 4636 4637struct gen_req64_wqe { 4638 struct ulp_bde64 bde; 4639 uint32_t request_payload_len; 4640 uint32_t relative_offset; 4641 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4642 struct wqe_common wqe_com; /* words 6-11 */ 4643 uint32_t rsvd_12_14[3]; 4644 uint32_t max_response_payload_len; 4645}; 4646 4647/* Define NVME PRLI request to fabric. NVME is a 4648 * fabric-only protocol. 4649 * Updated to red-lined v1.08 on Sept 16, 2016 4650 */ 4651struct lpfc_nvme_prli { 4652 uint32_t word1; 4653 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */ 4654#define prli_acc_rsp_code_SHIFT 8 4655#define prli_acc_rsp_code_MASK 0x0000000f 4656#define prli_acc_rsp_code_WORD word1 4657#define prli_estabImagePair_SHIFT 13 4658#define prli_estabImagePair_MASK 0x00000001 4659#define prli_estabImagePair_WORD word1 4660#define prli_type_code_ext_SHIFT 16 4661#define prli_type_code_ext_MASK 0x000000ff 4662#define prli_type_code_ext_WORD word1 4663#define prli_type_code_SHIFT 24 4664#define prli_type_code_MASK 0x000000ff 4665#define prli_type_code_WORD word1 4666 uint32_t word_rsvd2; 4667 uint32_t word_rsvd3; 4668 4669 uint32_t word4; 4670#define prli_fba_SHIFT 0 4671#define prli_fba_MASK 0x00000001 4672#define prli_fba_WORD word4 4673#define prli_disc_SHIFT 3 4674#define prli_disc_MASK 0x00000001 4675#define prli_disc_WORD word4 4676#define prli_tgt_SHIFT 4 4677#define prli_tgt_MASK 0x00000001 4678#define prli_tgt_WORD word4 4679#define prli_init_SHIFT 5 4680#define prli_init_MASK 0x00000001 4681#define prli_init_WORD word4 4682#define prli_conf_SHIFT 7 4683#define prli_conf_MASK 0x00000001 4684#define prli_conf_WORD word4 4685#define prli_nsler_SHIFT 8 4686#define prli_nsler_MASK 0x00000001 4687#define prli_nsler_WORD word4 4688 uint32_t word5; 4689#define prli_fb_sz_SHIFT 0 4690#define prli_fb_sz_MASK 0x0000ffff 4691#define prli_fb_sz_WORD word5 4692#define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */ 4693}; 4694 4695struct create_xri_wqe { 4696 uint32_t rsrvd[5]; /* words 0-4 */ 4697 struct wqe_did wqe_dest; /* word 5 */ 4698 struct wqe_common wqe_com; /* words 6-11 */ 4699 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4700}; 4701 4702#define INHIBIT_ABORT 1 4703#define T_REQUEST_TAG 3 4704#define T_XRI_TAG 1 4705 4706struct abort_cmd_wqe { 4707 uint32_t rsrvd[3]; 4708 uint32_t word3; 4709#define abort_cmd_ia_SHIFT 0 4710#define abort_cmd_ia_MASK 0x000000001 4711#define abort_cmd_ia_WORD word3 4712#define abort_cmd_criteria_SHIFT 8 4713#define abort_cmd_criteria_MASK 0x0000000ff 4714#define abort_cmd_criteria_WORD word3 4715 uint32_t rsrvd4; 4716 uint32_t rsrvd5; 4717 struct wqe_common wqe_com; /* words 6-11 */ 4718 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4719}; 4720 4721struct fcp_iwrite64_wqe { 4722 struct ulp_bde64 bde; 4723 uint32_t word3; 4724#define cmd_buff_len_SHIFT 16 4725#define cmd_buff_len_MASK 0x00000ffff 4726#define cmd_buff_len_WORD word3 4727#define payload_offset_len_SHIFT 0 4728#define payload_offset_len_MASK 0x0000ffff 4729#define payload_offset_len_WORD word3 4730 uint32_t total_xfer_len; 4731 uint32_t initial_xfer_len; 4732 struct wqe_common wqe_com; /* words 6-11 */ 4733 uint32_t rsrvd12; 4734 struct ulp_bde64 ph_bde; /* words 13-15 */ 4735}; 4736 4737struct fcp_iread64_wqe { 4738 struct ulp_bde64 bde; 4739 uint32_t word3; 4740#define cmd_buff_len_SHIFT 16 4741#define cmd_buff_len_MASK 0x00000ffff 4742#define cmd_buff_len_WORD word3 4743#define payload_offset_len_SHIFT 0 4744#define payload_offset_len_MASK 0x0000ffff 4745#define payload_offset_len_WORD word3 4746 uint32_t total_xfer_len; /* word 4 */ 4747 uint32_t rsrvd5; /* word 5 */ 4748 struct wqe_common wqe_com; /* words 6-11 */ 4749 uint32_t rsrvd12; 4750 struct ulp_bde64 ph_bde; /* words 13-15 */ 4751}; 4752 4753struct fcp_icmnd64_wqe { 4754 struct ulp_bde64 bde; /* words 0-2 */ 4755 uint32_t word3; 4756#define cmd_buff_len_SHIFT 16 4757#define cmd_buff_len_MASK 0x00000ffff 4758#define cmd_buff_len_WORD word3 4759#define payload_offset_len_SHIFT 0 4760#define payload_offset_len_MASK 0x0000ffff 4761#define payload_offset_len_WORD word3 4762 uint32_t rsrvd4; /* word 4 */ 4763 uint32_t rsrvd5; /* word 5 */ 4764 struct wqe_common wqe_com; /* words 6-11 */ 4765 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4766}; 4767 4768struct fcp_trsp64_wqe { 4769 struct ulp_bde64 bde; 4770 uint32_t response_len; 4771 uint32_t rsvd_4_5[2]; 4772 struct wqe_common wqe_com; /* words 6-11 */ 4773 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4774}; 4775 4776struct fcp_tsend64_wqe { 4777 struct ulp_bde64 bde; 4778 uint32_t payload_offset_len; 4779 uint32_t relative_offset; 4780 uint32_t reserved; 4781 struct wqe_common wqe_com; /* words 6-11 */ 4782 uint32_t fcp_data_len; /* word 12 */ 4783 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4784}; 4785 4786struct fcp_treceive64_wqe { 4787 struct ulp_bde64 bde; 4788 uint32_t payload_offset_len; 4789 uint32_t relative_offset; 4790 uint32_t reserved; 4791 struct wqe_common wqe_com; /* words 6-11 */ 4792 uint32_t fcp_data_len; /* word 12 */ 4793 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4794}; 4795#define TXRDY_PAYLOAD_LEN 12 4796 4797#define CMD_SEND_FRAME 0xE1 4798 4799struct send_frame_wqe { 4800 struct ulp_bde64 bde; /* words 0-2 */ 4801 uint32_t frame_len; /* word 3 */ 4802 uint32_t fc_hdr_wd0; /* word 4 */ 4803 uint32_t fc_hdr_wd1; /* word 5 */ 4804 struct wqe_common wqe_com; /* words 6-11 */ 4805 uint32_t fc_hdr_wd2; /* word 12 */ 4806 uint32_t fc_hdr_wd3; /* word 13 */ 4807 uint32_t fc_hdr_wd4; /* word 14 */ 4808 uint32_t fc_hdr_wd5; /* word 15 */ 4809}; 4810 4811#define ELS_RDF_REG_TAG_CNT 4 4812struct lpfc_els_rdf_reg_desc { 4813 struct fc_df_desc_fpin_reg reg_desc; /* descriptor header */ 4814 __be32 desc_tags[ELS_RDF_REG_TAG_CNT]; 4815 /* tags in reg_desc */ 4816}; 4817 4818struct lpfc_els_rdf_req { 4819 struct fc_els_rdf rdf; /* hdr up to descriptors */ 4820 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */ 4821}; 4822 4823struct lpfc_els_rdf_rsp { 4824 struct fc_els_rdf_resp rdf_resp; /* hdr up to descriptors */ 4825 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */ 4826}; 4827 4828union lpfc_wqe { 4829 uint32_t words[16]; 4830 struct lpfc_wqe_generic generic; 4831 struct fcp_icmnd64_wqe fcp_icmd; 4832 struct fcp_iread64_wqe fcp_iread; 4833 struct fcp_iwrite64_wqe fcp_iwrite; 4834 struct abort_cmd_wqe abort_cmd; 4835 struct create_xri_wqe create_xri; 4836 struct xmit_bcast64_wqe xmit_bcast64; 4837 struct xmit_seq64_wqe xmit_sequence; 4838 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4839 struct xmit_els_rsp64_wqe xmit_els_rsp; 4840 struct els_request64_wqe els_req; 4841 struct gen_req64_wqe gen_req; 4842 struct fcp_trsp64_wqe fcp_trsp; 4843 struct fcp_tsend64_wqe fcp_tsend; 4844 struct fcp_treceive64_wqe fcp_treceive; 4845 struct send_frame_wqe send_frame; 4846}; 4847 4848union lpfc_wqe128 { 4849 uint32_t words[32]; 4850 struct lpfc_wqe_generic generic; 4851 struct fcp_icmnd64_wqe fcp_icmd; 4852 struct fcp_iread64_wqe fcp_iread; 4853 struct fcp_iwrite64_wqe fcp_iwrite; 4854 struct abort_cmd_wqe abort_cmd; 4855 struct create_xri_wqe create_xri; 4856 struct xmit_bcast64_wqe xmit_bcast64; 4857 struct xmit_seq64_wqe xmit_sequence; 4858 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4859 struct xmit_els_rsp64_wqe xmit_els_rsp; 4860 struct els_request64_wqe els_req; 4861 struct gen_req64_wqe gen_req; 4862 struct fcp_trsp64_wqe fcp_trsp; 4863 struct fcp_tsend64_wqe fcp_tsend; 4864 struct fcp_treceive64_wqe fcp_treceive; 4865 struct send_frame_wqe send_frame; 4866}; 4867 4868#define MAGIC_NUMBER_G6 0xFEAA0003 4869#define MAGIC_NUMBER_G7 0xFEAA0005 4870 4871struct lpfc_grp_hdr { 4872 uint32_t size; 4873 uint32_t magic_number; 4874 uint32_t word2; 4875#define lpfc_grp_hdr_file_type_SHIFT 24 4876#define lpfc_grp_hdr_file_type_MASK 0x000000FF 4877#define lpfc_grp_hdr_file_type_WORD word2 4878#define lpfc_grp_hdr_id_SHIFT 16 4879#define lpfc_grp_hdr_id_MASK 0x000000FF 4880#define lpfc_grp_hdr_id_WORD word2 4881 uint8_t rev_name[128]; 4882 uint8_t date[12]; 4883 uint8_t revision[32]; 4884}; 4885 4886/* Defines for WQE command type */ 4887#define FCP_COMMAND 0x0 4888#define NVME_READ_CMD 0x0 4889#define FCP_COMMAND_DATA_OUT 0x1 4890#define NVME_WRITE_CMD 0x1 4891#define COMMAND_DATA_IN 0x0 4892#define COMMAND_DATA_OUT 0x1 4893#define FCP_COMMAND_TRECEIVE 0x2 4894#define FCP_COMMAND_TRSP 0x3 4895#define FCP_COMMAND_TSEND 0x7 4896#define OTHER_COMMAND 0x8 4897#define ELS_COMMAND_NON_FIP 0xC 4898#define ELS_COMMAND_FIP 0xD 4899 4900#define LPFC_NVME_EMBED_CMD 0x0 4901#define LPFC_NVME_EMBED_WRITE 0x1 4902#define LPFC_NVME_EMBED_READ 0x2 4903 4904/* WQE Commands */ 4905#define CMD_ABORT_XRI_WQE 0x0F 4906#define CMD_XMIT_SEQUENCE64_WQE 0x82 4907#define CMD_XMIT_BCAST64_WQE 0x84 4908#define CMD_ELS_REQUEST64_WQE 0x8A 4909#define CMD_XMIT_ELS_RSP64_WQE 0x95 4910#define CMD_XMIT_BLS_RSP64_WQE 0x97 4911#define CMD_FCP_IWRITE64_WQE 0x98 4912#define CMD_FCP_IREAD64_WQE 0x9A 4913#define CMD_FCP_ICMND64_WQE 0x9C 4914#define CMD_FCP_TSEND64_WQE 0x9F 4915#define CMD_FCP_TRECEIVE64_WQE 0xA1 4916#define CMD_FCP_TRSP64_WQE 0xA3 4917#define CMD_GEN_REQUEST64_WQE 0xC2 4918 4919#define CMD_WQE_MASK 0xff 4920 4921 4922#define LPFC_FW_DUMP 1 4923#define LPFC_FW_RESET 2 4924#define LPFC_DV_RESET 3 4925