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6#include "qla_def.h"
7#include <linux/delay.h>
8#include <linux/ktime.h>
9#include <linux/pci.h>
10#include <linux/ratelimit.h>
11#include <linux/vmalloc.h>
12#include <scsi/scsi_tcq.h>
13#include <linux/utsname.h>
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36
37static int
38qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp)
39
40{
41 int rval;
42 unsigned long flags = 0;
43 device_reg_t *reg;
44 uint8_t abort_active;
45 uint8_t io_lock_on;
46 uint16_t command = 0;
47 uint32_t *iptr;
48 __le32 __iomem *optr;
49 uint32_t cnt;
50 uint32_t mboxes;
51 unsigned long wait_time;
52 struct qla_hw_data *ha = vha->hw;
53 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
54
55 if (ha->pdev->error_state == pci_channel_io_perm_failure) {
56 ql_log(ql_log_warn, vha, 0x115c,
57 "PCI channel failed permanently, exiting.\n");
58 return QLA_FUNCTION_TIMEOUT;
59 }
60
61 if (vha->device_flags & DFLG_DEV_FAILED) {
62 ql_log(ql_log_warn, vha, 0x115f,
63 "Device in failed state, exiting.\n");
64 return QLA_FUNCTION_TIMEOUT;
65 }
66
67 reg = ha->iobase;
68 io_lock_on = base_vha->flags.init_done;
69
70 rval = QLA_SUCCESS;
71 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
72
73 if (ha->flags.pci_channel_io_perm_failure) {
74 ql_log(ql_log_warn, vha, 0x1175,
75 "Perm failure on EEH timeout MBX, exiting.\n");
76 return QLA_FUNCTION_TIMEOUT;
77 }
78
79 if (ha->flags.isp82xx_fw_hung) {
80
81 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
82 ql_log(ql_log_warn, vha, 0x1176,
83 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
84 rval = QLA_FUNCTION_FAILED;
85 goto premature_exit;
86 }
87
88
89
90
91
92
93 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
94
95 ql_log(ql_log_warn, vha, 0x1177,
96 "Cmd access timeout, cmd=0x%x, Exiting.\n",
97 mcp->mb[0]);
98 return QLA_FUNCTION_TIMEOUT;
99 }
100
101 ha->flags.mbox_busy = 1;
102
103 ha->mcp32 = mcp;
104
105 ql_dbg(ql_dbg_mbx, vha, 0x1178,
106 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
107
108 spin_lock_irqsave(&ha->hardware_lock, flags);
109
110
111 optr = ®->ispfx00.mailbox0;
112
113 iptr = mcp->mb;
114 command = mcp->mb[0];
115 mboxes = mcp->out_mb;
116
117 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
118 if (mboxes & BIT_0)
119 wrt_reg_dword(optr, *iptr);
120
121 mboxes >>= 1;
122 optr++;
123 iptr++;
124 }
125
126
127 ha->flags.mbox_int = 0;
128 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
129
130 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172,
131 (uint8_t *)mcp->mb, 16);
132 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173,
133 ((uint8_t *)mcp->mb + 0x10), 16);
134 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174,
135 ((uint8_t *)mcp->mb + 0x20), 8);
136
137
138 ql_dbg(ql_dbg_mbx, vha, 0x1179,
139 "Going to unlock irq & waiting for interrupts. "
140 "jiffies=%lx.\n", jiffies);
141
142
143 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
144 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
145
146 QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
147 spin_unlock_irqrestore(&ha->hardware_lock, flags);
148
149 WARN_ON_ONCE(wait_for_completion_timeout(&ha->mbx_intr_comp,
150 mcp->tov * HZ) != 0);
151 } else {
152 ql_dbg(ql_dbg_mbx, vha, 0x112c,
153 "Cmd=%x Polling Mode.\n", command);
154
155 QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
156 spin_unlock_irqrestore(&ha->hardware_lock, flags);
157
158 wait_time = jiffies + mcp->tov * HZ;
159 while (!ha->flags.mbox_int) {
160 if (time_after(jiffies, wait_time))
161 break;
162
163
164 qla2x00_poll(ha->rsp_q_map[0]);
165
166 if (!ha->flags.mbox_int &&
167 !(IS_QLA2200(ha) &&
168 command == MBC_LOAD_RISC_RAM_EXTENDED))
169 usleep_range(10000, 11000);
170 }
171 ql_dbg(ql_dbg_mbx, vha, 0x112d,
172 "Waited %d sec.\n",
173 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
174 }
175
176
177 if (ha->flags.mbox_int) {
178 uint32_t *iptr2;
179
180 ql_dbg(ql_dbg_mbx, vha, 0x112e,
181 "Cmd=%x completed.\n", command);
182
183
184 ha->flags.mbox_int = 0;
185 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
186
187 if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE)
188 rval = QLA_FUNCTION_FAILED;
189
190
191 iptr2 = mcp->mb;
192 iptr = (uint32_t *)&ha->mailbox_out32[0];
193 mboxes = mcp->in_mb;
194 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
195 if (mboxes & BIT_0)
196 *iptr2 = *iptr;
197
198 mboxes >>= 1;
199 iptr2++;
200 iptr++;
201 }
202 } else {
203
204 rval = QLA_FUNCTION_TIMEOUT;
205 }
206
207 ha->flags.mbox_busy = 0;
208
209
210 ha->mcp32 = NULL;
211
212 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
213 ql_dbg(ql_dbg_mbx, vha, 0x113a,
214 "checking for additional resp interrupt.\n");
215
216
217 qla2x00_poll(ha->rsp_q_map[0]);
218 }
219
220 if (rval == QLA_FUNCTION_TIMEOUT &&
221 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
222 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
223 ha->flags.eeh_busy) {
224
225 ql_dbg(ql_dbg_mbx, vha, 0x115d,
226 "Timeout, schedule isp_abort_needed.\n");
227
228 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
229 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
230 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
231
232 ql_log(ql_log_info, base_vha, 0x115e,
233 "Mailbox cmd timeout occurred, cmd=0x%x, "
234 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
235 "abort.\n", command, mcp->mb[0],
236 ha->flags.eeh_busy);
237 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
238 qla2xxx_wake_dpc(vha);
239 }
240 } else if (!abort_active) {
241
242 ql_dbg(ql_dbg_mbx, vha, 0x1160,
243 "Timeout, calling abort_isp.\n");
244
245 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
246 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
247 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
248
249 ql_log(ql_log_info, base_vha, 0x1161,
250 "Mailbox cmd timeout occurred, cmd=0x%x, "
251 "mb[0]=0x%x. Scheduling ISP abort ",
252 command, mcp->mb[0]);
253
254 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
255 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
256 if (ha->isp_ops->abort_isp(vha)) {
257
258 set_bit(ISP_ABORT_NEEDED,
259 &vha->dpc_flags);
260 }
261 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
262 ql_dbg(ql_dbg_mbx, vha, 0x1162,
263 "Finished abort_isp.\n");
264 }
265 }
266 }
267
268premature_exit:
269
270 complete(&ha->mbx_cmd_comp);
271
272 if (rval) {
273 ql_log(ql_log_warn, base_vha, 0x1163,
274 "**** Failed=%x mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
275 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
276 command);
277 } else {
278 ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__);
279 }
280
281 return rval;
282}
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295
296
297int
298qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo)
299{
300 int rval;
301 struct mbx_cmd_32 mc;
302 struct mbx_cmd_32 *mcp = &mc;
303
304 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166,
305 "Entered %s.\n", __func__);
306
307 mcp->mb[0] = MBC_MR_DRV_SHUTDOWN;
308 mcp->out_mb = MBX_0;
309 mcp->in_mb = MBX_0;
310 if (tmo)
311 mcp->tov = tmo;
312 else
313 mcp->tov = MBX_TOV_SECONDS;
314 mcp->flags = 0;
315 rval = qlafx00_mailbox_command(vha, mcp);
316
317 if (rval != QLA_SUCCESS) {
318 ql_dbg(ql_dbg_mbx, vha, 0x1167,
319 "Failed=%x.\n", rval);
320 } else {
321 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168,
322 "Done %s.\n", __func__);
323 }
324
325 return rval;
326}
327
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339
340
341
342
343static int
344qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states)
345{
346 int rval;
347 struct mbx_cmd_32 mc;
348 struct mbx_cmd_32 *mcp = &mc;
349
350 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169,
351 "Entered %s.\n", __func__);
352
353 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
354 mcp->out_mb = MBX_0;
355 mcp->in_mb = MBX_1|MBX_0;
356 mcp->tov = MBX_TOV_SECONDS;
357 mcp->flags = 0;
358 rval = qlafx00_mailbox_command(vha, mcp);
359
360
361 states[0] = mcp->mb[1];
362
363 if (rval != QLA_SUCCESS) {
364 ql_dbg(ql_dbg_mbx, vha, 0x116a,
365 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
366 } else {
367 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b,
368 "Done %s.\n", __func__);
369 }
370 return rval;
371}
372
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375
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387
388
389
390int
391qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
392{
393 int rval;
394 struct mbx_cmd_32 mc;
395 struct mbx_cmd_32 *mcp = &mc;
396 struct qla_hw_data *ha = vha->hw;
397
398 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c,
399 "Entered %s.\n", __func__);
400
401 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
402
403 mcp->mb[1] = 0;
404 mcp->mb[2] = MSD(ha->init_cb_dma);
405 mcp->mb[3] = LSD(ha->init_cb_dma);
406
407 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
408 mcp->in_mb = MBX_0;
409 mcp->buf_size = size;
410 mcp->flags = MBX_DMA_OUT;
411 mcp->tov = MBX_TOV_SECONDS;
412 rval = qlafx00_mailbox_command(vha, mcp);
413
414 if (rval != QLA_SUCCESS) {
415 ql_dbg(ql_dbg_mbx, vha, 0x116d,
416 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
417 } else {
418 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e,
419 "Done %s.\n", __func__);
420 }
421 return rval;
422}
423
424
425
426
427static int
428qlafx00_mbx_reg_test(scsi_qla_host_t *vha)
429{
430 int rval;
431 struct mbx_cmd_32 mc;
432 struct mbx_cmd_32 *mcp = &mc;
433
434 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f,
435 "Entered %s.\n", __func__);
436
437
438 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
439 mcp->mb[1] = 0xAAAA;
440 mcp->mb[2] = 0x5555;
441 mcp->mb[3] = 0xAA55;
442 mcp->mb[4] = 0x55AA;
443 mcp->mb[5] = 0xA5A5;
444 mcp->mb[6] = 0x5A5A;
445 mcp->mb[7] = 0x2525;
446 mcp->mb[8] = 0xBBBB;
447 mcp->mb[9] = 0x6666;
448 mcp->mb[10] = 0xBB66;
449 mcp->mb[11] = 0x66BB;
450 mcp->mb[12] = 0xB6B6;
451 mcp->mb[13] = 0x6B6B;
452 mcp->mb[14] = 0x3636;
453 mcp->mb[15] = 0xCCCC;
454
455
456 mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
457 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
458 mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
459 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
460 mcp->buf_size = 0;
461 mcp->flags = MBX_DMA_OUT;
462 mcp->tov = MBX_TOV_SECONDS;
463 rval = qlafx00_mailbox_command(vha, mcp);
464 if (rval == QLA_SUCCESS) {
465 if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 ||
466 mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA)
467 rval = QLA_FUNCTION_FAILED;
468 if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A ||
469 mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB)
470 rval = QLA_FUNCTION_FAILED;
471 if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 ||
472 mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6)
473 rval = QLA_FUNCTION_FAILED;
474 if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 ||
475 mcp->mb[31] != 0xCCCC)
476 rval = QLA_FUNCTION_FAILED;
477 }
478
479 if (rval != QLA_SUCCESS) {
480 ql_dbg(ql_dbg_mbx, vha, 0x1170,
481 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
482 } else {
483 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171,
484 "Done %s.\n", __func__);
485 }
486 return rval;
487}
488
489
490
491
492
493
494
495int
496qlafx00_pci_config(scsi_qla_host_t *vha)
497{
498 uint16_t w;
499 struct qla_hw_data *ha = vha->hw;
500
501 pci_set_master(ha->pdev);
502 pci_try_set_mwi(ha->pdev);
503
504 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
505 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
506 w &= ~PCI_COMMAND_INTX_DISABLE;
507 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
508
509
510 if (pci_is_pcie(ha->pdev))
511 pcie_set_readrq(ha->pdev, 2048);
512
513 ha->chip_revision = ha->pdev->revision;
514
515 return QLA_SUCCESS;
516}
517
518
519
520
521
522
523static inline void
524qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
525{
526 unsigned long flags = 0;
527 struct qla_hw_data *ha = vha->hw;
528 int i, core;
529 uint32_t cnt;
530 uint32_t reg_val;
531
532 spin_lock_irqsave(&ha->hardware_lock, flags);
533
534 QLAFX00_SET_HBA_SOC_REG(ha, 0x80004, 0);
535 QLAFX00_SET_HBA_SOC_REG(ha, 0x82004, 0);
536
537
538 QLAFX00_SET_HBA_SOC_REG(ha, 0x60920, 0x02);
539 QLAFX00_SET_HBA_SOC_REG(ha, 0x60924, 0x02);
540 QLAFX00_SET_HBA_SOC_REG(ha, 0xf0920, 0x02);
541 QLAFX00_SET_HBA_SOC_REG(ha, 0xf0924, 0x02);
542
543
544 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60840);
545 reg_val &= ~(1<<12);
546 QLAFX00_SET_HBA_SOC_REG(ha, 0x60840, reg_val);
547
548 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60844);
549 reg_val &= ~(1<<12);
550 QLAFX00_SET_HBA_SOC_REG(ha, 0x60844, reg_val);
551
552 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60848);
553 reg_val &= ~(1<<12);
554 QLAFX00_SET_HBA_SOC_REG(ha, 0x60848, reg_val);
555
556 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x6084C);
557 reg_val &= ~(1<<12);
558 QLAFX00_SET_HBA_SOC_REG(ha, 0x6084C, reg_val);
559
560 for (i = 0; i < 100000; i++) {
561 if ((QLAFX00_GET_HBA_SOC_REG(ha, 0xd0000) & 0x10000000) == 0 &&
562 (QLAFX00_GET_HBA_SOC_REG(ha, 0x10600) & 0x1) == 0)
563 break;
564 udelay(100);
565 }
566
567
568 for (i = 0; i < 4; i++) {
569 QLAFX00_SET_HBA_SOC_REG(ha,
570 (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
571 QLAFX00_SET_HBA_SOC_REG(ha,
572 (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
573 }
574
575
576 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x011f0101));
577
578
579 QLAFX00_SET_HBA_SOC_REG(ha, 0x10610, 1);
580 QLAFX00_SET_HBA_SOC_REG(ha, 0x10600, 0);
581
582
583 for (i = 0; i < 5; i++) {
584 QLAFX00_SET_HBA_SOC_REG(ha,
585 (SOC_PWR_MANAGEMENT_PWR_DOWN_REG + 4*i), (0x0));
586 }
587
588
589 for (i = 0; i < 115; i++) {
590 QLAFX00_SET_HBA_SOC_REG(ha,
591 (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0));
592 }
593
594
595 for (core = 0; core < 4; core++)
596 for (i = 0; i < 8; i++)
597 QLAFX00_SET_HBA_SOC_REG(ha,
598 (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0));
599
600
601 for (core = 0; core < 4; core++)
602 QLAFX00_SET_HBA_SOC_REG(ha,
603 (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF));
604
605
606 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
607 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
608
609
610 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
611
612
613 QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00));
614
615 spin_unlock_irqrestore(&ha->hardware_lock, flags);
616
617
618 for (cnt = 10; cnt; cnt--) {
619 msleep(1000);
620 barrier();
621 }
622}
623
624
625
626
627
628
629
630int
631qlafx00_soft_reset(scsi_qla_host_t *vha)
632{
633 struct qla_hw_data *ha = vha->hw;
634 int rval = QLA_FUNCTION_FAILED;
635
636 if (unlikely(pci_channel_offline(ha->pdev) &&
637 ha->flags.pci_channel_io_perm_failure))
638 return rval;
639
640 ha->isp_ops->disable_intrs(ha);
641 qlafx00_soc_cpu_reset(vha);
642
643 return QLA_SUCCESS;
644}
645
646
647
648
649
650
651
652int
653qlafx00_chip_diag(scsi_qla_host_t *vha)
654{
655 int rval = 0;
656 struct qla_hw_data *ha = vha->hw;
657 struct req_que *req = ha->req_q_map[0];
658
659 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
660
661 rval = qlafx00_mbx_reg_test(vha);
662 if (rval) {
663 ql_log(ql_log_warn, vha, 0x1165,
664 "Failed mailbox send register test\n");
665 } else {
666
667 rval = QLA_SUCCESS;
668 }
669 return rval;
670}
671
672void
673qlafx00_config_rings(struct scsi_qla_host *vha)
674{
675 struct qla_hw_data *ha = vha->hw;
676 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
677
678 wrt_reg_dword(®->req_q_in, 0);
679 wrt_reg_dword(®->req_q_out, 0);
680
681 wrt_reg_dword(®->rsp_q_in, 0);
682 wrt_reg_dword(®->rsp_q_out, 0);
683
684
685 rd_reg_dword(®->rsp_q_out);
686}
687
688char *
689qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
690{
691 struct qla_hw_data *ha = vha->hw;
692
693 if (pci_is_pcie(ha->pdev))
694 strlcpy(str, "PCIe iSA", str_len);
695 return str;
696}
697
698char *
699qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
700{
701 struct qla_hw_data *ha = vha->hw;
702
703 snprintf(str, size, "%s", ha->mr.fw_version);
704 return str;
705}
706
707void
708qlafx00_enable_intrs(struct qla_hw_data *ha)
709{
710 unsigned long flags = 0;
711
712 spin_lock_irqsave(&ha->hardware_lock, flags);
713 ha->interrupts_on = 1;
714 QLAFX00_ENABLE_ICNTRL_REG(ha);
715 spin_unlock_irqrestore(&ha->hardware_lock, flags);
716}
717
718void
719qlafx00_disable_intrs(struct qla_hw_data *ha)
720{
721 unsigned long flags = 0;
722
723 spin_lock_irqsave(&ha->hardware_lock, flags);
724 ha->interrupts_on = 0;
725 QLAFX00_DISABLE_ICNTRL_REG(ha);
726 spin_unlock_irqrestore(&ha->hardware_lock, flags);
727}
728
729int
730qlafx00_abort_target(fc_port_t *fcport, uint64_t l, int tag)
731{
732 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
733}
734
735int
736qlafx00_lun_reset(fc_port_t *fcport, uint64_t l, int tag)
737{
738 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
739}
740
741int
742qlafx00_loop_reset(scsi_qla_host_t *vha)
743{
744 int ret;
745 struct fc_port *fcport;
746 struct qla_hw_data *ha = vha->hw;
747
748 if (ql2xtargetreset) {
749 list_for_each_entry(fcport, &vha->vp_fcports, list) {
750 if (fcport->port_type != FCT_TARGET)
751 continue;
752
753 ret = ha->isp_ops->target_reset(fcport, 0, 0);
754 if (ret != QLA_SUCCESS) {
755 ql_dbg(ql_dbg_taskm, vha, 0x803d,
756 "Bus Reset failed: Reset=%d "
757 "d_id=%x.\n", ret, fcport->d_id.b24);
758 }
759 }
760 }
761 return QLA_SUCCESS;
762}
763
764int
765qlafx00_iospace_config(struct qla_hw_data *ha)
766{
767 if (pci_request_selected_regions(ha->pdev, ha->bars,
768 QLA2XXX_DRIVER_NAME)) {
769 ql_log_pci(ql_log_fatal, ha->pdev, 0x014e,
770 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
771 pci_name(ha->pdev));
772 goto iospace_error_exit;
773 }
774
775
776 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
777 ql_log_pci(ql_log_warn, ha->pdev, 0x014f,
778 "Invalid pci I/O region size (%s).\n",
779 pci_name(ha->pdev));
780 goto iospace_error_exit;
781 }
782 if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) {
783 ql_log_pci(ql_log_warn, ha->pdev, 0x0127,
784 "Invalid PCI mem BAR0 region size (%s), aborting\n",
785 pci_name(ha->pdev));
786 goto iospace_error_exit;
787 }
788
789 ha->cregbase =
790 ioremap(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00);
791 if (!ha->cregbase) {
792 ql_log_pci(ql_log_fatal, ha->pdev, 0x0128,
793 "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
794 goto iospace_error_exit;
795 }
796
797 if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) {
798 ql_log_pci(ql_log_warn, ha->pdev, 0x0129,
799 "region #2 not an MMIO resource (%s), aborting\n",
800 pci_name(ha->pdev));
801 goto iospace_error_exit;
802 }
803 if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) {
804 ql_log_pci(ql_log_warn, ha->pdev, 0x012a,
805 "Invalid PCI mem BAR2 region size (%s), aborting\n",
806 pci_name(ha->pdev));
807 goto iospace_error_exit;
808 }
809
810 ha->iobase =
811 ioremap(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00);
812 if (!ha->iobase) {
813 ql_log_pci(ql_log_fatal, ha->pdev, 0x012b,
814 "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
815 goto iospace_error_exit;
816 }
817
818
819 ha->max_req_queues = ha->max_rsp_queues = 1;
820
821 ql_log_pci(ql_log_info, ha->pdev, 0x012c,
822 "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n",
823 ha->bars, ha->cregbase, ha->iobase);
824
825 return 0;
826
827iospace_error_exit:
828 return -ENOMEM;
829}
830
831static void
832qlafx00_save_queue_ptrs(struct scsi_qla_host *vha)
833{
834 struct qla_hw_data *ha = vha->hw;
835 struct req_que *req = ha->req_q_map[0];
836 struct rsp_que *rsp = ha->rsp_q_map[0];
837
838 req->length_fx00 = req->length;
839 req->ring_fx00 = req->ring;
840 req->dma_fx00 = req->dma;
841
842 rsp->length_fx00 = rsp->length;
843 rsp->ring_fx00 = rsp->ring;
844 rsp->dma_fx00 = rsp->dma;
845
846 ql_dbg(ql_dbg_init, vha, 0x012d,
847 "req: %p, ring_fx00: %p, length_fx00: 0x%x,"
848 "req->dma_fx00: 0x%llx\n", req, req->ring_fx00,
849 req->length_fx00, (u64)req->dma_fx00);
850
851 ql_dbg(ql_dbg_init, vha, 0x012e,
852 "rsp: %p, ring_fx00: %p, length_fx00: 0x%x,"
853 "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00,
854 rsp->length_fx00, (u64)rsp->dma_fx00);
855}
856
857static int
858qlafx00_config_queues(struct scsi_qla_host *vha)
859{
860 struct qla_hw_data *ha = vha->hw;
861 struct req_que *req = ha->req_q_map[0];
862 struct rsp_que *rsp = ha->rsp_q_map[0];
863 dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
864
865 req->length = ha->req_que_len;
866 req->ring = (void __force *)ha->iobase + ha->req_que_off;
867 req->dma = bar2_hdl + ha->req_que_off;
868 if ((!req->ring) || (req->length == 0)) {
869 ql_log_pci(ql_log_info, ha->pdev, 0x012f,
870 "Unable to allocate memory for req_ring\n");
871 return QLA_FUNCTION_FAILED;
872 }
873
874 ql_dbg(ql_dbg_init, vha, 0x0130,
875 "req: %p req_ring pointer %p req len 0x%x "
876 "req off 0x%x\n, req->dma: 0x%llx",
877 req, req->ring, req->length,
878 ha->req_que_off, (u64)req->dma);
879
880 rsp->length = ha->rsp_que_len;
881 rsp->ring = (void __force *)ha->iobase + ha->rsp_que_off;
882 rsp->dma = bar2_hdl + ha->rsp_que_off;
883 if ((!rsp->ring) || (rsp->length == 0)) {
884 ql_log_pci(ql_log_info, ha->pdev, 0x0131,
885 "Unable to allocate memory for rsp_ring\n");
886 return QLA_FUNCTION_FAILED;
887 }
888
889 ql_dbg(ql_dbg_init, vha, 0x0132,
890 "rsp: %p rsp_ring pointer %p rsp len 0x%x "
891 "rsp off 0x%x, rsp->dma: 0x%llx\n",
892 rsp, rsp->ring, rsp->length,
893 ha->rsp_que_off, (u64)rsp->dma);
894
895 return QLA_SUCCESS;
896}
897
898static int
899qlafx00_init_fw_ready(scsi_qla_host_t *vha)
900{
901 int rval = 0;
902 unsigned long wtime;
903 uint16_t wait_time;
904 struct qla_hw_data *ha = vha->hw;
905 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
906 uint32_t aenmbx, aenmbx7 = 0;
907 uint32_t pseudo_aen;
908 uint32_t state[5];
909 bool done = false;
910
911
912 wait_time = 30;
913
914 pseudo_aen = rd_reg_dword(®->pseudoaen);
915 if (pseudo_aen == 1) {
916 aenmbx7 = rd_reg_dword(®->initval7);
917 ha->mbx_intr_code = MSW(aenmbx7);
918 ha->rqstq_intr_code = LSW(aenmbx7);
919 rval = qlafx00_driver_shutdown(vha, 10);
920 if (rval != QLA_SUCCESS)
921 qlafx00_soft_reset(vha);
922 }
923
924
925 wtime = jiffies + (wait_time * HZ);
926 do {
927 aenmbx = rd_reg_dword(®->aenmailbox0);
928 barrier();
929 ql_dbg(ql_dbg_mbx, vha, 0x0133,
930 "aenmbx: 0x%x\n", aenmbx);
931
932 switch (aenmbx) {
933 case MBA_FW_NOT_STARTED:
934 case MBA_FW_STARTING:
935 break;
936
937 case MBA_SYSTEM_ERR:
938 case MBA_REQ_TRANSFER_ERR:
939 case MBA_RSP_TRANSFER_ERR:
940 case MBA_FW_INIT_FAILURE:
941 qlafx00_soft_reset(vha);
942 break;
943
944 case MBA_FW_RESTART_CMPLT:
945
946 aenmbx7 = rd_reg_dword(®->aenmailbox7);
947 ha->mbx_intr_code = MSW(aenmbx7);
948 ha->rqstq_intr_code = LSW(aenmbx7);
949 ha->req_que_off = rd_reg_dword(®->aenmailbox1);
950 ha->rsp_que_off = rd_reg_dword(®->aenmailbox3);
951 ha->req_que_len = rd_reg_dword(®->aenmailbox5);
952 ha->rsp_que_len = rd_reg_dword(®->aenmailbox6);
953 wrt_reg_dword(®->aenmailbox0, 0);
954 rd_reg_dword_relaxed(®->aenmailbox0);
955 ql_dbg(ql_dbg_init, vha, 0x0134,
956 "f/w returned mbx_intr_code: 0x%x, "
957 "rqstq_intr_code: 0x%x\n",
958 ha->mbx_intr_code, ha->rqstq_intr_code);
959 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
960 rval = QLA_SUCCESS;
961 done = true;
962 break;
963
964 default:
965 if ((aenmbx & 0xFF00) == MBA_FW_INIT_INPROGRESS)
966 break;
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984 aenmbx7 = rd_reg_dword(®->initval7);
985 ha->mbx_intr_code = MSW(aenmbx7);
986 ha->rqstq_intr_code = LSW(aenmbx7);
987 ha->req_que_off = rd_reg_dword(®->initval1);
988 ha->rsp_que_off = rd_reg_dword(®->initval3);
989 ha->req_que_len = rd_reg_dword(®->initval5);
990 ha->rsp_que_len = rd_reg_dword(®->initval6);
991 ql_dbg(ql_dbg_init, vha, 0x0135,
992 "f/w returned mbx_intr_code: 0x%x, "
993 "rqstq_intr_code: 0x%x\n",
994 ha->mbx_intr_code, ha->rqstq_intr_code);
995 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
996
997
998 rval = qlafx00_get_firmware_state(vha, state);
999 if (rval != QLA_SUCCESS) {
1000
1001 break;
1002 }
1003
1004 if (state[0] == FSTATE_FX00_CONFIG_WAIT) {
1005
1006
1007
1008 rval = QLA_SUCCESS;
1009 done = true;
1010 break;
1011 }
1012
1013
1014
1015
1016
1017 ql_dbg(ql_dbg_init, vha, 0x0136,
1018 "Sending Driver shutdown fw_state 0x%x\n",
1019 state[0]);
1020
1021 rval = qlafx00_driver_shutdown(vha, 10);
1022 if (rval != QLA_SUCCESS) {
1023 rval = QLA_FUNCTION_FAILED;
1024 break;
1025 }
1026 msleep(500);
1027
1028 wtime = jiffies + (wait_time * HZ);
1029 break;
1030 }
1031
1032 if (!done) {
1033 if (time_after_eq(jiffies, wtime)) {
1034 ql_dbg(ql_dbg_init, vha, 0x0137,
1035 "Init f/w failed: aen[7]: 0x%x\n",
1036 rd_reg_dword(®->aenmailbox7));
1037 rval = QLA_FUNCTION_FAILED;
1038 done = true;
1039 break;
1040 }
1041
1042 msleep(500);
1043 }
1044 } while (!done);
1045
1046 if (rval)
1047 ql_dbg(ql_dbg_init, vha, 0x0138,
1048 "%s **** FAILED ****.\n", __func__);
1049 else
1050 ql_dbg(ql_dbg_init, vha, 0x0139,
1051 "%s **** SUCCESS ****.\n", __func__);
1052
1053 return rval;
1054}
1055
1056
1057
1058
1059
1060
1061
1062int
1063qlafx00_fw_ready(scsi_qla_host_t *vha)
1064{
1065 int rval;
1066 unsigned long wtime;
1067 uint16_t wait_time;
1068 uint32_t state[5];
1069
1070 rval = QLA_SUCCESS;
1071
1072 wait_time = 10;
1073
1074
1075 wtime = jiffies + (wait_time * HZ);
1076
1077
1078 if (!vha->flags.init_done)
1079 ql_dbg(ql_dbg_init, vha, 0x013a,
1080 "Waiting for init to complete...\n");
1081
1082 do {
1083 rval = qlafx00_get_firmware_state(vha, state);
1084
1085 if (rval == QLA_SUCCESS) {
1086 if (state[0] == FSTATE_FX00_INITIALIZED) {
1087 ql_dbg(ql_dbg_init, vha, 0x013b,
1088 "fw_state=%x\n", state[0]);
1089 rval = QLA_SUCCESS;
1090 break;
1091 }
1092 }
1093 rval = QLA_FUNCTION_FAILED;
1094
1095 if (time_after_eq(jiffies, wtime))
1096 break;
1097
1098
1099 msleep(500);
1100
1101 ql_dbg(ql_dbg_init, vha, 0x013c,
1102 "fw_state=%x curr time=%lx.\n", state[0], jiffies);
1103 } while (1);
1104
1105
1106 if (rval)
1107 ql_dbg(ql_dbg_init, vha, 0x013d,
1108 "Firmware ready **** FAILED ****.\n");
1109 else
1110 ql_dbg(ql_dbg_init, vha, 0x013e,
1111 "Firmware ready **** SUCCESS ****.\n");
1112
1113 return rval;
1114}
1115
1116static int
1117qlafx00_find_all_targets(scsi_qla_host_t *vha,
1118 struct list_head *new_fcports)
1119{
1120 int rval;
1121 uint16_t tgt_id;
1122 fc_port_t *fcport, *new_fcport;
1123 int found;
1124 struct qla_hw_data *ha = vha->hw;
1125
1126 rval = QLA_SUCCESS;
1127
1128 if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
1129 return QLA_FUNCTION_FAILED;
1130
1131 if ((atomic_read(&vha->loop_down_timer) ||
1132 STATE_TRANSITION(vha))) {
1133 atomic_set(&vha->loop_down_timer, 0);
1134 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1135 return QLA_FUNCTION_FAILED;
1136 }
1137
1138 ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
1139 "Listing Target bit map...\n");
1140 ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha, 0x2089,
1141 ha->gid_list, 32);
1142
1143
1144 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1145 if (new_fcport == NULL)
1146 return QLA_MEMORY_ALLOC_FAILED;
1147
1148 for_each_set_bit(tgt_id, (void *)ha->gid_list,
1149 QLAFX00_TGT_NODE_LIST_SIZE) {
1150
1151
1152 new_fcport->tgt_id = tgt_id;
1153 rval = qlafx00_fx_disc(vha, new_fcport,
1154 FXDISC_GET_TGT_NODE_INFO);
1155 if (rval != QLA_SUCCESS) {
1156 ql_log(ql_log_warn, vha, 0x208a,
1157 "Target info scan failed -- assuming zero-entry "
1158 "result...\n");
1159 continue;
1160 }
1161
1162
1163 found = 0;
1164 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1165 if (memcmp(new_fcport->port_name,
1166 fcport->port_name, WWN_SIZE))
1167 continue;
1168
1169 found++;
1170
1171
1172
1173
1174
1175 if (fcport->tgt_id == new_fcport->tgt_id &&
1176 atomic_read(&fcport->state) == FCS_ONLINE)
1177 break;
1178
1179
1180
1181
1182 ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b,
1183 "TGT-ID Change(%s): Present tgt id: "
1184 "0x%x state: 0x%x "
1185 "wwnn = %llx wwpn = %llx.\n",
1186 __func__, fcport->tgt_id,
1187 atomic_read(&fcport->state),
1188 (unsigned long long)wwn_to_u64(fcport->node_name),
1189 (unsigned long long)wwn_to_u64(fcport->port_name));
1190
1191 ql_log(ql_log_info, vha, 0x208c,
1192 "TGT-ID Announce(%s): Discovered tgt "
1193 "id 0x%x wwnn = %llx "
1194 "wwpn = %llx.\n", __func__, new_fcport->tgt_id,
1195 (unsigned long long)
1196 wwn_to_u64(new_fcport->node_name),
1197 (unsigned long long)
1198 wwn_to_u64(new_fcport->port_name));
1199
1200 if (atomic_read(&fcport->state) != FCS_ONLINE) {
1201 fcport->old_tgt_id = fcport->tgt_id;
1202 fcport->tgt_id = new_fcport->tgt_id;
1203 ql_log(ql_log_info, vha, 0x208d,
1204 "TGT-ID: New fcport Added: %p\n", fcport);
1205 qla2x00_update_fcport(vha, fcport);
1206 } else {
1207 ql_log(ql_log_info, vha, 0x208e,
1208 " Existing TGT-ID %x did not get "
1209 " offline event from firmware.\n",
1210 fcport->old_tgt_id);
1211 qla2x00_mark_device_lost(vha, fcport, 0);
1212 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1213 qla2x00_free_fcport(new_fcport);
1214 return rval;
1215 }
1216 break;
1217 }
1218
1219 if (found)
1220 continue;
1221
1222
1223 list_add_tail(&new_fcport->list, new_fcports);
1224
1225
1226 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1227 if (new_fcport == NULL)
1228 return QLA_MEMORY_ALLOC_FAILED;
1229 }
1230
1231 qla2x00_free_fcport(new_fcport);
1232 return rval;
1233}
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246static int
1247qlafx00_configure_all_targets(scsi_qla_host_t *vha)
1248{
1249 int rval;
1250 fc_port_t *fcport, *rmptemp;
1251 LIST_HEAD(new_fcports);
1252
1253 rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1254 FXDISC_GET_TGT_NODE_LIST);
1255 if (rval != QLA_SUCCESS) {
1256 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1257 return rval;
1258 }
1259
1260 rval = qlafx00_find_all_targets(vha, &new_fcports);
1261 if (rval != QLA_SUCCESS) {
1262 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1263 return rval;
1264 }
1265
1266
1267
1268
1269 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1270 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1271 break;
1272
1273 if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
1274 if (fcport->port_type != FCT_INITIATOR)
1275 qla2x00_mark_device_lost(vha, fcport, 0);
1276 }
1277 }
1278
1279
1280
1281
1282 list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
1283 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1284 break;
1285
1286 qla2x00_update_fcport(vha, fcport);
1287 list_move_tail(&fcport->list, &vha->vp_fcports);
1288 ql_log(ql_log_info, vha, 0x208f,
1289 "Attach new target id 0x%x wwnn = %llx "
1290 "wwpn = %llx.\n",
1291 fcport->tgt_id,
1292 (unsigned long long)wwn_to_u64(fcport->node_name),
1293 (unsigned long long)wwn_to_u64(fcport->port_name));
1294 }
1295
1296
1297 list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
1298 list_del(&fcport->list);
1299 qla2x00_free_fcport(fcport);
1300 }
1301
1302 return rval;
1303}
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317int
1318qlafx00_configure_devices(scsi_qla_host_t *vha)
1319{
1320 int rval;
1321 unsigned long flags;
1322
1323 rval = QLA_SUCCESS;
1324
1325 flags = vha->dpc_flags;
1326
1327 ql_dbg(ql_dbg_disc, vha, 0x2090,
1328 "Configure devices -- dpc flags =0x%lx\n", flags);
1329
1330 rval = qlafx00_configure_all_targets(vha);
1331
1332 if (rval == QLA_SUCCESS) {
1333 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1334 rval = QLA_FUNCTION_FAILED;
1335 } else {
1336 atomic_set(&vha->loop_state, LOOP_READY);
1337 ql_log(ql_log_info, vha, 0x2091,
1338 "Device Ready\n");
1339 }
1340 }
1341
1342 if (rval) {
1343 ql_dbg(ql_dbg_disc, vha, 0x2092,
1344 "%s *** FAILED ***.\n", __func__);
1345 } else {
1346 ql_dbg(ql_dbg_disc, vha, 0x2093,
1347 "%s: exiting normally.\n", __func__);
1348 }
1349 return rval;
1350}
1351
1352static void
1353qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha, bool critemp)
1354{
1355 struct qla_hw_data *ha = vha->hw;
1356 fc_port_t *fcport;
1357
1358 vha->flags.online = 0;
1359 ha->mr.fw_hbt_en = 0;
1360
1361 if (!critemp) {
1362 ha->flags.chip_reset_done = 0;
1363 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1364 vha->qla_stats.total_isp_aborts++;
1365 ql_log(ql_log_info, vha, 0x013f,
1366 "Performing ISP error recovery - ha = %p.\n", ha);
1367 ha->isp_ops->reset_chip(vha);
1368 }
1369
1370 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
1371 atomic_set(&vha->loop_state, LOOP_DOWN);
1372 atomic_set(&vha->loop_down_timer,
1373 QLAFX00_LOOP_DOWN_TIME);
1374 } else {
1375 if (!atomic_read(&vha->loop_down_timer))
1376 atomic_set(&vha->loop_down_timer,
1377 QLAFX00_LOOP_DOWN_TIME);
1378 }
1379
1380
1381 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1382 fcport->flags = 0;
1383 if (atomic_read(&fcport->state) == FCS_ONLINE)
1384 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1385 }
1386
1387 if (!ha->flags.eeh_busy) {
1388 if (critemp) {
1389 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
1390 } else {
1391
1392 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
1393 }
1394 }
1395
1396 qla2x00_free_irqs(vha);
1397 if (critemp)
1398 set_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags);
1399 else
1400 set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1401
1402
1403 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1404
1405 ql_log(ql_log_info, vha, 0x0140,
1406 "%s Done done - ha=%p.\n", __func__, ha);
1407}
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418void
1419qlafx00_init_response_q_entries(struct rsp_que *rsp)
1420{
1421 uint16_t cnt;
1422 response_t *pkt;
1423
1424 rsp->ring_ptr = rsp->ring;
1425 rsp->ring_index = 0;
1426 rsp->status_srb = NULL;
1427 pkt = rsp->ring_ptr;
1428 for (cnt = 0; cnt < rsp->length; cnt++) {
1429 pkt->signature = RESPONSE_PROCESSED;
1430 wrt_reg_dword((void __force __iomem *)&pkt->signature,
1431 RESPONSE_PROCESSED);
1432 pkt++;
1433 }
1434}
1435
1436int
1437qlafx00_rescan_isp(scsi_qla_host_t *vha)
1438{
1439 uint32_t status = QLA_FUNCTION_FAILED;
1440 struct qla_hw_data *ha = vha->hw;
1441 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
1442 uint32_t aenmbx7;
1443
1444 qla2x00_request_irqs(ha, ha->rsp_q_map[0]);
1445
1446 aenmbx7 = rd_reg_dword(®->aenmailbox7);
1447 ha->mbx_intr_code = MSW(aenmbx7);
1448 ha->rqstq_intr_code = LSW(aenmbx7);
1449 ha->req_que_off = rd_reg_dword(®->aenmailbox1);
1450 ha->rsp_que_off = rd_reg_dword(®->aenmailbox3);
1451 ha->req_que_len = rd_reg_dword(®->aenmailbox5);
1452 ha->rsp_que_len = rd_reg_dword(®->aenmailbox6);
1453
1454 ql_dbg(ql_dbg_disc, vha, 0x2094,
1455 "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x "
1456 " Req que offset 0x%x Rsp que offset 0x%x\n",
1457 ha->mbx_intr_code, ha->rqstq_intr_code,
1458 ha->req_que_off, ha->rsp_que_len);
1459
1460
1461 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1462
1463 status = qla2x00_init_rings(vha);
1464 if (!status) {
1465 vha->flags.online = 1;
1466
1467
1468 if ((vha->device_flags & DFLG_NO_CABLE))
1469 status = 0;
1470
1471 if (qlafx00_fx_disc(vha,
1472 &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO))
1473 ql_dbg(ql_dbg_disc, vha, 0x2095,
1474 "failed to register host info\n");
1475 }
1476 scsi_unblock_requests(vha->host);
1477 return status;
1478}
1479
1480void
1481qlafx00_timer_routine(scsi_qla_host_t *vha)
1482{
1483 struct qla_hw_data *ha = vha->hw;
1484 uint32_t fw_heart_beat;
1485 uint32_t aenmbx0;
1486 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
1487 uint32_t tempc;
1488
1489
1490 if (ha->mr.fw_hbt_cnt)
1491 ha->mr.fw_hbt_cnt--;
1492 else {
1493 if ((!ha->flags.mr_reset_hdlr_active) &&
1494 (!test_bit(UNLOADING, &vha->dpc_flags)) &&
1495 (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
1496 (ha->mr.fw_hbt_en)) {
1497 fw_heart_beat = rd_reg_dword(®->fwheartbeat);
1498 if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) {
1499 ha->mr.old_fw_hbt_cnt = fw_heart_beat;
1500 ha->mr.fw_hbt_miss_cnt = 0;
1501 } else {
1502 ha->mr.fw_hbt_miss_cnt++;
1503 if (ha->mr.fw_hbt_miss_cnt ==
1504 QLAFX00_HEARTBEAT_MISS_CNT) {
1505 set_bit(ISP_ABORT_NEEDED,
1506 &vha->dpc_flags);
1507 qla2xxx_wake_dpc(vha);
1508 ha->mr.fw_hbt_miss_cnt = 0;
1509 }
1510 }
1511 }
1512 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
1513 }
1514
1515 if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) {
1516
1517 aenmbx0 = rd_reg_dword(®->aenmailbox0);
1518 if (ha->mr.fw_reset_timer_exp) {
1519 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1520 qla2xxx_wake_dpc(vha);
1521 ha->mr.fw_reset_timer_exp = 0;
1522 } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) {
1523
1524 set_bit(FX00_TARGET_SCAN, &vha->dpc_flags);
1525 clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1526 qla2xxx_wake_dpc(vha);
1527 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1528 } else if ((aenmbx0 == MBA_FW_STARTING) &&
1529 (!ha->mr.fw_hbt_en)) {
1530 ha->mr.fw_hbt_en = 1;
1531 } else if (!ha->mr.fw_reset_timer_tick) {
1532 if (aenmbx0 == ha->mr.old_aenmbx0_state)
1533 ha->mr.fw_reset_timer_exp = 1;
1534 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1535 } else if (aenmbx0 == 0xFFFFFFFF) {
1536 uint32_t data0, data1;
1537
1538 data0 = QLAFX00_RD_REG(ha,
1539 QLAFX00_BAR1_BASE_ADDR_REG);
1540 data1 = QLAFX00_RD_REG(ha,
1541 QLAFX00_PEX0_WIN0_BASE_ADDR_REG);
1542
1543 data0 &= 0xffff0000;
1544 data1 &= 0x0000ffff;
1545
1546 QLAFX00_WR_REG(ha,
1547 QLAFX00_PEX0_WIN0_BASE_ADDR_REG,
1548 (data0 | data1));
1549 } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) {
1550 ha->mr.fw_reset_timer_tick =
1551 QLAFX00_MAX_RESET_INTERVAL;
1552 } else if (aenmbx0 == MBA_FW_RESET_FCT) {
1553 ha->mr.fw_reset_timer_tick =
1554 QLAFX00_MAX_RESET_INTERVAL;
1555 }
1556 if (ha->mr.old_aenmbx0_state != aenmbx0) {
1557 ha->mr.old_aenmbx0_state = aenmbx0;
1558 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1559 }
1560 ha->mr.fw_reset_timer_tick--;
1561 }
1562 if (test_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags)) {
1563
1564
1565
1566
1567 if (ha->mr.fw_critemp_timer_tick == 0) {
1568 tempc = QLAFX00_GET_TEMPERATURE(ha);
1569 ql_dbg(ql_dbg_timer, vha, 0x6012,
1570 "ISPFx00(%s): Critical temp timer, "
1571 "current SOC temperature: %d\n",
1572 __func__, tempc);
1573 if (tempc < ha->mr.critical_temperature) {
1574 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1575 clear_bit(FX00_CRITEMP_RECOVERY,
1576 &vha->dpc_flags);
1577 qla2xxx_wake_dpc(vha);
1578 }
1579 ha->mr.fw_critemp_timer_tick =
1580 QLAFX00_CRITEMP_INTERVAL;
1581 } else {
1582 ha->mr.fw_critemp_timer_tick--;
1583 }
1584 }
1585 if (ha->mr.host_info_resend) {
1586
1587
1588
1589
1590 if (ha->mr.hinfo_resend_timer_tick == 0) {
1591 ha->mr.host_info_resend = false;
1592 set_bit(FX00_HOST_INFO_RESEND, &vha->dpc_flags);
1593 ha->mr.hinfo_resend_timer_tick =
1594 QLAFX00_HINFO_RESEND_INTERVAL;
1595 qla2xxx_wake_dpc(vha);
1596 } else {
1597 ha->mr.hinfo_resend_timer_tick--;
1598 }
1599 }
1600
1601}
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613int
1614qlafx00_reset_initialize(scsi_qla_host_t *vha)
1615{
1616 struct qla_hw_data *ha = vha->hw;
1617
1618 if (vha->device_flags & DFLG_DEV_FAILED) {
1619 ql_dbg(ql_dbg_init, vha, 0x0142,
1620 "Device in failed state\n");
1621 return QLA_SUCCESS;
1622 }
1623
1624 ha->flags.mr_reset_hdlr_active = 1;
1625
1626 if (vha->flags.online) {
1627 scsi_block_requests(vha->host);
1628 qlafx00_abort_isp_cleanup(vha, false);
1629 }
1630
1631 ql_log(ql_log_info, vha, 0x0143,
1632 "(%s): succeeded.\n", __func__);
1633 ha->flags.mr_reset_hdlr_active = 0;
1634 return QLA_SUCCESS;
1635}
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647int
1648qlafx00_abort_isp(scsi_qla_host_t *vha)
1649{
1650 struct qla_hw_data *ha = vha->hw;
1651
1652 if (vha->flags.online) {
1653 if (unlikely(pci_channel_offline(ha->pdev) &&
1654 ha->flags.pci_channel_io_perm_failure)) {
1655 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1656 return QLA_SUCCESS;
1657 }
1658
1659 scsi_block_requests(vha->host);
1660 qlafx00_abort_isp_cleanup(vha, false);
1661 } else {
1662 scsi_block_requests(vha->host);
1663 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1664 vha->qla_stats.total_isp_aborts++;
1665 ha->isp_ops->reset_chip(vha);
1666 set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1667
1668 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1669 }
1670
1671 ql_log(ql_log_info, vha, 0x0145,
1672 "(%s): succeeded.\n", __func__);
1673
1674 return QLA_SUCCESS;
1675}
1676
1677static inline fc_port_t*
1678qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id)
1679{
1680 fc_port_t *fcport;
1681
1682
1683 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1684 if (fcport->tgt_id == tgt_id) {
1685 ql_dbg(ql_dbg_async, vha, 0x5072,
1686 "Matching fcport(%p) found with TGT-ID: 0x%x "
1687 "and Remote TGT_ID: 0x%x\n",
1688 fcport, fcport->tgt_id, tgt_id);
1689 return fcport;
1690 }
1691 }
1692 return NULL;
1693}
1694
1695static void
1696qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id)
1697{
1698 fc_port_t *fcport;
1699
1700 ql_log(ql_log_info, vha, 0x5073,
1701 "Detach TGT-ID: 0x%x\n", tgt_id);
1702
1703 fcport = qlafx00_get_fcport(vha, tgt_id);
1704 if (!fcport)
1705 return;
1706
1707 qla2x00_mark_device_lost(vha, fcport, 0);
1708
1709 return;
1710}
1711
1712void
1713qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt)
1714{
1715 uint32_t aen_code, aen_data;
1716
1717 aen_code = FCH_EVT_VENDOR_UNIQUE;
1718 aen_data = evt->u.aenfx.evtcode;
1719
1720 switch (evt->u.aenfx.evtcode) {
1721 case QLAFX00_MBA_PORT_UPDATE:
1722 if (evt->u.aenfx.mbx[1] == 0) {
1723 if (evt->u.aenfx.mbx[2] == 1) {
1724 if (!vha->flags.fw_tgt_reported)
1725 vha->flags.fw_tgt_reported = 1;
1726 atomic_set(&vha->loop_down_timer, 0);
1727 atomic_set(&vha->loop_state, LOOP_UP);
1728 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1729 qla2xxx_wake_dpc(vha);
1730 } else if (evt->u.aenfx.mbx[2] == 2) {
1731 qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]);
1732 }
1733 } else if (evt->u.aenfx.mbx[1] == 0xffff) {
1734 if (evt->u.aenfx.mbx[2] == 1) {
1735 if (!vha->flags.fw_tgt_reported)
1736 vha->flags.fw_tgt_reported = 1;
1737 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1738 } else if (evt->u.aenfx.mbx[2] == 2) {
1739 vha->device_flags |= DFLG_NO_CABLE;
1740 qla2x00_mark_all_devices_lost(vha);
1741 }
1742 }
1743 break;
1744 case QLAFX00_MBA_LINK_UP:
1745 aen_code = FCH_EVT_LINKUP;
1746 aen_data = 0;
1747 break;
1748 case QLAFX00_MBA_LINK_DOWN:
1749 aen_code = FCH_EVT_LINKDOWN;
1750 aen_data = 0;
1751 break;
1752 case QLAFX00_MBA_TEMP_CRIT:
1753 ql_log(ql_log_info, vha, 0x5082,
1754 "Process critical temperature event "
1755 "aenmb[0]: %x\n",
1756 evt->u.aenfx.evtcode);
1757 scsi_block_requests(vha->host);
1758 qlafx00_abort_isp_cleanup(vha, true);
1759 scsi_unblock_requests(vha->host);
1760 break;
1761 }
1762
1763 fc_host_post_event(vha->host, fc_get_event_number(),
1764 aen_code, aen_data);
1765}
1766
1767static void
1768qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo)
1769{
1770 u64 port_name = 0, node_name = 0;
1771
1772 port_name = (unsigned long long)wwn_to_u64(pinfo->port_name);
1773 node_name = (unsigned long long)wwn_to_u64(pinfo->node_name);
1774
1775 fc_host_node_name(vha->host) = node_name;
1776 fc_host_port_name(vha->host) = port_name;
1777 if (!pinfo->port_type)
1778 vha->hw->current_topology = ISP_CFG_F;
1779 if (pinfo->link_status == QLAFX00_LINK_STATUS_UP)
1780 atomic_set(&vha->loop_state, LOOP_READY);
1781 else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN)
1782 atomic_set(&vha->loop_state, LOOP_DOWN);
1783 vha->hw->link_data_rate = (uint16_t)pinfo->link_config;
1784}
1785
1786static void
1787qla2x00_fxdisc_iocb_timeout(void *data)
1788{
1789 srb_t *sp = data;
1790 struct srb_iocb *lio = &sp->u.iocb_cmd;
1791
1792 complete(&lio->u.fxiocb.fxiocb_comp);
1793}
1794
1795static void qla2x00_fxdisc_sp_done(srb_t *sp, int res)
1796{
1797 struct srb_iocb *lio = &sp->u.iocb_cmd;
1798
1799 complete(&lio->u.fxiocb.fxiocb_comp);
1800}
1801
1802int
1803qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
1804{
1805 srb_t *sp;
1806 struct srb_iocb *fdisc;
1807 int rval = QLA_FUNCTION_FAILED;
1808 struct qla_hw_data *ha = vha->hw;
1809 struct host_system_info *phost_info;
1810 struct register_host_info *preg_hsi;
1811 struct new_utsname *p_sysid = NULL;
1812
1813 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1814 if (!sp)
1815 goto done;
1816
1817 sp->type = SRB_FXIOCB_DCMD;
1818 sp->name = "fxdisc";
1819
1820 fdisc = &sp->u.iocb_cmd;
1821 fdisc->timeout = qla2x00_fxdisc_iocb_timeout;
1822 qla2x00_init_timer(sp, FXDISC_TIMEOUT);
1823
1824 switch (fx_type) {
1825 case FXDISC_GET_CONFIG_INFO:
1826 fdisc->u.fxiocb.flags =
1827 SRB_FXDISC_RESP_DMA_VALID;
1828 fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data);
1829 break;
1830 case FXDISC_GET_PORT_INFO:
1831 fdisc->u.fxiocb.flags =
1832 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1833 fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO;
1834 fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id);
1835 break;
1836 case FXDISC_GET_TGT_NODE_INFO:
1837 fdisc->u.fxiocb.flags =
1838 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1839 fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO;
1840 fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id);
1841 break;
1842 case FXDISC_GET_TGT_NODE_LIST:
1843 fdisc->u.fxiocb.flags =
1844 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1845 fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE;
1846 break;
1847 case FXDISC_REG_HOST_INFO:
1848 fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID;
1849 fdisc->u.fxiocb.req_len = sizeof(struct register_host_info);
1850 p_sysid = utsname();
1851 if (!p_sysid) {
1852 ql_log(ql_log_warn, vha, 0x303c,
1853 "Not able to get the system information\n");
1854 goto done_free_sp;
1855 }
1856 break;
1857 case FXDISC_ABORT_IOCTL:
1858 default:
1859 break;
1860 }
1861
1862 if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
1863 fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev,
1864 fdisc->u.fxiocb.req_len,
1865 &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL);
1866 if (!fdisc->u.fxiocb.req_addr)
1867 goto done_free_sp;
1868
1869 if (fx_type == FXDISC_REG_HOST_INFO) {
1870 preg_hsi = (struct register_host_info *)
1871 fdisc->u.fxiocb.req_addr;
1872 phost_info = &preg_hsi->hsi;
1873 memset(preg_hsi, 0, sizeof(struct register_host_info));
1874 phost_info->os_type = OS_TYPE_LINUX;
1875 strlcpy(phost_info->sysname, p_sysid->sysname,
1876 sizeof(phost_info->sysname));
1877 strlcpy(phost_info->nodename, p_sysid->nodename,
1878 sizeof(phost_info->nodename));
1879 if (!strcmp(phost_info->nodename, "(none)"))
1880 ha->mr.host_info_resend = true;
1881 strlcpy(phost_info->release, p_sysid->release,
1882 sizeof(phost_info->release));
1883 strlcpy(phost_info->version, p_sysid->version,
1884 sizeof(phost_info->version));
1885 strlcpy(phost_info->machine, p_sysid->machine,
1886 sizeof(phost_info->machine));
1887 strlcpy(phost_info->domainname, p_sysid->domainname,
1888 sizeof(phost_info->domainname));
1889 strlcpy(phost_info->hostdriver, QLA2XXX_VERSION,
1890 sizeof(phost_info->hostdriver));
1891 preg_hsi->utc = (uint64_t)ktime_get_real_seconds();
1892 ql_dbg(ql_dbg_init, vha, 0x0149,
1893 "ISP%04X: Host registration with firmware\n",
1894 ha->pdev->device);
1895 ql_dbg(ql_dbg_init, vha, 0x014a,
1896 "os_type = '%d', sysname = '%s', nodname = '%s'\n",
1897 phost_info->os_type,
1898 phost_info->sysname,
1899 phost_info->nodename);
1900 ql_dbg(ql_dbg_init, vha, 0x014b,
1901 "release = '%s', version = '%s'\n",
1902 phost_info->release,
1903 phost_info->version);
1904 ql_dbg(ql_dbg_init, vha, 0x014c,
1905 "machine = '%s' "
1906 "domainname = '%s', hostdriver = '%s'\n",
1907 phost_info->machine,
1908 phost_info->domainname,
1909 phost_info->hostdriver);
1910 ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
1911 phost_info, sizeof(*phost_info));
1912 }
1913 }
1914
1915 if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
1916 fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev,
1917 fdisc->u.fxiocb.rsp_len,
1918 &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL);
1919 if (!fdisc->u.fxiocb.rsp_addr)
1920 goto done_unmap_req;
1921 }
1922
1923 fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type);
1924 sp->done = qla2x00_fxdisc_sp_done;
1925
1926 rval = qla2x00_start_sp(sp);
1927 if (rval != QLA_SUCCESS)
1928 goto done_unmap_dma;
1929
1930 wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp);
1931
1932 if (fx_type == FXDISC_GET_CONFIG_INFO) {
1933 struct config_info_data *pinfo =
1934 (struct config_info_data *) fdisc->u.fxiocb.rsp_addr;
1935 strlcpy(vha->hw->model_number, pinfo->model_num,
1936 ARRAY_SIZE(vha->hw->model_number));
1937 strlcpy(vha->hw->model_desc, pinfo->model_description,
1938 ARRAY_SIZE(vha->hw->model_desc));
1939 memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name,
1940 sizeof(vha->hw->mr.symbolic_name));
1941 memcpy(&vha->hw->mr.serial_num, pinfo->serial_num,
1942 sizeof(vha->hw->mr.serial_num));
1943 memcpy(&vha->hw->mr.hw_version, pinfo->hw_version,
1944 sizeof(vha->hw->mr.hw_version));
1945 memcpy(&vha->hw->mr.fw_version, pinfo->fw_version,
1946 sizeof(vha->hw->mr.fw_version));
1947 strim(vha->hw->mr.fw_version);
1948 memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version,
1949 sizeof(vha->hw->mr.uboot_version));
1950 memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num,
1951 sizeof(vha->hw->mr.fru_serial_num));
1952 vha->hw->mr.critical_temperature =
1953 (pinfo->nominal_temp_value) ?
1954 pinfo->nominal_temp_value : QLAFX00_CRITEMP_THRSHLD;
1955 ha->mr.extended_io_enabled = (pinfo->enabled_capabilities &
1956 QLAFX00_EXTENDED_IO_EN_MASK) != 0;
1957 } else if (fx_type == FXDISC_GET_PORT_INFO) {
1958 struct port_info_data *pinfo =
1959 (struct port_info_data *) fdisc->u.fxiocb.rsp_addr;
1960 memcpy(vha->node_name, pinfo->node_name, WWN_SIZE);
1961 memcpy(vha->port_name, pinfo->port_name, WWN_SIZE);
1962 vha->d_id.b.domain = pinfo->port_id[0];
1963 vha->d_id.b.area = pinfo->port_id[1];
1964 vha->d_id.b.al_pa = pinfo->port_id[2];
1965 qlafx00_update_host_attr(vha, pinfo);
1966 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
1967 pinfo, 16);
1968 } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
1969 struct qlafx00_tgt_node_info *pinfo =
1970 (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
1971 memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE);
1972 memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
1973 fcport->port_type = FCT_TARGET;
1974 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
1975 pinfo, 16);
1976 } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
1977 struct qlafx00_tgt_node_info *pinfo =
1978 (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
1979 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
1980 pinfo, 16);
1981 memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
1982 } else if (fx_type == FXDISC_ABORT_IOCTL)
1983 fdisc->u.fxiocb.result =
1984 (fdisc->u.fxiocb.result ==
1985 cpu_to_le32(QLAFX00_IOCTL_ICOB_ABORT_SUCCESS)) ?
1986 cpu_to_le32(QLA_SUCCESS) : cpu_to_le32(QLA_FUNCTION_FAILED);
1987
1988 rval = le32_to_cpu(fdisc->u.fxiocb.result);
1989
1990done_unmap_dma:
1991 if (fdisc->u.fxiocb.rsp_addr)
1992 dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len,
1993 fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle);
1994
1995done_unmap_req:
1996 if (fdisc->u.fxiocb.req_addr)
1997 dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len,
1998 fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle);
1999done_free_sp:
2000 sp->free(sp);
2001done:
2002 return rval;
2003}
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015int
2016qlafx00_initialize_adapter(scsi_qla_host_t *vha)
2017{
2018 int rval;
2019 struct qla_hw_data *ha = vha->hw;
2020 uint32_t tempc;
2021
2022
2023 vha->flags.online = 0;
2024 ha->flags.chip_reset_done = 0;
2025 vha->flags.reset_active = 0;
2026 ha->flags.pci_channel_io_perm_failure = 0;
2027 ha->flags.eeh_busy = 0;
2028 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
2029 atomic_set(&vha->loop_state, LOOP_DOWN);
2030 vha->device_flags = DFLG_NO_CABLE;
2031 vha->dpc_flags = 0;
2032 vha->flags.management_server_logged_in = 0;
2033 ha->isp_abort_cnt = 0;
2034 ha->beacon_blink_led = 0;
2035
2036 set_bit(0, ha->req_qid_map);
2037 set_bit(0, ha->rsp_qid_map);
2038
2039 ql_dbg(ql_dbg_init, vha, 0x0147,
2040 "Configuring PCI space...\n");
2041
2042 rval = ha->isp_ops->pci_config(vha);
2043 if (rval) {
2044 ql_log(ql_log_warn, vha, 0x0148,
2045 "Unable to configure PCI space.\n");
2046 return rval;
2047 }
2048
2049 rval = qlafx00_init_fw_ready(vha);
2050 if (rval != QLA_SUCCESS)
2051 return rval;
2052
2053 qlafx00_save_queue_ptrs(vha);
2054
2055 rval = qlafx00_config_queues(vha);
2056 if (rval != QLA_SUCCESS)
2057 return rval;
2058
2059
2060
2061
2062
2063 rval = qla2x00_alloc_outstanding_cmds(ha, vha->req);
2064 if (rval != QLA_SUCCESS)
2065 return rval;
2066
2067 rval = qla2x00_init_rings(vha);
2068 ha->flags.chip_reset_done = 1;
2069
2070 tempc = QLAFX00_GET_TEMPERATURE(ha);
2071 ql_dbg(ql_dbg_init, vha, 0x0152,
2072 "ISPFx00(%s): Critical temp timer, current SOC temperature: 0x%x\n",
2073 __func__, tempc);
2074
2075 return rval;
2076}
2077
2078uint32_t
2079qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr,
2080 char *buf)
2081{
2082 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
2083 int rval = QLA_FUNCTION_FAILED;
2084 uint32_t state[1];
2085
2086 if (qla2x00_reset_active(vha))
2087 ql_log(ql_log_warn, vha, 0x70ce,
2088 "ISP reset active.\n");
2089 else if (!vha->hw->flags.eeh_busy) {
2090 rval = qlafx00_get_firmware_state(vha, state);
2091 }
2092 if (rval != QLA_SUCCESS)
2093 memset(state, -1, sizeof(state));
2094
2095 return state[0];
2096}
2097
2098void
2099qlafx00_get_host_speed(struct Scsi_Host *shost)
2100{
2101 struct qla_hw_data *ha = ((struct scsi_qla_host *)
2102 (shost_priv(shost)))->hw;
2103 u32 speed = FC_PORTSPEED_UNKNOWN;
2104
2105 switch (ha->link_data_rate) {
2106 case QLAFX00_PORT_SPEED_2G:
2107 speed = FC_PORTSPEED_2GBIT;
2108 break;
2109 case QLAFX00_PORT_SPEED_4G:
2110 speed = FC_PORTSPEED_4GBIT;
2111 break;
2112 case QLAFX00_PORT_SPEED_8G:
2113 speed = FC_PORTSPEED_8GBIT;
2114 break;
2115 case QLAFX00_PORT_SPEED_10G:
2116 speed = FC_PORTSPEED_10GBIT;
2117 break;
2118 }
2119 fc_host_speed(shost) = speed;
2120}
2121
2122
2123
2124static inline void
2125qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
2126 uint32_t sense_len, struct rsp_que *rsp, int res)
2127{
2128 struct scsi_qla_host *vha = sp->vha;
2129 struct scsi_cmnd *cp = GET_CMD_SP(sp);
2130 uint32_t track_sense_len;
2131
2132 SET_FW_SENSE_LEN(sp, sense_len);
2133
2134 if (sense_len >= SCSI_SENSE_BUFFERSIZE)
2135 sense_len = SCSI_SENSE_BUFFERSIZE;
2136
2137 SET_CMD_SENSE_LEN(sp, sense_len);
2138 SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
2139 track_sense_len = sense_len;
2140
2141 if (sense_len > par_sense_len)
2142 sense_len = par_sense_len;
2143
2144 memcpy(cp->sense_buffer, sense_data, sense_len);
2145
2146 SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len);
2147
2148 SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
2149 track_sense_len -= sense_len;
2150 SET_CMD_SENSE_LEN(sp, track_sense_len);
2151
2152 ql_dbg(ql_dbg_io, vha, 0x304d,
2153 "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n",
2154 sense_len, par_sense_len, track_sense_len);
2155 if (GET_FW_SENSE_LEN(sp) > 0) {
2156 rsp->status_srb = sp;
2157 cp->result = res;
2158 }
2159
2160 if (sense_len) {
2161 ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039,
2162 "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
2163 sp->vha->host_no, cp->device->id, cp->device->lun,
2164 cp);
2165 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049,
2166 cp->sense_buffer, sense_len);
2167 }
2168}
2169
2170static void
2171qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
2172 struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp,
2173 __le16 sstatus, __le16 cpstatus)
2174{
2175 struct srb_iocb *tmf;
2176
2177 tmf = &sp->u.iocb_cmd;
2178 if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) ||
2179 (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID)))
2180 cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE);
2181 tmf->u.tmf.comp_status = cpstatus;
2182 sp->done(sp, 0);
2183}
2184
2185static void
2186qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
2187 struct abort_iocb_entry_fx00 *pkt)
2188{
2189 const char func[] = "ABT_IOCB";
2190 srb_t *sp;
2191 struct srb_iocb *abt;
2192
2193 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2194 if (!sp)
2195 return;
2196
2197 abt = &sp->u.iocb_cmd;
2198 abt->u.abt.comp_status = pkt->tgt_id_sts;
2199 sp->done(sp, 0);
2200}
2201
2202static void
2203qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
2204 struct ioctl_iocb_entry_fx00 *pkt)
2205{
2206 const char func[] = "IOSB_IOCB";
2207 srb_t *sp;
2208 struct bsg_job *bsg_job;
2209 struct fc_bsg_reply *bsg_reply;
2210 struct srb_iocb *iocb_job;
2211 int res = 0;
2212 struct qla_mt_iocb_rsp_fx00 fstatus;
2213 uint8_t *fw_sts_ptr;
2214
2215 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2216 if (!sp)
2217 return;
2218
2219 if (sp->type == SRB_FXIOCB_DCMD) {
2220 iocb_job = &sp->u.iocb_cmd;
2221 iocb_job->u.fxiocb.seq_number = pkt->seq_no;
2222 iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags;
2223 iocb_job->u.fxiocb.result = pkt->status;
2224 if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID)
2225 iocb_job->u.fxiocb.req_data =
2226 pkt->dataword_r;
2227 } else {
2228 bsg_job = sp->u.bsg_job;
2229 bsg_reply = bsg_job->reply;
2230
2231 memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00));
2232
2233 fstatus.reserved_1 = pkt->reserved_0;
2234 fstatus.func_type = pkt->comp_func_num;
2235 fstatus.ioctl_flags = pkt->fw_iotcl_flags;
2236 fstatus.ioctl_data = pkt->dataword_r;
2237 fstatus.adapid = pkt->adapid;
2238 fstatus.reserved_2 = pkt->dataword_r_extra;
2239 fstatus.res_count = pkt->residuallen;
2240 fstatus.status = pkt->status;
2241 fstatus.seq_number = pkt->seq_no;
2242 memcpy(fstatus.reserved_3,
2243 pkt->reserved_2, 20 * sizeof(uint8_t));
2244
2245 fw_sts_ptr = bsg_job->reply + sizeof(struct fc_bsg_reply);
2246
2247 memcpy(fw_sts_ptr, &fstatus, sizeof(fstatus));
2248 bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
2249 sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
2250
2251 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
2252 sp->vha, 0x5080, pkt, sizeof(*pkt));
2253
2254 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
2255 sp->vha, 0x5074,
2256 fw_sts_ptr, sizeof(fstatus));
2257
2258 res = bsg_reply->result = DID_OK << 16;
2259 bsg_reply->reply_payload_rcv_len =
2260 bsg_job->reply_payload.payload_len;
2261 }
2262 sp->done(sp, res);
2263}
2264
2265
2266
2267
2268
2269
2270
2271static void
2272qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
2273{
2274 srb_t *sp;
2275 fc_port_t *fcport;
2276 struct scsi_cmnd *cp;
2277 struct sts_entry_fx00 *sts;
2278 __le16 comp_status;
2279 __le16 scsi_status;
2280 __le16 lscsi_status;
2281 int32_t resid;
2282 uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
2283 fw_resid_len;
2284 uint8_t *rsp_info = NULL, *sense_data = NULL;
2285 struct qla_hw_data *ha = vha->hw;
2286 uint32_t hindex, handle;
2287 uint16_t que;
2288 struct req_que *req;
2289 int logit = 1;
2290 int res = 0;
2291
2292 sts = (struct sts_entry_fx00 *) pkt;
2293
2294 comp_status = sts->comp_status;
2295 scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK);
2296 hindex = sts->handle;
2297 handle = LSW(hindex);
2298
2299 que = MSW(hindex);
2300 req = ha->req_q_map[que];
2301
2302
2303 if (handle < req->num_outstanding_cmds)
2304 sp = req->outstanding_cmds[handle];
2305 else
2306 sp = NULL;
2307
2308 if (sp == NULL) {
2309 ql_dbg(ql_dbg_io, vha, 0x3034,
2310 "Invalid status handle (0x%x).\n", handle);
2311
2312 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2313 qla2xxx_wake_dpc(vha);
2314 return;
2315 }
2316
2317 if (sp->type == SRB_TM_CMD) {
2318 req->outstanding_cmds[handle] = NULL;
2319 qlafx00_tm_iocb_entry(vha, req, pkt, sp,
2320 scsi_status, comp_status);
2321 return;
2322 }
2323
2324
2325 if (comp_status == CS_COMPLETE && scsi_status == 0) {
2326 qla2x00_process_completed_request(vha, req, handle);
2327 return;
2328 }
2329
2330 req->outstanding_cmds[handle] = NULL;
2331 cp = GET_CMD_SP(sp);
2332 if (cp == NULL) {
2333 ql_dbg(ql_dbg_io, vha, 0x3048,
2334 "Command already returned (0x%x/%p).\n",
2335 handle, sp);
2336
2337 return;
2338 }
2339
2340 lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK);
2341
2342 fcport = sp->fcport;
2343
2344 sense_len = par_sense_len = rsp_info_len = resid_len =
2345 fw_resid_len = 0;
2346 if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))
2347 sense_len = sts->sense_len;
2348 if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
2349 | (uint16_t)SS_RESIDUAL_OVER)))
2350 resid_len = le32_to_cpu(sts->residual_len);
2351 if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN))
2352 fw_resid_len = le32_to_cpu(sts->residual_len);
2353 rsp_info = sense_data = sts->data;
2354 par_sense_len = sizeof(sts->data);
2355
2356
2357 if (comp_status == CS_COMPLETE &&
2358 scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER))
2359 comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN);
2360
2361
2362
2363
2364 switch (le16_to_cpu(comp_status)) {
2365 case CS_COMPLETE:
2366 case CS_QUEUE_FULL:
2367 if (scsi_status == 0) {
2368 res = DID_OK << 16;
2369 break;
2370 }
2371 if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
2372 | (uint16_t)SS_RESIDUAL_OVER))) {
2373 resid = resid_len;
2374 scsi_set_resid(cp, resid);
2375
2376 if (!lscsi_status &&
2377 ((unsigned)(scsi_bufflen(cp) - resid) <
2378 cp->underflow)) {
2379 ql_dbg(ql_dbg_io, fcport->vha, 0x3050,
2380 "Mid-layer underflow "
2381 "detected (0x%x of 0x%x bytes).\n",
2382 resid, scsi_bufflen(cp));
2383
2384 res = DID_ERROR << 16;
2385 break;
2386 }
2387 }
2388 res = DID_OK << 16 | le16_to_cpu(lscsi_status);
2389
2390 if (lscsi_status ==
2391 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
2392 ql_dbg(ql_dbg_io, fcport->vha, 0x3051,
2393 "QUEUE FULL detected.\n");
2394 break;
2395 }
2396 logit = 0;
2397 if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
2398 break;
2399
2400 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
2401 if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
2402 break;
2403
2404 qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len,
2405 rsp, res);
2406 break;
2407
2408 case CS_DATA_UNDERRUN:
2409
2410 if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
2411 resid = fw_resid_len;
2412 else
2413 resid = resid_len;
2414 scsi_set_resid(cp, resid);
2415 if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) {
2416 if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
2417 && fw_resid_len != resid_len) {
2418 ql_dbg(ql_dbg_io, fcport->vha, 0x3052,
2419 "Dropped frame(s) detected "
2420 "(0x%x of 0x%x bytes).\n",
2421 resid, scsi_bufflen(cp));
2422
2423 res = DID_ERROR << 16 |
2424 le16_to_cpu(lscsi_status);
2425 goto check_scsi_status;
2426 }
2427
2428 if (!lscsi_status &&
2429 ((unsigned)(scsi_bufflen(cp) - resid) <
2430 cp->underflow)) {
2431 ql_dbg(ql_dbg_io, fcport->vha, 0x3053,
2432 "Mid-layer underflow "
2433 "detected (0x%x of 0x%x bytes, "
2434 "cp->underflow: 0x%x).\n",
2435 resid, scsi_bufflen(cp), cp->underflow);
2436
2437 res = DID_ERROR << 16;
2438 break;
2439 }
2440 } else if (lscsi_status !=
2441 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) &&
2442 lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) {
2443
2444
2445
2446
2447
2448 ql_dbg(ql_dbg_io, fcport->vha, 0x3054,
2449 "Dropped frame(s) detected (0x%x "
2450 "of 0x%x bytes).\n", resid,
2451 scsi_bufflen(cp));
2452
2453 res = DID_ERROR << 16 | le16_to_cpu(lscsi_status);
2454 goto check_scsi_status;
2455 } else {
2456 ql_dbg(ql_dbg_io, fcport->vha, 0x3055,
2457 "scsi_status: 0x%x, lscsi_status: 0x%x\n",
2458 scsi_status, lscsi_status);
2459 }
2460
2461 res = DID_OK << 16 | le16_to_cpu(lscsi_status);
2462 logit = 0;
2463
2464check_scsi_status:
2465
2466
2467
2468
2469 if (lscsi_status != 0) {
2470 if (lscsi_status ==
2471 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
2472 ql_dbg(ql_dbg_io, fcport->vha, 0x3056,
2473 "QUEUE FULL detected.\n");
2474 logit = 1;
2475 break;
2476 }
2477 if (lscsi_status !=
2478 cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
2479 break;
2480
2481 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
2482 if (!(scsi_status &
2483 cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
2484 break;
2485
2486 qlafx00_handle_sense(sp, sense_data, par_sense_len,
2487 sense_len, rsp, res);
2488 }
2489 break;
2490
2491 case CS_PORT_LOGGED_OUT:
2492 case CS_PORT_CONFIG_CHG:
2493 case CS_PORT_BUSY:
2494 case CS_INCOMPLETE:
2495 case CS_PORT_UNAVAILABLE:
2496 case CS_TIMEOUT:
2497 case CS_RESET:
2498
2499
2500
2501
2502
2503
2504 res = DID_TRANSPORT_DISRUPTED << 16;
2505
2506 ql_dbg(ql_dbg_io, fcport->vha, 0x3057,
2507 "Port down status: port-state=0x%x.\n",
2508 atomic_read(&fcport->state));
2509
2510 if (atomic_read(&fcport->state) == FCS_ONLINE)
2511 qla2x00_mark_device_lost(fcport->vha, fcport, 1);
2512 break;
2513
2514 case CS_ABORTED:
2515 res = DID_RESET << 16;
2516 break;
2517
2518 default:
2519 res = DID_ERROR << 16;
2520 break;
2521 }
2522
2523 if (logit)
2524 ql_dbg(ql_dbg_io, fcport->vha, 0x3058,
2525 "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
2526 "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x "
2527 "rsp_info=%p resid=0x%x fw_resid=0x%x sense_len=0x%x, "
2528 "par_sense_len=0x%x, rsp_info_len=0x%x\n",
2529 comp_status, scsi_status, res, vha->host_no,
2530 cp->device->id, cp->device->lun, fcport->tgt_id,
2531 lscsi_status, cp->cmnd, scsi_bufflen(cp),
2532 rsp_info, resid_len, fw_resid_len, sense_len,
2533 par_sense_len, rsp_info_len);
2534
2535 if (rsp->status_srb == NULL)
2536 sp->done(sp, res);
2537 else
2538 WARN_ON_ONCE(true);
2539}
2540
2541
2542
2543
2544
2545
2546
2547
2548static void
2549qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
2550{
2551 uint8_t sense_sz = 0;
2552 struct qla_hw_data *ha = rsp->hw;
2553 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
2554 srb_t *sp = rsp->status_srb;
2555 struct scsi_cmnd *cp;
2556 uint32_t sense_len;
2557 uint8_t *sense_ptr;
2558
2559 if (!sp) {
2560 ql_dbg(ql_dbg_io, vha, 0x3037,
2561 "no SP, sp = %p\n", sp);
2562 return;
2563 }
2564
2565 if (!GET_FW_SENSE_LEN(sp)) {
2566 ql_dbg(ql_dbg_io, vha, 0x304b,
2567 "no fw sense data, sp = %p\n", sp);
2568 return;
2569 }
2570 cp = GET_CMD_SP(sp);
2571 if (cp == NULL) {
2572 ql_log(ql_log_warn, vha, 0x303b,
2573 "cmd is NULL: already returned to OS (sp=%p).\n", sp);
2574
2575 rsp->status_srb = NULL;
2576 return;
2577 }
2578
2579 if (!GET_CMD_SENSE_LEN(sp)) {
2580 ql_dbg(ql_dbg_io, vha, 0x304c,
2581 "no sense data, sp = %p\n", sp);
2582 } else {
2583 sense_len = GET_CMD_SENSE_LEN(sp);
2584 sense_ptr = GET_CMD_SENSE_PTR(sp);
2585 ql_dbg(ql_dbg_io, vha, 0x304f,
2586 "sp=%p sense_len=0x%x sense_ptr=%p.\n",
2587 sp, sense_len, sense_ptr);
2588
2589 if (sense_len > sizeof(pkt->data))
2590 sense_sz = sizeof(pkt->data);
2591 else
2592 sense_sz = sense_len;
2593
2594
2595 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
2596 pkt, sizeof(*pkt));
2597 memcpy(sense_ptr, pkt->data, sense_sz);
2598 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
2599 sense_ptr, sense_sz);
2600
2601 sense_len -= sense_sz;
2602 sense_ptr += sense_sz;
2603
2604 SET_CMD_SENSE_PTR(sp, sense_ptr);
2605 SET_CMD_SENSE_LEN(sp, sense_len);
2606 }
2607 sense_len = GET_FW_SENSE_LEN(sp);
2608 sense_len = (sense_len > sizeof(pkt->data)) ?
2609 (sense_len - sizeof(pkt->data)) : 0;
2610 SET_FW_SENSE_LEN(sp, sense_len);
2611
2612
2613 if (sense_len == 0) {
2614 rsp->status_srb = NULL;
2615 sp->done(sp, cp->result);
2616 } else {
2617 WARN_ON_ONCE(true);
2618 }
2619}
2620
2621
2622
2623
2624
2625
2626
2627static void
2628qlafx00_multistatus_entry(struct scsi_qla_host *vha,
2629 struct rsp_que *rsp, void *pkt)
2630{
2631 srb_t *sp;
2632 struct multi_sts_entry_fx00 *stsmfx;
2633 struct qla_hw_data *ha = vha->hw;
2634 uint32_t handle, hindex, handle_count, i;
2635 uint16_t que;
2636 struct req_que *req;
2637 __le32 *handle_ptr;
2638
2639 stsmfx = (struct multi_sts_entry_fx00 *) pkt;
2640
2641 handle_count = stsmfx->handle_count;
2642
2643 if (handle_count > MAX_HANDLE_COUNT) {
2644 ql_dbg(ql_dbg_io, vha, 0x3035,
2645 "Invalid handle count (0x%x).\n", handle_count);
2646 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2647 qla2xxx_wake_dpc(vha);
2648 return;
2649 }
2650
2651 handle_ptr = &stsmfx->handles[0];
2652
2653 for (i = 0; i < handle_count; i++) {
2654 hindex = le32_to_cpu(*handle_ptr);
2655 handle = LSW(hindex);
2656 que = MSW(hindex);
2657 req = ha->req_q_map[que];
2658
2659
2660 if (handle < req->num_outstanding_cmds)
2661 sp = req->outstanding_cmds[handle];
2662 else
2663 sp = NULL;
2664
2665 if (sp == NULL) {
2666 ql_dbg(ql_dbg_io, vha, 0x3044,
2667 "Invalid status handle (0x%x).\n", handle);
2668 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2669 qla2xxx_wake_dpc(vha);
2670 return;
2671 }
2672 qla2x00_process_completed_request(vha, req, handle);
2673 handle_ptr++;
2674 }
2675}
2676
2677
2678
2679
2680
2681
2682
2683static void
2684qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp,
2685 struct sts_entry_fx00 *pkt)
2686{
2687 srb_t *sp;
2688 struct qla_hw_data *ha = vha->hw;
2689 const char func[] = "ERROR-IOCB";
2690 uint16_t que = 0;
2691 struct req_que *req = NULL;
2692 int res = DID_ERROR << 16;
2693
2694 req = ha->req_q_map[que];
2695
2696 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2697 if (sp) {
2698 sp->done(sp, res);
2699 return;
2700 }
2701
2702 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2703 qla2xxx_wake_dpc(vha);
2704}
2705
2706
2707
2708
2709
2710
2711static void
2712qlafx00_process_response_queue(struct scsi_qla_host *vha,
2713 struct rsp_que *rsp)
2714{
2715 struct sts_entry_fx00 *pkt;
2716 response_t *lptr;
2717 uint16_t lreq_q_in = 0;
2718 uint16_t lreq_q_out = 0;
2719
2720 lreq_q_in = rd_reg_dword(rsp->rsp_q_in);
2721 lreq_q_out = rsp->ring_index;
2722
2723 while (lreq_q_in != lreq_q_out) {
2724 lptr = rsp->ring_ptr;
2725 memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr,
2726 sizeof(rsp->rsp_pkt));
2727 pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt;
2728
2729 rsp->ring_index++;
2730 lreq_q_out++;
2731 if (rsp->ring_index == rsp->length) {
2732 lreq_q_out = 0;
2733 rsp->ring_index = 0;
2734 rsp->ring_ptr = rsp->ring;
2735 } else {
2736 rsp->ring_ptr++;
2737 }
2738
2739 if (pkt->entry_status != 0 &&
2740 pkt->entry_type != IOCTL_IOSB_TYPE_FX00) {
2741 ql_dbg(ql_dbg_async, vha, 0x507f,
2742 "type of error status in response: 0x%x\n",
2743 pkt->entry_status);
2744 qlafx00_error_entry(vha, rsp,
2745 (struct sts_entry_fx00 *)pkt);
2746 continue;
2747 }
2748
2749 switch (pkt->entry_type) {
2750 case STATUS_TYPE_FX00:
2751 qlafx00_status_entry(vha, rsp, pkt);
2752 break;
2753
2754 case STATUS_CONT_TYPE_FX00:
2755 qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
2756 break;
2757
2758 case MULTI_STATUS_TYPE_FX00:
2759 qlafx00_multistatus_entry(vha, rsp, pkt);
2760 break;
2761
2762 case ABORT_IOCB_TYPE_FX00:
2763 qlafx00_abort_iocb_entry(vha, rsp->req,
2764 (struct abort_iocb_entry_fx00 *)pkt);
2765 break;
2766
2767 case IOCTL_IOSB_TYPE_FX00:
2768 qlafx00_ioctl_iosb_entry(vha, rsp->req,
2769 (struct ioctl_iocb_entry_fx00 *)pkt);
2770 break;
2771 default:
2772
2773 ql_dbg(ql_dbg_async, vha, 0x5081,
2774 "Received unknown response pkt type %x "
2775 "entry status=%x.\n",
2776 pkt->entry_type, pkt->entry_status);
2777 break;
2778 }
2779 }
2780
2781
2782 wrt_reg_dword(rsp->rsp_q_out, rsp->ring_index);
2783}
2784
2785
2786
2787
2788
2789static void
2790qlafx00_async_event(scsi_qla_host_t *vha)
2791{
2792 struct qla_hw_data *ha = vha->hw;
2793 struct device_reg_fx00 __iomem *reg;
2794 int data_size = 1;
2795
2796 reg = &ha->iobase->ispfx00;
2797
2798 switch (ha->aenmb[0]) {
2799 case QLAFX00_MBA_SYSTEM_ERR:
2800 ql_log(ql_log_warn, vha, 0x5079,
2801 "ISP System Error - mbx1=%x\n", ha->aenmb[0]);
2802 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2803 break;
2804
2805 case QLAFX00_MBA_SHUTDOWN_RQSTD:
2806 ql_dbg(ql_dbg_async, vha, 0x5076,
2807 "Asynchronous FW shutdown requested.\n");
2808 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2809 qla2xxx_wake_dpc(vha);
2810 break;
2811
2812 case QLAFX00_MBA_PORT_UPDATE:
2813 ha->aenmb[1] = rd_reg_dword(®->aenmailbox1);
2814 ha->aenmb[2] = rd_reg_dword(®->aenmailbox2);
2815 ha->aenmb[3] = rd_reg_dword(®->aenmailbox3);
2816 ql_dbg(ql_dbg_async, vha, 0x5077,
2817 "Asynchronous port Update received "
2818 "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n",
2819 ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]);
2820 data_size = 4;
2821 break;
2822
2823 case QLAFX00_MBA_TEMP_OVER:
2824 ql_log(ql_log_info, vha, 0x5085,
2825 "Asynchronous over temperature event received "
2826 "aenmb[0]: %x\n",
2827 ha->aenmb[0]);
2828 break;
2829
2830 case QLAFX00_MBA_TEMP_NORM:
2831 ql_log(ql_log_info, vha, 0x5086,
2832 "Asynchronous normal temperature event received "
2833 "aenmb[0]: %x\n",
2834 ha->aenmb[0]);
2835 break;
2836
2837 case QLAFX00_MBA_TEMP_CRIT:
2838 ql_log(ql_log_info, vha, 0x5083,
2839 "Asynchronous critical temperature event received "
2840 "aenmb[0]: %x\n",
2841 ha->aenmb[0]);
2842 break;
2843
2844 default:
2845 ha->aenmb[1] = rd_reg_dword(®->aenmailbox1);
2846 ha->aenmb[2] = rd_reg_dword(®->aenmailbox2);
2847 ha->aenmb[3] = rd_reg_dword(®->aenmailbox3);
2848 ha->aenmb[4] = rd_reg_dword(®->aenmailbox4);
2849 ha->aenmb[5] = rd_reg_dword(®->aenmailbox5);
2850 ha->aenmb[6] = rd_reg_dword(®->aenmailbox6);
2851 ha->aenmb[7] = rd_reg_dword(®->aenmailbox7);
2852 ql_dbg(ql_dbg_async, vha, 0x5078,
2853 "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n",
2854 ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3],
2855 ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]);
2856 break;
2857 }
2858 qlafx00_post_aenfx_work(vha, ha->aenmb[0],
2859 (uint32_t *)ha->aenmb, data_size);
2860}
2861
2862
2863
2864
2865
2866
2867static void
2868qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0)
2869{
2870 uint16_t cnt;
2871 __le32 __iomem *wptr;
2872 struct qla_hw_data *ha = vha->hw;
2873 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
2874
2875 if (!ha->mcp32)
2876 ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n");
2877
2878
2879 ha->flags.mbox_int = 1;
2880 ha->mailbox_out32[0] = mb0;
2881 wptr = ®->mailbox17;
2882
2883 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
2884 ha->mailbox_out32[cnt] = rd_reg_dword(wptr);
2885 wptr++;
2886 }
2887}
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898irqreturn_t
2899qlafx00_intr_handler(int irq, void *dev_id)
2900{
2901 scsi_qla_host_t *vha;
2902 struct qla_hw_data *ha;
2903 struct device_reg_fx00 __iomem *reg;
2904 int status;
2905 unsigned long iter;
2906 uint32_t stat;
2907 uint32_t mb[8];
2908 struct rsp_que *rsp;
2909 unsigned long flags;
2910 uint32_t clr_intr = 0;
2911 uint32_t intr_stat = 0;
2912
2913 rsp = (struct rsp_que *) dev_id;
2914 if (!rsp) {
2915 ql_log(ql_log_info, NULL, 0x507d,
2916 "%s: NULL response queue pointer.\n", __func__);
2917 return IRQ_NONE;
2918 }
2919
2920 ha = rsp->hw;
2921 reg = &ha->iobase->ispfx00;
2922 status = 0;
2923
2924 if (unlikely(pci_channel_offline(ha->pdev)))
2925 return IRQ_HANDLED;
2926
2927 spin_lock_irqsave(&ha->hardware_lock, flags);
2928 vha = pci_get_drvdata(ha->pdev);
2929 for (iter = 50; iter--; clr_intr = 0) {
2930 stat = QLAFX00_RD_INTR_REG(ha);
2931 if (qla2x00_check_reg32_for_disconnect(vha, stat))
2932 break;
2933 intr_stat = stat & QLAFX00_HST_INT_STS_BITS;
2934 if (!intr_stat)
2935 break;
2936
2937 if (stat & QLAFX00_INTR_MB_CMPLT) {
2938 mb[0] = rd_reg_dword(®->mailbox16);
2939 qlafx00_mbx_completion(vha, mb[0]);
2940 status |= MBX_INTERRUPT;
2941 clr_intr |= QLAFX00_INTR_MB_CMPLT;
2942 }
2943 if (intr_stat & QLAFX00_INTR_ASYNC_CMPLT) {
2944 ha->aenmb[0] = rd_reg_dword(®->aenmailbox0);
2945 qlafx00_async_event(vha);
2946 clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
2947 }
2948 if (intr_stat & QLAFX00_INTR_RSP_CMPLT) {
2949 qlafx00_process_response_queue(vha, rsp);
2950 clr_intr |= QLAFX00_INTR_RSP_CMPLT;
2951 }
2952
2953 QLAFX00_CLR_INTR_REG(ha, clr_intr);
2954 QLAFX00_RD_INTR_REG(ha);
2955 }
2956
2957 qla2x00_handle_mbx_completion(ha, status);
2958 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2959
2960 return IRQ_HANDLED;
2961}
2962
2963
2964
2965static inline cont_a64_entry_t *
2966qlafx00_prep_cont_type1_iocb(struct req_que *req,
2967 cont_a64_entry_t *lcont_pkt)
2968{
2969 cont_a64_entry_t *cont_pkt;
2970
2971
2972 req->ring_index++;
2973 if (req->ring_index == req->length) {
2974 req->ring_index = 0;
2975 req->ring_ptr = req->ring;
2976 } else {
2977 req->ring_ptr++;
2978 }
2979
2980 cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
2981
2982
2983 lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00;
2984
2985 return cont_pkt;
2986}
2987
2988static inline void
2989qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
2990 uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt)
2991{
2992 uint16_t avail_dsds;
2993 struct dsd64 *cur_dsd;
2994 scsi_qla_host_t *vha;
2995 struct scsi_cmnd *cmd;
2996 struct scatterlist *sg;
2997 int i, cont;
2998 struct req_que *req;
2999 cont_a64_entry_t lcont_pkt;
3000 cont_a64_entry_t *cont_pkt;
3001
3002 vha = sp->vha;
3003 req = vha->req;
3004
3005 cmd = GET_CMD_SP(sp);
3006 cont = 0;
3007 cont_pkt = NULL;
3008
3009
3010 lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7;
3011
3012
3013 if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
3014 lcmd_pkt->byte_count = cpu_to_le32(0);
3015 return;
3016 }
3017
3018
3019 if (cmd->sc_data_direction == DMA_TO_DEVICE) {
3020 lcmd_pkt->cntrl_flags = TMF_WRITE_DATA;
3021 vha->qla_stats.output_bytes += scsi_bufflen(cmd);
3022 } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
3023 lcmd_pkt->cntrl_flags = TMF_READ_DATA;
3024 vha->qla_stats.input_bytes += scsi_bufflen(cmd);
3025 }
3026
3027
3028 avail_dsds = 1;
3029 cur_dsd = &lcmd_pkt->dsd;
3030
3031
3032 scsi_for_each_sg(cmd, sg, tot_dsds, i) {
3033
3034 if (avail_dsds == 0) {
3035
3036
3037
3038
3039 memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE);
3040 cont_pkt =
3041 qlafx00_prep_cont_type1_iocb(req, &lcont_pkt);
3042 cur_dsd = lcont_pkt.dsd;
3043 avail_dsds = 5;
3044 cont = 1;
3045 }
3046
3047 append_dsd64(&cur_dsd, sg);
3048 avail_dsds--;
3049 if (avail_dsds == 0 && cont == 1) {
3050 cont = 0;
3051 memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
3052 sizeof(lcont_pkt));
3053 }
3054
3055 }
3056 if (avail_dsds != 0 && cont == 1) {
3057 memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
3058 sizeof(lcont_pkt));
3059 }
3060}
3061
3062
3063
3064
3065
3066
3067
3068int
3069qlafx00_start_scsi(srb_t *sp)
3070{
3071 int nseg;
3072 unsigned long flags;
3073 uint32_t handle;
3074 uint16_t cnt;
3075 uint16_t req_cnt;
3076 uint16_t tot_dsds;
3077 struct req_que *req = NULL;
3078 struct rsp_que *rsp = NULL;
3079 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
3080 struct scsi_qla_host *vha = sp->vha;
3081 struct qla_hw_data *ha = vha->hw;
3082 struct cmd_type_7_fx00 *cmd_pkt;
3083 struct cmd_type_7_fx00 lcmd_pkt;
3084 struct scsi_lun llun;
3085
3086
3087 rsp = ha->rsp_q_map[0];
3088 req = vha->req;
3089
3090
3091 tot_dsds = 0;
3092
3093
3094 spin_lock_irqsave(&ha->hardware_lock, flags);
3095
3096 handle = qla2xxx_get_next_handle(req);
3097 if (handle == 0)
3098 goto queuing_error;
3099
3100
3101 if (scsi_sg_count(cmd)) {
3102 nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
3103 scsi_sg_count(cmd), cmd->sc_data_direction);
3104 if (unlikely(!nseg))
3105 goto queuing_error;
3106 } else
3107 nseg = 0;
3108
3109 tot_dsds = nseg;
3110 req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);
3111 if (req->cnt < (req_cnt + 2)) {
3112 cnt = rd_reg_dword_relaxed(req->req_q_out);
3113
3114 if (req->ring_index < cnt)
3115 req->cnt = cnt - req->ring_index;
3116 else
3117 req->cnt = req->length -
3118 (req->ring_index - cnt);
3119 if (req->cnt < (req_cnt + 2))
3120 goto queuing_error;
3121 }
3122
3123
3124 req->current_outstanding_cmd = handle;
3125 req->outstanding_cmds[handle] = sp;
3126 sp->handle = handle;
3127 cmd->host_scribble = (unsigned char *)(unsigned long)handle;
3128 req->cnt -= req_cnt;
3129
3130 cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr;
3131
3132 memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE);
3133
3134 lcmd_pkt.handle = make_handle(req->id, sp->handle);
3135 lcmd_pkt.reserved_0 = 0;
3136 lcmd_pkt.port_path_ctrl = 0;
3137 lcmd_pkt.reserved_1 = 0;
3138 lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds);
3139 lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id);
3140
3141 int_to_scsilun(cmd->device->lun, &llun);
3142 host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,
3143 sizeof(lcmd_pkt.lun));
3144
3145
3146 host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb));
3147 lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
3148
3149
3150 qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt);
3151
3152
3153 lcmd_pkt.entry_count = (uint8_t)req_cnt;
3154
3155
3156 lcmd_pkt.entry_status = (uint8_t) rsp->id;
3157
3158 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
3159 cmd->cmnd, cmd->cmd_len);
3160 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
3161 &lcmd_pkt, sizeof(lcmd_pkt));
3162
3163 memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
3164 wmb();
3165
3166
3167 req->ring_index++;
3168 if (req->ring_index == req->length) {
3169 req->ring_index = 0;
3170 req->ring_ptr = req->ring;
3171 } else
3172 req->ring_ptr++;
3173
3174 sp->flags |= SRB_DMA_VALID;
3175
3176
3177 wrt_reg_dword(req->req_q_in, req->ring_index);
3178 QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);
3179
3180 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3181 return QLA_SUCCESS;
3182
3183queuing_error:
3184 if (tot_dsds)
3185 scsi_dma_unmap(cmd);
3186
3187 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3188
3189 return QLA_FUNCTION_FAILED;
3190}
3191
3192void
3193qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb)
3194{
3195 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3196 scsi_qla_host_t *vha = sp->vha;
3197 struct req_que *req = vha->req;
3198 struct tsk_mgmt_entry_fx00 tm_iocb;
3199 struct scsi_lun llun;
3200
3201 memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00));
3202 tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00;
3203 tm_iocb.entry_count = 1;
3204 tm_iocb.handle = make_handle(req->id, sp->handle);
3205 tm_iocb.reserved_0 = 0;
3206 tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id);
3207 tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags);
3208 if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) {
3209 int_to_scsilun(fxio->u.tmf.lun, &llun);
3210 host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,
3211 sizeof(struct scsi_lun));
3212 }
3213
3214 memcpy(ptm_iocb, &tm_iocb,
3215 sizeof(struct tsk_mgmt_entry_fx00));
3216 wmb();
3217}
3218
3219void
3220qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb)
3221{
3222 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3223 scsi_qla_host_t *vha = sp->vha;
3224 struct req_que *req = vha->req;
3225 struct abort_iocb_entry_fx00 abt_iocb;
3226
3227 memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00));
3228 abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00;
3229 abt_iocb.entry_count = 1;
3230 abt_iocb.handle = make_handle(req->id, sp->handle);
3231 abt_iocb.abort_handle = make_handle(req->id, fxio->u.abt.cmd_hndl);
3232 abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id);
3233 abt_iocb.req_que_no = cpu_to_le16(req->id);
3234
3235 memcpy(pabt_iocb, &abt_iocb,
3236 sizeof(struct abort_iocb_entry_fx00));
3237 wmb();
3238}
3239
3240void
3241qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
3242{
3243 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3244 struct qla_mt_iocb_rqst_fx00 *piocb_rqst;
3245 struct bsg_job *bsg_job;
3246 struct fc_bsg_request *bsg_request;
3247 struct fxdisc_entry_fx00 fx_iocb;
3248 uint8_t entry_cnt = 1;
3249
3250 memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00));
3251 fx_iocb.entry_type = FX00_IOCB_TYPE;
3252 fx_iocb.handle = sp->handle;
3253 fx_iocb.entry_count = entry_cnt;
3254
3255 if (sp->type == SRB_FXIOCB_DCMD) {
3256 fx_iocb.func_num =
3257 sp->u.iocb_cmd.u.fxiocb.req_func_type;
3258 fx_iocb.adapid = fxio->u.fxiocb.adapter_id;
3259 fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi;
3260 fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0;
3261 fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1;
3262 fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra;
3263
3264 if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
3265 fx_iocb.req_dsdcnt = cpu_to_le16(1);
3266 fx_iocb.req_xfrcnt =
3267 cpu_to_le16(fxio->u.fxiocb.req_len);
3268 put_unaligned_le64(fxio->u.fxiocb.req_dma_handle,
3269 &fx_iocb.dseg_rq.address);
3270 fx_iocb.dseg_rq.length =
3271 cpu_to_le32(fxio->u.fxiocb.req_len);
3272 }
3273
3274 if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
3275 fx_iocb.rsp_dsdcnt = cpu_to_le16(1);
3276 fx_iocb.rsp_xfrcnt =
3277 cpu_to_le16(fxio->u.fxiocb.rsp_len);
3278 put_unaligned_le64(fxio->u.fxiocb.rsp_dma_handle,
3279 &fx_iocb.dseg_rsp.address);
3280 fx_iocb.dseg_rsp.length =
3281 cpu_to_le32(fxio->u.fxiocb.rsp_len);
3282 }
3283
3284 if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) {
3285 fx_iocb.dataword = fxio->u.fxiocb.req_data;
3286 }
3287 fx_iocb.flags = fxio->u.fxiocb.flags;
3288 } else {
3289 struct scatterlist *sg;
3290
3291 bsg_job = sp->u.bsg_job;
3292 bsg_request = bsg_job->request;
3293 piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *)
3294 &bsg_request->rqst_data.h_vendor.vendor_cmd[1];
3295
3296 fx_iocb.func_num = piocb_rqst->func_type;
3297 fx_iocb.adapid = piocb_rqst->adapid;
3298 fx_iocb.adapid_hi = piocb_rqst->adapid_hi;
3299 fx_iocb.reserved_0 = piocb_rqst->reserved_0;
3300 fx_iocb.reserved_1 = piocb_rqst->reserved_1;
3301 fx_iocb.dataword_extra = piocb_rqst->dataword_extra;
3302 fx_iocb.dataword = piocb_rqst->dataword;
3303 fx_iocb.req_xfrcnt = piocb_rqst->req_len;
3304 fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len;
3305
3306 if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) {
3307 int avail_dsds, tot_dsds;
3308 cont_a64_entry_t lcont_pkt;
3309 cont_a64_entry_t *cont_pkt = NULL;
3310 struct dsd64 *cur_dsd;
3311 int index = 0, cont = 0;
3312
3313 fx_iocb.req_dsdcnt =
3314 cpu_to_le16(bsg_job->request_payload.sg_cnt);
3315 tot_dsds =
3316 bsg_job->request_payload.sg_cnt;
3317 cur_dsd = &fx_iocb.dseg_rq;
3318 avail_dsds = 1;
3319 for_each_sg(bsg_job->request_payload.sg_list, sg,
3320 tot_dsds, index) {
3321
3322 if (avail_dsds == 0) {
3323
3324
3325
3326
3327 memset(&lcont_pkt, 0,
3328 REQUEST_ENTRY_SIZE);
3329 cont_pkt =
3330 qlafx00_prep_cont_type1_iocb(
3331 sp->vha->req, &lcont_pkt);
3332 cur_dsd = lcont_pkt.dsd;
3333 avail_dsds = 5;
3334 cont = 1;
3335 entry_cnt++;
3336 }
3337
3338 append_dsd64(&cur_dsd, sg);
3339 avail_dsds--;
3340
3341 if (avail_dsds == 0 && cont == 1) {
3342 cont = 0;
3343 memcpy_toio(
3344 (void __iomem *)cont_pkt,
3345 &lcont_pkt, REQUEST_ENTRY_SIZE);
3346 ql_dump_buffer(
3347 ql_dbg_user + ql_dbg_verbose,
3348 sp->vha, 0x3042,
3349 (uint8_t *)&lcont_pkt,
3350 REQUEST_ENTRY_SIZE);
3351 }
3352 }
3353 if (avail_dsds != 0 && cont == 1) {
3354 memcpy_toio((void __iomem *)cont_pkt,
3355 &lcont_pkt, REQUEST_ENTRY_SIZE);
3356 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3357 sp->vha, 0x3043,
3358 (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
3359 }
3360 }
3361
3362 if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) {
3363 int avail_dsds, tot_dsds;
3364 cont_a64_entry_t lcont_pkt;
3365 cont_a64_entry_t *cont_pkt = NULL;
3366 struct dsd64 *cur_dsd;
3367 int index = 0, cont = 0;
3368
3369 fx_iocb.rsp_dsdcnt =
3370 cpu_to_le16(bsg_job->reply_payload.sg_cnt);
3371 tot_dsds = bsg_job->reply_payload.sg_cnt;
3372 cur_dsd = &fx_iocb.dseg_rsp;
3373 avail_dsds = 1;
3374
3375 for_each_sg(bsg_job->reply_payload.sg_list, sg,
3376 tot_dsds, index) {
3377
3378 if (avail_dsds == 0) {
3379
3380
3381
3382
3383 memset(&lcont_pkt, 0,
3384 REQUEST_ENTRY_SIZE);
3385 cont_pkt =
3386 qlafx00_prep_cont_type1_iocb(
3387 sp->vha->req, &lcont_pkt);
3388 cur_dsd = lcont_pkt.dsd;
3389 avail_dsds = 5;
3390 cont = 1;
3391 entry_cnt++;
3392 }
3393
3394 append_dsd64(&cur_dsd, sg);
3395 avail_dsds--;
3396
3397 if (avail_dsds == 0 && cont == 1) {
3398 cont = 0;
3399 memcpy_toio((void __iomem *)cont_pkt,
3400 &lcont_pkt,
3401 REQUEST_ENTRY_SIZE);
3402 ql_dump_buffer(
3403 ql_dbg_user + ql_dbg_verbose,
3404 sp->vha, 0x3045,
3405 (uint8_t *)&lcont_pkt,
3406 REQUEST_ENTRY_SIZE);
3407 }
3408 }
3409 if (avail_dsds != 0 && cont == 1) {
3410 memcpy_toio((void __iomem *)cont_pkt,
3411 &lcont_pkt, REQUEST_ENTRY_SIZE);
3412 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3413 sp->vha, 0x3046,
3414 (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
3415 }
3416 }
3417
3418 if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID)
3419 fx_iocb.dataword = piocb_rqst->dataword;
3420 fx_iocb.flags = piocb_rqst->flags;
3421 fx_iocb.entry_count = entry_cnt;
3422 }
3423
3424 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3425 sp->vha, 0x3047, &fx_iocb, sizeof(fx_iocb));
3426
3427 memcpy_toio((void __iomem *)pfxiocb, &fx_iocb, sizeof(fx_iocb));
3428 wmb();
3429}
3430
