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5
6#ifndef __QLA_MR_H
7#define __QLA_MR_H
8
9#include "qla_dsd.h"
10
11
12
13
14#define PCI_DEVICE_ID_QLOGIC_ISPF001 0xF001
15
16
17
18#define FX00_COMMAND_TYPE_7 0x07
19struct cmd_type_7_fx00 {
20 uint8_t entry_type;
21 uint8_t entry_count;
22 uint8_t sys_define;
23 uint8_t entry_status;
24
25 uint32_t handle;
26 uint8_t reserved_0;
27 uint8_t port_path_ctrl;
28 uint16_t reserved_1;
29
30 __le16 tgt_idx;
31 uint16_t timeout;
32
33 __le16 dseg_count;
34 uint8_t scsi_rsp_dsd_len;
35 uint8_t reserved_2;
36
37 struct scsi_lun lun;
38
39 uint8_t cntrl_flags;
40
41 uint8_t task_mgmt_flags;
42
43 uint8_t task;
44
45 uint8_t crn;
46
47 uint8_t fcp_cdb[MAX_CMDSZ];
48 __le32 byte_count;
49
50 struct dsd64 dsd;
51};
52
53#define STATUS_TYPE_FX00 0x01
54struct sts_entry_fx00 {
55 uint8_t entry_type;
56 uint8_t entry_count;
57 uint8_t sys_define;
58 uint8_t entry_status;
59
60 uint32_t handle;
61 uint32_t reserved_3;
62
63 __le16 comp_status;
64 uint16_t reserved_0;
65
66 __le32 residual_len;
67
68 uint16_t reserved_1;
69 uint16_t state_flags;
70
71 uint16_t reserved_2;
72 __le16 scsi_status;
73
74 uint32_t sense_len;
75 uint8_t data[32];
76};
77
78
79#define MAX_HANDLE_COUNT 15
80#define MULTI_STATUS_TYPE_FX00 0x0D
81
82struct multi_sts_entry_fx00 {
83 uint8_t entry_type;
84 uint8_t entry_count;
85 uint8_t handle_count;
86 uint8_t entry_status;
87
88 __le32 handles[MAX_HANDLE_COUNT];
89};
90
91#define TSK_MGMT_IOCB_TYPE_FX00 0x05
92struct tsk_mgmt_entry_fx00 {
93 uint8_t entry_type;
94 uint8_t entry_count;
95 uint8_t sys_define;
96 uint8_t entry_status;
97
98 uint32_t handle;
99
100 uint32_t reserved_0;
101
102 __le16 tgt_id;
103
104 uint16_t reserved_1;
105 uint16_t reserved_3;
106 uint16_t reserved_4;
107
108 struct scsi_lun lun;
109
110 __le32 control_flags;
111
112 uint8_t reserved_2[32];
113};
114
115
116#define ABORT_IOCB_TYPE_FX00 0x08
117struct abort_iocb_entry_fx00 {
118 uint8_t entry_type;
119 uint8_t entry_count;
120 uint8_t sys_define;
121 uint8_t entry_status;
122
123 uint32_t handle;
124 __le32 reserved_0;
125
126 __le16 tgt_id_sts;
127 __le16 options;
128
129 uint32_t abort_handle;
130 __le32 reserved_2;
131
132 __le16 req_que_no;
133 uint8_t reserved_1[38];
134};
135
136#define IOCTL_IOSB_TYPE_FX00 0x0C
137struct ioctl_iocb_entry_fx00 {
138 uint8_t entry_type;
139 uint8_t entry_count;
140 uint8_t sys_define;
141 uint8_t entry_status;
142
143 uint32_t handle;
144 uint32_t reserved_0;
145
146 uint16_t comp_func_num;
147 __le16 fw_iotcl_flags;
148
149 __le32 dataword_r;
150 uint32_t adapid;
151 uint32_t dataword_r_extra;
152
153 __le32 seq_no;
154 uint8_t reserved_2[20];
155 uint32_t residuallen;
156 __le32 status;
157};
158
159#define STATUS_CONT_TYPE_FX00 0x04
160
161#define FX00_IOCB_TYPE 0x0B
162struct fxdisc_entry_fx00 {
163 uint8_t entry_type;
164 uint8_t entry_count;
165 uint8_t sys_define;
166 uint8_t entry_status;
167
168 uint32_t handle;
169 __le32 reserved_0;
170
171 __le16 func_num;
172 __le16 req_xfrcnt;
173 __le16 req_dsdcnt;
174 __le16 rsp_xfrcnt;
175 __le16 rsp_dsdcnt;
176 uint8_t flags;
177 uint8_t reserved_1;
178
179 struct dsd64 dseg_rq;
180 struct dsd64 dseg_rsp;
181
182 __le32 dataword;
183 __le32 adapid;
184 __le32 adapid_hi;
185 __le32 dataword_extra;
186};
187
188struct qlafx00_tgt_node_info {
189 uint8_t tgt_node_wwpn[WWN_SIZE];
190 uint8_t tgt_node_wwnn[WWN_SIZE];
191 uint32_t tgt_node_state;
192 uint8_t reserved[128];
193 uint32_t reserved_1[8];
194 uint64_t reserved_2[4];
195} __packed;
196
197#define QLAFX00_TGT_NODE_INFO sizeof(struct qlafx00_tgt_node_info)
198
199#define QLAFX00_LINK_STATUS_DOWN 0x10
200#define QLAFX00_LINK_STATUS_UP 0x11
201
202#define QLAFX00_PORT_SPEED_2G 0x2
203#define QLAFX00_PORT_SPEED_4G 0x4
204#define QLAFX00_PORT_SPEED_8G 0x8
205#define QLAFX00_PORT_SPEED_10G 0xa
206struct port_info_data {
207 uint8_t port_state;
208 uint8_t port_type;
209 uint16_t port_identifier;
210 uint32_t up_port_state;
211 uint8_t fw_ver_num[32];
212 uint8_t portal_attrib;
213 uint16_t host_option;
214 uint8_t reset_delay;
215 uint8_t pdwn_retry_cnt;
216 uint16_t max_luns2tgt;
217 uint8_t risc_ver;
218 uint8_t pconn_option;
219 uint16_t risc_option;
220 uint16_t max_frame_len;
221 uint16_t max_iocb_alloc;
222 uint16_t exec_throttle;
223 uint8_t retry_cnt;
224 uint8_t retry_delay;
225 uint8_t port_name[8];
226 uint8_t port_id[3];
227 uint8_t link_status;
228 uint8_t plink_rate;
229 uint32_t link_config;
230 uint16_t adap_haddr;
231 uint8_t tgt_disc;
232 uint8_t log_tout;
233 uint8_t node_name[8];
234 uint16_t erisc_opt1;
235 uint8_t resp_acc_tmr;
236 uint8_t intr_del_tmr;
237 uint8_t erisc_opt2;
238 uint8_t alt_port_name[8];
239 uint8_t alt_node_name[8];
240 uint8_t link_down_tout;
241 uint8_t conn_type;
242 uint8_t fc_fw_mode;
243 uint32_t uiReserved[48];
244} __packed;
245
246
247#define OS_TYPE_UNKNOWN 0
248#define OS_TYPE_LINUX 2
249
250
251#define SYSNAME_LENGTH 128
252#define NODENAME_LENGTH 64
253#define RELEASE_LENGTH 64
254#define VERSION_LENGTH 64
255#define MACHINE_LENGTH 64
256#define DOMNAME_LENGTH 64
257
258struct host_system_info {
259 uint32_t os_type;
260 char sysname[SYSNAME_LENGTH];
261 char nodename[NODENAME_LENGTH];
262 char release[RELEASE_LENGTH];
263 char version[VERSION_LENGTH];
264 char machine[MACHINE_LENGTH];
265 char domainname[DOMNAME_LENGTH];
266 char hostdriver[VERSION_LENGTH];
267 uint32_t reserved[64];
268} __packed;
269
270struct register_host_info {
271 struct host_system_info hsi;
272 uint64_t utc;
273 uint32_t reserved[64];
274} __packed;
275
276
277#define QLAFX00_PORT_DATA_INFO (sizeof(struct port_info_data))
278#define QLAFX00_TGT_NODE_LIST_SIZE (sizeof(uint32_t) * 32)
279
280struct config_info_data {
281 uint8_t model_num[16];
282 uint8_t model_description[80];
283 uint8_t reserved0[160];
284 uint8_t symbolic_name[64];
285 uint8_t serial_num[32];
286 uint8_t hw_version[16];
287 uint8_t fw_version[16];
288 uint8_t uboot_version[16];
289 uint8_t fru_serial_num[32];
290
291 uint8_t fc_port_count;
292 uint8_t iscsi_port_count;
293 uint8_t reserved1[2];
294
295 uint8_t mode;
296 uint8_t log_level;
297 uint8_t reserved2[2];
298
299 uint32_t log_size;
300
301 uint8_t tgt_pres_mode;
302 uint8_t iqn_flags;
303 uint8_t lun_mapping;
304
305 uint64_t adapter_id;
306
307 uint32_t cluster_key_len;
308 uint8_t cluster_key[16];
309
310 uint64_t cluster_master_id;
311 uint64_t cluster_slave_id;
312 uint8_t cluster_flags;
313 uint32_t enabled_capabilities;
314 uint32_t nominal_temp_value;
315} __packed;
316
317#define FXDISC_GET_CONFIG_INFO 0x01
318#define FXDISC_GET_PORT_INFO 0x02
319#define FXDISC_GET_TGT_NODE_INFO 0x80
320#define FXDISC_GET_TGT_NODE_LIST 0x81
321#define FXDISC_REG_HOST_INFO 0x99
322#define FXDISC_ABORT_IOCTL 0xff
323
324#define QLAFX00_HBA_ICNTRL_REG 0x20B08
325#define QLAFX00_ICR_ENB_MASK 0x80000000
326#define QLAFX00_ICR_DIS_MASK 0x7fffffff
327#define QLAFX00_HST_RST_REG 0x18264
328#define QLAFX00_SOC_TEMP_REG 0x184C4
329#define QLAFX00_HST_TO_HBA_REG 0x20A04
330#define QLAFX00_HBA_TO_HOST_REG 0x21B70
331#define QLAFX00_HST_INT_STS_BITS 0x7
332#define QLAFX00_BAR1_BASE_ADDR_REG 0x40018
333#define QLAFX00_PEX0_WIN0_BASE_ADDR_REG 0x41824
334
335#define QLAFX00_INTR_MB_CMPLT 0x1
336#define QLAFX00_INTR_RSP_CMPLT 0x2
337#define QLAFX00_INTR_ASYNC_CMPLT 0x4
338
339#define QLAFX00_MBA_SYSTEM_ERR 0x8002
340#define QLAFX00_MBA_TEMP_OVER 0x8005
341#define QLAFX00_MBA_TEMP_NORM 0x8006
342#define QLAFX00_MBA_TEMP_CRIT 0x8007
343#define QLAFX00_MBA_LINK_UP 0x8011
344#define QLAFX00_MBA_LINK_DOWN 0x8012
345#define QLAFX00_MBA_PORT_UPDATE 0x8014
346#define QLAFX00_MBA_SHUTDOWN_RQSTD 0x8062
347
348#define SOC_SW_RST_CONTROL_REG_CORE0 0x0020800
349#define SOC_FABRIC_RST_CONTROL_REG 0x0020840
350#define SOC_FABRIC_CONTROL_REG 0x0020200
351#define SOC_FABRIC_CONFIG_REG 0x0020204
352#define SOC_PWR_MANAGEMENT_PWR_DOWN_REG 0x001820C
353
354#define SOC_INTERRUPT_SOURCE_I_CONTROL_REG 0x0020B00
355#define SOC_CORE_TIMER_REG 0x0021850
356#define SOC_IRQ_ACK_REG 0x00218b4
357
358#define CONTINUE_A64_TYPE_FX00 0x03
359
360#define QLAFX00_SET_HST_INTR(ha, value) \
361 wrt_reg_dword((ha)->cregbase + QLAFX00_HST_TO_HBA_REG, \
362 value)
363
364#define QLAFX00_CLR_HST_INTR(ha, value) \
365 wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
366 ~value)
367
368#define QLAFX00_RD_INTR_REG(ha) \
369 rd_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)
370
371#define QLAFX00_CLR_INTR_REG(ha, value) \
372 wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
373 ~value)
374
375#define QLAFX00_SET_HBA_SOC_REG(ha, off, val)\
376 wrt_reg_dword((ha)->cregbase + off, val)
377
378#define QLAFX00_GET_HBA_SOC_REG(ha, off)\
379 rd_reg_dword((ha)->cregbase + off)
380
381#define QLAFX00_HBA_RST_REG(ha, val)\
382 wrt_reg_dword((ha)->cregbase + QLAFX00_HST_RST_REG, val)
383
384#define QLAFX00_RD_ICNTRL_REG(ha) \
385 rd_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)
386
387#define QLAFX00_ENABLE_ICNTRL_REG(ha) \
388 wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
389 (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) | \
390 QLAFX00_ICR_ENB_MASK))
391
392#define QLAFX00_DISABLE_ICNTRL_REG(ha) \
393 wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
394 (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) & \
395 QLAFX00_ICR_DIS_MASK))
396
397#define QLAFX00_RD_REG(ha, off) \
398 rd_reg_dword((ha)->cregbase + off)
399
400#define QLAFX00_WR_REG(ha, off, val) \
401 wrt_reg_dword((ha)->cregbase + off, val)
402
403struct qla_mt_iocb_rqst_fx00 {
404 __le32 reserved_0;
405
406 __le16 func_type;
407 uint8_t flags;
408 uint8_t reserved_1;
409
410 __le32 dataword;
411
412 __le32 adapid;
413 __le32 adapid_hi;
414
415 __le32 dataword_extra;
416
417 __le16 req_len;
418 __le16 reserved_2;
419
420 __le16 rsp_len;
421 __le16 reserved_3;
422};
423
424struct qla_mt_iocb_rsp_fx00 {
425 uint32_t reserved_1;
426
427 uint16_t func_type;
428 __le16 ioctl_flags;
429
430 __le32 ioctl_data;
431
432 uint32_t adapid;
433 uint32_t adapid_hi;
434
435 uint32_t reserved_2;
436 __le32 seq_number;
437
438 uint8_t reserved_3[20];
439
440 int32_t res_count;
441
442 __le32 status;
443};
444
445
446#define MAILBOX_REGISTER_COUNT_FX00 16
447#define AEN_MAILBOX_REGISTER_COUNT_FX00 8
448#define MAX_FIBRE_DEVICES_FX00 512
449#define MAX_LUNS_FX00 0x1024
450#define MAX_TARGETS_FX00 MAX_ISA_DEVICES
451#define REQUEST_ENTRY_CNT_FX00 512
452#define RESPONSE_ENTRY_CNT_FX00 256
453
454
455
456
457#define FSTATE_FX00_CONFIG_WAIT 0x0000
458
459
460#define FSTATE_FX00_INITIALIZED 0x1000
461
462
463
464#define FX00_DEF_RATOV 10
465
466struct mr_data_fx00 {
467 uint8_t symbolic_name[64];
468 uint8_t serial_num[32];
469 uint8_t hw_version[16];
470 uint8_t fw_version[16];
471 uint8_t uboot_version[16];
472 uint8_t fru_serial_num[32];
473 fc_port_t fcport;
474
475
476
477 uint8_t fw_hbt_en;
478 uint8_t fw_hbt_cnt;
479 uint8_t fw_hbt_miss_cnt;
480 uint32_t old_fw_hbt_cnt;
481 uint16_t fw_reset_timer_tick;
482 uint8_t fw_reset_timer_exp;
483 uint16_t fw_critemp_timer_tick;
484 uint32_t old_aenmbx0_state;
485 uint32_t critical_temperature;
486 bool extended_io_enabled;
487 bool host_info_resend;
488 uint8_t hinfo_resend_timer_tick;
489};
490
491#define QLAFX00_EXTENDED_IO_EN_MASK 0x20
492
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503
504
505#define QLAFX00_GET_TEMPERATURE(ha) ((3153000 - (10000 * \
506 ((QLAFX00_RD_REG(ha, QLAFX00_SOC_TEMP_REG) & 0x3FE) >> 1))) / 13825)
507
508
509#define QLAFX00_LOOP_DOWN_TIME 615
510#define QLAFX00_HEARTBEAT_INTERVAL 6
511#define QLAFX00_HEARTBEAT_MISS_CNT 3
512#define QLAFX00_RESET_INTERVAL 120
513#define QLAFX00_MAX_RESET_INTERVAL 600
514#define QLAFX00_CRITEMP_INTERVAL 60
515#define QLAFX00_HINFO_RESEND_INTERVAL 60
516
517#define QLAFX00_CRITEMP_THRSHLD 80
518
519
520#define QLAFX00_MAX_CANQUEUE 1024
521
522
523#define QLAFX00_IOCTL_ICOB_ABORT_SUCCESS 0x68
524
525#endif
526
