1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18#include <linux/delay.h>
19#include <linux/dma-mapping.h>
20#include <linux/fsl_devices.h>
21#include <linux/gpio/consumer.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/kernel.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/mutex.h>
28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_platform.h>
32#include <linux/platform_device.h>
33#include <linux/spi/spi.h>
34#include <linux/spi/spi_bitbang.h>
35#include <linux/types.h>
36
37#ifdef CONFIG_FSL_SOC
38#include <sysdev/fsl_soc.h>
39#endif
40
41
42#define IMMR_SPI_CS_OFFSET 0x14c
43#define SPI_BOOT_SEL_BIT 0x80000000
44
45#include "spi-fsl-lib.h"
46#include "spi-fsl-cpm.h"
47#include "spi-fsl-spi.h"
48
49#define TYPE_FSL 0
50#define TYPE_GRLIB 1
51
52struct fsl_spi_match_data {
53 int type;
54};
55
56static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
57 .type = TYPE_FSL,
58};
59
60static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
61 .type = TYPE_GRLIB,
62};
63
64static const struct of_device_id of_fsl_spi_match[] = {
65 {
66 .compatible = "fsl,spi",
67 .data = &of_fsl_spi_fsl_config,
68 },
69 {
70 .compatible = "aeroflexgaisler,spictrl",
71 .data = &of_fsl_spi_grlib_config,
72 },
73 {}
74};
75MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
76
77static int fsl_spi_get_type(struct device *dev)
78{
79 const struct of_device_id *match;
80
81 if (dev->of_node) {
82 match = of_match_node(of_fsl_spi_match, dev->of_node);
83 if (match && match->data)
84 return ((struct fsl_spi_match_data *)match->data)->type;
85 }
86 return TYPE_FSL;
87}
88
89static void fsl_spi_change_mode(struct spi_device *spi)
90{
91 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
92 struct spi_mpc8xxx_cs *cs = spi->controller_state;
93 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
94 __be32 __iomem *mode = ®_base->mode;
95 unsigned long flags;
96
97 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
98 return;
99
100
101 local_irq_save(flags);
102
103
104 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
105
106
107 if (mspi->flags & SPI_CPM_MODE) {
108 fsl_spi_cpm_reinit_txrx(mspi);
109 }
110 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
111 local_irq_restore(flags);
112}
113
114static void fsl_spi_chipselect(struct spi_device *spi, int value)
115{
116 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
117 struct fsl_spi_platform_data *pdata;
118 struct spi_mpc8xxx_cs *cs = spi->controller_state;
119
120 pdata = spi->dev.parent->parent->platform_data;
121
122 if (value == BITBANG_CS_INACTIVE) {
123 if (pdata->cs_control)
124 pdata->cs_control(spi, false);
125 }
126
127 if (value == BITBANG_CS_ACTIVE) {
128 mpc8xxx_spi->rx_shift = cs->rx_shift;
129 mpc8xxx_spi->tx_shift = cs->tx_shift;
130 mpc8xxx_spi->get_rx = cs->get_rx;
131 mpc8xxx_spi->get_tx = cs->get_tx;
132
133 fsl_spi_change_mode(spi);
134
135 if (pdata->cs_control)
136 pdata->cs_control(spi, true);
137 }
138}
139
140static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
141 int bits_per_word, int msb_first)
142{
143 *rx_shift = 0;
144 *tx_shift = 0;
145 if (msb_first) {
146 if (bits_per_word <= 8) {
147 *rx_shift = 16;
148 *tx_shift = 24;
149 } else if (bits_per_word <= 16) {
150 *rx_shift = 16;
151 *tx_shift = 16;
152 }
153 } else {
154 if (bits_per_word <= 8)
155 *rx_shift = 8;
156 }
157}
158
159static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
160 int bits_per_word, int msb_first)
161{
162 *rx_shift = 0;
163 *tx_shift = 0;
164 if (bits_per_word <= 16) {
165 if (msb_first) {
166 *rx_shift = 16;
167 *tx_shift = 32 - bits_per_word;
168 } else {
169 *rx_shift = 16 - bits_per_word;
170 }
171 }
172}
173
174static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
175 struct spi_device *spi,
176 struct mpc8xxx_spi *mpc8xxx_spi,
177 int bits_per_word)
178{
179 cs->rx_shift = 0;
180 cs->tx_shift = 0;
181 if (bits_per_word <= 8) {
182 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
183 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
184 } else if (bits_per_word <= 16) {
185 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
186 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
187 } else if (bits_per_word <= 32) {
188 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
189 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
190 } else
191 return -EINVAL;
192
193 if (mpc8xxx_spi->set_shifts)
194 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
195 bits_per_word,
196 !(spi->mode & SPI_LSB_FIRST));
197
198 mpc8xxx_spi->rx_shift = cs->rx_shift;
199 mpc8xxx_spi->tx_shift = cs->tx_shift;
200 mpc8xxx_spi->get_rx = cs->get_rx;
201 mpc8xxx_spi->get_tx = cs->get_tx;
202
203 return bits_per_word;
204}
205
206static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
207 struct spi_device *spi,
208 int bits_per_word)
209{
210
211
212
213
214
215
216 if (spi->mode & SPI_LSB_FIRST &&
217 bits_per_word > 8)
218 return -EINVAL;
219 if (bits_per_word > 8)
220 return 8;
221 return bits_per_word;
222}
223
224static int fsl_spi_setup_transfer(struct spi_device *spi,
225 struct spi_transfer *t)
226{
227 struct mpc8xxx_spi *mpc8xxx_spi;
228 int bits_per_word = 0;
229 u8 pm;
230 u32 hz = 0;
231 struct spi_mpc8xxx_cs *cs = spi->controller_state;
232
233 mpc8xxx_spi = spi_master_get_devdata(spi->master);
234
235 if (t) {
236 bits_per_word = t->bits_per_word;
237 hz = t->speed_hz;
238 }
239
240
241 if (!bits_per_word)
242 bits_per_word = spi->bits_per_word;
243
244 if (!hz)
245 hz = spi->max_speed_hz;
246
247 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
248 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
249 mpc8xxx_spi,
250 bits_per_word);
251 else if (mpc8xxx_spi->flags & SPI_QE)
252 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
253 bits_per_word);
254
255 if (bits_per_word < 0)
256 return bits_per_word;
257
258 if (bits_per_word == 32)
259 bits_per_word = 0;
260 else
261 bits_per_word = bits_per_word - 1;
262
263
264 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
265 | SPMODE_PM(0xF));
266
267 cs->hw_mode |= SPMODE_LEN(bits_per_word);
268
269 if ((mpc8xxx_spi->spibrg / hz) > 64) {
270 cs->hw_mode |= SPMODE_DIV16;
271 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
272 WARN_ONCE(pm > 16,
273 "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
274 dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
275 if (pm > 16)
276 pm = 16;
277 } else {
278 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
279 }
280 if (pm)
281 pm--;
282
283 cs->hw_mode |= SPMODE_PM(pm);
284
285 fsl_spi_change_mode(spi);
286 return 0;
287}
288
289static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
290 struct spi_transfer *t, unsigned int len)
291{
292 u32 word;
293 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
294
295 mspi->count = len;
296
297
298 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
299
300
301 word = mspi->get_tx(mspi);
302 mpc8xxx_spi_write_reg(®_base->transmit, word);
303
304 return 0;
305}
306
307static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
308 bool is_dma_mapped)
309{
310 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
311 struct fsl_spi_reg __iomem *reg_base;
312 unsigned int len = t->len;
313 u8 bits_per_word;
314 int ret;
315
316 reg_base = mpc8xxx_spi->reg_base;
317 bits_per_word = spi->bits_per_word;
318 if (t->bits_per_word)
319 bits_per_word = t->bits_per_word;
320
321 if (bits_per_word > 8) {
322
323 if (len & 1)
324 return -EINVAL;
325 len /= 2;
326 }
327 if (bits_per_word > 16) {
328
329 if (len & 1)
330 return -EINVAL;
331 len /= 2;
332 }
333
334 mpc8xxx_spi->tx = t->tx_buf;
335 mpc8xxx_spi->rx = t->rx_buf;
336
337 reinit_completion(&mpc8xxx_spi->done);
338
339 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
340 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
341 else
342 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
343 if (ret)
344 return ret;
345
346 wait_for_completion(&mpc8xxx_spi->done);
347
348
349 mpc8xxx_spi_write_reg(®_base->mask, 0);
350
351 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
352 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
353
354 return mpc8xxx_spi->count;
355}
356
357static int fsl_spi_do_one_msg(struct spi_master *master,
358 struct spi_message *m)
359{
360 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
361 struct spi_device *spi = m->spi;
362 struct spi_transfer *t, *first;
363 unsigned int cs_change;
364 const int nsecs = 50;
365 int status, last_bpw;
366
367
368
369
370
371 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
372 list_for_each_entry(t, &m->transfers, transfer_list) {
373 if (t->len < 256 || t->bits_per_word != 8)
374 continue;
375 if ((t->len & 3) == 0)
376 t->bits_per_word = 32;
377 else if ((t->len & 1) == 0)
378 t->bits_per_word = 16;
379 }
380 }
381
382
383 cs_change = 1;
384 list_for_each_entry(t, &m->transfers, transfer_list) {
385 if (cs_change)
386 first = t;
387 cs_change = t->cs_change;
388 if (first->speed_hz != t->speed_hz) {
389 dev_err(&spi->dev,
390 "speed_hz cannot change while CS is active\n");
391 return -EINVAL;
392 }
393 }
394
395 last_bpw = -1;
396 cs_change = 1;
397 status = -EINVAL;
398 list_for_each_entry(t, &m->transfers, transfer_list) {
399 if (cs_change || last_bpw != t->bits_per_word)
400 status = fsl_spi_setup_transfer(spi, t);
401 if (status < 0)
402 break;
403 last_bpw = t->bits_per_word;
404
405 if (cs_change) {
406 fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
407 ndelay(nsecs);
408 }
409 cs_change = t->cs_change;
410 if (t->len)
411 status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
412 if (status) {
413 status = -EMSGSIZE;
414 break;
415 }
416 m->actual_length += t->len;
417
418 spi_transfer_delay_exec(t);
419
420 if (cs_change) {
421 ndelay(nsecs);
422 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
423 ndelay(nsecs);
424 }
425 }
426
427 m->status = status;
428
429 if (status || !cs_change) {
430 ndelay(nsecs);
431 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
432 }
433
434 fsl_spi_setup_transfer(spi, NULL);
435 spi_finalize_current_message(master);
436 return 0;
437}
438
439static int fsl_spi_setup(struct spi_device *spi)
440{
441 struct mpc8xxx_spi *mpc8xxx_spi;
442 struct fsl_spi_reg __iomem *reg_base;
443 int retval;
444 u32 hw_mode;
445 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
446
447 if (!spi->max_speed_hz)
448 return -EINVAL;
449
450 if (!cs) {
451 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
452 if (!cs)
453 return -ENOMEM;
454 spi_set_ctldata(spi, cs);
455 }
456 mpc8xxx_spi = spi_master_get_devdata(spi->master);
457
458 reg_base = mpc8xxx_spi->reg_base;
459
460 hw_mode = cs->hw_mode;
461 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode);
462
463 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
464 | SPMODE_REV | SPMODE_LOOP);
465
466 if (spi->mode & SPI_CPHA)
467 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
468 if (spi->mode & SPI_CPOL)
469 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
470 if (!(spi->mode & SPI_LSB_FIRST))
471 cs->hw_mode |= SPMODE_REV;
472 if (spi->mode & SPI_LOOP)
473 cs->hw_mode |= SPMODE_LOOP;
474
475 retval = fsl_spi_setup_transfer(spi, NULL);
476 if (retval < 0) {
477 cs->hw_mode = hw_mode;
478 return retval;
479 }
480
481
482 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
483
484 return 0;
485}
486
487static void fsl_spi_cleanup(struct spi_device *spi)
488{
489 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
490
491 kfree(cs);
492 spi_set_ctldata(spi, NULL);
493}
494
495static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
496{
497 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
498
499
500 if (events & SPIE_NE) {
501 u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
502
503 if (mspi->rx)
504 mspi->get_rx(rx_data, mspi);
505 }
506
507 if ((events & SPIE_NF) == 0)
508
509 while (((events =
510 mpc8xxx_spi_read_reg(®_base->event)) &
511 SPIE_NF) == 0)
512 cpu_relax();
513
514
515 mpc8xxx_spi_write_reg(®_base->event, events);
516
517 mspi->count -= 1;
518 if (mspi->count) {
519 u32 word = mspi->get_tx(mspi);
520
521 mpc8xxx_spi_write_reg(®_base->transmit, word);
522 } else {
523 complete(&mspi->done);
524 }
525}
526
527static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
528{
529 struct mpc8xxx_spi *mspi = context_data;
530 irqreturn_t ret = IRQ_NONE;
531 u32 events;
532 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
533
534
535 events = mpc8xxx_spi_read_reg(®_base->event);
536 if (events)
537 ret = IRQ_HANDLED;
538
539 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
540
541 if (mspi->flags & SPI_CPM_MODE)
542 fsl_spi_cpm_irq(mspi, events);
543 else
544 fsl_spi_cpu_irq(mspi, events);
545
546 return ret;
547}
548
549static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
550{
551 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
552 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
553 u32 slvsel;
554 u16 cs = spi->chip_select;
555
556 if (spi->cs_gpiod) {
557 gpiod_set_value(spi->cs_gpiod, on);
558 } else if (cs < mpc8xxx_spi->native_chipselects) {
559 slvsel = mpc8xxx_spi_read_reg(®_base->slvsel);
560 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
561 mpc8xxx_spi_write_reg(®_base->slvsel, slvsel);
562 }
563}
564
565static void fsl_spi_grlib_probe(struct device *dev)
566{
567 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
568 struct spi_master *master = dev_get_drvdata(dev);
569 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
570 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
571 int mbits;
572 u32 capabilities;
573
574 capabilities = mpc8xxx_spi_read_reg(®_base->cap);
575
576 mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
577 mbits = SPCAP_MAXWLEN(capabilities);
578 if (mbits)
579 mpc8xxx_spi->max_bits_per_word = mbits + 1;
580
581 mpc8xxx_spi->native_chipselects = 0;
582 if (SPCAP_SSEN(capabilities)) {
583 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
584 mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff);
585 }
586 master->num_chipselect = mpc8xxx_spi->native_chipselects;
587 pdata->cs_control = fsl_spi_grlib_cs_control;
588}
589
590static struct spi_master *fsl_spi_probe(struct device *dev,
591 struct resource *mem, unsigned int irq)
592{
593 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
594 struct spi_master *master;
595 struct mpc8xxx_spi *mpc8xxx_spi;
596 struct fsl_spi_reg __iomem *reg_base;
597 u32 regval;
598 int ret = 0;
599
600 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
601 if (master == NULL) {
602 ret = -ENOMEM;
603 goto err;
604 }
605
606 dev_set_drvdata(dev, master);
607
608 mpc8xxx_spi_probe(dev, mem, irq);
609
610 master->setup = fsl_spi_setup;
611 master->cleanup = fsl_spi_cleanup;
612 master->transfer_one_message = fsl_spi_do_one_msg;
613 master->use_gpio_descriptors = true;
614
615 mpc8xxx_spi = spi_master_get_devdata(master);
616 mpc8xxx_spi->max_bits_per_word = 32;
617 mpc8xxx_spi->type = fsl_spi_get_type(dev);
618
619 ret = fsl_spi_cpm_init(mpc8xxx_spi);
620 if (ret)
621 goto err_cpm_init;
622
623 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
624 if (IS_ERR(mpc8xxx_spi->reg_base)) {
625 ret = PTR_ERR(mpc8xxx_spi->reg_base);
626 goto err_probe;
627 }
628
629 if (mpc8xxx_spi->type == TYPE_GRLIB)
630 fsl_spi_grlib_probe(dev);
631
632 master->bits_per_word_mask =
633 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
634 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
635
636 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
637 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
638
639 if (mpc8xxx_spi->set_shifts)
640
641 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
642 &mpc8xxx_spi->tx_shift, 8, 1);
643
644
645 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
646 0, "fsl_spi", mpc8xxx_spi);
647
648 if (ret != 0)
649 goto err_probe;
650
651 reg_base = mpc8xxx_spi->reg_base;
652
653
654 mpc8xxx_spi_write_reg(®_base->mode, 0);
655 mpc8xxx_spi_write_reg(®_base->mask, 0);
656 mpc8xxx_spi_write_reg(®_base->command, 0);
657 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
658
659
660 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
661 if (mpc8xxx_spi->max_bits_per_word < 8) {
662 regval &= ~SPMODE_LEN(0xF);
663 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
664 }
665 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
666 regval |= SPMODE_OP;
667
668 mpc8xxx_spi_write_reg(®_base->mode, regval);
669
670 ret = devm_spi_register_master(dev, master);
671 if (ret < 0)
672 goto err_probe;
673
674 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
675 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
676
677 return master;
678
679err_probe:
680 fsl_spi_cpm_free(mpc8xxx_spi);
681err_cpm_init:
682 spi_master_put(master);
683err:
684 return ERR_PTR(ret);
685}
686
687static void fsl_spi_cs_control(struct spi_device *spi, bool on)
688{
689 if (spi->cs_gpiod) {
690 gpiod_set_value(spi->cs_gpiod, on);
691 } else {
692 struct device *dev = spi->dev.parent->parent;
693 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
694 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
695
696 if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
697 return;
698 iowrite32be(on ? SPI_BOOT_SEL_BIT : 0, pinfo->immr_spi_cs);
699 }
700}
701
702static int of_fsl_spi_probe(struct platform_device *ofdev)
703{
704 struct device *dev = &ofdev->dev;
705 struct device_node *np = ofdev->dev.of_node;
706 struct spi_master *master;
707 struct resource mem;
708 int irq, type;
709 int ret;
710
711 ret = of_mpc8xxx_spi_probe(ofdev);
712 if (ret)
713 return ret;
714
715 type = fsl_spi_get_type(&ofdev->dev);
716 if (type == TYPE_FSL) {
717 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
718 bool spisel_boot = false;
719#if IS_ENABLED(CONFIG_FSL_SOC)
720 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
721
722 spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
723 if (spisel_boot) {
724 pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
725 if (!pinfo->immr_spi_cs)
726 return -ENOMEM;
727 }
728#endif
729
730
731
732
733
734
735
736 ret = gpiod_count(dev, "cs");
737 if (ret < 0)
738 ret = 0;
739 if (ret == 0 && !spisel_boot) {
740 pdata->max_chipselect = 1;
741 } else {
742 pdata->max_chipselect = ret + spisel_boot;
743 pdata->cs_control = fsl_spi_cs_control;
744 }
745 }
746
747 ret = of_address_to_resource(np, 0, &mem);
748 if (ret)
749 return ret;
750
751 irq = platform_get_irq(ofdev, 0);
752 if (irq < 0)
753 return irq;
754
755 master = fsl_spi_probe(dev, &mem, irq);
756
757 return PTR_ERR_OR_ZERO(master);
758}
759
760static int of_fsl_spi_remove(struct platform_device *ofdev)
761{
762 struct spi_master *master = platform_get_drvdata(ofdev);
763 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
764
765 fsl_spi_cpm_free(mpc8xxx_spi);
766 return 0;
767}
768
769static struct platform_driver of_fsl_spi_driver = {
770 .driver = {
771 .name = "fsl_spi",
772 .of_match_table = of_fsl_spi_match,
773 },
774 .probe = of_fsl_spi_probe,
775 .remove = of_fsl_spi_remove,
776};
777
778#ifdef CONFIG_MPC832x_RDB
779
780
781
782
783
784
785
786static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
787{
788 struct resource *mem;
789 int irq;
790 struct spi_master *master;
791
792 if (!dev_get_platdata(&pdev->dev))
793 return -EINVAL;
794
795 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
796 if (!mem)
797 return -EINVAL;
798
799 irq = platform_get_irq(pdev, 0);
800 if (irq <= 0)
801 return -EINVAL;
802
803 master = fsl_spi_probe(&pdev->dev, mem, irq);
804 return PTR_ERR_OR_ZERO(master);
805}
806
807static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
808{
809 struct spi_master *master = platform_get_drvdata(pdev);
810 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
811
812 fsl_spi_cpm_free(mpc8xxx_spi);
813
814 return 0;
815}
816
817MODULE_ALIAS("platform:mpc8xxx_spi");
818static struct platform_driver mpc8xxx_spi_driver = {
819 .probe = plat_mpc8xxx_spi_probe,
820 .remove = plat_mpc8xxx_spi_remove,
821 .driver = {
822 .name = "mpc8xxx_spi",
823 },
824};
825
826static bool legacy_driver_failed;
827
828static void __init legacy_driver_register(void)
829{
830 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
831}
832
833static void __exit legacy_driver_unregister(void)
834{
835 if (legacy_driver_failed)
836 return;
837 platform_driver_unregister(&mpc8xxx_spi_driver);
838}
839#else
840static void __init legacy_driver_register(void) {}
841static void __exit legacy_driver_unregister(void) {}
842#endif
843
844static int __init fsl_spi_init(void)
845{
846 legacy_driver_register();
847 return platform_driver_register(&of_fsl_spi_driver);
848}
849module_init(fsl_spi_init);
850
851static void __exit fsl_spi_exit(void)
852{
853 platform_driver_unregister(&of_fsl_spi_driver);
854 legacy_driver_unregister();
855}
856module_exit(fsl_spi_exit);
857
858MODULE_AUTHOR("Kumar Gala");
859MODULE_DESCRIPTION("Simple Freescale SPI Driver");
860MODULE_LICENSE("GPL");
861