1
2
3
4
5
6
7
8#include <linux/interrupt.h>
9#include <linux/irq.h>
10#include <linux/delay.h>
11#include <linux/device.h>
12#include <linux/kernel.h>
13#include <linux/spi/spi.h>
14#include <linux/slab.h>
15#include <linux/sysfs.h>
16#include <linux/list.h>
17#include <linux/module.h>
18
19#include <linux/iio/iio.h>
20#include <linux/iio/sysfs.h>
21#include <linux/iio/buffer.h>
22#include <linux/iio/imu/adis.h>
23
24#define ADIS16240_STARTUP_DELAY 220
25
26
27#define ADIS16240_FLASH_CNT 0x00
28
29
30#define ADIS16240_SUPPLY_OUT 0x02
31
32
33#define ADIS16240_XACCL_OUT 0x04
34
35
36#define ADIS16240_YACCL_OUT 0x06
37
38
39#define ADIS16240_ZACCL_OUT 0x08
40
41
42#define ADIS16240_AUX_ADC 0x0A
43
44
45#define ADIS16240_TEMP_OUT 0x0C
46
47
48#define ADIS16240_XPEAK_OUT 0x0E
49
50
51#define ADIS16240_YPEAK_OUT 0x10
52
53
54#define ADIS16240_ZPEAK_OUT 0x12
55
56
57#define ADIS16240_XYZPEAK_OUT 0x14
58
59
60#define ADIS16240_CAPT_BUF1 0x16
61
62
63#define ADIS16240_CAPT_BUF2 0x18
64
65
66#define ADIS16240_DIAG_STAT 0x1A
67
68
69#define ADIS16240_EVNT_CNTR 0x1C
70
71
72#define ADIS16240_CHK_SUM 0x1E
73
74
75#define ADIS16240_XACCL_OFF 0x20
76
77
78#define ADIS16240_YACCL_OFF 0x22
79
80
81#define ADIS16240_ZACCL_OFF 0x24
82
83
84#define ADIS16240_CLK_TIME 0x2E
85
86
87#define ADIS16240_CLK_DATE 0x30
88
89
90#define ADIS16240_CLK_YEAR 0x32
91
92
93#define ADIS16240_WAKE_TIME 0x34
94
95
96#define ADIS16240_WAKE_DATE 0x36
97
98
99#define ADIS16240_ALM_MAG1 0x38
100
101
102#define ADIS16240_ALM_MAG2 0x3A
103
104
105#define ADIS16240_ALM_CTRL 0x3C
106
107
108#define ADIS16240_XTRIG_CTRL 0x3E
109
110
111#define ADIS16240_CAPT_PNTR 0x40
112
113
114#define ADIS16240_CAPT_CTRL 0x42
115
116
117#define ADIS16240_GPIO_CTRL 0x44
118
119
120#define ADIS16240_MSC_CTRL 0x46
121
122
123#define ADIS16240_SMPL_PRD 0x48
124
125
126#define ADIS16240_GLOB_CMD 0x4A
127
128
129
130
131#define ADIS16240_MSC_CTRL_XYZPEAK_OUT_EN BIT(15)
132
133
134#define ADIS16240_MSC_CTRL_X_Y_ZPEAK_OUT_EN BIT(14)
135
136
137#define ADIS16240_MSC_CTRL_SELF_TEST_EN BIT(8)
138
139
140#define ADIS16240_MSC_CTRL_DATA_RDY_EN BIT(2)
141
142
143#define ADIS16240_MSC_CTRL_ACTIVE_HIGH BIT(1)
144
145
146#define ADIS16240_MSC_CTRL_DATA_RDY_DIO2 BIT(0)
147
148
149
150
151#define ADIS16240_DIAG_STAT_ALARM2 BIT(9)
152
153
154#define ADIS16240_DIAG_STAT_ALARM1 BIT(8)
155
156
157#define ADIS16240_DIAG_STAT_CPT_BUF_FUL BIT(7)
158
159
160#define ADIS16240_DIAG_STAT_CHKSUM BIT(6)
161
162
163#define ADIS16240_DIAG_STAT_PWRON_FAIL_BIT 5
164
165
166#define ADIS16240_DIAG_STAT_PWRON_BUSY BIT(4)
167
168
169#define ADIS16240_DIAG_STAT_SPI_FAIL_BIT 3
170
171
172#define ADIS16240_DIAG_STAT_FLASH_UPT_BIT 2
173
174
175#define ADIS16240_DIAG_STAT_POWER_HIGH_BIT 1
176
177
178#define ADIS16240_DIAG_STAT_POWER_LOW_BIT 0
179
180
181
182#define ADIS16240_GLOB_CMD_RESUME BIT(8)
183#define ADIS16240_GLOB_CMD_SW_RESET BIT(7)
184#define ADIS16240_GLOB_CMD_STANDBY BIT(2)
185
186#define ADIS16240_ERROR_ACTIVE BIT(14)
187
188
189
190
191
192enum adis16240_scan {
193 ADIS16240_SCAN_ACC_X,
194 ADIS16240_SCAN_ACC_Y,
195 ADIS16240_SCAN_ACC_Z,
196 ADIS16240_SCAN_SUPPLY,
197 ADIS16240_SCAN_AUX_ADC,
198 ADIS16240_SCAN_TEMP,
199};
200
201static ssize_t adis16240_spi_read_signed(struct device *dev,
202 struct device_attribute *attr,
203 char *buf,
204 unsigned int bits)
205{
206 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
207 struct adis *st = iio_priv(indio_dev);
208 int ret;
209 s16 val = 0;
210 unsigned int shift = 16 - bits;
211 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
212
213 ret = adis_read_reg_16(st,
214 this_attr->address, (u16 *)&val);
215 if (ret)
216 return ret;
217
218 if (val & ADIS16240_ERROR_ACTIVE)
219 adis_check_status(st);
220
221 val = (s16)(val << shift) >> shift;
222 return sprintf(buf, "%d\n", val);
223}
224
225static ssize_t adis16240_read_12bit_signed(struct device *dev,
226 struct device_attribute *attr,
227 char *buf)
228{
229 return adis16240_spi_read_signed(dev, attr, buf, 12);
230}
231
232static IIO_DEVICE_ATTR(in_accel_xyz_squared_peak_raw, 0444,
233 adis16240_read_12bit_signed, NULL,
234 ADIS16240_XYZPEAK_OUT);
235
236static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("4096");
237
238static const u8 adis16240_addresses[][2] = {
239 [ADIS16240_SCAN_ACC_X] = { ADIS16240_XACCL_OFF, ADIS16240_XPEAK_OUT },
240 [ADIS16240_SCAN_ACC_Y] = { ADIS16240_YACCL_OFF, ADIS16240_YPEAK_OUT },
241 [ADIS16240_SCAN_ACC_Z] = { ADIS16240_ZACCL_OFF, ADIS16240_ZPEAK_OUT },
242};
243
244static int adis16240_read_raw(struct iio_dev *indio_dev,
245 struct iio_chan_spec const *chan,
246 int *val, int *val2,
247 long mask)
248{
249 struct adis *st = iio_priv(indio_dev);
250 int ret;
251 u8 addr;
252 s16 val16;
253
254 switch (mask) {
255 case IIO_CHAN_INFO_RAW:
256 return adis_single_conversion(indio_dev, chan,
257 ADIS16240_ERROR_ACTIVE, val);
258 case IIO_CHAN_INFO_SCALE:
259 switch (chan->type) {
260 case IIO_VOLTAGE:
261 if (chan->channel == 0) {
262 *val = 4;
263 *val2 = 880000;
264 return IIO_VAL_INT_PLUS_MICRO;
265 }
266 return -EINVAL;
267 case IIO_TEMP:
268 *val = 244;
269 *val2 = 0;
270 return IIO_VAL_INT_PLUS_MICRO;
271 case IIO_ACCEL:
272 *val = 0;
273 *val2 = IIO_G_TO_M_S_2(51400);
274 return IIO_VAL_INT_PLUS_MICRO;
275 default:
276 return -EINVAL;
277 }
278 break;
279 case IIO_CHAN_INFO_PEAK_SCALE:
280 *val = 0;
281 *val2 = IIO_G_TO_M_S_2(51400);
282 return IIO_VAL_INT_PLUS_MICRO;
283 case IIO_CHAN_INFO_OFFSET:
284 *val = 25000 / 244 - 0x133;
285 return IIO_VAL_INT;
286 case IIO_CHAN_INFO_CALIBBIAS:
287 addr = adis16240_addresses[chan->scan_index][0];
288 ret = adis_read_reg_16(st, addr, &val16);
289 if (ret)
290 return ret;
291 *val = sign_extend32(val16, 9);
292 return IIO_VAL_INT;
293 case IIO_CHAN_INFO_PEAK:
294 addr = adis16240_addresses[chan->scan_index][1];
295 ret = adis_read_reg_16(st, addr, &val16);
296 if (ret)
297 return ret;
298 *val = sign_extend32(val16, 9);
299 return IIO_VAL_INT;
300 }
301 return -EINVAL;
302}
303
304static int adis16240_write_raw(struct iio_dev *indio_dev,
305 struct iio_chan_spec const *chan,
306 int val,
307 int val2,
308 long mask)
309{
310 struct adis *st = iio_priv(indio_dev);
311 u8 addr;
312
313 switch (mask) {
314 case IIO_CHAN_INFO_CALIBBIAS:
315 addr = adis16240_addresses[chan->scan_index][0];
316 return adis_write_reg_16(st, addr, val & GENMASK(9, 0));
317 }
318 return -EINVAL;
319}
320
321static const struct iio_chan_spec adis16240_channels[] = {
322 ADIS_SUPPLY_CHAN(ADIS16240_SUPPLY_OUT, ADIS16240_SCAN_SUPPLY, 0, 10),
323 ADIS_AUX_ADC_CHAN(ADIS16240_AUX_ADC, ADIS16240_SCAN_AUX_ADC, 0, 10),
324 ADIS_ACCEL_CHAN(X, ADIS16240_XACCL_OUT, ADIS16240_SCAN_ACC_X,
325 BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT(IIO_CHAN_INFO_PEAK),
326 0, 10),
327 ADIS_ACCEL_CHAN(Y, ADIS16240_YACCL_OUT, ADIS16240_SCAN_ACC_Y,
328 BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT(IIO_CHAN_INFO_PEAK),
329 0, 10),
330 ADIS_ACCEL_CHAN(Z, ADIS16240_ZACCL_OUT, ADIS16240_SCAN_ACC_Z,
331 BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT(IIO_CHAN_INFO_PEAK),
332 0, 10),
333 ADIS_TEMP_CHAN(ADIS16240_TEMP_OUT, ADIS16240_SCAN_TEMP, 0, 10),
334 IIO_CHAN_SOFT_TIMESTAMP(6)
335};
336
337static struct attribute *adis16240_attributes[] = {
338 &iio_dev_attr_in_accel_xyz_squared_peak_raw.dev_attr.attr,
339 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
340 NULL
341};
342
343static const struct attribute_group adis16240_attribute_group = {
344 .attrs = adis16240_attributes,
345};
346
347static const struct iio_info adis16240_info = {
348 .attrs = &adis16240_attribute_group,
349 .read_raw = adis16240_read_raw,
350 .write_raw = adis16240_write_raw,
351 .update_scan_mode = adis_update_scan_mode,
352};
353
354static const char * const adis16240_status_error_msgs[] = {
355 [ADIS16240_DIAG_STAT_PWRON_FAIL_BIT] = "Power on, self-test failed",
356 [ADIS16240_DIAG_STAT_SPI_FAIL_BIT] = "SPI failure",
357 [ADIS16240_DIAG_STAT_FLASH_UPT_BIT] = "Flash update failed",
358 [ADIS16240_DIAG_STAT_POWER_HIGH_BIT] = "Power supply above 3.625V",
359 [ADIS16240_DIAG_STAT_POWER_LOW_BIT] = "Power supply below 2.225V",
360};
361
362static const struct adis_timeout adis16240_timeouts = {
363 .reset_ms = ADIS16240_STARTUP_DELAY,
364 .sw_reset_ms = ADIS16240_STARTUP_DELAY,
365 .self_test_ms = ADIS16240_STARTUP_DELAY,
366};
367
368static const struct adis_data adis16240_data = {
369 .write_delay = 35,
370 .read_delay = 35,
371 .msc_ctrl_reg = ADIS16240_MSC_CTRL,
372 .glob_cmd_reg = ADIS16240_GLOB_CMD,
373 .diag_stat_reg = ADIS16240_DIAG_STAT,
374
375 .self_test_mask = ADIS16240_MSC_CTRL_SELF_TEST_EN,
376 .self_test_reg = ADIS16240_MSC_CTRL,
377 .self_test_no_autoclear = true,
378 .timeouts = &adis16240_timeouts,
379
380 .status_error_msgs = adis16240_status_error_msgs,
381 .status_error_mask = BIT(ADIS16240_DIAG_STAT_PWRON_FAIL_BIT) |
382 BIT(ADIS16240_DIAG_STAT_SPI_FAIL_BIT) |
383 BIT(ADIS16240_DIAG_STAT_FLASH_UPT_BIT) |
384 BIT(ADIS16240_DIAG_STAT_POWER_HIGH_BIT) |
385 BIT(ADIS16240_DIAG_STAT_POWER_LOW_BIT),
386};
387
388static int adis16240_probe(struct spi_device *spi)
389{
390 int ret;
391 struct adis *st;
392 struct iio_dev *indio_dev;
393
394
395 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
396 if (!indio_dev)
397 return -ENOMEM;
398 st = iio_priv(indio_dev);
399
400 spi_set_drvdata(spi, indio_dev);
401
402 indio_dev->name = spi->dev.driver->name;
403 indio_dev->info = &adis16240_info;
404 indio_dev->channels = adis16240_channels;
405 indio_dev->num_channels = ARRAY_SIZE(adis16240_channels);
406 indio_dev->modes = INDIO_DIRECT_MODE;
407
408 spi->mode = SPI_MODE_3;
409 ret = spi_setup(spi);
410 if (ret) {
411 dev_err(&spi->dev, "spi_setup failed!\n");
412 return ret;
413 }
414
415 ret = adis_init(st, indio_dev, spi, &adis16240_data);
416 if (ret)
417 return ret;
418 ret = devm_adis_setup_buffer_and_trigger(st, indio_dev, NULL);
419 if (ret)
420 return ret;
421
422
423 ret = adis_initial_startup(st);
424 if (ret)
425 return ret;
426
427 return devm_iio_device_register(&spi->dev, indio_dev);
428}
429
430static const struct of_device_id adis16240_of_match[] = {
431 { .compatible = "adi,adis16240" },
432 { },
433};
434MODULE_DEVICE_TABLE(of, adis16240_of_match);
435
436static struct spi_driver adis16240_driver = {
437 .driver = {
438 .name = "adis16240",
439 .of_match_table = adis16240_of_match,
440 },
441 .probe = adis16240_probe,
442};
443module_spi_driver(adis16240_driver);
444
445MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
446MODULE_DESCRIPTION("Analog Devices Programmable Impact Sensor and Recorder");
447MODULE_LICENSE("GPL v2");
448MODULE_ALIAS("spi:adis16240");
449