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10#include <linux/kernel.h>
11#include <linux/atomic.h>
12#include <linux/dma-mapping.h>
13#include <linux/dmaengine.h>
14#include <linux/module.h>
15#include <linux/io.h>
16#include <linux/ioport.h>
17#include <linux/interrupt.h>
18#include <linux/init.h>
19#include <linux/console.h>
20#include <linux/tty.h>
21#include <linux/tty_flip.h>
22#include <linux/serial_core.h>
23#include <linux/slab.h>
24#include <linux/clk.h>
25#include <linux/platform_device.h>
26#include <linux/delay.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/wait.h>
30
31#define UART_MR1 0x0000
32
33#define UART_MR1_AUTO_RFR_LEVEL0 0x3F
34#define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
35#define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00
36#define UART_MR1_RX_RDY_CTL BIT(7)
37#define UART_MR1_CTS_CTL BIT(6)
38
39#define UART_MR2 0x0004
40#define UART_MR2_ERROR_MODE BIT(6)
41#define UART_MR2_BITS_PER_CHAR 0x30
42#define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
43#define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
44#define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
45#define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
46#define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
47#define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
48#define UART_MR2_PARITY_MODE_NONE 0x0
49#define UART_MR2_PARITY_MODE_ODD 0x1
50#define UART_MR2_PARITY_MODE_EVEN 0x2
51#define UART_MR2_PARITY_MODE_SPACE 0x3
52#define UART_MR2_PARITY_MODE 0x3
53
54#define UART_CSR 0x0008
55
56#define UART_TF 0x000C
57#define UARTDM_TF 0x0070
58
59#define UART_CR 0x0010
60#define UART_CR_CMD_NULL (0 << 4)
61#define UART_CR_CMD_RESET_RX (1 << 4)
62#define UART_CR_CMD_RESET_TX (2 << 4)
63#define UART_CR_CMD_RESET_ERR (3 << 4)
64#define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
65#define UART_CR_CMD_START_BREAK (5 << 4)
66#define UART_CR_CMD_STOP_BREAK (6 << 4)
67#define UART_CR_CMD_RESET_CTS (7 << 4)
68#define UART_CR_CMD_RESET_STALE_INT (8 << 4)
69#define UART_CR_CMD_PACKET_MODE (9 << 4)
70#define UART_CR_CMD_MODE_RESET (12 << 4)
71#define UART_CR_CMD_SET_RFR (13 << 4)
72#define UART_CR_CMD_RESET_RFR (14 << 4)
73#define UART_CR_CMD_PROTECTION_EN (16 << 4)
74#define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
75#define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
76#define UART_CR_CMD_FORCE_STALE (4 << 8)
77#define UART_CR_CMD_RESET_TX_READY (3 << 8)
78#define UART_CR_TX_DISABLE BIT(3)
79#define UART_CR_TX_ENABLE BIT(2)
80#define UART_CR_RX_DISABLE BIT(1)
81#define UART_CR_RX_ENABLE BIT(0)
82#define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
83
84#define UART_IMR 0x0014
85#define UART_IMR_TXLEV BIT(0)
86#define UART_IMR_RXSTALE BIT(3)
87#define UART_IMR_RXLEV BIT(4)
88#define UART_IMR_DELTA_CTS BIT(5)
89#define UART_IMR_CURRENT_CTS BIT(6)
90#define UART_IMR_RXBREAK_START BIT(10)
91
92#define UART_IPR_RXSTALE_LAST 0x20
93#define UART_IPR_STALE_LSB 0x1F
94#define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
95#define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80
96
97#define UART_IPR 0x0018
98#define UART_TFWR 0x001C
99#define UART_RFWR 0x0020
100#define UART_HCR 0x0024
101
102#define UART_MREG 0x0028
103#define UART_NREG 0x002C
104#define UART_DREG 0x0030
105#define UART_MNDREG 0x0034
106#define UART_IRDA 0x0038
107#define UART_MISR_MODE 0x0040
108#define UART_MISR_RESET 0x0044
109#define UART_MISR_EXPORT 0x0048
110#define UART_MISR_VAL 0x004C
111#define UART_TEST_CTRL 0x0050
112
113#define UART_SR 0x0008
114#define UART_SR_HUNT_CHAR BIT(7)
115#define UART_SR_RX_BREAK BIT(6)
116#define UART_SR_PAR_FRAME_ERR BIT(5)
117#define UART_SR_OVERRUN BIT(4)
118#define UART_SR_TX_EMPTY BIT(3)
119#define UART_SR_TX_READY BIT(2)
120#define UART_SR_RX_FULL BIT(1)
121#define UART_SR_RX_READY BIT(0)
122
123#define UART_RF 0x000C
124#define UARTDM_RF 0x0070
125#define UART_MISR 0x0010
126#define UART_ISR 0x0014
127#define UART_ISR_TX_READY BIT(7)
128
129#define UARTDM_RXFS 0x50
130#define UARTDM_RXFS_BUF_SHIFT 0x7
131#define UARTDM_RXFS_BUF_MASK 0x7
132
133#define UARTDM_DMEN 0x3C
134#define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
135#define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
136
137#define UARTDM_DMEN_TX_BAM_ENABLE BIT(2)
138#define UARTDM_DMEN_TX_DM_ENABLE BIT(0)
139
140#define UARTDM_DMEN_RX_BAM_ENABLE BIT(3)
141#define UARTDM_DMEN_RX_DM_ENABLE BIT(1)
142
143#define UARTDM_DMRX 0x34
144#define UARTDM_NCF_TX 0x40
145#define UARTDM_RX_TOTAL_SNAP 0x38
146
147#define UARTDM_BURST_SIZE 16
148#define UARTDM_TX_AIGN(x) ((x) & ~0x3)
149#define UARTDM_TX_MAX 256
150#define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)
151
152enum {
153 UARTDM_1P1 = 1,
154 UARTDM_1P2,
155 UARTDM_1P3,
156 UARTDM_1P4,
157};
158
159struct msm_dma {
160 struct dma_chan *chan;
161 enum dma_data_direction dir;
162 dma_addr_t phys;
163 unsigned char *virt;
164 dma_cookie_t cookie;
165 u32 enable_bit;
166 unsigned int count;
167 struct dma_async_tx_descriptor *desc;
168};
169
170struct msm_port {
171 struct uart_port uart;
172 char name[16];
173 struct clk *clk;
174 struct clk *pclk;
175 unsigned int imr;
176 int is_uartdm;
177 unsigned int old_snap_state;
178 bool break_detected;
179 struct msm_dma tx_dma;
180 struct msm_dma rx_dma;
181};
182
183#define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart)
184
185static
186void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
187{
188 writel_relaxed(val, port->membase + off);
189}
190
191static
192unsigned int msm_read(struct uart_port *port, unsigned int off)
193{
194 return readl_relaxed(port->membase + off);
195}
196
197
198
199
200static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
201{
202 msm_write(port, 0x06, UART_MREG);
203 msm_write(port, 0xF1, UART_NREG);
204 msm_write(port, 0x0F, UART_DREG);
205 msm_write(port, 0x1A, UART_MNDREG);
206 port->uartclk = 1843200;
207}
208
209
210
211
212static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
213{
214 msm_write(port, 0x18, UART_MREG);
215 msm_write(port, 0xF6, UART_NREG);
216 msm_write(port, 0x0F, UART_DREG);
217 msm_write(port, 0x0A, UART_MNDREG);
218 port->uartclk = 1843200;
219}
220
221static void msm_serial_set_mnd_regs(struct uart_port *port)
222{
223 struct msm_port *msm_port = UART_TO_MSM(port);
224
225
226
227
228
229 if (msm_port->is_uartdm)
230 return;
231
232 if (port->uartclk == 19200000)
233 msm_serial_set_mnd_regs_tcxo(port);
234 else if (port->uartclk == 4800000)
235 msm_serial_set_mnd_regs_tcxoby4(port);
236}
237
238static void msm_handle_tx(struct uart_port *port);
239static void msm_start_rx_dma(struct msm_port *msm_port);
240
241static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
242{
243 struct device *dev = port->dev;
244 unsigned int mapped;
245 u32 val;
246
247 mapped = dma->count;
248 dma->count = 0;
249
250 dmaengine_terminate_all(dma->chan);
251
252
253
254
255
256
257
258
259 val = msm_read(port, UARTDM_DMEN);
260 val &= ~dma->enable_bit;
261 msm_write(port, val, UARTDM_DMEN);
262
263 if (mapped)
264 dma_unmap_single(dev, dma->phys, mapped, dma->dir);
265}
266
267static void msm_release_dma(struct msm_port *msm_port)
268{
269 struct msm_dma *dma;
270
271 dma = &msm_port->tx_dma;
272 if (dma->chan) {
273 msm_stop_dma(&msm_port->uart, dma);
274 dma_release_channel(dma->chan);
275 }
276
277 memset(dma, 0, sizeof(*dma));
278
279 dma = &msm_port->rx_dma;
280 if (dma->chan) {
281 msm_stop_dma(&msm_port->uart, dma);
282 dma_release_channel(dma->chan);
283 kfree(dma->virt);
284 }
285
286 memset(dma, 0, sizeof(*dma));
287}
288
289static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
290{
291 struct device *dev = msm_port->uart.dev;
292 struct dma_slave_config conf;
293 struct msm_dma *dma;
294 u32 crci = 0;
295 int ret;
296
297 dma = &msm_port->tx_dma;
298
299
300 dma->chan = dma_request_chan(dev, "tx");
301 if (IS_ERR(dma->chan))
302 goto no_tx;
303
304 of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
305
306 memset(&conf, 0, sizeof(conf));
307 conf.direction = DMA_MEM_TO_DEV;
308 conf.device_fc = true;
309 conf.dst_addr = base + UARTDM_TF;
310 conf.dst_maxburst = UARTDM_BURST_SIZE;
311 conf.slave_id = crci;
312
313 ret = dmaengine_slave_config(dma->chan, &conf);
314 if (ret)
315 goto rel_tx;
316
317 dma->dir = DMA_TO_DEVICE;
318
319 if (msm_port->is_uartdm < UARTDM_1P4)
320 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
321 else
322 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
323
324 return;
325
326rel_tx:
327 dma_release_channel(dma->chan);
328no_tx:
329 memset(dma, 0, sizeof(*dma));
330}
331
332static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
333{
334 struct device *dev = msm_port->uart.dev;
335 struct dma_slave_config conf;
336 struct msm_dma *dma;
337 u32 crci = 0;
338 int ret;
339
340 dma = &msm_port->rx_dma;
341
342
343 dma->chan = dma_request_chan(dev, "rx");
344 if (IS_ERR(dma->chan))
345 goto no_rx;
346
347 of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
348
349 dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
350 if (!dma->virt)
351 goto rel_rx;
352
353 memset(&conf, 0, sizeof(conf));
354 conf.direction = DMA_DEV_TO_MEM;
355 conf.device_fc = true;
356 conf.src_addr = base + UARTDM_RF;
357 conf.src_maxburst = UARTDM_BURST_SIZE;
358 conf.slave_id = crci;
359
360 ret = dmaengine_slave_config(dma->chan, &conf);
361 if (ret)
362 goto err;
363
364 dma->dir = DMA_FROM_DEVICE;
365
366 if (msm_port->is_uartdm < UARTDM_1P4)
367 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
368 else
369 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
370
371 return;
372err:
373 kfree(dma->virt);
374rel_rx:
375 dma_release_channel(dma->chan);
376no_rx:
377 memset(dma, 0, sizeof(*dma));
378}
379
380static inline void msm_wait_for_xmitr(struct uart_port *port)
381{
382 unsigned int timeout = 500000;
383
384 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
385 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
386 break;
387 udelay(1);
388 if (!timeout--)
389 break;
390 }
391 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
392}
393
394static void msm_stop_tx(struct uart_port *port)
395{
396 struct msm_port *msm_port = UART_TO_MSM(port);
397
398 msm_port->imr &= ~UART_IMR_TXLEV;
399 msm_write(port, msm_port->imr, UART_IMR);
400}
401
402static void msm_start_tx(struct uart_port *port)
403{
404 struct msm_port *msm_port = UART_TO_MSM(port);
405 struct msm_dma *dma = &msm_port->tx_dma;
406
407
408 if (dma->count)
409 return;
410
411 msm_port->imr |= UART_IMR_TXLEV;
412 msm_write(port, msm_port->imr, UART_IMR);
413}
414
415static void msm_reset_dm_count(struct uart_port *port, int count)
416{
417 msm_wait_for_xmitr(port);
418 msm_write(port, count, UARTDM_NCF_TX);
419 msm_read(port, UARTDM_NCF_TX);
420}
421
422static void msm_complete_tx_dma(void *args)
423{
424 struct msm_port *msm_port = args;
425 struct uart_port *port = &msm_port->uart;
426 struct circ_buf *xmit = &port->state->xmit;
427 struct msm_dma *dma = &msm_port->tx_dma;
428 struct dma_tx_state state;
429 unsigned long flags;
430 unsigned int count;
431 u32 val;
432
433 spin_lock_irqsave(&port->lock, flags);
434
435
436 if (!dma->count)
437 goto done;
438
439 dmaengine_tx_status(dma->chan, dma->cookie, &state);
440
441 dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
442
443 val = msm_read(port, UARTDM_DMEN);
444 val &= ~dma->enable_bit;
445 msm_write(port, val, UARTDM_DMEN);
446
447 if (msm_port->is_uartdm > UARTDM_1P3) {
448 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
449 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
450 }
451
452 count = dma->count - state.residue;
453 port->icount.tx += count;
454 dma->count = 0;
455
456 xmit->tail += count;
457 xmit->tail &= UART_XMIT_SIZE - 1;
458
459
460 msm_port->imr |= UART_IMR_TXLEV;
461 msm_write(port, msm_port->imr, UART_IMR);
462
463 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
464 uart_write_wakeup(port);
465
466 msm_handle_tx(port);
467done:
468 spin_unlock_irqrestore(&port->lock, flags);
469}
470
471static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
472{
473 struct circ_buf *xmit = &msm_port->uart.state->xmit;
474 struct uart_port *port = &msm_port->uart;
475 struct msm_dma *dma = &msm_port->tx_dma;
476 void *cpu_addr;
477 int ret;
478 u32 val;
479
480 cpu_addr = &xmit->buf[xmit->tail];
481
482 dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
483 ret = dma_mapping_error(port->dev, dma->phys);
484 if (ret)
485 return ret;
486
487 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
488 count, DMA_MEM_TO_DEV,
489 DMA_PREP_INTERRUPT |
490 DMA_PREP_FENCE);
491 if (!dma->desc) {
492 ret = -EIO;
493 goto unmap;
494 }
495
496 dma->desc->callback = msm_complete_tx_dma;
497 dma->desc->callback_param = msm_port;
498
499 dma->cookie = dmaengine_submit(dma->desc);
500 ret = dma_submit_error(dma->cookie);
501 if (ret)
502 goto unmap;
503
504
505
506
507
508 msm_port->imr &= ~UART_IMR_TXLEV;
509 msm_write(port, msm_port->imr, UART_IMR);
510
511 dma->count = count;
512
513 val = msm_read(port, UARTDM_DMEN);
514 val |= dma->enable_bit;
515
516 if (msm_port->is_uartdm < UARTDM_1P4)
517 msm_write(port, val, UARTDM_DMEN);
518
519 msm_reset_dm_count(port, count);
520
521 if (msm_port->is_uartdm > UARTDM_1P3)
522 msm_write(port, val, UARTDM_DMEN);
523
524 dma_async_issue_pending(dma->chan);
525 return 0;
526unmap:
527 dma_unmap_single(port->dev, dma->phys, count, dma->dir);
528 return ret;
529}
530
531static void msm_complete_rx_dma(void *args)
532{
533 struct msm_port *msm_port = args;
534 struct uart_port *port = &msm_port->uart;
535 struct tty_port *tport = &port->state->port;
536 struct msm_dma *dma = &msm_port->rx_dma;
537 int count = 0, i, sysrq;
538 unsigned long flags;
539 u32 val;
540
541 spin_lock_irqsave(&port->lock, flags);
542
543
544 if (!dma->count)
545 goto done;
546
547 val = msm_read(port, UARTDM_DMEN);
548 val &= ~dma->enable_bit;
549 msm_write(port, val, UARTDM_DMEN);
550
551 if (msm_read(port, UART_SR) & UART_SR_OVERRUN) {
552 port->icount.overrun++;
553 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
554 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
555 }
556
557 count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
558
559 port->icount.rx += count;
560
561 dma->count = 0;
562
563 dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
564
565 for (i = 0; i < count; i++) {
566 char flag = TTY_NORMAL;
567
568 if (msm_port->break_detected && dma->virt[i] == 0) {
569 port->icount.brk++;
570 flag = TTY_BREAK;
571 msm_port->break_detected = false;
572 if (uart_handle_break(port))
573 continue;
574 }
575
576 if (!(port->read_status_mask & UART_SR_RX_BREAK))
577 flag = TTY_NORMAL;
578
579 spin_unlock_irqrestore(&port->lock, flags);
580 sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
581 spin_lock_irqsave(&port->lock, flags);
582 if (!sysrq)
583 tty_insert_flip_char(tport, dma->virt[i], flag);
584 }
585
586 msm_start_rx_dma(msm_port);
587done:
588 spin_unlock_irqrestore(&port->lock, flags);
589
590 if (count)
591 tty_flip_buffer_push(tport);
592}
593
594static void msm_start_rx_dma(struct msm_port *msm_port)
595{
596 struct msm_dma *dma = &msm_port->rx_dma;
597 struct uart_port *uart = &msm_port->uart;
598 u32 val;
599 int ret;
600
601 if (!dma->chan)
602 return;
603
604 dma->phys = dma_map_single(uart->dev, dma->virt,
605 UARTDM_RX_SIZE, dma->dir);
606 ret = dma_mapping_error(uart->dev, dma->phys);
607 if (ret)
608 goto sw_mode;
609
610 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
611 UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
612 DMA_PREP_INTERRUPT);
613 if (!dma->desc)
614 goto unmap;
615
616 dma->desc->callback = msm_complete_rx_dma;
617 dma->desc->callback_param = msm_port;
618
619 dma->cookie = dmaengine_submit(dma->desc);
620 ret = dma_submit_error(dma->cookie);
621 if (ret)
622 goto unmap;
623
624
625
626
627 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
628
629
630
631
632
633 if (msm_port->is_uartdm < UARTDM_1P4)
634 msm_port->imr |= UART_IMR_RXSTALE;
635
636 msm_write(uart, msm_port->imr, UART_IMR);
637
638 dma->count = UARTDM_RX_SIZE;
639
640 dma_async_issue_pending(dma->chan);
641
642 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
643 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
644
645 val = msm_read(uart, UARTDM_DMEN);
646 val |= dma->enable_bit;
647
648 if (msm_port->is_uartdm < UARTDM_1P4)
649 msm_write(uart, val, UARTDM_DMEN);
650
651 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
652
653 if (msm_port->is_uartdm > UARTDM_1P3)
654 msm_write(uart, val, UARTDM_DMEN);
655
656 return;
657unmap:
658 dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
659
660sw_mode:
661
662
663
664
665 msm_write(uart, UART_CR_CMD_RESET_RX, UART_CR);
666 msm_write(uart, UART_CR_RX_ENABLE, UART_CR);
667
668 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
669 msm_write(uart, 0xFFFFFF, UARTDM_DMRX);
670 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
671
672
673 msm_port->imr |= (UART_IMR_RXLEV | UART_IMR_RXSTALE);
674 msm_write(uart, msm_port->imr, UART_IMR);
675}
676
677static void msm_stop_rx(struct uart_port *port)
678{
679 struct msm_port *msm_port = UART_TO_MSM(port);
680 struct msm_dma *dma = &msm_port->rx_dma;
681
682 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
683 msm_write(port, msm_port->imr, UART_IMR);
684
685 if (dma->chan)
686 msm_stop_dma(port, dma);
687}
688
689static void msm_enable_ms(struct uart_port *port)
690{
691 struct msm_port *msm_port = UART_TO_MSM(port);
692
693 msm_port->imr |= UART_IMR_DELTA_CTS;
694 msm_write(port, msm_port->imr, UART_IMR);
695}
696
697static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
698 __must_hold(&port->lock)
699{
700 struct tty_port *tport = &port->state->port;
701 unsigned int sr;
702 int count = 0;
703 struct msm_port *msm_port = UART_TO_MSM(port);
704
705 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
706 port->icount.overrun++;
707 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
708 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
709 }
710
711 if (misr & UART_IMR_RXSTALE) {
712 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
713 msm_port->old_snap_state;
714 msm_port->old_snap_state = 0;
715 } else {
716 count = 4 * (msm_read(port, UART_RFWR));
717 msm_port->old_snap_state += count;
718 }
719
720
721
722 port->icount.rx += count;
723
724 while (count > 0) {
725 unsigned char buf[4];
726 int sysrq, r_count, i;
727
728 sr = msm_read(port, UART_SR);
729 if ((sr & UART_SR_RX_READY) == 0) {
730 msm_port->old_snap_state -= count;
731 break;
732 }
733
734 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
735 r_count = min_t(int, count, sizeof(buf));
736
737 for (i = 0; i < r_count; i++) {
738 char flag = TTY_NORMAL;
739
740 if (msm_port->break_detected && buf[i] == 0) {
741 port->icount.brk++;
742 flag = TTY_BREAK;
743 msm_port->break_detected = false;
744 if (uart_handle_break(port))
745 continue;
746 }
747
748 if (!(port->read_status_mask & UART_SR_RX_BREAK))
749 flag = TTY_NORMAL;
750
751 spin_unlock(&port->lock);
752 sysrq = uart_handle_sysrq_char(port, buf[i]);
753 spin_lock(&port->lock);
754 if (!sysrq)
755 tty_insert_flip_char(tport, buf[i], flag);
756 }
757 count -= r_count;
758 }
759
760 spin_unlock(&port->lock);
761 tty_flip_buffer_push(tport);
762 spin_lock(&port->lock);
763
764 if (misr & (UART_IMR_RXSTALE))
765 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
766 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
767 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
768
769
770 msm_start_rx_dma(msm_port);
771}
772
773static void msm_handle_rx(struct uart_port *port)
774 __must_hold(&port->lock)
775{
776 struct tty_port *tport = &port->state->port;
777 unsigned int sr;
778
779
780
781
782
783 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
784 port->icount.overrun++;
785 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
786 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
787 }
788
789
790 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
791 unsigned int c;
792 char flag = TTY_NORMAL;
793 int sysrq;
794
795 c = msm_read(port, UART_RF);
796
797 if (sr & UART_SR_RX_BREAK) {
798 port->icount.brk++;
799 if (uart_handle_break(port))
800 continue;
801 } else if (sr & UART_SR_PAR_FRAME_ERR) {
802 port->icount.frame++;
803 } else {
804 port->icount.rx++;
805 }
806
807
808 sr &= port->read_status_mask;
809
810 if (sr & UART_SR_RX_BREAK)
811 flag = TTY_BREAK;
812 else if (sr & UART_SR_PAR_FRAME_ERR)
813 flag = TTY_FRAME;
814
815 spin_unlock(&port->lock);
816 sysrq = uart_handle_sysrq_char(port, c);
817 spin_lock(&port->lock);
818 if (!sysrq)
819 tty_insert_flip_char(tport, c, flag);
820 }
821
822 spin_unlock(&port->lock);
823 tty_flip_buffer_push(tport);
824 spin_lock(&port->lock);
825}
826
827static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
828{
829 struct circ_buf *xmit = &port->state->xmit;
830 struct msm_port *msm_port = UART_TO_MSM(port);
831 unsigned int num_chars;
832 unsigned int tf_pointer = 0;
833 void __iomem *tf;
834
835 if (msm_port->is_uartdm)
836 tf = port->membase + UARTDM_TF;
837 else
838 tf = port->membase + UART_TF;
839
840 if (tx_count && msm_port->is_uartdm)
841 msm_reset_dm_count(port, tx_count);
842
843 while (tf_pointer < tx_count) {
844 int i;
845 char buf[4] = { 0 };
846
847 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
848 break;
849
850 if (msm_port->is_uartdm)
851 num_chars = min(tx_count - tf_pointer,
852 (unsigned int)sizeof(buf));
853 else
854 num_chars = 1;
855
856 for (i = 0; i < num_chars; i++) {
857 buf[i] = xmit->buf[xmit->tail + i];
858 port->icount.tx++;
859 }
860
861 iowrite32_rep(tf, buf, 1);
862 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
863 tf_pointer += num_chars;
864 }
865
866
867 if (uart_circ_empty(xmit))
868 msm_stop_tx(port);
869
870 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
871 uart_write_wakeup(port);
872}
873
874static void msm_handle_tx(struct uart_port *port)
875{
876 struct msm_port *msm_port = UART_TO_MSM(port);
877 struct circ_buf *xmit = &msm_port->uart.state->xmit;
878 struct msm_dma *dma = &msm_port->tx_dma;
879 unsigned int pio_count, dma_count, dma_min;
880 char buf[4] = { 0 };
881 void __iomem *tf;
882 int err = 0;
883
884 if (port->x_char) {
885 if (msm_port->is_uartdm)
886 tf = port->membase + UARTDM_TF;
887 else
888 tf = port->membase + UART_TF;
889
890 buf[0] = port->x_char;
891
892 if (msm_port->is_uartdm)
893 msm_reset_dm_count(port, 1);
894
895 iowrite32_rep(tf, buf, 1);
896 port->icount.tx++;
897 port->x_char = 0;
898 return;
899 }
900
901 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
902 msm_stop_tx(port);
903 return;
904 }
905
906 pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
907 dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
908
909 dma_min = 1;
910 if (msm_port->is_uartdm > UARTDM_1P3) {
911 dma_count = UARTDM_TX_AIGN(dma_count);
912 dma_min = UARTDM_BURST_SIZE;
913 } else {
914 if (dma_count > UARTDM_TX_MAX)
915 dma_count = UARTDM_TX_MAX;
916 }
917
918 if (pio_count > port->fifosize)
919 pio_count = port->fifosize;
920
921 if (!dma->chan || dma_count < dma_min)
922 msm_handle_tx_pio(port, pio_count);
923 else
924 err = msm_handle_tx_dma(msm_port, dma_count);
925
926 if (err)
927 msm_handle_tx_pio(port, pio_count);
928}
929
930static void msm_handle_delta_cts(struct uart_port *port)
931{
932 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
933 port->icount.cts++;
934 wake_up_interruptible(&port->state->port.delta_msr_wait);
935}
936
937static irqreturn_t msm_uart_irq(int irq, void *dev_id)
938{
939 struct uart_port *port = dev_id;
940 struct msm_port *msm_port = UART_TO_MSM(port);
941 struct msm_dma *dma = &msm_port->rx_dma;
942 unsigned long flags;
943 unsigned int misr;
944 u32 val;
945
946 spin_lock_irqsave(&port->lock, flags);
947 misr = msm_read(port, UART_MISR);
948 msm_write(port, 0, UART_IMR);
949
950 if (misr & UART_IMR_RXBREAK_START) {
951 msm_port->break_detected = true;
952 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
953 }
954
955 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
956 if (dma->count) {
957 val = UART_CR_CMD_STALE_EVENT_DISABLE;
958 msm_write(port, val, UART_CR);
959 val = UART_CR_CMD_RESET_STALE_INT;
960 msm_write(port, val, UART_CR);
961
962
963
964
965 dmaengine_terminate_all(dma->chan);
966 } else if (msm_port->is_uartdm) {
967 msm_handle_rx_dm(port, misr);
968 } else {
969 msm_handle_rx(port);
970 }
971 }
972 if (misr & UART_IMR_TXLEV)
973 msm_handle_tx(port);
974 if (misr & UART_IMR_DELTA_CTS)
975 msm_handle_delta_cts(port);
976
977 msm_write(port, msm_port->imr, UART_IMR);
978 spin_unlock_irqrestore(&port->lock, flags);
979
980 return IRQ_HANDLED;
981}
982
983static unsigned int msm_tx_empty(struct uart_port *port)
984{
985 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
986}
987
988static unsigned int msm_get_mctrl(struct uart_port *port)
989{
990 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
991}
992
993static void msm_reset(struct uart_port *port)
994{
995 struct msm_port *msm_port = UART_TO_MSM(port);
996 unsigned int mr;
997
998
999 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
1000 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
1001 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
1002 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
1003 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
1004 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1005 mr = msm_read(port, UART_MR1);
1006 mr &= ~UART_MR1_RX_RDY_CTL;
1007 msm_write(port, mr, UART_MR1);
1008
1009
1010 if (msm_port->is_uartdm)
1011 msm_write(port, 0, UARTDM_DMEN);
1012}
1013
1014static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
1015{
1016 unsigned int mr;
1017
1018 mr = msm_read(port, UART_MR1);
1019
1020 if (!(mctrl & TIOCM_RTS)) {
1021 mr &= ~UART_MR1_RX_RDY_CTL;
1022 msm_write(port, mr, UART_MR1);
1023 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1024 } else {
1025 mr |= UART_MR1_RX_RDY_CTL;
1026 msm_write(port, mr, UART_MR1);
1027 }
1028}
1029
1030static void msm_break_ctl(struct uart_port *port, int break_ctl)
1031{
1032 if (break_ctl)
1033 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
1034 else
1035 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
1036}
1037
1038struct msm_baud_map {
1039 u16 divisor;
1040 u8 code;
1041 u8 rxstale;
1042};
1043
1044static const struct msm_baud_map *
1045msm_find_best_baud(struct uart_port *port, unsigned int baud,
1046 unsigned long *rate)
1047{
1048 struct msm_port *msm_port = UART_TO_MSM(port);
1049 unsigned int divisor, result;
1050 unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
1051 const struct msm_baud_map *entry, *end, *best;
1052 static const struct msm_baud_map table[] = {
1053 { 1, 0xff, 31 },
1054 { 2, 0xee, 16 },
1055 { 3, 0xdd, 8 },
1056 { 4, 0xcc, 6 },
1057 { 6, 0xbb, 6 },
1058 { 8, 0xaa, 6 },
1059 { 12, 0x99, 6 },
1060 { 16, 0x88, 1 },
1061 { 24, 0x77, 1 },
1062 { 32, 0x66, 1 },
1063 { 48, 0x55, 1 },
1064 { 96, 0x44, 1 },
1065 { 192, 0x33, 1 },
1066 { 384, 0x22, 1 },
1067 { 768, 0x11, 1 },
1068 { 1536, 0x00, 1 },
1069 };
1070
1071 best = table;
1072 target = clk_round_rate(msm_port->clk, 16 * baud);
1073 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1074
1075 end = table + ARRAY_SIZE(table);
1076 entry = table;
1077 while (entry < end) {
1078 if (entry->divisor <= divisor) {
1079 result = target / entry->divisor / 16;
1080 diff = abs(result - baud);
1081
1082
1083 if (diff < best_diff) {
1084 best_diff = diff;
1085 best = entry;
1086 best_rate = target;
1087 }
1088
1089 if (result == baud)
1090 break;
1091 } else if (entry->divisor > divisor) {
1092 old = target;
1093 target = clk_round_rate(msm_port->clk, old + 1);
1094
1095
1096
1097
1098 if (target == old)
1099 break;
1100
1101
1102 entry = table;
1103 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1104 continue;
1105 }
1106 entry++;
1107 }
1108
1109 *rate = best_rate;
1110 return best;
1111}
1112
1113static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
1114 unsigned long *saved_flags)
1115{
1116 unsigned int rxstale, watermark, mask;
1117 struct msm_port *msm_port = UART_TO_MSM(port);
1118 const struct msm_baud_map *entry;
1119 unsigned long flags, rate;
1120
1121 flags = *saved_flags;
1122 spin_unlock_irqrestore(&port->lock, flags);
1123
1124 entry = msm_find_best_baud(port, baud, &rate);
1125 clk_set_rate(msm_port->clk, rate);
1126 baud = rate / 16 / entry->divisor;
1127
1128 spin_lock_irqsave(&port->lock, flags);
1129 *saved_flags = flags;
1130 port->uartclk = rate;
1131
1132 msm_write(port, entry->code, UART_CSR);
1133
1134
1135 rxstale = entry->rxstale;
1136 watermark = UART_IPR_STALE_LSB & rxstale;
1137 if (msm_port->is_uartdm) {
1138 mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
1139 } else {
1140 watermark |= UART_IPR_RXSTALE_LAST;
1141 mask = UART_IPR_STALE_TIMEOUT_MSB;
1142 }
1143
1144 watermark |= mask & (rxstale << 2);
1145
1146 msm_write(port, watermark, UART_IPR);
1147
1148
1149 watermark = (port->fifosize * 3) / 4;
1150 msm_write(port, watermark, UART_RFWR);
1151
1152
1153 msm_write(port, 10, UART_TFWR);
1154
1155 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
1156 msm_reset(port);
1157
1158
1159 msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
1160
1161
1162 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
1163 UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START;
1164
1165 msm_write(port, msm_port->imr, UART_IMR);
1166
1167 if (msm_port->is_uartdm) {
1168 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1169 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1170 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
1171 }
1172
1173 return baud;
1174}
1175
1176static void msm_init_clock(struct uart_port *port)
1177{
1178 struct msm_port *msm_port = UART_TO_MSM(port);
1179
1180 clk_prepare_enable(msm_port->clk);
1181 clk_prepare_enable(msm_port->pclk);
1182 msm_serial_set_mnd_regs(port);
1183}
1184
1185static int msm_startup(struct uart_port *port)
1186{
1187 struct msm_port *msm_port = UART_TO_MSM(port);
1188 unsigned int data, rfr_level, mask;
1189 int ret;
1190
1191 snprintf(msm_port->name, sizeof(msm_port->name),
1192 "msm_serial%d", port->line);
1193
1194 msm_init_clock(port);
1195
1196 if (likely(port->fifosize > 12))
1197 rfr_level = port->fifosize - 12;
1198 else
1199 rfr_level = port->fifosize;
1200
1201
1202 data = msm_read(port, UART_MR1);
1203
1204 if (msm_port->is_uartdm)
1205 mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
1206 else
1207 mask = UART_MR1_AUTO_RFR_LEVEL1;
1208
1209 data &= ~mask;
1210 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
1211 data |= mask & (rfr_level << 2);
1212 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1213 msm_write(port, data, UART_MR1);
1214
1215 if (msm_port->is_uartdm) {
1216 msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1217 msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1218 }
1219
1220 ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
1221 msm_port->name, port);
1222 if (unlikely(ret))
1223 goto err_irq;
1224
1225 return 0;
1226
1227err_irq:
1228 if (msm_port->is_uartdm)
1229 msm_release_dma(msm_port);
1230
1231 clk_disable_unprepare(msm_port->pclk);
1232 clk_disable_unprepare(msm_port->clk);
1233
1234 return ret;
1235}
1236
1237static void msm_shutdown(struct uart_port *port)
1238{
1239 struct msm_port *msm_port = UART_TO_MSM(port);
1240
1241 msm_port->imr = 0;
1242 msm_write(port, 0, UART_IMR);
1243
1244 if (msm_port->is_uartdm)
1245 msm_release_dma(msm_port);
1246
1247 clk_disable_unprepare(msm_port->clk);
1248
1249 free_irq(port->irq, port);
1250}
1251
1252static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1253 struct ktermios *old)
1254{
1255 struct msm_port *msm_port = UART_TO_MSM(port);
1256 struct msm_dma *dma = &msm_port->rx_dma;
1257 unsigned long flags;
1258 unsigned int baud, mr;
1259
1260 spin_lock_irqsave(&port->lock, flags);
1261
1262 if (dma->chan)
1263 msm_stop_dma(port, dma);
1264
1265
1266 baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1267 baud = msm_set_baud_rate(port, baud, &flags);
1268 if (tty_termios_baud_rate(termios))
1269 tty_termios_encode_baud_rate(termios, baud, baud);
1270
1271
1272 mr = msm_read(port, UART_MR2);
1273 mr &= ~UART_MR2_PARITY_MODE;
1274 if (termios->c_cflag & PARENB) {
1275 if (termios->c_cflag & PARODD)
1276 mr |= UART_MR2_PARITY_MODE_ODD;
1277 else if (termios->c_cflag & CMSPAR)
1278 mr |= UART_MR2_PARITY_MODE_SPACE;
1279 else
1280 mr |= UART_MR2_PARITY_MODE_EVEN;
1281 }
1282
1283
1284 mr &= ~UART_MR2_BITS_PER_CHAR;
1285 switch (termios->c_cflag & CSIZE) {
1286 case CS5:
1287 mr |= UART_MR2_BITS_PER_CHAR_5;
1288 break;
1289 case CS6:
1290 mr |= UART_MR2_BITS_PER_CHAR_6;
1291 break;
1292 case CS7:
1293 mr |= UART_MR2_BITS_PER_CHAR_7;
1294 break;
1295 case CS8:
1296 default:
1297 mr |= UART_MR2_BITS_PER_CHAR_8;
1298 break;
1299 }
1300
1301
1302 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
1303 if (termios->c_cflag & CSTOPB)
1304 mr |= UART_MR2_STOP_BIT_LEN_TWO;
1305 else
1306 mr |= UART_MR2_STOP_BIT_LEN_ONE;
1307
1308
1309 msm_write(port, mr, UART_MR2);
1310
1311
1312 mr = msm_read(port, UART_MR1);
1313 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
1314 if (termios->c_cflag & CRTSCTS) {
1315 mr |= UART_MR1_CTS_CTL;
1316 mr |= UART_MR1_RX_RDY_CTL;
1317 }
1318 msm_write(port, mr, UART_MR1);
1319
1320
1321 port->read_status_mask = 0;
1322 if (termios->c_iflag & INPCK)
1323 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
1324 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1325 port->read_status_mask |= UART_SR_RX_BREAK;
1326
1327 uart_update_timeout(port, termios->c_cflag, baud);
1328
1329
1330 msm_start_rx_dma(msm_port);
1331
1332 spin_unlock_irqrestore(&port->lock, flags);
1333}
1334
1335static const char *msm_type(struct uart_port *port)
1336{
1337 return "MSM";
1338}
1339
1340static void msm_release_port(struct uart_port *port)
1341{
1342 struct platform_device *pdev = to_platform_device(port->dev);
1343 struct resource *uart_resource;
1344 resource_size_t size;
1345
1346 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1347 if (unlikely(!uart_resource))
1348 return;
1349 size = resource_size(uart_resource);
1350
1351 release_mem_region(port->mapbase, size);
1352 iounmap(port->membase);
1353 port->membase = NULL;
1354}
1355
1356static int msm_request_port(struct uart_port *port)
1357{
1358 struct platform_device *pdev = to_platform_device(port->dev);
1359 struct resource *uart_resource;
1360 resource_size_t size;
1361 int ret;
1362
1363 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1364 if (unlikely(!uart_resource))
1365 return -ENXIO;
1366
1367 size = resource_size(uart_resource);
1368
1369 if (!request_mem_region(port->mapbase, size, "msm_serial"))
1370 return -EBUSY;
1371
1372 port->membase = ioremap(port->mapbase, size);
1373 if (!port->membase) {
1374 ret = -EBUSY;
1375 goto fail_release_port;
1376 }
1377
1378 return 0;
1379
1380fail_release_port:
1381 release_mem_region(port->mapbase, size);
1382 return ret;
1383}
1384
1385static void msm_config_port(struct uart_port *port, int flags)
1386{
1387 int ret;
1388
1389 if (flags & UART_CONFIG_TYPE) {
1390 port->type = PORT_MSM;
1391 ret = msm_request_port(port);
1392 if (ret)
1393 return;
1394 }
1395}
1396
1397static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1398{
1399 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1400 return -EINVAL;
1401 if (unlikely(port->irq != ser->irq))
1402 return -EINVAL;
1403 return 0;
1404}
1405
1406static void msm_power(struct uart_port *port, unsigned int state,
1407 unsigned int oldstate)
1408{
1409 struct msm_port *msm_port = UART_TO_MSM(port);
1410
1411 switch (state) {
1412 case 0:
1413 clk_prepare_enable(msm_port->clk);
1414 clk_prepare_enable(msm_port->pclk);
1415 break;
1416 case 3:
1417 clk_disable_unprepare(msm_port->clk);
1418 clk_disable_unprepare(msm_port->pclk);
1419 break;
1420 default:
1421 pr_err("msm_serial: Unknown PM state %d\n", state);
1422 }
1423}
1424
1425#ifdef CONFIG_CONSOLE_POLL
1426static int msm_poll_get_char_single(struct uart_port *port)
1427{
1428 struct msm_port *msm_port = UART_TO_MSM(port);
1429 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
1430
1431 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
1432 return NO_POLL_CHAR;
1433
1434 return msm_read(port, rf_reg) & 0xff;
1435}
1436
1437static int msm_poll_get_char_dm(struct uart_port *port)
1438{
1439 int c;
1440 static u32 slop;
1441 static int count;
1442 unsigned char *sp = (unsigned char *)&slop;
1443
1444
1445 if (count) {
1446 c = sp[sizeof(slop) - count];
1447 count--;
1448
1449 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
1450
1451
1452
1453
1454 count = msm_read(port, UARTDM_RXFS);
1455 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1456 if (count) {
1457 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
1458 slop = msm_read(port, UARTDM_RF);
1459 c = sp[0];
1460 count--;
1461 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1462 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1463 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
1464 UART_CR);
1465 } else {
1466 c = NO_POLL_CHAR;
1467 }
1468
1469 } else {
1470 slop = msm_read(port, UARTDM_RF);
1471 c = sp[0];
1472 count = sizeof(slop) - 1;
1473 }
1474
1475 return c;
1476}
1477
1478static int msm_poll_get_char(struct uart_port *port)
1479{
1480 u32 imr;
1481 int c;
1482 struct msm_port *msm_port = UART_TO_MSM(port);
1483
1484
1485 imr = msm_read(port, UART_IMR);
1486 msm_write(port, 0, UART_IMR);
1487
1488 if (msm_port->is_uartdm)
1489 c = msm_poll_get_char_dm(port);
1490 else
1491 c = msm_poll_get_char_single(port);
1492
1493
1494 msm_write(port, imr, UART_IMR);
1495
1496 return c;
1497}
1498
1499static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1500{
1501 u32 imr;
1502 struct msm_port *msm_port = UART_TO_MSM(port);
1503
1504
1505 imr = msm_read(port, UART_IMR);
1506 msm_write(port, 0, UART_IMR);
1507
1508 if (msm_port->is_uartdm)
1509 msm_reset_dm_count(port, 1);
1510
1511
1512 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1513 cpu_relax();
1514
1515
1516 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
1517
1518
1519 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1520 cpu_relax();
1521
1522
1523 msm_write(port, imr, UART_IMR);
1524}
1525#endif
1526
1527static const struct uart_ops msm_uart_pops = {
1528 .tx_empty = msm_tx_empty,
1529 .set_mctrl = msm_set_mctrl,
1530 .get_mctrl = msm_get_mctrl,
1531 .stop_tx = msm_stop_tx,
1532 .start_tx = msm_start_tx,
1533 .stop_rx = msm_stop_rx,
1534 .enable_ms = msm_enable_ms,
1535 .break_ctl = msm_break_ctl,
1536 .startup = msm_startup,
1537 .shutdown = msm_shutdown,
1538 .set_termios = msm_set_termios,
1539 .type = msm_type,
1540 .release_port = msm_release_port,
1541 .request_port = msm_request_port,
1542 .config_port = msm_config_port,
1543 .verify_port = msm_verify_port,
1544 .pm = msm_power,
1545#ifdef CONFIG_CONSOLE_POLL
1546 .poll_get_char = msm_poll_get_char,
1547 .poll_put_char = msm_poll_put_char,
1548#endif
1549};
1550
1551static struct msm_port msm_uart_ports[] = {
1552 {
1553 .uart = {
1554 .iotype = UPIO_MEM,
1555 .ops = &msm_uart_pops,
1556 .flags = UPF_BOOT_AUTOCONF,
1557 .fifosize = 64,
1558 .line = 0,
1559 },
1560 },
1561 {
1562 .uart = {
1563 .iotype = UPIO_MEM,
1564 .ops = &msm_uart_pops,
1565 .flags = UPF_BOOT_AUTOCONF,
1566 .fifosize = 64,
1567 .line = 1,
1568 },
1569 },
1570 {
1571 .uart = {
1572 .iotype = UPIO_MEM,
1573 .ops = &msm_uart_pops,
1574 .flags = UPF_BOOT_AUTOCONF,
1575 .fifosize = 64,
1576 .line = 2,
1577 },
1578 },
1579};
1580
1581#define UART_NR ARRAY_SIZE(msm_uart_ports)
1582
1583static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1584{
1585 return &msm_uart_ports[line].uart;
1586}
1587
1588#ifdef CONFIG_SERIAL_MSM_CONSOLE
1589static void __msm_console_write(struct uart_port *port, const char *s,
1590 unsigned int count, bool is_uartdm)
1591{
1592 int i;
1593 int num_newlines = 0;
1594 bool replaced = false;
1595 void __iomem *tf;
1596 int locked = 1;
1597
1598 if (is_uartdm)
1599 tf = port->membase + UARTDM_TF;
1600 else
1601 tf = port->membase + UART_TF;
1602
1603
1604 for (i = 0; i < count; i++)
1605 if (s[i] == '\n')
1606 num_newlines++;
1607 count += num_newlines;
1608
1609 if (port->sysrq)
1610 locked = 0;
1611 else if (oops_in_progress)
1612 locked = spin_trylock(&port->lock);
1613 else
1614 spin_lock(&port->lock);
1615
1616 if (is_uartdm)
1617 msm_reset_dm_count(port, count);
1618
1619 i = 0;
1620 while (i < count) {
1621 int j;
1622 unsigned int num_chars;
1623 char buf[4] = { 0 };
1624
1625 if (is_uartdm)
1626 num_chars = min(count - i, (unsigned int)sizeof(buf));
1627 else
1628 num_chars = 1;
1629
1630 for (j = 0; j < num_chars; j++) {
1631 char c = *s;
1632
1633 if (c == '\n' && !replaced) {
1634 buf[j] = '\r';
1635 j++;
1636 replaced = true;
1637 }
1638 if (j < num_chars) {
1639 buf[j] = c;
1640 s++;
1641 replaced = false;
1642 }
1643 }
1644
1645 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1646 cpu_relax();
1647
1648 iowrite32_rep(tf, buf, 1);
1649 i += num_chars;
1650 }
1651
1652 if (locked)
1653 spin_unlock(&port->lock);
1654}
1655
1656static void msm_console_write(struct console *co, const char *s,
1657 unsigned int count)
1658{
1659 struct uart_port *port;
1660 struct msm_port *msm_port;
1661
1662 BUG_ON(co->index < 0 || co->index >= UART_NR);
1663
1664 port = msm_get_port_from_line(co->index);
1665 msm_port = UART_TO_MSM(port);
1666
1667 __msm_console_write(port, s, count, msm_port->is_uartdm);
1668}
1669
1670static int msm_console_setup(struct console *co, char *options)
1671{
1672 struct uart_port *port;
1673 int baud = 115200;
1674 int bits = 8;
1675 int parity = 'n';
1676 int flow = 'n';
1677
1678 if (unlikely(co->index >= UART_NR || co->index < 0))
1679 return -ENXIO;
1680
1681 port = msm_get_port_from_line(co->index);
1682
1683 if (unlikely(!port->membase))
1684 return -ENXIO;
1685
1686 msm_init_clock(port);
1687
1688 if (options)
1689 uart_parse_options(options, &baud, &parity, &bits, &flow);
1690
1691 pr_info("msm_serial: console setup on port #%d\n", port->line);
1692
1693 return uart_set_options(port, co, baud, parity, bits, flow);
1694}
1695
1696static void
1697msm_serial_early_write(struct console *con, const char *s, unsigned n)
1698{
1699 struct earlycon_device *dev = con->data;
1700
1701 __msm_console_write(&dev->port, s, n, false);
1702}
1703
1704static int __init
1705msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1706{
1707 if (!device->port.membase)
1708 return -ENODEV;
1709
1710 device->con->write = msm_serial_early_write;
1711 return 0;
1712}
1713OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1714 msm_serial_early_console_setup);
1715
1716static void
1717msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1718{
1719 struct earlycon_device *dev = con->data;
1720
1721 __msm_console_write(&dev->port, s, n, true);
1722}
1723
1724static int __init
1725msm_serial_early_console_setup_dm(struct earlycon_device *device,
1726 const char *opt)
1727{
1728 if (!device->port.membase)
1729 return -ENODEV;
1730
1731 device->con->write = msm_serial_early_write_dm;
1732 return 0;
1733}
1734OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1735 msm_serial_early_console_setup_dm);
1736
1737static struct uart_driver msm_uart_driver;
1738
1739static struct console msm_console = {
1740 .name = "ttyMSM",
1741 .write = msm_console_write,
1742 .device = uart_console_device,
1743 .setup = msm_console_setup,
1744 .flags = CON_PRINTBUFFER,
1745 .index = -1,
1746 .data = &msm_uart_driver,
1747};
1748
1749#define MSM_CONSOLE (&msm_console)
1750
1751#else
1752#define MSM_CONSOLE NULL
1753#endif
1754
1755static struct uart_driver msm_uart_driver = {
1756 .owner = THIS_MODULE,
1757 .driver_name = "msm_serial",
1758 .dev_name = "ttyMSM",
1759 .nr = UART_NR,
1760 .cons = MSM_CONSOLE,
1761};
1762
1763static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1764
1765static const struct of_device_id msm_uartdm_table[] = {
1766 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1767 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1768 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1769 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1770 { }
1771};
1772
1773static int msm_serial_probe(struct platform_device *pdev)
1774{
1775 struct msm_port *msm_port;
1776 struct resource *resource;
1777 struct uart_port *port;
1778 const struct of_device_id *id;
1779 int irq, line;
1780
1781 if (pdev->dev.of_node)
1782 line = of_alias_get_id(pdev->dev.of_node, "serial");
1783 else
1784 line = pdev->id;
1785
1786 if (line < 0)
1787 line = atomic_inc_return(&msm_uart_next_id) - 1;
1788
1789 if (unlikely(line < 0 || line >= UART_NR))
1790 return -ENXIO;
1791
1792 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1793
1794 port = msm_get_port_from_line(line);
1795 port->dev = &pdev->dev;
1796 msm_port = UART_TO_MSM(port);
1797
1798 id = of_match_device(msm_uartdm_table, &pdev->dev);
1799 if (id)
1800 msm_port->is_uartdm = (unsigned long)id->data;
1801 else
1802 msm_port->is_uartdm = 0;
1803
1804 msm_port->clk = devm_clk_get(&pdev->dev, "core");
1805 if (IS_ERR(msm_port->clk))
1806 return PTR_ERR(msm_port->clk);
1807
1808 if (msm_port->is_uartdm) {
1809 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1810 if (IS_ERR(msm_port->pclk))
1811 return PTR_ERR(msm_port->pclk);
1812 }
1813
1814 port->uartclk = clk_get_rate(msm_port->clk);
1815 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1816
1817 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1818 if (unlikely(!resource))
1819 return -ENXIO;
1820 port->mapbase = resource->start;
1821
1822 irq = platform_get_irq(pdev, 0);
1823 if (unlikely(irq < 0))
1824 return -ENXIO;
1825 port->irq = irq;
1826 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MSM_CONSOLE);
1827
1828 platform_set_drvdata(pdev, port);
1829
1830 return uart_add_one_port(&msm_uart_driver, port);
1831}
1832
1833static int msm_serial_remove(struct platform_device *pdev)
1834{
1835 struct uart_port *port = platform_get_drvdata(pdev);
1836
1837 uart_remove_one_port(&msm_uart_driver, port);
1838
1839 return 0;
1840}
1841
1842static const struct of_device_id msm_match_table[] = {
1843 { .compatible = "qcom,msm-uart" },
1844 { .compatible = "qcom,msm-uartdm" },
1845 {}
1846};
1847MODULE_DEVICE_TABLE(of, msm_match_table);
1848
1849static int __maybe_unused msm_serial_suspend(struct device *dev)
1850{
1851 struct msm_port *port = dev_get_drvdata(dev);
1852
1853 uart_suspend_port(&msm_uart_driver, &port->uart);
1854
1855 return 0;
1856}
1857
1858static int __maybe_unused msm_serial_resume(struct device *dev)
1859{
1860 struct msm_port *port = dev_get_drvdata(dev);
1861
1862 uart_resume_port(&msm_uart_driver, &port->uart);
1863
1864 return 0;
1865}
1866
1867static const struct dev_pm_ops msm_serial_dev_pm_ops = {
1868 SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume)
1869};
1870
1871static struct platform_driver msm_platform_driver = {
1872 .remove = msm_serial_remove,
1873 .probe = msm_serial_probe,
1874 .driver = {
1875 .name = "msm_serial",
1876 .pm = &msm_serial_dev_pm_ops,
1877 .of_match_table = msm_match_table,
1878 },
1879};
1880
1881static int __init msm_serial_init(void)
1882{
1883 int ret;
1884
1885 ret = uart_register_driver(&msm_uart_driver);
1886 if (unlikely(ret))
1887 return ret;
1888
1889 ret = platform_driver_register(&msm_platform_driver);
1890 if (unlikely(ret))
1891 uart_unregister_driver(&msm_uart_driver);
1892
1893 pr_info("msm_serial: driver initialized\n");
1894
1895 return ret;
1896}
1897
1898static void __exit msm_serial_exit(void)
1899{
1900 platform_driver_unregister(&msm_platform_driver);
1901 uart_unregister_driver(&msm_uart_driver);
1902}
1903
1904module_init(msm_serial_init);
1905module_exit(msm_serial_exit);
1906
1907MODULE_AUTHOR("Robert Love <rlove@google.com>");
1908MODULE_DESCRIPTION("Driver for msm7x serial device");
1909MODULE_LICENSE("GPL");
1910
