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15#include <linux/kernel.h>
16#include <linux/errno.h>
17#include <linux/init.h>
18#include <linux/console.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
21#include <linux/slab.h>
22#include <linux/wait.h>
23#include <linux/tty.h>
24#include <linux/tty_driver.h>
25#include <linux/tty_flip.h>
26#include <linux/serial.h>
27#include <linux/serial_core.h>
28#include <linux/platform_device.h>
29#include <linux/device.h>
30#include <linux/clk.h>
31#include <linux/delay.h>
32#include <linux/io.h>
33#include <linux/of_device.h>
34#include <linux/dma-mapping.h>
35#include <linux/dmaengine.h>
36
37#include <asm/cacheflush.h>
38
39#include <linux/gpio/consumer.h>
40#include <linux/err.h>
41#include <linux/irq.h>
42#include "serial_mctrl_gpio.h"
43
44#define MXS_AUART_PORTS 5
45#define MXS_AUART_FIFO_SIZE 16
46
47#define SET_REG 0x4
48#define CLR_REG 0x8
49#define TOG_REG 0xc
50
51#define AUART_CTRL0 0x00000000
52#define AUART_CTRL1 0x00000010
53#define AUART_CTRL2 0x00000020
54#define AUART_LINECTRL 0x00000030
55#define AUART_LINECTRL2 0x00000040
56#define AUART_INTR 0x00000050
57#define AUART_DATA 0x00000060
58#define AUART_STAT 0x00000070
59#define AUART_DEBUG 0x00000080
60#define AUART_VERSION 0x00000090
61#define AUART_AUTOBAUD 0x000000a0
62
63#define AUART_CTRL0_SFTRST (1 << 31)
64#define AUART_CTRL0_CLKGATE (1 << 30)
65#define AUART_CTRL0_RXTO_ENABLE (1 << 27)
66#define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
67#define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
68
69#define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
70
71#define AUART_CTRL2_DMAONERR (1 << 26)
72#define AUART_CTRL2_TXDMAE (1 << 25)
73#define AUART_CTRL2_RXDMAE (1 << 24)
74
75#define AUART_CTRL2_CTSEN (1 << 15)
76#define AUART_CTRL2_RTSEN (1 << 14)
77#define AUART_CTRL2_RTS (1 << 11)
78#define AUART_CTRL2_RXE (1 << 9)
79#define AUART_CTRL2_TXE (1 << 8)
80#define AUART_CTRL2_UARTEN (1 << 0)
81
82#define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc0
83#define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec
84#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
85#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
86#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
87#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
88#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
89#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
90#define AUART_LINECTRL_SPS (1 << 7)
91#define AUART_LINECTRL_WLEN_MASK 0x00000060
92#define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
93#define AUART_LINECTRL_FEN (1 << 4)
94#define AUART_LINECTRL_STP2 (1 << 3)
95#define AUART_LINECTRL_EPS (1 << 2)
96#define AUART_LINECTRL_PEN (1 << 1)
97#define AUART_LINECTRL_BRK (1 << 0)
98
99#define AUART_INTR_RTIEN (1 << 22)
100#define AUART_INTR_TXIEN (1 << 21)
101#define AUART_INTR_RXIEN (1 << 20)
102#define AUART_INTR_CTSMIEN (1 << 17)
103#define AUART_INTR_RTIS (1 << 6)
104#define AUART_INTR_TXIS (1 << 5)
105#define AUART_INTR_RXIS (1 << 4)
106#define AUART_INTR_CTSMIS (1 << 1)
107
108#define AUART_STAT_BUSY (1 << 29)
109#define AUART_STAT_CTS (1 << 28)
110#define AUART_STAT_TXFE (1 << 27)
111#define AUART_STAT_TXFF (1 << 25)
112#define AUART_STAT_RXFE (1 << 24)
113#define AUART_STAT_OERR (1 << 19)
114#define AUART_STAT_BERR (1 << 18)
115#define AUART_STAT_PERR (1 << 17)
116#define AUART_STAT_FERR (1 << 16)
117#define AUART_STAT_RXCOUNT_MASK 0xffff
118
119
120
121
122
123
124#define ASM9260_HW_CTRL0 0x0000
125
126
127
128
129#define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28)
130
131#define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25)
132
133
134
135
136
137
138#define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24)
139
140
141
142
143
144
145
146
147
148
149
150#define ASM9260_BM_CTRL0_RXTO_MASK (0xff << 16)
151
152#define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT (20 << 16)
153
154
155#define ASM9260_HW_CTRL1 0x0010
156
157
158
159
160#define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28)
161
162#define ASM9260_HW_CTRL2 0x0020
163
164
165
166
167
168
169
170
171
172#define ASM9260_BM_CTRL2_RXIFLSEL (7 << 20)
173#define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL (3 << 20)
174
175#define ASM9260_BM_CTRL2_TXIFLSEL (7 << 16)
176#define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL (2 << 16)
177
178#define ASM9260_BM_CTRL2_DTR BIT(10)
179
180#define ASM9260_BM_CTRL2_LBE BIT(7)
181#define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0)
182
183#define ASM9260_HW_LINECTRL 0x0030
184
185
186
187
188
189
190#define ASM9260_BM_LCTRL_SPS BIT(7)
191
192#define ASM9260_BM_LCTRL_WLEN (3 << 5)
193#define ASM9260_BM_LCTRL_CHRL_5 (0 << 5)
194#define ASM9260_BM_LCTRL_CHRL_6 (1 << 5)
195#define ASM9260_BM_LCTRL_CHRL_7 (2 << 5)
196#define ASM9260_BM_LCTRL_CHRL_8 (3 << 5)
197
198
199
200
201
202#define ASM9260_HW_INTR 0x0040
203
204#define ASM9260_BM_INTR_TFEIEN BIT(27)
205
206#define ASM9260_BM_INTR_OEIEN BIT(26)
207
208#define ASM9260_BM_INTR_BEIEN BIT(25)
209
210#define ASM9260_BM_INTR_PEIEN BIT(24)
211
212#define ASM9260_BM_INTR_FEIEN BIT(23)
213
214
215#define ASM9260_BM_INTR_DSRMIEN BIT(19)
216
217#define ASM9260_BM_INTR_DCDMIEN BIT(18)
218
219#define ASM9260_BM_INTR_RIMIEN BIT(16)
220
221#define ASM9260_BM_INTR_ABTO BIT(13)
222#define ASM9260_BM_INTR_ABEO BIT(12)
223
224#define ASM9260_BM_INTR_TFEIS BIT(11)
225
226#define ASM9260_BM_INTR_OEIS BIT(10)
227
228#define ASM9260_BM_INTR_BEIS BIT(9)
229
230#define ASM9260_BM_INTR_PEIS BIT(8)
231
232#define ASM9260_BM_INTR_FEIS BIT(7)
233#define ASM9260_BM_INTR_DSRMIS BIT(3)
234#define ASM9260_BM_INTR_DCDMIS BIT(2)
235#define ASM9260_BM_INTR_RIMIS BIT(0)
236
237
238
239
240
241
242#define ASM9260_HW_DATA 0x0050
243
244#define ASM9260_HW_STAT 0x0060
245
246#define ASM9260_BM_STAT_PRESENT BIT(31)
247
248#define ASM9260_BM_STAT_HISPEED BIT(30)
249
250#define ASM9260_BM_STAT_RXFULL BIT(26)
251
252
253#define ASM9260_HW_DEBUG 0x0070
254
255#define ASM9260_BM_DEBUG_TXDMARUN BIT(5)
256#define ASM9260_BM_DEBUG_RXDMARUN BIT(4)
257
258#define ASM9260_BM_DEBUG_TXCMDEND BIT(3)
259#define ASM9260_BM_DEBUG_RXCMDEND BIT(2)
260
261#define ASM9260_BM_DEBUG_TXDMARQ BIT(1)
262#define ASM9260_BM_DEBUG_RXDMARQ BIT(0)
263
264#define ASM9260_HW_ILPR 0x0080
265
266#define ASM9260_HW_RS485CTRL 0x0090
267
268
269
270
271
272
273
274#define ASM9260_BM_RS485CTRL_ONIV BIT(5)
275
276#define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4)
277
278
279
280
281#define ASM9260_BM_RS485CTRL_PINSEL BIT(3)
282
283#define ASM9260_BM_RS485CTRL_AADEN BIT(2)
284
285#define ASM9260_BM_RS485CTRL_RXDIS BIT(1)
286
287#define ASM9260_BM_RS485CTRL_RS485EN BIT(0)
288
289#define ASM9260_HW_RS485ADRMATCH 0x00a0
290
291#define ASM9260_BM_RS485ADRMATCH_MASK (0xff << 0)
292
293#define ASM9260_HW_RS485DLY 0x00b0
294
295
296
297
298#define ASM9260_BM_RS485DLY_MASK (0xff << 0)
299
300#define ASM9260_HW_AUTOBAUD 0x00c0
301
302#define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9)
303
304#define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8)
305
306#define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2)
307
308#define ASM9260_BM_AUTOBAUD_MODE BIT(1)
309
310
311
312
313#define ASM9260_BM_AUTOBAUD_START BIT(0)
314
315#define ASM9260_HW_CTRL3 0x00d0
316#define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK (0xffff << 16)
317
318
319
320
321#define ASM9260_BM_CTRL3_MASTERMODE BIT(6)
322
323#define ASM9260_BM_CTRL3_SYNCMODE BIT(4)
324
325#define ASM9260_BM_CTRL3_MSBF BIT(2)
326
327#define ASM9260_BM_CTRL3_BAUD8 BIT(1)
328
329#define ASM9260_BM_CTRL3_9BIT BIT(0)
330
331#define ASM9260_HW_ISO7816_CTRL 0x00e0
332
333#define ASM9260_BM_ISO7816CTRL_HS BIT(12)
334
335#define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8)
336#define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK (0xff << 4)
337
338#define ASM9260_BM_ISO7816CTRL_INACK BIT(3)
339#define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2)
340
341#define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0)
342
343#define ASM9260_HW_ISO7816_ERRCNT 0x00f0
344
345#define ASM9260_BM_ISO7816_NB_ERRORS_MASK (0xff << 0)
346
347#define ASM9260_HW_ISO7816_STATUS 0x0100
348
349#define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0)
350
351
352
353static struct uart_driver auart_driver;
354
355enum mxs_auart_type {
356 IMX23_AUART,
357 IMX28_AUART,
358 ASM9260_AUART,
359};
360
361struct vendor_data {
362 const u16 *reg_offset;
363};
364
365enum {
366 REG_CTRL0,
367 REG_CTRL1,
368 REG_CTRL2,
369 REG_LINECTRL,
370 REG_LINECTRL2,
371 REG_INTR,
372 REG_DATA,
373 REG_STAT,
374 REG_DEBUG,
375 REG_VERSION,
376 REG_AUTOBAUD,
377
378
379 REG_ARRAY_SIZE,
380};
381
382static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = {
383 [REG_CTRL0] = ASM9260_HW_CTRL0,
384 [REG_CTRL1] = ASM9260_HW_CTRL1,
385 [REG_CTRL2] = ASM9260_HW_CTRL2,
386 [REG_LINECTRL] = ASM9260_HW_LINECTRL,
387 [REG_INTR] = ASM9260_HW_INTR,
388 [REG_DATA] = ASM9260_HW_DATA,
389 [REG_STAT] = ASM9260_HW_STAT,
390 [REG_DEBUG] = ASM9260_HW_DEBUG,
391 [REG_AUTOBAUD] = ASM9260_HW_AUTOBAUD,
392};
393
394static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = {
395 [REG_CTRL0] = AUART_CTRL0,
396 [REG_CTRL1] = AUART_CTRL1,
397 [REG_CTRL2] = AUART_CTRL2,
398 [REG_LINECTRL] = AUART_LINECTRL,
399 [REG_LINECTRL2] = AUART_LINECTRL2,
400 [REG_INTR] = AUART_INTR,
401 [REG_DATA] = AUART_DATA,
402 [REG_STAT] = AUART_STAT,
403 [REG_DEBUG] = AUART_DEBUG,
404 [REG_VERSION] = AUART_VERSION,
405 [REG_AUTOBAUD] = AUART_AUTOBAUD,
406};
407
408static const struct vendor_data vendor_alphascale_asm9260 = {
409 .reg_offset = mxs_asm9260_offsets,
410};
411
412static const struct vendor_data vendor_freescale_stmp37xx = {
413 .reg_offset = mxs_stmp37xx_offsets,
414};
415
416struct mxs_auart_port {
417 struct uart_port port;
418
419#define MXS_AUART_DMA_ENABLED 0x2
420#define MXS_AUART_DMA_TX_SYNC 2
421#define MXS_AUART_DMA_RX_READY 3
422#define MXS_AUART_RTSCTS 4
423 unsigned long flags;
424 unsigned int mctrl_prev;
425 enum mxs_auart_type devtype;
426 const struct vendor_data *vendor;
427
428 struct clk *clk;
429 struct clk *clk_ahb;
430 struct device *dev;
431
432
433 struct scatterlist tx_sgl;
434 struct dma_chan *tx_dma_chan;
435 void *tx_dma_buf;
436
437 struct scatterlist rx_sgl;
438 struct dma_chan *rx_dma_chan;
439 void *rx_dma_buf;
440
441 struct mctrl_gpios *gpios;
442 int gpio_irq[UART_GPIO_MAX];
443 bool ms_irq_enabled;
444};
445
446static const struct of_device_id mxs_auart_dt_ids[] = {
447 {
448 .compatible = "fsl,imx28-auart",
449 .data = (const void *)IMX28_AUART
450 }, {
451 .compatible = "fsl,imx23-auart",
452 .data = (const void *)IMX23_AUART
453 }, {
454 .compatible = "alphascale,asm9260-auart",
455 .data = (const void *)ASM9260_AUART
456 }, { }
457};
458MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
459
460static inline int is_imx28_auart(struct mxs_auart_port *s)
461{
462 return s->devtype == IMX28_AUART;
463}
464
465static inline int is_asm9260_auart(struct mxs_auart_port *s)
466{
467 return s->devtype == ASM9260_AUART;
468}
469
470static inline bool auart_dma_enabled(struct mxs_auart_port *s)
471{
472 return s->flags & MXS_AUART_DMA_ENABLED;
473}
474
475static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap,
476 unsigned int reg)
477{
478 return uap->vendor->reg_offset[reg];
479}
480
481static unsigned int mxs_read(const struct mxs_auart_port *uap,
482 unsigned int reg)
483{
484 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
485
486 return readl_relaxed(addr);
487}
488
489static void mxs_write(unsigned int val, struct mxs_auart_port *uap,
490 unsigned int reg)
491{
492 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
493
494 writel_relaxed(val, addr);
495}
496
497static void mxs_set(unsigned int val, struct mxs_auart_port *uap,
498 unsigned int reg)
499{
500 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
501
502 writel_relaxed(val, addr + SET_REG);
503}
504
505static void mxs_clr(unsigned int val, struct mxs_auart_port *uap,
506 unsigned int reg)
507{
508 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
509
510 writel_relaxed(val, addr + CLR_REG);
511}
512
513static void mxs_auart_stop_tx(struct uart_port *u);
514
515#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
516
517static void mxs_auart_tx_chars(struct mxs_auart_port *s);
518
519static void dma_tx_callback(void *param)
520{
521 struct mxs_auart_port *s = param;
522 struct circ_buf *xmit = &s->port.state->xmit;
523
524 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
525
526
527 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
528 smp_mb__after_atomic();
529
530
531 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
532 uart_write_wakeup(&s->port);
533
534 mxs_auart_tx_chars(s);
535}
536
537static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
538{
539 struct dma_async_tx_descriptor *desc;
540 struct scatterlist *sgl = &s->tx_sgl;
541 struct dma_chan *channel = s->tx_dma_chan;
542 u32 pio;
543
544
545 pio = AUART_CTRL1_XFER_COUNT(size);
546 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
547 1, DMA_TRANS_NONE, 0);
548 if (!desc) {
549 dev_err(s->dev, "step 1 error\n");
550 return -EINVAL;
551 }
552
553
554 sg_init_one(sgl, s->tx_dma_buf, size);
555 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
556 desc = dmaengine_prep_slave_sg(channel, sgl,
557 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
558 if (!desc) {
559 dev_err(s->dev, "step 2 error\n");
560 return -EINVAL;
561 }
562
563
564 desc->callback = dma_tx_callback;
565 desc->callback_param = s;
566 dmaengine_submit(desc);
567 dma_async_issue_pending(channel);
568 return 0;
569}
570
571static void mxs_auart_tx_chars(struct mxs_auart_port *s)
572{
573 struct circ_buf *xmit = &s->port.state->xmit;
574
575 if (auart_dma_enabled(s)) {
576 u32 i = 0;
577 int size;
578 void *buffer = s->tx_dma_buf;
579
580 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
581 return;
582
583 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
584 size = min_t(u32, UART_XMIT_SIZE - i,
585 CIRC_CNT_TO_END(xmit->head,
586 xmit->tail,
587 UART_XMIT_SIZE));
588 memcpy(buffer + i, xmit->buf + xmit->tail, size);
589 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
590
591 i += size;
592 if (i >= UART_XMIT_SIZE)
593 break;
594 }
595
596 if (uart_tx_stopped(&s->port))
597 mxs_auart_stop_tx(&s->port);
598
599 if (i) {
600 mxs_auart_dma_tx(s, i);
601 } else {
602 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
603 smp_mb__after_atomic();
604 }
605 return;
606 }
607
608
609 while (!(mxs_read(s, REG_STAT) & AUART_STAT_TXFF)) {
610 if (s->port.x_char) {
611 s->port.icount.tx++;
612 mxs_write(s->port.x_char, s, REG_DATA);
613 s->port.x_char = 0;
614 continue;
615 }
616 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
617 s->port.icount.tx++;
618 mxs_write(xmit->buf[xmit->tail], s, REG_DATA);
619 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
620 } else
621 break;
622 }
623 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
624 uart_write_wakeup(&s->port);
625
626 if (uart_circ_empty(&(s->port.state->xmit)))
627 mxs_clr(AUART_INTR_TXIEN, s, REG_INTR);
628 else
629 mxs_set(AUART_INTR_TXIEN, s, REG_INTR);
630
631 if (uart_tx_stopped(&s->port))
632 mxs_auart_stop_tx(&s->port);
633}
634
635static void mxs_auart_rx_char(struct mxs_auart_port *s)
636{
637 int flag;
638 u32 stat;
639 u8 c;
640
641 c = mxs_read(s, REG_DATA);
642 stat = mxs_read(s, REG_STAT);
643
644 flag = TTY_NORMAL;
645 s->port.icount.rx++;
646
647 if (stat & AUART_STAT_BERR) {
648 s->port.icount.brk++;
649 if (uart_handle_break(&s->port))
650 goto out;
651 } else if (stat & AUART_STAT_PERR) {
652 s->port.icount.parity++;
653 } else if (stat & AUART_STAT_FERR) {
654 s->port.icount.frame++;
655 }
656
657
658
659
660 stat &= s->port.read_status_mask;
661
662 if (stat & AUART_STAT_BERR) {
663 flag = TTY_BREAK;
664 } else if (stat & AUART_STAT_PERR)
665 flag = TTY_PARITY;
666 else if (stat & AUART_STAT_FERR)
667 flag = TTY_FRAME;
668
669 if (stat & AUART_STAT_OERR)
670 s->port.icount.overrun++;
671
672 if (uart_handle_sysrq_char(&s->port, c))
673 goto out;
674
675 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
676out:
677 mxs_write(stat, s, REG_STAT);
678}
679
680static void mxs_auart_rx_chars(struct mxs_auart_port *s)
681{
682 u32 stat = 0;
683
684 for (;;) {
685 stat = mxs_read(s, REG_STAT);
686 if (stat & AUART_STAT_RXFE)
687 break;
688 mxs_auart_rx_char(s);
689 }
690
691 mxs_write(stat, s, REG_STAT);
692 tty_flip_buffer_push(&s->port.state->port);
693}
694
695static int mxs_auart_request_port(struct uart_port *u)
696{
697 return 0;
698}
699
700static int mxs_auart_verify_port(struct uart_port *u,
701 struct serial_struct *ser)
702{
703 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
704 return -EINVAL;
705 return 0;
706}
707
708static void mxs_auart_config_port(struct uart_port *u, int flags)
709{
710}
711
712static const char *mxs_auart_type(struct uart_port *u)
713{
714 struct mxs_auart_port *s = to_auart_port(u);
715
716 return dev_name(s->dev);
717}
718
719static void mxs_auart_release_port(struct uart_port *u)
720{
721}
722
723static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
724{
725 struct mxs_auart_port *s = to_auart_port(u);
726
727 u32 ctrl = mxs_read(s, REG_CTRL2);
728
729 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
730 if (mctrl & TIOCM_RTS) {
731 if (uart_cts_enabled(u))
732 ctrl |= AUART_CTRL2_RTSEN;
733 else
734 ctrl |= AUART_CTRL2_RTS;
735 }
736
737 mxs_write(ctrl, s, REG_CTRL2);
738
739 mctrl_gpio_set(s->gpios, mctrl);
740}
741
742#define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
743static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)
744{
745 u32 mctrl_diff;
746
747 mctrl_diff = mctrl ^ s->mctrl_prev;
748 s->mctrl_prev = mctrl;
749 if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled &&
750 s->port.state != NULL) {
751 if (mctrl_diff & TIOCM_RI)
752 s->port.icount.rng++;
753 if (mctrl_diff & TIOCM_DSR)
754 s->port.icount.dsr++;
755 if (mctrl_diff & TIOCM_CD)
756 uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD);
757 if (mctrl_diff & TIOCM_CTS)
758 uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS);
759
760 wake_up_interruptible(&s->port.state->port.delta_msr_wait);
761 }
762 return mctrl;
763}
764
765static u32 mxs_auart_get_mctrl(struct uart_port *u)
766{
767 struct mxs_auart_port *s = to_auart_port(u);
768 u32 stat = mxs_read(s, REG_STAT);
769 u32 mctrl = 0;
770
771 if (stat & AUART_STAT_CTS)
772 mctrl |= TIOCM_CTS;
773
774 return mctrl_gpio_get(s->gpios, &mctrl);
775}
776
777
778
779
780static void mxs_auart_enable_ms(struct uart_port *port)
781{
782 struct mxs_auart_port *s = to_auart_port(port);
783
784
785
786
787 if (s->ms_irq_enabled)
788 return;
789
790 s->ms_irq_enabled = true;
791
792 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
793 enable_irq(s->gpio_irq[UART_GPIO_CTS]);
794
795
796 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
797 enable_irq(s->gpio_irq[UART_GPIO_DSR]);
798
799 if (s->gpio_irq[UART_GPIO_RI] >= 0)
800 enable_irq(s->gpio_irq[UART_GPIO_RI]);
801
802 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
803 enable_irq(s->gpio_irq[UART_GPIO_DCD]);
804}
805
806
807
808
809static void mxs_auart_disable_ms(struct uart_port *port)
810{
811 struct mxs_auart_port *s = to_auart_port(port);
812
813
814
815
816 if (!s->ms_irq_enabled)
817 return;
818
819 s->ms_irq_enabled = false;
820
821 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
822 disable_irq(s->gpio_irq[UART_GPIO_CTS]);
823
824
825 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
826 disable_irq(s->gpio_irq[UART_GPIO_DSR]);
827
828 if (s->gpio_irq[UART_GPIO_RI] >= 0)
829 disable_irq(s->gpio_irq[UART_GPIO_RI]);
830
831 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
832 disable_irq(s->gpio_irq[UART_GPIO_DCD]);
833}
834
835static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
836static void dma_rx_callback(void *arg)
837{
838 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
839 struct tty_port *port = &s->port.state->port;
840 int count;
841 u32 stat;
842
843 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
844
845 stat = mxs_read(s, REG_STAT);
846 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
847 AUART_STAT_PERR | AUART_STAT_FERR);
848
849 count = stat & AUART_STAT_RXCOUNT_MASK;
850 tty_insert_flip_string(port, s->rx_dma_buf, count);
851
852 mxs_write(stat, s, REG_STAT);
853 tty_flip_buffer_push(port);
854
855
856 mxs_auart_dma_prep_rx(s);
857}
858
859static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
860{
861 struct dma_async_tx_descriptor *desc;
862 struct scatterlist *sgl = &s->rx_sgl;
863 struct dma_chan *channel = s->rx_dma_chan;
864 u32 pio[1];
865
866
867 pio[0] = AUART_CTRL0_RXTO_ENABLE
868 | AUART_CTRL0_RXTIMEOUT(0x80)
869 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
870 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
871 1, DMA_TRANS_NONE, 0);
872 if (!desc) {
873 dev_err(s->dev, "step 1 error\n");
874 return -EINVAL;
875 }
876
877
878 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
879 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
880 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
881 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
882 if (!desc) {
883 dev_err(s->dev, "step 2 error\n");
884 return -1;
885 }
886
887
888 desc->callback = dma_rx_callback;
889 desc->callback_param = s;
890 dmaengine_submit(desc);
891 dma_async_issue_pending(channel);
892 return 0;
893}
894
895static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
896{
897 if (s->tx_dma_chan) {
898 dma_release_channel(s->tx_dma_chan);
899 s->tx_dma_chan = NULL;
900 }
901 if (s->rx_dma_chan) {
902 dma_release_channel(s->rx_dma_chan);
903 s->rx_dma_chan = NULL;
904 }
905
906 kfree(s->tx_dma_buf);
907 kfree(s->rx_dma_buf);
908 s->tx_dma_buf = NULL;
909 s->rx_dma_buf = NULL;
910}
911
912static void mxs_auart_dma_exit(struct mxs_auart_port *s)
913{
914
915 mxs_clr(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
916 s, REG_CTRL2);
917
918 mxs_auart_dma_exit_channel(s);
919 s->flags &= ~MXS_AUART_DMA_ENABLED;
920 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
921 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
922}
923
924static int mxs_auart_dma_init(struct mxs_auart_port *s)
925{
926 if (auart_dma_enabled(s))
927 return 0;
928
929
930 s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
931 if (!s->rx_dma_chan)
932 goto err_out;
933 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
934 if (!s->rx_dma_buf)
935 goto err_out;
936
937
938 s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
939 if (!s->tx_dma_chan)
940 goto err_out;
941 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
942 if (!s->tx_dma_buf)
943 goto err_out;
944
945
946 s->flags |= MXS_AUART_DMA_ENABLED;
947 dev_dbg(s->dev, "enabled the DMA support.");
948
949
950 s->port.fifosize = UART_XMIT_SIZE;
951
952 return 0;
953
954err_out:
955 mxs_auart_dma_exit_channel(s);
956 return -EINVAL;
957
958}
959
960#define RTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_RTS)
961#define CTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_CTS)
962static void mxs_auart_settermios(struct uart_port *u,
963 struct ktermios *termios,
964 struct ktermios *old)
965{
966 struct mxs_auart_port *s = to_auart_port(u);
967 u32 bm, ctrl, ctrl2, div;
968 unsigned int cflag, baud, baud_min, baud_max;
969
970 cflag = termios->c_cflag;
971
972 ctrl = AUART_LINECTRL_FEN;
973 ctrl2 = mxs_read(s, REG_CTRL2);
974
975
976 switch (cflag & CSIZE) {
977 case CS5:
978 bm = 0;
979 break;
980 case CS6:
981 bm = 1;
982 break;
983 case CS7:
984 bm = 2;
985 break;
986 case CS8:
987 bm = 3;
988 break;
989 default:
990 return;
991 }
992
993 ctrl |= AUART_LINECTRL_WLEN(bm);
994
995
996 if (cflag & PARENB) {
997 ctrl |= AUART_LINECTRL_PEN;
998 if ((cflag & PARODD) == 0)
999 ctrl |= AUART_LINECTRL_EPS;
1000 if (cflag & CMSPAR)
1001 ctrl |= AUART_LINECTRL_SPS;
1002 }
1003
1004 u->read_status_mask = AUART_STAT_OERR;
1005
1006 if (termios->c_iflag & INPCK)
1007 u->read_status_mask |= AUART_STAT_PERR;
1008 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1009 u->read_status_mask |= AUART_STAT_BERR;
1010
1011
1012
1013
1014 u->ignore_status_mask = 0;
1015 if (termios->c_iflag & IGNPAR)
1016 u->ignore_status_mask |= AUART_STAT_PERR;
1017 if (termios->c_iflag & IGNBRK) {
1018 u->ignore_status_mask |= AUART_STAT_BERR;
1019
1020
1021
1022
1023 if (termios->c_iflag & IGNPAR)
1024 u->ignore_status_mask |= AUART_STAT_OERR;
1025 }
1026
1027
1028
1029
1030 if (cflag & CREAD)
1031 ctrl2 |= AUART_CTRL2_RXE;
1032 else
1033 ctrl2 &= ~AUART_CTRL2_RXE;
1034
1035
1036 if (cflag & CSTOPB)
1037 ctrl |= AUART_LINECTRL_STP2;
1038
1039
1040 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
1041 if (cflag & CRTSCTS) {
1042
1043
1044
1045
1046
1047
1048 if (is_imx28_auart(s)
1049 && test_bit(MXS_AUART_RTSCTS, &s->flags)) {
1050 if (!mxs_auart_dma_init(s))
1051
1052 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
1053 | AUART_CTRL2_DMAONERR;
1054 }
1055
1056
1057 ctrl2 |= AUART_CTRL2_RTSEN;
1058 if (CTS_AT_AUART())
1059 ctrl2 |= AUART_CTRL2_CTSEN;
1060 }
1061
1062
1063 if (is_asm9260_auart(s)) {
1064 baud = uart_get_baud_rate(u, termios, old,
1065 u->uartclk * 4 / 0x3FFFFF,
1066 u->uartclk / 16);
1067 div = u->uartclk * 4 / baud;
1068 } else {
1069 baud_min = DIV_ROUND_UP(u->uartclk * 32,
1070 AUART_LINECTRL_BAUD_DIV_MAX);
1071 baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN;
1072 baud = uart_get_baud_rate(u, termios, old, baud_min, baud_max);
1073 div = DIV_ROUND_CLOSEST(u->uartclk * 32, baud);
1074 }
1075
1076 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
1077 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
1078 mxs_write(ctrl, s, REG_LINECTRL);
1079
1080 mxs_write(ctrl2, s, REG_CTRL2);
1081
1082 uart_update_timeout(u, termios->c_cflag, baud);
1083
1084
1085 if (auart_dma_enabled(s) &&
1086 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
1087 if (!mxs_auart_dma_prep_rx(s)) {
1088
1089 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
1090 s, REG_INTR);
1091 } else {
1092 mxs_auart_dma_exit(s);
1093 dev_err(s->dev, "We can not start up the DMA.\n");
1094 }
1095 }
1096
1097
1098 if (UART_ENABLE_MS(u, termios->c_cflag))
1099 mxs_auart_enable_ms(u);
1100 else
1101 mxs_auart_disable_ms(u);
1102}
1103
1104static void mxs_auart_set_ldisc(struct uart_port *port,
1105 struct ktermios *termios)
1106{
1107 if (termios->c_line == N_PPS) {
1108 port->flags |= UPF_HARDPPS_CD;
1109 mxs_auart_enable_ms(port);
1110 } else {
1111 port->flags &= ~UPF_HARDPPS_CD;
1112 }
1113}
1114
1115static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
1116{
1117 u32 istat;
1118 struct mxs_auart_port *s = context;
1119 u32 mctrl_temp = s->mctrl_prev;
1120 u32 stat = mxs_read(s, REG_STAT);
1121
1122 istat = mxs_read(s, REG_INTR);
1123
1124
1125 mxs_clr(istat & (AUART_INTR_RTIS | AUART_INTR_TXIS | AUART_INTR_RXIS
1126 | AUART_INTR_CTSMIS), s, REG_INTR);
1127
1128
1129
1130
1131 if (irq == s->gpio_irq[UART_GPIO_CTS] ||
1132 irq == s->gpio_irq[UART_GPIO_DCD] ||
1133 irq == s->gpio_irq[UART_GPIO_DSR] ||
1134 irq == s->gpio_irq[UART_GPIO_RI])
1135 mxs_auart_modem_status(s,
1136 mctrl_gpio_get(s->gpios, &mctrl_temp));
1137
1138 if (istat & AUART_INTR_CTSMIS) {
1139 if (CTS_AT_AUART() && s->ms_irq_enabled)
1140 uart_handle_cts_change(&s->port,
1141 stat & AUART_STAT_CTS);
1142 mxs_clr(AUART_INTR_CTSMIS, s, REG_INTR);
1143 istat &= ~AUART_INTR_CTSMIS;
1144 }
1145
1146 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
1147 if (!auart_dma_enabled(s))
1148 mxs_auart_rx_chars(s);
1149 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
1150 }
1151
1152 if (istat & AUART_INTR_TXIS) {
1153 mxs_auart_tx_chars(s);
1154 istat &= ~AUART_INTR_TXIS;
1155 }
1156
1157 return IRQ_HANDLED;
1158}
1159
1160static void mxs_auart_reset_deassert(struct mxs_auart_port *s)
1161{
1162 int i;
1163 unsigned int reg;
1164
1165 mxs_clr(AUART_CTRL0_SFTRST, s, REG_CTRL0);
1166
1167 for (i = 0; i < 10000; i++) {
1168 reg = mxs_read(s, REG_CTRL0);
1169 if (!(reg & AUART_CTRL0_SFTRST))
1170 break;
1171 udelay(3);
1172 }
1173 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1174}
1175
1176static void mxs_auart_reset_assert(struct mxs_auart_port *s)
1177{
1178 int i;
1179 u32 reg;
1180
1181 reg = mxs_read(s, REG_CTRL0);
1182
1183 if (reg & AUART_CTRL0_SFTRST)
1184 return;
1185
1186 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1187 mxs_set(AUART_CTRL0_SFTRST, s, REG_CTRL0);
1188
1189 for (i = 0; i < 1000; i++) {
1190 reg = mxs_read(s, REG_CTRL0);
1191
1192 if (reg & AUART_CTRL0_CLKGATE)
1193 return;
1194 udelay(10);
1195 }
1196
1197 dev_err(s->dev, "Failed to reset the unit.");
1198}
1199
1200static int mxs_auart_startup(struct uart_port *u)
1201{
1202 int ret;
1203 struct mxs_auart_port *s = to_auart_port(u);
1204
1205 ret = clk_prepare_enable(s->clk);
1206 if (ret)
1207 return ret;
1208
1209 if (uart_console(u)) {
1210 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1211 } else {
1212
1213 mxs_auart_reset_assert(s);
1214 mxs_auart_reset_deassert(s);
1215 }
1216
1217 mxs_set(AUART_CTRL2_UARTEN, s, REG_CTRL2);
1218
1219 mxs_write(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
1220 s, REG_INTR);
1221
1222
1223 u->fifosize = MXS_AUART_FIFO_SIZE;
1224
1225
1226
1227
1228
1229 mxs_set(AUART_LINECTRL_FEN, s, REG_LINECTRL);
1230
1231
1232 mctrl_gpio_get(s->gpios, &s->mctrl_prev);
1233
1234 s->ms_irq_enabled = false;
1235 return 0;
1236}
1237
1238static void mxs_auart_shutdown(struct uart_port *u)
1239{
1240 struct mxs_auart_port *s = to_auart_port(u);
1241
1242 mxs_auart_disable_ms(u);
1243
1244 if (auart_dma_enabled(s))
1245 mxs_auart_dma_exit(s);
1246
1247 if (uart_console(u)) {
1248 mxs_clr(AUART_CTRL2_UARTEN, s, REG_CTRL2);
1249
1250 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN |
1251 AUART_INTR_CTSMIEN, s, REG_INTR);
1252 mxs_set(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1253 } else {
1254 mxs_auart_reset_assert(s);
1255 }
1256
1257 clk_disable_unprepare(s->clk);
1258}
1259
1260static unsigned int mxs_auart_tx_empty(struct uart_port *u)
1261{
1262 struct mxs_auart_port *s = to_auart_port(u);
1263
1264 if ((mxs_read(s, REG_STAT) &
1265 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE)
1266 return TIOCSER_TEMT;
1267
1268 return 0;
1269}
1270
1271static void mxs_auart_start_tx(struct uart_port *u)
1272{
1273 struct mxs_auart_port *s = to_auart_port(u);
1274
1275
1276 mxs_set(AUART_CTRL2_TXE, s, REG_CTRL2);
1277
1278 mxs_auart_tx_chars(s);
1279}
1280
1281static void mxs_auart_stop_tx(struct uart_port *u)
1282{
1283 struct mxs_auart_port *s = to_auart_port(u);
1284
1285 mxs_clr(AUART_CTRL2_TXE, s, REG_CTRL2);
1286}
1287
1288static void mxs_auart_stop_rx(struct uart_port *u)
1289{
1290 struct mxs_auart_port *s = to_auart_port(u);
1291
1292 mxs_clr(AUART_CTRL2_RXE, s, REG_CTRL2);
1293}
1294
1295static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
1296{
1297 struct mxs_auart_port *s = to_auart_port(u);
1298
1299 if (ctl)
1300 mxs_set(AUART_LINECTRL_BRK, s, REG_LINECTRL);
1301 else
1302 mxs_clr(AUART_LINECTRL_BRK, s, REG_LINECTRL);
1303}
1304
1305static const struct uart_ops mxs_auart_ops = {
1306 .tx_empty = mxs_auart_tx_empty,
1307 .start_tx = mxs_auart_start_tx,
1308 .stop_tx = mxs_auart_stop_tx,
1309 .stop_rx = mxs_auart_stop_rx,
1310 .enable_ms = mxs_auart_enable_ms,
1311 .break_ctl = mxs_auart_break_ctl,
1312 .set_mctrl = mxs_auart_set_mctrl,
1313 .get_mctrl = mxs_auart_get_mctrl,
1314 .startup = mxs_auart_startup,
1315 .shutdown = mxs_auart_shutdown,
1316 .set_termios = mxs_auart_settermios,
1317 .set_ldisc = mxs_auart_set_ldisc,
1318 .type = mxs_auart_type,
1319 .release_port = mxs_auart_release_port,
1320 .request_port = mxs_auart_request_port,
1321 .config_port = mxs_auart_config_port,
1322 .verify_port = mxs_auart_verify_port,
1323};
1324
1325static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
1326
1327#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1328static void mxs_auart_console_putchar(struct uart_port *port, int ch)
1329{
1330 struct mxs_auart_port *s = to_auart_port(port);
1331 unsigned int to = 1000;
1332
1333 while (mxs_read(s, REG_STAT) & AUART_STAT_TXFF) {
1334 if (!to--)
1335 break;
1336 udelay(1);
1337 }
1338
1339 mxs_write(ch, s, REG_DATA);
1340}
1341
1342static void
1343auart_console_write(struct console *co, const char *str, unsigned int count)
1344{
1345 struct mxs_auart_port *s;
1346 struct uart_port *port;
1347 unsigned int old_ctrl0, old_ctrl2;
1348 unsigned int to = 20000;
1349
1350 if (co->index >= MXS_AUART_PORTS || co->index < 0)
1351 return;
1352
1353 s = auart_port[co->index];
1354 port = &s->port;
1355
1356 clk_enable(s->clk);
1357
1358
1359 old_ctrl2 = mxs_read(s, REG_CTRL2);
1360 old_ctrl0 = mxs_read(s, REG_CTRL0);
1361
1362 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1363 mxs_set(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, s, REG_CTRL2);
1364
1365 uart_console_write(port, str, count, mxs_auart_console_putchar);
1366
1367
1368 while (mxs_read(s, REG_STAT) & AUART_STAT_BUSY) {
1369 udelay(1);
1370 if (!to--)
1371 break;
1372 }
1373
1374
1375
1376
1377
1378
1379
1380 if (!(mxs_read(s, REG_STAT) & AUART_STAT_BUSY)) {
1381 mxs_write(old_ctrl0, s, REG_CTRL0);
1382 mxs_write(old_ctrl2, s, REG_CTRL2);
1383 }
1384
1385 clk_disable(s->clk);
1386}
1387
1388static void __init
1389auart_console_get_options(struct mxs_auart_port *s, int *baud,
1390 int *parity, int *bits)
1391{
1392 struct uart_port *port = &s->port;
1393 unsigned int lcr_h, quot;
1394
1395 if (!(mxs_read(s, REG_CTRL2) & AUART_CTRL2_UARTEN))
1396 return;
1397
1398 lcr_h = mxs_read(s, REG_LINECTRL);
1399
1400 *parity = 'n';
1401 if (lcr_h & AUART_LINECTRL_PEN) {
1402 if (lcr_h & AUART_LINECTRL_EPS)
1403 *parity = 'e';
1404 else
1405 *parity = 'o';
1406 }
1407
1408 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
1409 *bits = 7;
1410 else
1411 *bits = 8;
1412
1413 quot = ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVINT_MASK))
1414 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
1415 quot |= ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
1416 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
1417 if (quot == 0)
1418 quot = 1;
1419
1420 *baud = (port->uartclk << 2) / quot;
1421}
1422
1423static int __init
1424auart_console_setup(struct console *co, char *options)
1425{
1426 struct mxs_auart_port *s;
1427 int baud = 9600;
1428 int bits = 8;
1429 int parity = 'n';
1430 int flow = 'n';
1431 int ret;
1432
1433
1434
1435
1436
1437
1438 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
1439 co->index = 0;
1440 s = auart_port[co->index];
1441 if (!s)
1442 return -ENODEV;
1443
1444 ret = clk_prepare_enable(s->clk);
1445 if (ret)
1446 return ret;
1447
1448 if (options)
1449 uart_parse_options(options, &baud, &parity, &bits, &flow);
1450 else
1451 auart_console_get_options(s, &baud, &parity, &bits);
1452
1453 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
1454
1455 clk_disable_unprepare(s->clk);
1456
1457 return ret;
1458}
1459
1460static struct console auart_console = {
1461 .name = "ttyAPP",
1462 .write = auart_console_write,
1463 .device = uart_console_device,
1464 .setup = auart_console_setup,
1465 .flags = CON_PRINTBUFFER,
1466 .index = -1,
1467 .data = &auart_driver,
1468};
1469#endif
1470
1471static struct uart_driver auart_driver = {
1472 .owner = THIS_MODULE,
1473 .driver_name = "ttyAPP",
1474 .dev_name = "ttyAPP",
1475 .major = 0,
1476 .minor = 0,
1477 .nr = MXS_AUART_PORTS,
1478#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1479 .cons = &auart_console,
1480#endif
1481};
1482
1483static void mxs_init_regs(struct mxs_auart_port *s)
1484{
1485 if (is_asm9260_auart(s))
1486 s->vendor = &vendor_alphascale_asm9260;
1487 else
1488 s->vendor = &vendor_freescale_stmp37xx;
1489}
1490
1491static int mxs_get_clks(struct mxs_auart_port *s,
1492 struct platform_device *pdev)
1493{
1494 int err;
1495
1496 if (!is_asm9260_auart(s)) {
1497 s->clk = devm_clk_get(&pdev->dev, NULL);
1498 return PTR_ERR_OR_ZERO(s->clk);
1499 }
1500
1501 s->clk = devm_clk_get(s->dev, "mod");
1502 if (IS_ERR(s->clk)) {
1503 dev_err(s->dev, "Failed to get \"mod\" clk\n");
1504 return PTR_ERR(s->clk);
1505 }
1506
1507 s->clk_ahb = devm_clk_get(s->dev, "ahb");
1508 if (IS_ERR(s->clk_ahb)) {
1509 dev_err(s->dev, "Failed to get \"ahb\" clk\n");
1510 return PTR_ERR(s->clk_ahb);
1511 }
1512
1513 err = clk_prepare_enable(s->clk_ahb);
1514 if (err) {
1515 dev_err(s->dev, "Failed to enable ahb_clk!\n");
1516 return err;
1517 }
1518
1519 err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb));
1520 if (err) {
1521 dev_err(s->dev, "Failed to set rate!\n");
1522 goto disable_clk_ahb;
1523 }
1524
1525 err = clk_prepare_enable(s->clk);
1526 if (err) {
1527 dev_err(s->dev, "Failed to enable clk!\n");
1528 goto disable_clk_ahb;
1529 }
1530
1531 return 0;
1532
1533disable_clk_ahb:
1534 clk_disable_unprepare(s->clk_ahb);
1535 return err;
1536}
1537
1538
1539
1540
1541
1542static int serial_mxs_probe_dt(struct mxs_auart_port *s,
1543 struct platform_device *pdev)
1544{
1545 struct device_node *np = pdev->dev.of_node;
1546 int ret;
1547
1548 if (!np)
1549
1550 return 1;
1551
1552 ret = of_alias_get_id(np, "serial");
1553 if (ret < 0) {
1554 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1555 return ret;
1556 }
1557 s->port.line = ret;
1558
1559 if (of_get_property(np, "uart-has-rtscts", NULL) ||
1560 of_get_property(np, "fsl,uart-has-rtscts", NULL) )
1561 set_bit(MXS_AUART_RTSCTS, &s->flags);
1562
1563 return 0;
1564}
1565
1566static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)
1567{
1568 enum mctrl_gpio_idx i;
1569 struct gpio_desc *gpiod;
1570
1571 s->gpios = mctrl_gpio_init_noauto(dev, 0);
1572 if (IS_ERR(s->gpios))
1573 return PTR_ERR(s->gpios);
1574
1575
1576 if (!RTS_AT_AUART() || !CTS_AT_AUART()) {
1577 if (test_bit(MXS_AUART_RTSCTS, &s->flags))
1578 dev_warn(dev,
1579 "DMA and flow control via gpio may cause some problems. DMA disabled!\n");
1580 clear_bit(MXS_AUART_RTSCTS, &s->flags);
1581 }
1582
1583 for (i = 0; i < UART_GPIO_MAX; i++) {
1584 gpiod = mctrl_gpio_to_gpiod(s->gpios, i);
1585 if (gpiod && (gpiod_get_direction(gpiod) == 1))
1586 s->gpio_irq[i] = gpiod_to_irq(gpiod);
1587 else
1588 s->gpio_irq[i] = -EINVAL;
1589 }
1590
1591 return 0;
1592}
1593
1594static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)
1595{
1596 enum mctrl_gpio_idx i;
1597
1598 for (i = 0; i < UART_GPIO_MAX; i++)
1599 if (s->gpio_irq[i] >= 0)
1600 free_irq(s->gpio_irq[i], s);
1601}
1602
1603static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
1604{
1605 int *irq = s->gpio_irq;
1606 enum mctrl_gpio_idx i;
1607 int err = 0;
1608
1609 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1610 if (irq[i] < 0)
1611 continue;
1612
1613 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1614 err = request_irq(irq[i], mxs_auart_irq_handle,
1615 IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);
1616 if (err)
1617 dev_err(s->dev, "%s - Can't get %d irq\n",
1618 __func__, irq[i]);
1619 }
1620
1621
1622
1623
1624
1625 while (err && (i-- > 0))
1626 if (irq[i] >= 0)
1627 free_irq(irq[i], s);
1628
1629 return err;
1630}
1631
1632static int mxs_auart_probe(struct platform_device *pdev)
1633{
1634 struct mxs_auart_port *s;
1635 u32 version;
1636 int ret, irq;
1637 struct resource *r;
1638
1639 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
1640 if (!s)
1641 return -ENOMEM;
1642
1643 s->port.dev = &pdev->dev;
1644 s->dev = &pdev->dev;
1645
1646 ret = serial_mxs_probe_dt(s, pdev);
1647 if (ret > 0)
1648 s->port.line = pdev->id < 0 ? 0 : pdev->id;
1649 else if (ret < 0)
1650 return ret;
1651 if (s->port.line >= ARRAY_SIZE(auart_port)) {
1652 dev_err(&pdev->dev, "serial%d out of range\n", s->port.line);
1653 return -EINVAL;
1654 }
1655
1656 s->devtype = (enum mxs_auart_type)of_device_get_match_data(&pdev->dev);
1657
1658 ret = mxs_get_clks(s, pdev);
1659 if (ret)
1660 return ret;
1661
1662 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1663 if (!r) {
1664 ret = -ENXIO;
1665 goto out_disable_clks;
1666 }
1667
1668 s->port.mapbase = r->start;
1669 s->port.membase = ioremap(r->start, resource_size(r));
1670 if (!s->port.membase) {
1671 ret = -ENOMEM;
1672 goto out_disable_clks;
1673 }
1674 s->port.ops = &mxs_auart_ops;
1675 s->port.iotype = UPIO_MEM;
1676 s->port.fifosize = MXS_AUART_FIFO_SIZE;
1677 s->port.uartclk = clk_get_rate(s->clk);
1678 s->port.type = PORT_IMX;
1679 s->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_MXS_AUART_CONSOLE);
1680
1681 mxs_init_regs(s);
1682
1683 s->mctrl_prev = 0;
1684
1685 irq = platform_get_irq(pdev, 0);
1686 if (irq < 0) {
1687 ret = irq;
1688 goto out_iounmap;
1689 }
1690
1691 s->port.irq = irq;
1692 ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,
1693 dev_name(&pdev->dev), s);
1694 if (ret)
1695 goto out_iounmap;
1696
1697 platform_set_drvdata(pdev, s);
1698
1699 ret = mxs_auart_init_gpios(s, &pdev->dev);
1700 if (ret) {
1701 dev_err(&pdev->dev, "Failed to initialize GPIOs.\n");
1702 goto out_iounmap;
1703 }
1704
1705
1706
1707
1708 ret = mxs_auart_request_gpio_irq(s);
1709 if (ret)
1710 goto out_iounmap;
1711
1712 auart_port[s->port.line] = s;
1713
1714 mxs_auart_reset_deassert(s);
1715
1716 ret = uart_add_one_port(&auart_driver, &s->port);
1717 if (ret)
1718 goto out_free_qpio_irq;
1719
1720
1721 if (is_asm9260_auart(s)) {
1722 dev_info(&pdev->dev, "Found APPUART ASM9260\n");
1723 } else {
1724 version = mxs_read(s, REG_VERSION);
1725 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1726 (version >> 24) & 0xff,
1727 (version >> 16) & 0xff, version & 0xffff);
1728 }
1729
1730 return 0;
1731
1732out_free_qpio_irq:
1733 mxs_auart_free_gpio_irq(s);
1734 auart_port[pdev->id] = NULL;
1735
1736out_iounmap:
1737 iounmap(s->port.membase);
1738
1739out_disable_clks:
1740 if (is_asm9260_auart(s)) {
1741 clk_disable_unprepare(s->clk);
1742 clk_disable_unprepare(s->clk_ahb);
1743 }
1744 return ret;
1745}
1746
1747static int mxs_auart_remove(struct platform_device *pdev)
1748{
1749 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1750
1751 uart_remove_one_port(&auart_driver, &s->port);
1752 auart_port[pdev->id] = NULL;
1753 mxs_auart_free_gpio_irq(s);
1754 iounmap(s->port.membase);
1755 if (is_asm9260_auart(s)) {
1756 clk_disable_unprepare(s->clk);
1757 clk_disable_unprepare(s->clk_ahb);
1758 }
1759
1760 return 0;
1761}
1762
1763static struct platform_driver mxs_auart_driver = {
1764 .probe = mxs_auart_probe,
1765 .remove = mxs_auart_remove,
1766 .driver = {
1767 .name = "mxs-auart",
1768 .of_match_table = mxs_auart_dt_ids,
1769 },
1770};
1771
1772static int __init mxs_auart_init(void)
1773{
1774 int r;
1775
1776 r = uart_register_driver(&auart_driver);
1777 if (r)
1778 goto out;
1779
1780 r = platform_driver_register(&mxs_auart_driver);
1781 if (r)
1782 goto out_err;
1783
1784 return 0;
1785out_err:
1786 uart_unregister_driver(&auart_driver);
1787out:
1788 return r;
1789}
1790
1791static void __exit mxs_auart_exit(void)
1792{
1793 platform_driver_unregister(&mxs_auart_driver);
1794 uart_unregister_driver(&auart_driver);
1795}
1796
1797module_init(mxs_auart_init);
1798module_exit(mxs_auart_exit);
1799MODULE_LICENSE("GPL");
1800MODULE_DESCRIPTION("Freescale MXS application uart driver");
1801MODULE_ALIAS("platform:mxs-auart");
1802