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14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/spinlock.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/mutex.h>
21#include <linux/seq_file.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/of_platform.h>
26
27#include <linux/usb/ch9.h>
28#include <linux/usb/gadget.h>
29#include <linux/usb/phy.h>
30#include <linux/usb/composite.h>
31
32
33#include "core.h"
34#include "hw.h"
35
36
37static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
38{
39 return container_of(req, struct dwc2_hsotg_req, req);
40}
41
42static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
43{
44 return container_of(ep, struct dwc2_hsotg_ep, ep);
45}
46
47static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
48{
49 return container_of(gadget, struct dwc2_hsotg, gadget);
50}
51
52static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
53{
54 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
55}
56
57static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
58{
59 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
60}
61
62static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
63 u32 ep_index, u32 dir_in)
64{
65 if (dir_in)
66 return hsotg->eps_in[ep_index];
67 else
68 return hsotg->eps_out[ep_index];
69}
70
71
72static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
73
74
75
76
77
78
79
80
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91
92
93static inline bool using_dma(struct dwc2_hsotg *hsotg)
94{
95 return hsotg->params.g_dma;
96}
97
98
99
100
101
102
103
104static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
105{
106 return hsotg->params.g_dma_desc;
107}
108
109
110
111
112
113
114
115
116static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
117{
118 hs_ep->target_frame += hs_ep->interval;
119 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
120 hs_ep->frame_overrun = true;
121 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
122 } else {
123 hs_ep->frame_overrun = false;
124 }
125}
126
127
128
129
130
131
132
133
134
135
136
137static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
138{
139 if (hs_ep->target_frame)
140 hs_ep->target_frame -= 1;
141 else
142 hs_ep->target_frame = DSTS_SOFFN_LIMIT;
143}
144
145
146
147
148
149
150static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
151{
152 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
153 u32 new_gsintmsk;
154
155 new_gsintmsk = gsintmsk | ints;
156
157 if (new_gsintmsk != gsintmsk) {
158 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
159 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
160 }
161}
162
163
164
165
166
167
168static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
169{
170 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
171 u32 new_gsintmsk;
172
173 new_gsintmsk = gsintmsk & ~ints;
174
175 if (new_gsintmsk != gsintmsk)
176 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
177}
178
179
180
181
182
183
184
185
186
187
188
189static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
190 unsigned int ep, unsigned int dir_in,
191 unsigned int en)
192{
193 unsigned long flags;
194 u32 bit = 1 << ep;
195 u32 daint;
196
197 if (!dir_in)
198 bit <<= 16;
199
200 local_irq_save(flags);
201 daint = dwc2_readl(hsotg, DAINTMSK);
202 if (en)
203 daint |= bit;
204 else
205 daint &= ~bit;
206 dwc2_writel(hsotg, daint, DAINTMSK);
207 local_irq_restore(flags);
208}
209
210
211
212
213
214
215int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
216{
217 if (hsotg->hw_params.en_multiple_tx_fifo)
218
219 return hsotg->hw_params.num_dev_in_eps;
220 else
221
222 return hsotg->hw_params.num_dev_perio_in_ep;
223}
224
225
226
227
228
229
230
231int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
232{
233 int addr;
234 int tx_addr_max;
235 u32 np_tx_fifo_size;
236
237 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
238 hsotg->params.g_np_tx_fifo_size);
239
240
241 tx_addr_max = hsotg->hw_params.total_fifo_size;
242
243 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
244 if (tx_addr_max <= addr)
245 return 0;
246
247 return tx_addr_max - addr;
248}
249
250
251
252
253
254
255
256static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
257{
258 u32 gintsts2;
259 u32 gintmsk2;
260
261 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
262 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
263 gintsts2 &= gintmsk2;
264
265 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
266 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
267 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
268 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
269 }
270}
271
272
273
274
275
276
277
278int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
279{
280 int tx_fifo_count;
281 int tx_fifo_depth;
282
283 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
284
285 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
286
287 if (!tx_fifo_count)
288 return tx_fifo_depth;
289 else
290 return tx_fifo_depth / tx_fifo_count;
291}
292
293
294
295
296
297static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
298{
299 unsigned int ep;
300 unsigned int addr;
301 int timeout;
302
303 u32 val;
304 u32 *txfsz = hsotg->params.g_tx_fifo_size;
305
306
307 WARN_ON(hsotg->fifo_map);
308 hsotg->fifo_map = 0;
309
310
311 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
312 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
313 FIFOSIZE_STARTADDR_SHIFT) |
314 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
315 GNPTXFSIZ);
316
317
318
319
320
321
322
323
324
325 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
326
327
328
329
330
331
332 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
333 if (!txfsz[ep])
334 continue;
335 val = addr;
336 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
337 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
338 "insufficient fifo memory");
339 addr += txfsz[ep];
340
341 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
342 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
343 }
344
345 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
346 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
347 GDFIFOCFG);
348
349
350
351
352
353 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
354 GRSTCTL_RXFFLSH, GRSTCTL);
355
356
357 timeout = 100;
358 while (1) {
359 val = dwc2_readl(hsotg, GRSTCTL);
360
361 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
362 break;
363
364 if (--timeout == 0) {
365 dev_err(hsotg->dev,
366 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
367 __func__, val);
368 break;
369 }
370
371 udelay(1);
372 }
373
374 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
375}
376
377
378
379
380
381
382
383
384static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
385 gfp_t flags)
386{
387 struct dwc2_hsotg_req *req;
388
389 req = kzalloc(sizeof(*req), flags);
390 if (!req)
391 return NULL;
392
393 INIT_LIST_HEAD(&req->queue);
394
395 return &req->req;
396}
397
398
399
400
401
402
403
404
405static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
406{
407 return hs_ep->periodic;
408}
409
410
411
412
413
414
415
416
417
418
419static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
420 struct dwc2_hsotg_ep *hs_ep,
421 struct dwc2_hsotg_req *hs_req)
422{
423 struct usb_request *req = &hs_req->req;
424
425 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
426}
427
428
429
430
431
432
433
434
435
436static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
437{
438 hsotg->setup_desc[0] =
439 dmam_alloc_coherent(hsotg->dev,
440 sizeof(struct dwc2_dma_desc),
441 &hsotg->setup_desc_dma[0],
442 GFP_KERNEL);
443 if (!hsotg->setup_desc[0])
444 goto fail;
445
446 hsotg->setup_desc[1] =
447 dmam_alloc_coherent(hsotg->dev,
448 sizeof(struct dwc2_dma_desc),
449 &hsotg->setup_desc_dma[1],
450 GFP_KERNEL);
451 if (!hsotg->setup_desc[1])
452 goto fail;
453
454 hsotg->ctrl_in_desc =
455 dmam_alloc_coherent(hsotg->dev,
456 sizeof(struct dwc2_dma_desc),
457 &hsotg->ctrl_in_desc_dma,
458 GFP_KERNEL);
459 if (!hsotg->ctrl_in_desc)
460 goto fail;
461
462 hsotg->ctrl_out_desc =
463 dmam_alloc_coherent(hsotg->dev,
464 sizeof(struct dwc2_dma_desc),
465 &hsotg->ctrl_out_desc_dma,
466 GFP_KERNEL);
467 if (!hsotg->ctrl_out_desc)
468 goto fail;
469
470 return 0;
471
472fail:
473 return -ENOMEM;
474}
475
476
477
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484
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489
490
491
492static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
493 struct dwc2_hsotg_ep *hs_ep,
494 struct dwc2_hsotg_req *hs_req)
495{
496 bool periodic = is_ep_periodic(hs_ep);
497 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
498 int buf_pos = hs_req->req.actual;
499 int to_write = hs_ep->size_loaded;
500 void *data;
501 int can_write;
502 int pkt_round;
503 int max_transfer;
504
505 to_write -= (buf_pos - hs_ep->last_load);
506
507
508 if (to_write == 0)
509 return 0;
510
511 if (periodic && !hsotg->dedicated_fifos) {
512 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
513 int size_left;
514 int size_done;
515
516
517
518
519
520
521 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
522
523
524
525
526
527 if (hs_ep->fifo_load != 0) {
528 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
529 return -ENOSPC;
530 }
531
532 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
533 __func__, size_left,
534 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
535
536
537 size_done = hs_ep->size_loaded - size_left;
538
539
540 can_write = hs_ep->fifo_load - size_done;
541 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
542 __func__, can_write);
543
544 can_write = hs_ep->fifo_size - can_write;
545 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
546 __func__, can_write);
547
548 if (can_write <= 0) {
549 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
550 return -ENOSPC;
551 }
552 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
553 can_write = dwc2_readl(hsotg,
554 DTXFSTS(hs_ep->fifo_index));
555
556 can_write &= 0xffff;
557 can_write *= 4;
558 } else {
559 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
560 dev_dbg(hsotg->dev,
561 "%s: no queue slots available (0x%08x)\n",
562 __func__, gnptxsts);
563
564 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
565 return -ENOSPC;
566 }
567
568 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
569 can_write *= 4;
570 }
571
572 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
573
574 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
575 __func__, gnptxsts, can_write, to_write, max_transfer);
576
577
578
579
580
581
582 if (can_write > 512 && !periodic)
583 can_write = 512;
584
585
586
587
588
589
590 if (to_write > max_transfer) {
591 to_write = max_transfer;
592
593
594 if (!hsotg->dedicated_fifos)
595 dwc2_hsotg_en_gsint(hsotg,
596 periodic ? GINTSTS_PTXFEMP :
597 GINTSTS_NPTXFEMP);
598 }
599
600
601
602 if (to_write > can_write) {
603 to_write = can_write;
604 pkt_round = to_write % max_transfer;
605
606
607
608
609
610
611
612
613
614 if (pkt_round)
615 to_write -= pkt_round;
616
617
618
619
620
621
622
623 if (!hsotg->dedicated_fifos)
624 dwc2_hsotg_en_gsint(hsotg,
625 periodic ? GINTSTS_PTXFEMP :
626 GINTSTS_NPTXFEMP);
627 }
628
629 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
630 to_write, hs_req->req.length, can_write, buf_pos);
631
632 if (to_write <= 0)
633 return -ENOSPC;
634
635 hs_req->req.actual = buf_pos + to_write;
636 hs_ep->total_data += to_write;
637
638 if (periodic)
639 hs_ep->fifo_load += to_write;
640
641 to_write = DIV_ROUND_UP(to_write, 4);
642 data = hs_req->req.buf + buf_pos;
643
644 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
645
646 return (to_write >= can_write) ? -ENOSPC : 0;
647}
648
649
650
651
652
653
654
655
656static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
657{
658 int index = hs_ep->index;
659 unsigned int maxsize;
660 unsigned int maxpkt;
661
662 if (index != 0) {
663 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
664 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
665 } else {
666 maxsize = 64 + 64;
667 if (hs_ep->dir_in)
668 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
669 else
670 maxpkt = 2;
671 }
672
673
674 maxpkt--;
675 maxsize--;
676
677
678
679
680
681
682 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
683 maxsize = maxpkt * hs_ep->ep.maxpacket;
684
685 return maxsize;
686}
687
688
689
690
691
692
693
694static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
695{
696 u32 dsts;
697
698 dsts = dwc2_readl(hsotg, DSTS);
699 dsts &= DSTS_SOFFN_MASK;
700 dsts >>= DSTS_SOFFN_SHIFT;
701
702 return dsts;
703}
704
705
706
707
708
709
710
711
712
713
714static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
715{
716 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
717 int is_isoc = hs_ep->isochronous;
718 unsigned int maxsize;
719 u32 mps = hs_ep->ep.maxpacket;
720 int dir_in = hs_ep->dir_in;
721
722 if (is_isoc)
723 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
724 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
725 MAX_DMA_DESC_NUM_HS_ISOC;
726 else
727 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
728
729
730 if (hs_ep->index)
731 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
732 maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
733
734 return maxsize;
735}
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
755{
756 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
757 u32 mps = hs_ep->ep.maxpacket;
758 int dir_in = hs_ep->dir_in;
759 u32 desc_size = 0;
760
761 if (!hs_ep->index && !dir_in) {
762 desc_size = mps;
763 *mask = DEV_DMA_NBYTES_MASK;
764 } else if (hs_ep->isochronous) {
765 if (dir_in) {
766 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
767 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
768 } else {
769 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
770 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
771 }
772 } else {
773 desc_size = DEV_DMA_NBYTES_LIMIT;
774 *mask = DEV_DMA_NBYTES_MASK;
775
776
777 desc_size -= desc_size % mps;
778 }
779
780
781 if (hs_ep->index)
782 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
783 desc_size = mps;
784 *mask = DEV_DMA_NBYTES_MASK;
785 }
786
787 return desc_size;
788}
789
790static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
791 struct dwc2_dma_desc **desc,
792 dma_addr_t dma_buff,
793 unsigned int len,
794 bool true_last)
795{
796 int dir_in = hs_ep->dir_in;
797 u32 mps = hs_ep->ep.maxpacket;
798 u32 maxsize = 0;
799 u32 offset = 0;
800 u32 mask = 0;
801 int i;
802
803 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
804
805 hs_ep->desc_count = (len / maxsize) +
806 ((len % maxsize) ? 1 : 0);
807 if (len == 0)
808 hs_ep->desc_count = 1;
809
810 for (i = 0; i < hs_ep->desc_count; ++i) {
811 (*desc)->status = 0;
812 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
813 << DEV_DMA_BUFF_STS_SHIFT);
814
815 if (len > maxsize) {
816 if (!hs_ep->index && !dir_in)
817 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
818
819 (*desc)->status |=
820 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
821 (*desc)->buf = dma_buff + offset;
822
823 len -= maxsize;
824 offset += maxsize;
825 } else {
826 if (true_last)
827 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
828
829 if (dir_in)
830 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
831 ((hs_ep->send_zlp && true_last) ?
832 DEV_DMA_SHORT : 0);
833
834 (*desc)->status |=
835 len << DEV_DMA_NBYTES_SHIFT & mask;
836 (*desc)->buf = dma_buff + offset;
837 }
838
839 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
840 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
841 << DEV_DMA_BUFF_STS_SHIFT);
842 (*desc)++;
843 }
844}
845
846
847
848
849
850
851
852
853
854
855
856static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
857 dma_addr_t dma_buff,
858 unsigned int len)
859{
860 struct usb_request *ureq = NULL;
861 struct dwc2_dma_desc *desc = hs_ep->desc_list;
862 struct scatterlist *sg;
863 int i;
864 u8 desc_count = 0;
865
866 if (hs_ep->req)
867 ureq = &hs_ep->req->req;
868
869
870 if (!ureq || !ureq->num_sgs) {
871 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
872 dma_buff, len, true);
873 return;
874 }
875
876
877 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
878 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
879 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
880 sg_is_last(sg));
881 desc_count += hs_ep->desc_count;
882 }
883
884 hs_ep->desc_count = desc_count;
885}
886
887
888
889
890
891
892
893
894
895
896
897
898static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
899 dma_addr_t dma_buff, unsigned int len)
900{
901 struct dwc2_dma_desc *desc;
902 struct dwc2_hsotg *hsotg = hs_ep->parent;
903 u32 index;
904 u32 mask = 0;
905 u8 pid = 0;
906
907 dwc2_gadget_get_desc_params(hs_ep, &mask);
908
909 index = hs_ep->next_desc;
910 desc = &hs_ep->desc_list[index];
911
912
913 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
914 DEV_DMA_BUFF_STS_HREADY) {
915 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
916 return 1;
917 }
918
919
920 if (hs_ep->next_desc)
921 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
922
923 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
924 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
925
926 desc->status = 0;
927 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
928
929 desc->buf = dma_buff;
930 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
931 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
932
933 if (hs_ep->dir_in) {
934 if (len)
935 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
936 else
937 pid = 1;
938 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
939 DEV_DMA_ISOC_PID_MASK) |
940 ((len % hs_ep->ep.maxpacket) ?
941 DEV_DMA_SHORT : 0) |
942 ((hs_ep->target_frame <<
943 DEV_DMA_ISOC_FRNUM_SHIFT) &
944 DEV_DMA_ISOC_FRNUM_MASK);
945 }
946
947 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
948 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
949
950
951 if (hs_ep->dir_in)
952 dwc2_gadget_incr_frame_num(hs_ep);
953
954
955 hs_ep->next_desc++;
956 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
957 hs_ep->next_desc = 0;
958
959 return 0;
960}
961
962
963
964
965
966
967
968
969static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
970{
971 struct dwc2_hsotg *hsotg = hs_ep->parent;
972 struct dwc2_hsotg_req *hs_req, *treq;
973 int index = hs_ep->index;
974 int ret;
975 int i;
976 u32 dma_reg;
977 u32 depctl;
978 u32 ctrl;
979 struct dwc2_dma_desc *desc;
980
981 if (list_empty(&hs_ep->queue)) {
982 hs_ep->target_frame = TARGET_FRAME_INITIAL;
983 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
984 return;
985 }
986
987
988 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
989 desc = &hs_ep->desc_list[i];
990 desc->status = 0;
991 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
992 << DEV_DMA_BUFF_STS_SHIFT);
993 }
994
995 hs_ep->next_desc = 0;
996 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
997 dma_addr_t dma_addr = hs_req->req.dma;
998
999 if (hs_req->req.num_sgs) {
1000 WARN_ON(hs_req->req.num_sgs > 1);
1001 dma_addr = sg_dma_address(hs_req->req.sg);
1002 }
1003 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1004 hs_req->req.length);
1005 if (ret)
1006 break;
1007 }
1008
1009 hs_ep->compl_desc = 0;
1010 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1011 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
1012
1013
1014 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1015
1016 ctrl = dwc2_readl(hsotg, depctl);
1017 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1018 dwc2_writel(hsotg, ctrl, depctl);
1019}
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1032 struct dwc2_hsotg_ep *hs_ep,
1033 struct dwc2_hsotg_req *hs_req,
1034 bool continuing)
1035{
1036 struct usb_request *ureq = &hs_req->req;
1037 int index = hs_ep->index;
1038 int dir_in = hs_ep->dir_in;
1039 u32 epctrl_reg;
1040 u32 epsize_reg;
1041 u32 epsize;
1042 u32 ctrl;
1043 unsigned int length;
1044 unsigned int packets;
1045 unsigned int maxreq;
1046 unsigned int dma_reg;
1047
1048 if (index != 0) {
1049 if (hs_ep->req && !continuing) {
1050 dev_err(hsotg->dev, "%s: active request\n", __func__);
1051 WARN_ON(1);
1052 return;
1053 } else if (hs_ep->req != hs_req && continuing) {
1054 dev_err(hsotg->dev,
1055 "%s: continue different req\n", __func__);
1056 WARN_ON(1);
1057 return;
1058 }
1059 }
1060
1061 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1062 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1063 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1064
1065 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1066 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1067 hs_ep->dir_in ? "in" : "out");
1068
1069
1070 ctrl = dwc2_readl(hsotg, epctrl_reg);
1071
1072 if (index && ctrl & DXEPCTL_STALL) {
1073 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1074 return;
1075 }
1076
1077 length = ureq->length - ureq->actual;
1078 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1079 ureq->length, ureq->actual);
1080
1081 if (!using_desc_dma(hsotg))
1082 maxreq = get_ep_limit(hs_ep);
1083 else
1084 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1085
1086 if (length > maxreq) {
1087 int round = maxreq % hs_ep->ep.maxpacket;
1088
1089 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1090 __func__, length, maxreq, round);
1091
1092
1093 if (round)
1094 maxreq -= round;
1095
1096 length = maxreq;
1097 }
1098
1099 if (length)
1100 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1101 else
1102 packets = 1;
1103
1104 if (dir_in && index != 0)
1105 if (hs_ep->isochronous)
1106 epsize = DXEPTSIZ_MC(packets);
1107 else
1108 epsize = DXEPTSIZ_MC(1);
1109 else
1110 epsize = 0;
1111
1112
1113
1114
1115
1116 if (dir_in && ureq->zero && !continuing) {
1117
1118 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1119 !(ureq->length % hs_ep->ep.maxpacket))
1120 hs_ep->send_zlp = 1;
1121 }
1122
1123 epsize |= DXEPTSIZ_PKTCNT(packets);
1124 epsize |= DXEPTSIZ_XFERSIZE(length);
1125
1126 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1127 __func__, packets, length, ureq->length, epsize, epsize_reg);
1128
1129
1130 hs_ep->req = hs_req;
1131
1132 if (using_desc_dma(hsotg)) {
1133 u32 offset = 0;
1134 u32 mps = hs_ep->ep.maxpacket;
1135
1136
1137 if (!dir_in) {
1138 if (!index)
1139 length = mps;
1140 else if (length % mps)
1141 length += (mps - (length % mps));
1142 }
1143
1144 if (continuing)
1145 offset = ureq->actual;
1146
1147
1148 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1149 length);
1150
1151
1152 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1153
1154 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1155 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1156 } else {
1157
1158 dwc2_writel(hsotg, epsize, epsize_reg);
1159
1160 if (using_dma(hsotg) && !continuing && (length != 0)) {
1161
1162
1163
1164
1165
1166 dwc2_writel(hsotg, ureq->dma, dma_reg);
1167
1168 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1169 __func__, &ureq->dma, dma_reg);
1170 }
1171 }
1172
1173 if (hs_ep->isochronous && hs_ep->interval == 1) {
1174 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
1175 dwc2_gadget_incr_frame_num(hs_ep);
1176
1177 if (hs_ep->target_frame & 0x1)
1178 ctrl |= DXEPCTL_SETODDFR;
1179 else
1180 ctrl |= DXEPCTL_SETEVENFR;
1181 }
1182
1183 ctrl |= DXEPCTL_EPENA;
1184
1185 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1186
1187
1188 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1189 ctrl |= DXEPCTL_CNAK;
1190
1191 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1192 dwc2_writel(hsotg, ctrl, epctrl_reg);
1193
1194
1195
1196
1197
1198
1199 hs_ep->size_loaded = length;
1200 hs_ep->last_load = ureq->actual;
1201
1202 if (dir_in && !using_dma(hsotg)) {
1203
1204 hs_ep->fifo_load = 0;
1205
1206 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1207 }
1208
1209
1210
1211
1212
1213
1214
1215 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1216 dev_dbg(hsotg->dev,
1217 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1218 index, dwc2_readl(hsotg, epctrl_reg));
1219
1220 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1221 __func__, dwc2_readl(hsotg, epctrl_reg));
1222
1223
1224 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1225}
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1240 struct dwc2_hsotg_ep *hs_ep,
1241 struct usb_request *req)
1242{
1243 int ret;
1244
1245 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1246 if (ret)
1247 goto dma_error;
1248
1249 return 0;
1250
1251dma_error:
1252 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1253 __func__, req->buf, req->length);
1254
1255 return -EIO;
1256}
1257
1258static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1259 struct dwc2_hsotg_ep *hs_ep,
1260 struct dwc2_hsotg_req *hs_req)
1261{
1262 void *req_buf = hs_req->req.buf;
1263
1264
1265 if (!using_dma(hsotg) || !((long)req_buf & 3))
1266 return 0;
1267
1268 WARN_ON(hs_req->saved_req_buf);
1269
1270 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1271 hs_ep->ep.name, req_buf, hs_req->req.length);
1272
1273 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1274 if (!hs_req->req.buf) {
1275 hs_req->req.buf = req_buf;
1276 dev_err(hsotg->dev,
1277 "%s: unable to allocate memory for bounce buffer\n",
1278 __func__);
1279 return -ENOMEM;
1280 }
1281
1282
1283 hs_req->saved_req_buf = req_buf;
1284
1285 if (hs_ep->dir_in)
1286 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1287 return 0;
1288}
1289
1290static void
1291dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1292 struct dwc2_hsotg_ep *hs_ep,
1293 struct dwc2_hsotg_req *hs_req)
1294{
1295
1296 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1297 return;
1298
1299 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1300 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1301
1302
1303 if (!hs_ep->dir_in && !hs_req->req.status)
1304 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1305 hs_req->req.actual);
1306
1307
1308 kfree(hs_req->req.buf);
1309
1310 hs_req->req.buf = hs_req->saved_req_buf;
1311 hs_req->saved_req_buf = NULL;
1312}
1313
1314
1315
1316
1317
1318
1319
1320
1321static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1322{
1323 struct dwc2_hsotg *hsotg = hs_ep->parent;
1324 u32 target_frame = hs_ep->target_frame;
1325 u32 current_frame = hsotg->frame_number;
1326 bool frame_overrun = hs_ep->frame_overrun;
1327
1328 if (!frame_overrun && current_frame >= target_frame)
1329 return true;
1330
1331 if (frame_overrun && current_frame >= target_frame &&
1332 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
1333 return true;
1334
1335 return false;
1336}
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1347 struct dwc2_hsotg_ep *hs_ep)
1348{
1349 switch (hsotg->ep0_state) {
1350 case DWC2_EP0_SETUP:
1351 case DWC2_EP0_STATUS_OUT:
1352 hs_ep->desc_list = hsotg->setup_desc[0];
1353 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1354 break;
1355 case DWC2_EP0_DATA_IN:
1356 case DWC2_EP0_STATUS_IN:
1357 hs_ep->desc_list = hsotg->ctrl_in_desc;
1358 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1359 break;
1360 case DWC2_EP0_DATA_OUT:
1361 hs_ep->desc_list = hsotg->ctrl_out_desc;
1362 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1363 break;
1364 default:
1365 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1366 hsotg->ep0_state);
1367 return -EINVAL;
1368 }
1369
1370 return 0;
1371}
1372
1373static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1374 gfp_t gfp_flags)
1375{
1376 struct dwc2_hsotg_req *hs_req = our_req(req);
1377 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1378 struct dwc2_hsotg *hs = hs_ep->parent;
1379 bool first;
1380 int ret;
1381 u32 maxsize = 0;
1382 u32 mask = 0;
1383
1384
1385 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1386 ep->name, req, req->length, req->buf, req->no_interrupt,
1387 req->zero, req->short_not_ok);
1388
1389
1390 if (hs->lx_state != DWC2_L0) {
1391 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1392 __func__);
1393 return -EAGAIN;
1394 }
1395
1396
1397 INIT_LIST_HEAD(&hs_req->queue);
1398 req->actual = 0;
1399 req->status = -EINPROGRESS;
1400
1401
1402 if (hs_ep->isochronous &&
1403 req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1404 dev_err(hs->dev, "req length > maxpacket*mc\n");
1405 return -EINVAL;
1406 }
1407
1408
1409
1410
1411 if (using_desc_dma(hs) && hs_ep->isochronous) {
1412 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1413 if (hs_ep->dir_in && req->length > maxsize) {
1414 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1415 req->length, maxsize);
1416 return -EINVAL;
1417 }
1418
1419 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1420 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1421 req->length, hs_ep->ep.maxpacket);
1422 return -EINVAL;
1423 }
1424 }
1425
1426 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1427 if (ret)
1428 return ret;
1429
1430
1431 if (using_dma(hs)) {
1432 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1433 if (ret)
1434 return ret;
1435 }
1436
1437 if (using_desc_dma(hs) && !hs_ep->index) {
1438 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1439 if (ret)
1440 return ret;
1441 }
1442
1443 first = list_empty(&hs_ep->queue);
1444 list_add_tail(&hs_req->queue, &hs_ep->queue);
1445
1446
1447
1448
1449
1450
1451
1452 if (using_desc_dma(hs) && hs_ep->isochronous) {
1453 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1454 dma_addr_t dma_addr = hs_req->req.dma;
1455
1456 if (hs_req->req.num_sgs) {
1457 WARN_ON(hs_req->req.num_sgs > 1);
1458 dma_addr = sg_dma_address(hs_req->req.sg);
1459 }
1460 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1461 hs_req->req.length);
1462 }
1463 return 0;
1464 }
1465
1466
1467 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1468 hs->ep0_state == DWC2_EP0_DATA_OUT)
1469 hs_ep->dir_in = 1;
1470
1471 if (first) {
1472 if (!hs_ep->isochronous) {
1473 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1474 return 0;
1475 }
1476
1477
1478 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1479 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1480 dwc2_gadget_incr_frame_num(hs_ep);
1481
1482
1483
1484 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1485 }
1486
1487 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1488 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1489 }
1490 return 0;
1491}
1492
1493static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1494 gfp_t gfp_flags)
1495{
1496 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1497 struct dwc2_hsotg *hs = hs_ep->parent;
1498 unsigned long flags = 0;
1499 int ret = 0;
1500
1501 spin_lock_irqsave(&hs->lock, flags);
1502 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1503 spin_unlock_irqrestore(&hs->lock, flags);
1504
1505 return ret;
1506}
1507
1508static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1509 struct usb_request *req)
1510{
1511 struct dwc2_hsotg_req *hs_req = our_req(req);
1512
1513 kfree(hs_req);
1514}
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1525 struct usb_request *req)
1526{
1527 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1528 struct dwc2_hsotg *hsotg = hs_ep->parent;
1529
1530 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1531
1532 dwc2_hsotg_ep_free_request(ep, req);
1533}
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1544 u32 windex)
1545{
1546 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1547 int idx = windex & 0x7F;
1548
1549 if (windex >= 0x100)
1550 return NULL;
1551
1552 if (idx > hsotg->num_of_eps)
1553 return NULL;
1554
1555 return index_to_ep(hsotg, idx, dir);
1556}
1557
1558
1559
1560
1561
1562
1563
1564int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1565{
1566 int dctl = dwc2_readl(hsotg, DCTL);
1567
1568 dctl &= ~DCTL_TSTCTL_MASK;
1569 switch (testmode) {
1570 case USB_TEST_J:
1571 case USB_TEST_K:
1572 case USB_TEST_SE0_NAK:
1573 case USB_TEST_PACKET:
1574 case USB_TEST_FORCE_ENABLE:
1575 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1576 break;
1577 default:
1578 return -EINVAL;
1579 }
1580 dwc2_writel(hsotg, dctl, DCTL);
1581 return 0;
1582}
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1595 struct dwc2_hsotg_ep *ep,
1596 void *buff,
1597 int length)
1598{
1599 struct usb_request *req;
1600 int ret;
1601
1602 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1603
1604 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1605 hsotg->ep0_reply = req;
1606 if (!req) {
1607 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1608 return -ENOMEM;
1609 }
1610
1611 req->buf = hsotg->ep0_buff;
1612 req->length = length;
1613
1614
1615
1616
1617 req->zero = 0;
1618 req->complete = dwc2_hsotg_complete_oursetup;
1619
1620 if (length)
1621 memcpy(req->buf, buff, length);
1622
1623 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1624 if (ret) {
1625 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1626 return ret;
1627 }
1628
1629 return 0;
1630}
1631
1632
1633
1634
1635
1636
1637static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1638 struct usb_ctrlrequest *ctrl)
1639{
1640 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1641 struct dwc2_hsotg_ep *ep;
1642 __le16 reply;
1643 u16 status;
1644 int ret;
1645
1646 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1647
1648 if (!ep0->dir_in) {
1649 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1650 return -EINVAL;
1651 }
1652
1653 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1654 case USB_RECIP_DEVICE:
1655 status = hsotg->gadget.is_selfpowered <<
1656 USB_DEVICE_SELF_POWERED;
1657 status |= hsotg->remote_wakeup_allowed <<
1658 USB_DEVICE_REMOTE_WAKEUP;
1659 reply = cpu_to_le16(status);
1660 break;
1661
1662 case USB_RECIP_INTERFACE:
1663
1664 reply = cpu_to_le16(0);
1665 break;
1666
1667 case USB_RECIP_ENDPOINT:
1668 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1669 if (!ep)
1670 return -ENOENT;
1671
1672 reply = cpu_to_le16(ep->halted ? 1 : 0);
1673 break;
1674
1675 default:
1676 return 0;
1677 }
1678
1679 if (le16_to_cpu(ctrl->wLength) != 2)
1680 return -EINVAL;
1681
1682 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1683 if (ret) {
1684 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1685 return ret;
1686 }
1687
1688 return 1;
1689}
1690
1691static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1692
1693
1694
1695
1696
1697
1698
1699static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1700{
1701 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1702 queue);
1703}
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1714{
1715 u32 mask;
1716 struct dwc2_hsotg *hsotg = hs_ep->parent;
1717 int dir_in = hs_ep->dir_in;
1718 struct dwc2_hsotg_req *hs_req;
1719 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1720
1721 if (!list_empty(&hs_ep->queue)) {
1722 hs_req = get_ep_head(hs_ep);
1723 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1724 return;
1725 }
1726 if (!hs_ep->isochronous)
1727 return;
1728
1729 if (dir_in) {
1730 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1731 __func__);
1732 } else {
1733 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1734 __func__);
1735 mask = dwc2_readl(hsotg, epmsk_reg);
1736 mask |= DOEPMSK_OUTTKNEPDISMSK;
1737 dwc2_writel(hsotg, mask, epmsk_reg);
1738 }
1739}
1740
1741
1742
1743
1744
1745
1746static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1747 struct usb_ctrlrequest *ctrl)
1748{
1749 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1750 struct dwc2_hsotg_req *hs_req;
1751 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1752 struct dwc2_hsotg_ep *ep;
1753 int ret;
1754 bool halted;
1755 u32 recip;
1756 u32 wValue;
1757 u32 wIndex;
1758
1759 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1760 __func__, set ? "SET" : "CLEAR");
1761
1762 wValue = le16_to_cpu(ctrl->wValue);
1763 wIndex = le16_to_cpu(ctrl->wIndex);
1764 recip = ctrl->bRequestType & USB_RECIP_MASK;
1765
1766 switch (recip) {
1767 case USB_RECIP_DEVICE:
1768 switch (wValue) {
1769 case USB_DEVICE_REMOTE_WAKEUP:
1770 if (set)
1771 hsotg->remote_wakeup_allowed = 1;
1772 else
1773 hsotg->remote_wakeup_allowed = 0;
1774 break;
1775
1776 case USB_DEVICE_TEST_MODE:
1777 if ((wIndex & 0xff) != 0)
1778 return -EINVAL;
1779 if (!set)
1780 return -EINVAL;
1781
1782 hsotg->test_mode = wIndex >> 8;
1783 break;
1784 default:
1785 return -ENOENT;
1786 }
1787
1788 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1789 if (ret) {
1790 dev_err(hsotg->dev,
1791 "%s: failed to send reply\n", __func__);
1792 return ret;
1793 }
1794 break;
1795
1796 case USB_RECIP_ENDPOINT:
1797 ep = ep_from_windex(hsotg, wIndex);
1798 if (!ep) {
1799 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1800 __func__, wIndex);
1801 return -ENOENT;
1802 }
1803
1804 switch (wValue) {
1805 case USB_ENDPOINT_HALT:
1806 halted = ep->halted;
1807
1808 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1809
1810 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1811 if (ret) {
1812 dev_err(hsotg->dev,
1813 "%s: failed to send reply\n", __func__);
1814 return ret;
1815 }
1816
1817
1818
1819
1820
1821
1822 if (!set && halted) {
1823
1824
1825
1826
1827 if (ep->req) {
1828 hs_req = ep->req;
1829 ep->req = NULL;
1830 list_del_init(&hs_req->queue);
1831 if (hs_req->req.complete) {
1832 spin_unlock(&hsotg->lock);
1833 usb_gadget_giveback_request(
1834 &ep->ep, &hs_req->req);
1835 spin_lock(&hsotg->lock);
1836 }
1837 }
1838
1839
1840 if (!ep->req)
1841 dwc2_gadget_start_next_request(ep);
1842 }
1843
1844 break;
1845
1846 default:
1847 return -ENOENT;
1848 }
1849 break;
1850 default:
1851 return -ENOENT;
1852 }
1853 return 1;
1854}
1855
1856static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1857
1858
1859
1860
1861
1862
1863
1864static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1865{
1866 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1867 u32 reg;
1868 u32 ctrl;
1869
1870 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1871 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1872
1873
1874
1875
1876
1877
1878 ctrl = dwc2_readl(hsotg, reg);
1879 ctrl |= DXEPCTL_STALL;
1880 ctrl |= DXEPCTL_CNAK;
1881 dwc2_writel(hsotg, ctrl, reg);
1882
1883 dev_dbg(hsotg->dev,
1884 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1885 ctrl, reg, dwc2_readl(hsotg, reg));
1886
1887
1888
1889
1890
1891 dwc2_hsotg_enqueue_setup(hsotg);
1892}
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1904 struct usb_ctrlrequest *ctrl)
1905{
1906 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1907 int ret = 0;
1908 u32 dcfg;
1909
1910 dev_dbg(hsotg->dev,
1911 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1912 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1913 ctrl->wIndex, ctrl->wLength);
1914
1915 if (ctrl->wLength == 0) {
1916 ep0->dir_in = 1;
1917 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1918 } else if (ctrl->bRequestType & USB_DIR_IN) {
1919 ep0->dir_in = 1;
1920 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1921 } else {
1922 ep0->dir_in = 0;
1923 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1924 }
1925
1926 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1927 switch (ctrl->bRequest) {
1928 case USB_REQ_SET_ADDRESS:
1929 hsotg->connected = 1;
1930 dcfg = dwc2_readl(hsotg, DCFG);
1931 dcfg &= ~DCFG_DEVADDR_MASK;
1932 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1933 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1934 dwc2_writel(hsotg, dcfg, DCFG);
1935
1936 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1937
1938 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1939 return;
1940
1941 case USB_REQ_GET_STATUS:
1942 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1943 break;
1944
1945 case USB_REQ_CLEAR_FEATURE:
1946 case USB_REQ_SET_FEATURE:
1947 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1948 break;
1949 }
1950 }
1951
1952
1953
1954 if (ret == 0 && hsotg->driver) {
1955 spin_unlock(&hsotg->lock);
1956 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1957 spin_lock(&hsotg->lock);
1958 if (ret < 0)
1959 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1960 }
1961
1962 hsotg->delayed_status = false;
1963 if (ret == USB_GADGET_DELAYED_STATUS)
1964 hsotg->delayed_status = true;
1965
1966
1967
1968
1969
1970
1971 if (ret < 0)
1972 dwc2_hsotg_stall_ep0(hsotg);
1973}
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1984 struct usb_request *req)
1985{
1986 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1987 struct dwc2_hsotg *hsotg = hs_ep->parent;
1988
1989 if (req->status < 0) {
1990 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1991 return;
1992 }
1993
1994 spin_lock(&hsotg->lock);
1995 if (req->actual == 0)
1996 dwc2_hsotg_enqueue_setup(hsotg);
1997 else
1998 dwc2_hsotg_process_control(hsotg, req->buf);
1999 spin_unlock(&hsotg->lock);
2000}
2001
2002
2003
2004
2005
2006
2007
2008
2009static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2010{
2011 struct usb_request *req = hsotg->ctrl_req;
2012 struct dwc2_hsotg_req *hs_req = our_req(req);
2013 int ret;
2014
2015 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2016
2017 req->zero = 0;
2018 req->length = 8;
2019 req->buf = hsotg->ctrl_buff;
2020 req->complete = dwc2_hsotg_complete_setup;
2021
2022 if (!list_empty(&hs_req->queue)) {
2023 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2024 return;
2025 }
2026
2027 hsotg->eps_out[0]->dir_in = 0;
2028 hsotg->eps_out[0]->send_zlp = 0;
2029 hsotg->ep0_state = DWC2_EP0_SETUP;
2030
2031 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2032 if (ret < 0) {
2033 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2034
2035
2036
2037
2038 }
2039}
2040
2041static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2042 struct dwc2_hsotg_ep *hs_ep)
2043{
2044 u32 ctrl;
2045 u8 index = hs_ep->index;
2046 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2047 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2048
2049 if (hs_ep->dir_in)
2050 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2051 index);
2052 else
2053 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2054 index);
2055 if (using_desc_dma(hsotg)) {
2056
2057 dma_addr_t dma = hs_ep->desc_list_dma;
2058
2059 if (!index)
2060 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2061
2062 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2063 } else {
2064 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2065 DXEPTSIZ_XFERSIZE(0),
2066 epsiz_reg);
2067 }
2068
2069 ctrl = dwc2_readl(hsotg, epctl_reg);
2070 ctrl |= DXEPCTL_CNAK;
2071 ctrl |= DXEPCTL_EPENA;
2072 ctrl |= DXEPCTL_USBACTEP;
2073 dwc2_writel(hsotg, ctrl, epctl_reg);
2074}
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2090 struct dwc2_hsotg_ep *hs_ep,
2091 struct dwc2_hsotg_req *hs_req,
2092 int result)
2093{
2094 if (!hs_req) {
2095 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2096 return;
2097 }
2098
2099 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2100 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2101
2102
2103
2104
2105
2106
2107 if (hs_req->req.status == -EINPROGRESS)
2108 hs_req->req.status = result;
2109
2110 if (using_dma(hsotg))
2111 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2112
2113 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2114
2115 hs_ep->req = NULL;
2116 list_del_init(&hs_req->queue);
2117
2118
2119
2120
2121
2122
2123 if (hs_req->req.complete) {
2124 spin_unlock(&hsotg->lock);
2125 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2126 spin_lock(&hsotg->lock);
2127 }
2128
2129
2130 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2131 return;
2132
2133
2134
2135
2136
2137
2138
2139 if (!hs_ep->req && result >= 0)
2140 dwc2_gadget_start_next_request(hs_ep);
2141}
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2153{
2154 struct dwc2_hsotg *hsotg = hs_ep->parent;
2155 struct dwc2_hsotg_req *hs_req;
2156 struct usb_request *ureq;
2157 u32 desc_sts;
2158 u32 mask;
2159
2160 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2161
2162
2163 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2164 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2165
2166 hs_req = get_ep_head(hs_ep);
2167 if (!hs_req) {
2168 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2169 return;
2170 }
2171 ureq = &hs_req->req;
2172
2173
2174 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2175 DEV_DMA_STS_SUCC) {
2176 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2177 DEV_DMA_ISOC_RX_NBYTES_MASK;
2178 ureq->actual = ureq->length - ((desc_sts & mask) >>
2179 DEV_DMA_ISOC_NBYTES_SHIFT);
2180
2181
2182
2183
2184 if (!hs_ep->dir_in && ureq->length & 0x3)
2185 ureq->actual += 4 - (ureq->length & 0x3);
2186
2187
2188 ureq->frame_number =
2189 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2190 DEV_DMA_ISOC_FRNUM_SHIFT;
2191 }
2192
2193 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2194
2195 hs_ep->compl_desc++;
2196 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2197 hs_ep->compl_desc = 0;
2198 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2199 }
2200}
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2212{
2213 struct dwc2_hsotg *hsotg = hs_ep->parent;
2214
2215 if (!hs_ep->dir_in)
2216 dwc2_flush_rx_fifo(hsotg);
2217 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2218
2219 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2220 hs_ep->next_desc = 0;
2221 hs_ep->compl_desc = 0;
2222}
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2235{
2236 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2237 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2238 int to_read;
2239 int max_req;
2240 int read_ptr;
2241
2242 if (!hs_req) {
2243 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2244 int ptr;
2245
2246 dev_dbg(hsotg->dev,
2247 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2248 __func__, size, ep_idx, epctl);
2249
2250
2251 for (ptr = 0; ptr < size; ptr += 4)
2252 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2253
2254 return;
2255 }
2256
2257 to_read = size;
2258 read_ptr = hs_req->req.actual;
2259 max_req = hs_req->req.length - read_ptr;
2260
2261 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2262 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2263
2264 if (to_read > max_req) {
2265
2266
2267
2268
2269
2270
2271 WARN_ON_ONCE(1);
2272 }
2273
2274 hs_ep->total_data += to_read;
2275 hs_req->req.actual += to_read;
2276 to_read = DIV_ROUND_UP(to_read, 4);
2277
2278
2279
2280
2281
2282 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2283 hs_req->req.buf + read_ptr, to_read);
2284}
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2299{
2300
2301 hsotg->eps_out[0]->dir_in = dir_in;
2302 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2303
2304 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2305}
2306
2307static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2308 u32 epctl_reg)
2309{
2310 u32 ctrl;
2311
2312 ctrl = dwc2_readl(hsotg, epctl_reg);
2313 if (ctrl & DXEPCTL_EOFRNUM)
2314 ctrl |= DXEPCTL_SETEVENFR;
2315 else
2316 ctrl |= DXEPCTL_SETODDFR;
2317 dwc2_writel(hsotg, ctrl, epctl_reg);
2318}
2319
2320
2321
2322
2323
2324
2325
2326
2327static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2328{
2329 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
2330 struct dwc2_hsotg *hsotg = hs_ep->parent;
2331 unsigned int bytes_rem = 0;
2332 unsigned int bytes_rem_correction = 0;
2333 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2334 int i;
2335 u32 status;
2336 u32 mps = hs_ep->ep.maxpacket;
2337 int dir_in = hs_ep->dir_in;
2338
2339 if (!desc)
2340 return -EINVAL;
2341
2342
2343 if (hs_ep->index)
2344 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
2345 bytes_rem_correction = 4 - (mps % 4);
2346
2347 for (i = 0; i < hs_ep->desc_count; ++i) {
2348 status = desc->status;
2349 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2350 bytes_rem -= bytes_rem_correction;
2351
2352 if (status & DEV_DMA_STS_MASK)
2353 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2354 i, status & DEV_DMA_STS_MASK);
2355
2356 if (status & DEV_DMA_L)
2357 break;
2358
2359 desc++;
2360 }
2361
2362 return bytes_rem;
2363}
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2375{
2376 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2377 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2378 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2379 struct usb_request *req = &hs_req->req;
2380 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2381 int result = 0;
2382
2383 if (!hs_req) {
2384 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2385 return;
2386 }
2387
2388 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2389 dev_dbg(hsotg->dev, "zlp packet received\n");
2390 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2391 dwc2_hsotg_enqueue_setup(hsotg);
2392 return;
2393 }
2394
2395 if (using_desc_dma(hsotg))
2396 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2397
2398 if (using_dma(hsotg)) {
2399 unsigned int size_done;
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410 size_done = hs_ep->size_loaded - size_left;
2411 size_done += hs_ep->last_load;
2412
2413 req->actual = size_done;
2414 }
2415
2416
2417 if (req->actual < req->length && size_left == 0) {
2418 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2419 return;
2420 }
2421
2422 if (req->actual < req->length && req->short_not_ok) {
2423 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2424 __func__, req->actual, req->length);
2425
2426
2427
2428
2429
2430 }
2431
2432
2433 if (!using_desc_dma(hsotg) && epnum == 0 &&
2434 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2435
2436 if (!hsotg->delayed_status)
2437 dwc2_hsotg_ep0_zlp(hsotg, true);
2438 }
2439
2440
2441
2442
2443
2444 if (!using_dma(hsotg)) {
2445 if (hs_ep->isochronous && hs_ep->interval == 1)
2446 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
2447 else if (hs_ep->isochronous && hs_ep->interval > 1)
2448 dwc2_gadget_incr_frame_num(hs_ep);
2449 }
2450
2451
2452 if (!using_desc_dma(hsotg) && hs_ep->isochronous)
2453 req->frame_number = hsotg->frame_number;
2454
2455 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2456}
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2475{
2476 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2477 u32 epnum, status, size;
2478
2479 WARN_ON(using_dma(hsotg));
2480
2481 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2482 status = grxstsr & GRXSTS_PKTSTS_MASK;
2483
2484 size = grxstsr & GRXSTS_BYTECNT_MASK;
2485 size >>= GRXSTS_BYTECNT_SHIFT;
2486
2487 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2488 __func__, grxstsr, size, epnum);
2489
2490 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2491 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2492 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2493 break;
2494
2495 case GRXSTS_PKTSTS_OUTDONE:
2496 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2497 dwc2_hsotg_read_frameno(hsotg));
2498
2499 if (!using_dma(hsotg))
2500 dwc2_hsotg_handle_outdone(hsotg, epnum);
2501 break;
2502
2503 case GRXSTS_PKTSTS_SETUPDONE:
2504 dev_dbg(hsotg->dev,
2505 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2506 dwc2_hsotg_read_frameno(hsotg),
2507 dwc2_readl(hsotg, DOEPCTL(0)));
2508
2509
2510
2511
2512
2513 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2514 dwc2_hsotg_handle_outdone(hsotg, epnum);
2515 break;
2516
2517 case GRXSTS_PKTSTS_OUTRX:
2518 dwc2_hsotg_rx_data(hsotg, epnum, size);
2519 break;
2520
2521 case GRXSTS_PKTSTS_SETUPRX:
2522 dev_dbg(hsotg->dev,
2523 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2524 dwc2_hsotg_read_frameno(hsotg),
2525 dwc2_readl(hsotg, DOEPCTL(0)));
2526
2527 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2528
2529 dwc2_hsotg_rx_data(hsotg, epnum, size);
2530 break;
2531
2532 default:
2533 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2534 __func__, grxstsr);
2535
2536 dwc2_hsotg_dump(hsotg);
2537 break;
2538 }
2539}
2540
2541
2542
2543
2544
2545static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2546{
2547 switch (mps) {
2548 case 64:
2549 return D0EPCTL_MPS_64;
2550 case 32:
2551 return D0EPCTL_MPS_32;
2552 case 16:
2553 return D0EPCTL_MPS_16;
2554 case 8:
2555 return D0EPCTL_MPS_8;
2556 }
2557
2558
2559 WARN_ON(1);
2560 return (u32)-1;
2561}
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2575 unsigned int ep, unsigned int mps,
2576 unsigned int mc, unsigned int dir_in)
2577{
2578 struct dwc2_hsotg_ep *hs_ep;
2579 u32 reg;
2580
2581 hs_ep = index_to_ep(hsotg, ep, dir_in);
2582 if (!hs_ep)
2583 return;
2584
2585 if (ep == 0) {
2586 u32 mps_bytes = mps;
2587
2588
2589 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2590 if (mps > 3)
2591 goto bad_mps;
2592 hs_ep->ep.maxpacket = mps_bytes;
2593 hs_ep->mc = 1;
2594 } else {
2595 if (mps > 1024)
2596 goto bad_mps;
2597 hs_ep->mc = mc;
2598 if (mc > 3)
2599 goto bad_mps;
2600 hs_ep->ep.maxpacket = mps;
2601 }
2602
2603 if (dir_in) {
2604 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2605 reg &= ~DXEPCTL_MPS_MASK;
2606 reg |= mps;
2607 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2608 } else {
2609 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2610 reg &= ~DXEPCTL_MPS_MASK;
2611 reg |= mps;
2612 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2613 }
2614
2615 return;
2616
2617bad_mps:
2618 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2619}
2620
2621
2622
2623
2624
2625
2626static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2627{
2628 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2629 GRSTCTL);
2630
2631
2632 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2633 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2634 __func__);
2635}
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2646 struct dwc2_hsotg_ep *hs_ep)
2647{
2648 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2649
2650 if (!hs_ep->dir_in || !hs_req) {
2651
2652
2653
2654
2655 if (hs_ep->index != 0)
2656 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2657 hs_ep->dir_in, 0);
2658 return 0;
2659 }
2660
2661 if (hs_req->req.actual < hs_req->req.length) {
2662 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2663 hs_ep->index);
2664 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2665 }
2666
2667 return 0;
2668}
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2679 struct dwc2_hsotg_ep *hs_ep)
2680{
2681 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2682 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2683 int size_left, size_done;
2684
2685 if (!hs_req) {
2686 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2687 return;
2688 }
2689
2690
2691 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2692 dev_dbg(hsotg->dev, "zlp packet sent\n");
2693
2694
2695
2696
2697
2698 hs_ep->dir_in = 0;
2699
2700 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2701 if (hsotg->test_mode) {
2702 int ret;
2703
2704 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2705 if (ret < 0) {
2706 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2707 hsotg->test_mode);
2708 dwc2_hsotg_stall_ep0(hsotg);
2709 return;
2710 }
2711 }
2712 dwc2_hsotg_enqueue_setup(hsotg);
2713 return;
2714 }
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725 if (using_desc_dma(hsotg)) {
2726 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2727 if (size_left < 0)
2728 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2729 size_left);
2730 } else {
2731 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2732 }
2733
2734 size_done = hs_ep->size_loaded - size_left;
2735 size_done += hs_ep->last_load;
2736
2737 if (hs_req->req.actual != size_done)
2738 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2739 __func__, hs_req->req.actual, size_done);
2740
2741 hs_req->req.actual = size_done;
2742 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2743 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2744
2745 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2746 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2747 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2748 return;
2749 }
2750
2751
2752 if (hs_ep->send_zlp) {
2753 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2754 hs_ep->send_zlp = 0;
2755
2756 return;
2757 }
2758
2759 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2760
2761 dwc2_hsotg_ep0_zlp(hsotg, false);
2762 return;
2763 }
2764
2765 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2766}
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2778 unsigned int idx, int dir_in)
2779{
2780 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2781 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2782 u32 ints;
2783 u32 mask;
2784 u32 diepempmsk;
2785
2786 mask = dwc2_readl(hsotg, epmsk_reg);
2787 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2788 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2789 mask |= DXEPINT_SETUP_RCVD;
2790
2791 ints = dwc2_readl(hsotg, epint_reg);
2792 ints &= mask;
2793 return ints;
2794}
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2810{
2811 struct dwc2_hsotg *hsotg = hs_ep->parent;
2812 struct dwc2_hsotg_req *hs_req;
2813 unsigned char idx = hs_ep->index;
2814 int dir_in = hs_ep->dir_in;
2815 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2816 int dctl = dwc2_readl(hsotg, DCTL);
2817
2818 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2819
2820 if (dir_in) {
2821 int epctl = dwc2_readl(hsotg, epctl_reg);
2822
2823 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2824
2825 if (hs_ep->isochronous) {
2826 dwc2_hsotg_complete_in(hsotg, hs_ep);
2827 return;
2828 }
2829
2830 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2831 int dctl = dwc2_readl(hsotg, DCTL);
2832
2833 dctl |= DCTL_CGNPINNAK;
2834 dwc2_writel(hsotg, dctl, DCTL);
2835 }
2836 return;
2837 }
2838
2839 if (dctl & DCTL_GOUTNAKSTS) {
2840 dctl |= DCTL_CGOUTNAK;
2841 dwc2_writel(hsotg, dctl, DCTL);
2842 }
2843
2844 if (!hs_ep->isochronous)
2845 return;
2846
2847 if (list_empty(&hs_ep->queue)) {
2848 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2849 __func__, hs_ep);
2850 return;
2851 }
2852
2853 do {
2854 hs_req = get_ep_head(hs_ep);
2855 if (hs_req)
2856 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2857 -ENODATA);
2858 dwc2_gadget_incr_frame_num(hs_ep);
2859
2860 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2861 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2862
2863 dwc2_gadget_start_next_request(hs_ep);
2864}
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2878{
2879 struct dwc2_hsotg *hsotg = ep->parent;
2880 int dir_in = ep->dir_in;
2881 u32 doepmsk;
2882
2883 if (dir_in || !ep->isochronous)
2884 return;
2885
2886 if (using_desc_dma(hsotg)) {
2887 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2888
2889 ep->target_frame = hsotg->frame_number;
2890 dwc2_gadget_start_isoc_ddma(ep);
2891 }
2892 return;
2893 }
2894
2895 if (ep->interval > 1 &&
2896 ep->target_frame == TARGET_FRAME_INITIAL) {
2897 u32 ctrl;
2898
2899 ep->target_frame = hsotg->frame_number;
2900 dwc2_gadget_incr_frame_num(ep);
2901
2902 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2903 if (ep->target_frame & 0x1)
2904 ctrl |= DXEPCTL_SETODDFR;
2905 else
2906 ctrl |= DXEPCTL_SETEVENFR;
2907
2908 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2909 }
2910
2911 dwc2_gadget_start_next_request(ep);
2912 doepmsk = dwc2_readl(hsotg, DOEPMSK);
2913 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2914 dwc2_writel(hsotg, doepmsk, DOEPMSK);
2915}
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2932{
2933 struct dwc2_hsotg *hsotg = hs_ep->parent;
2934 int dir_in = hs_ep->dir_in;
2935
2936 if (!dir_in || !hs_ep->isochronous)
2937 return;
2938
2939 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2940
2941 if (using_desc_dma(hsotg)) {
2942 hs_ep->target_frame = hsotg->frame_number;
2943 dwc2_gadget_incr_frame_num(hs_ep);
2944
2945
2946
2947
2948 if (hsotg->params.service_interval) {
2949
2950
2951
2952 hs_ep->target_frame &= ~hs_ep->interval + 1;
2953
2954
2955
2956
2957 dwc2_gadget_incr_frame_num(hs_ep);
2958 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2959 }
2960
2961 dwc2_gadget_start_isoc_ddma(hs_ep);
2962 return;
2963 }
2964
2965 hs_ep->target_frame = hsotg->frame_number;
2966 if (hs_ep->interval > 1) {
2967 u32 ctrl = dwc2_readl(hsotg,
2968 DIEPCTL(hs_ep->index));
2969 if (hs_ep->target_frame & 0x1)
2970 ctrl |= DXEPCTL_SETODDFR;
2971 else
2972 ctrl |= DXEPCTL_SETEVENFR;
2973
2974 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
2975 }
2976
2977 dwc2_hsotg_complete_request(hsotg, hs_ep,
2978 get_ep_head(hs_ep), 0);
2979 }
2980
2981 if (!using_desc_dma(hsotg))
2982 dwc2_gadget_incr_frame_num(hs_ep);
2983}
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2994 int dir_in)
2995{
2996 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2997 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2998 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2999 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
3000 u32 ints;
3001
3002 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
3003
3004
3005 dwc2_writel(hsotg, ints, epint_reg);
3006
3007 if (!hs_ep) {
3008 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
3009 __func__, idx, dir_in ? "in" : "out");
3010 return;
3011 }
3012
3013 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
3014 __func__, idx, dir_in ? "in" : "out", ints);
3015
3016
3017 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
3018 ints &= ~DXEPINT_XFERCOMPL;
3019
3020
3021
3022
3023
3024
3025
3026 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3027 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3028 ints &= ~DXEPINT_XFERCOMPL;
3029
3030 if (ints & DXEPINT_XFERCOMPL) {
3031 dev_dbg(hsotg->dev,
3032 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3033 __func__, dwc2_readl(hsotg, epctl_reg),
3034 dwc2_readl(hsotg, epsiz_reg));
3035
3036
3037 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3038
3039 if (!(ints & DXEPINT_BNAINTR))
3040 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3041 } else if (dir_in) {
3042
3043
3044
3045
3046
3047 if (hs_ep->isochronous && hs_ep->interval > 1)
3048 dwc2_gadget_incr_frame_num(hs_ep);
3049
3050 dwc2_hsotg_complete_in(hsotg, hs_ep);
3051 if (ints & DXEPINT_NAKINTRPT)
3052 ints &= ~DXEPINT_NAKINTRPT;
3053
3054 if (idx == 0 && !hs_ep->req)
3055 dwc2_hsotg_enqueue_setup(hsotg);
3056 } else if (using_dma(hsotg)) {
3057
3058
3059
3060
3061 if (hs_ep->isochronous && hs_ep->interval > 1)
3062 dwc2_gadget_incr_frame_num(hs_ep);
3063
3064 dwc2_hsotg_handle_outdone(hsotg, idx);
3065 }
3066 }
3067
3068 if (ints & DXEPINT_EPDISBLD)
3069 dwc2_gadget_handle_ep_disabled(hs_ep);
3070
3071 if (ints & DXEPINT_OUTTKNEPDIS)
3072 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3073
3074 if (ints & DXEPINT_NAKINTRPT)
3075 dwc2_gadget_handle_nak(hs_ep);
3076
3077 if (ints & DXEPINT_AHBERR)
3078 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3079
3080 if (ints & DXEPINT_SETUP) {
3081 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3082
3083 if (using_dma(hsotg) && idx == 0) {
3084
3085
3086
3087
3088
3089
3090
3091 if (dir_in)
3092 WARN_ON_ONCE(1);
3093 else
3094 dwc2_hsotg_handle_outdone(hsotg, 0);
3095 }
3096 }
3097
3098 if (ints & DXEPINT_STSPHSERCVD) {
3099 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3100
3101
3102 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3103
3104 if (using_desc_dma(hsotg)) {
3105 if (!hsotg->delayed_status)
3106 dwc2_hsotg_ep0_zlp(hsotg, true);
3107 else
3108
3109
3110
3111
3112
3113
3114
3115 dwc2_set_bit(hsotg, DIEPCTL(0),
3116 DXEPCTL_CNAK);
3117 }
3118 }
3119
3120 }
3121
3122 if (ints & DXEPINT_BACK2BACKSETUP)
3123 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3124
3125 if (ints & DXEPINT_BNAINTR) {
3126 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3127 if (hs_ep->isochronous)
3128 dwc2_gadget_handle_isoc_bna(hs_ep);
3129 }
3130
3131 if (dir_in && !hs_ep->isochronous) {
3132
3133 if (ints & DXEPINT_INTKNTXFEMP) {
3134 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3135 __func__, idx);
3136 }
3137
3138
3139 if (ints & DXEPINT_INTKNEPMIS) {
3140 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3141 __func__, idx);
3142 }
3143
3144
3145 if (hsotg->dedicated_fifos &&
3146 ints & DXEPINT_TXFEMP) {
3147 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3148 __func__, idx);
3149 if (!using_dma(hsotg))
3150 dwc2_hsotg_trytx(hsotg, hs_ep);
3151 }
3152 }
3153}
3154
3155
3156
3157
3158
3159
3160
3161
3162static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3163{
3164 u32 dsts = dwc2_readl(hsotg, DSTS);
3165 int ep0_mps = 0, ep_mps = 8;
3166
3167
3168
3169
3170
3171
3172
3173 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3174
3175
3176
3177
3178
3179
3180
3181
3182 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3183 case DSTS_ENUMSPD_FS:
3184 case DSTS_ENUMSPD_FS48:
3185 hsotg->gadget.speed = USB_SPEED_FULL;
3186 ep0_mps = EP0_MPS_LIMIT;
3187 ep_mps = 1023;
3188 break;
3189
3190 case DSTS_ENUMSPD_HS:
3191 hsotg->gadget.speed = USB_SPEED_HIGH;
3192 ep0_mps = EP0_MPS_LIMIT;
3193 ep_mps = 1024;
3194 break;
3195
3196 case DSTS_ENUMSPD_LS:
3197 hsotg->gadget.speed = USB_SPEED_LOW;
3198 ep0_mps = 8;
3199 ep_mps = 8;
3200
3201
3202
3203
3204
3205 break;
3206 }
3207 dev_info(hsotg->dev, "new device is %s\n",
3208 usb_speed_string(hsotg->gadget.speed));
3209
3210
3211
3212
3213
3214
3215 if (ep0_mps) {
3216 int i;
3217
3218 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3219 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3220 for (i = 1; i < hsotg->num_of_eps; i++) {
3221 if (hsotg->eps_in[i])
3222 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3223 0, 1);
3224 if (hsotg->eps_out[i])
3225 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3226 0, 0);
3227 }
3228 }
3229
3230
3231
3232 dwc2_hsotg_enqueue_setup(hsotg);
3233
3234 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3235 dwc2_readl(hsotg, DIEPCTL0),
3236 dwc2_readl(hsotg, DOEPCTL0));
3237}
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248static void kill_all_requests(struct dwc2_hsotg *hsotg,
3249 struct dwc2_hsotg_ep *ep,
3250 int result)
3251{
3252 unsigned int size;
3253
3254 ep->req = NULL;
3255
3256 while (!list_empty(&ep->queue)) {
3257 struct dwc2_hsotg_req *req = get_ep_head(ep);
3258
3259 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3260 }
3261
3262 if (!hsotg->dedicated_fifos)
3263 return;
3264 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3265 if (size < ep->fifo_size)
3266 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3267}
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3278{
3279 unsigned int ep;
3280
3281 if (!hsotg->connected)
3282 return;
3283
3284 hsotg->connected = 0;
3285 hsotg->test_mode = 0;
3286
3287
3288 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3289 if (hsotg->eps_in[ep])
3290 kill_all_requests(hsotg, hsotg->eps_in[ep],
3291 -ESHUTDOWN);
3292 if (hsotg->eps_out[ep])
3293 kill_all_requests(hsotg, hsotg->eps_out[ep],
3294 -ESHUTDOWN);
3295 }
3296
3297 call_gadget(hsotg, disconnect);
3298 hsotg->lx_state = DWC2_L3;
3299
3300 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3301}
3302
3303
3304
3305
3306
3307
3308static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3309{
3310 struct dwc2_hsotg_ep *ep;
3311 int epno, ret;
3312
3313
3314 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3315 ep = index_to_ep(hsotg, epno, 1);
3316
3317 if (!ep)
3318 continue;
3319
3320 if (!ep->dir_in)
3321 continue;
3322
3323 if ((periodic && !ep->periodic) ||
3324 (!periodic && ep->periodic))
3325 continue;
3326
3327 ret = dwc2_hsotg_trytx(hsotg, ep);
3328 if (ret < 0)
3329 break;
3330 }
3331}
3332
3333
3334#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3335 GINTSTS_PTXFEMP | \
3336 GINTSTS_RXFLVL)
3337
3338static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3339
3340
3341
3342
3343
3344
3345
3346void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3347 bool is_usb_reset)
3348{
3349 u32 intmsk;
3350 u32 val;
3351 u32 usbcfg;
3352 u32 dcfg = 0;
3353 int ep;
3354
3355
3356 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3357
3358 if (!is_usb_reset) {
3359 if (dwc2_core_reset(hsotg, true))
3360 return;
3361 } else {
3362
3363 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3364 if (hsotg->eps_in[ep])
3365 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3366 if (hsotg->eps_out[ep])
3367 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3368 }
3369 }
3370
3371
3372
3373
3374
3375
3376
3377 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3378 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3379 usbcfg |= GUSBCFG_TOUTCAL(7);
3380
3381
3382 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3383 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3384
3385 dwc2_phy_init(hsotg, true);
3386
3387 dwc2_hsotg_init_fifo(hsotg);
3388
3389 if (!is_usb_reset)
3390 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3391
3392 dcfg |= DCFG_EPMISCNT(1);
3393
3394 switch (hsotg->params.speed) {
3395 case DWC2_SPEED_PARAM_LOW:
3396 dcfg |= DCFG_DEVSPD_LS;
3397 break;
3398 case DWC2_SPEED_PARAM_FULL:
3399 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3400 dcfg |= DCFG_DEVSPD_FS48;
3401 else
3402 dcfg |= DCFG_DEVSPD_FS;
3403 break;
3404 default:
3405 dcfg |= DCFG_DEVSPD_HS;
3406 }
3407
3408 if (hsotg->params.ipg_isoc_en)
3409 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3410
3411 dwc2_writel(hsotg, dcfg, DCFG);
3412
3413
3414 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3415
3416
3417 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3418 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3419 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3420 GINTSTS_USBRST | GINTSTS_RESETDET |
3421 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3422 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3423 GINTSTS_LPMTRANRCVD;
3424
3425 if (!using_desc_dma(hsotg))
3426 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3427
3428 if (!hsotg->params.external_id_pin_ctl)
3429 intmsk |= GINTSTS_CONIDSTSCHNG;
3430
3431 dwc2_writel(hsotg, intmsk, GINTMSK);
3432
3433 if (using_dma(hsotg)) {
3434 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3435 hsotg->params.ahbcfg,
3436 GAHBCFG);
3437
3438
3439 if (using_desc_dma(hsotg))
3440 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3441
3442 } else {
3443 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3444 (GAHBCFG_NP_TXF_EMP_LVL |
3445 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3446 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3447 }
3448
3449
3450
3451
3452
3453
3454
3455 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3456 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3457 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3458 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3459 DIEPMSK);
3460
3461
3462
3463
3464
3465 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3466 DOEPMSK_STSPHSERCVDMSK) : 0) |
3467 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3468 DOEPMSK_SETUPMSK,
3469 DOEPMSK);
3470
3471
3472 if (using_desc_dma(hsotg)) {
3473 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3474 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3475 }
3476
3477
3478 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3479 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3480
3481 dwc2_writel(hsotg, 0, DAINTMSK);
3482
3483 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3484 dwc2_readl(hsotg, DIEPCTL0),
3485 dwc2_readl(hsotg, DOEPCTL0));
3486
3487
3488 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3489
3490
3491
3492
3493
3494
3495 if (!using_dma(hsotg))
3496 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3497
3498
3499 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3500 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3501
3502 if (!is_usb_reset) {
3503 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3504 udelay(10);
3505 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3506 }
3507
3508 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3509
3510
3511
3512
3513
3514
3515
3516 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3517 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3518
3519 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3520 DXEPCTL_CNAK | DXEPCTL_EPENA |
3521 DXEPCTL_USBACTEP,
3522 DOEPCTL0);
3523
3524
3525 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3526 DXEPCTL_USBACTEP, DIEPCTL0);
3527
3528
3529 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3530 if (!is_usb_reset)
3531 val |= DCTL_SFTDISCON;
3532 dwc2_set_bit(hsotg, DCTL, val);
3533
3534
3535 dwc2_gadget_init_lpm(hsotg);
3536
3537
3538 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3539 dwc2_gadget_program_ref_clk(hsotg);
3540
3541
3542 mdelay(3);
3543
3544 hsotg->lx_state = DWC2_L0;
3545
3546 dwc2_hsotg_enqueue_setup(hsotg);
3547
3548 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3549 dwc2_readl(hsotg, DIEPCTL0),
3550 dwc2_readl(hsotg, DOEPCTL0));
3551}
3552
3553void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3554{
3555
3556 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3557}
3558
3559void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3560{
3561
3562 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3563}
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3579{
3580 struct dwc2_hsotg_ep *hs_ep;
3581 u32 epctrl;
3582 u32 daintmsk;
3583 u32 idx;
3584
3585 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3586
3587 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3588
3589 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3590 hs_ep = hsotg->eps_in[idx];
3591
3592 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3593 continue;
3594
3595 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3596 if ((epctrl & DXEPCTL_EPENA) &&
3597 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3598 epctrl |= DXEPCTL_SNAK;
3599 epctrl |= DXEPCTL_EPDIS;
3600 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3601 }
3602 }
3603
3604
3605 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3606}
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3622{
3623 u32 gintsts;
3624 u32 gintmsk;
3625 u32 daintmsk;
3626 u32 epctrl;
3627 struct dwc2_hsotg_ep *hs_ep;
3628 int idx;
3629
3630 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3631
3632 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3633 daintmsk >>= DAINT_OUTEP_SHIFT;
3634
3635 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3636 hs_ep = hsotg->eps_out[idx];
3637
3638 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3639 continue;
3640
3641 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3642 if ((epctrl & DXEPCTL_EPENA) &&
3643 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3644
3645 gintmsk = dwc2_readl(hsotg, GINTMSK);
3646 gintmsk |= GINTSTS_GOUTNAKEFF;
3647 dwc2_writel(hsotg, gintmsk, GINTMSK);
3648
3649 gintsts = dwc2_readl(hsotg, GINTSTS);
3650 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3651 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3652 break;
3653 }
3654 }
3655 }
3656
3657
3658 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3659}
3660
3661
3662
3663
3664
3665
3666static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3667{
3668 struct dwc2_hsotg *hsotg = pw;
3669 int retry_count = 8;
3670 u32 gintsts;
3671 u32 gintmsk;
3672
3673 if (!dwc2_is_device_mode(hsotg))
3674 return IRQ_NONE;
3675
3676 spin_lock(&hsotg->lock);
3677irq_retry:
3678 gintsts = dwc2_readl(hsotg, GINTSTS);
3679 gintmsk = dwc2_readl(hsotg, GINTMSK);
3680
3681 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3682 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3683
3684 gintsts &= gintmsk;
3685
3686 if (gintsts & GINTSTS_RESETDET) {
3687 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3688
3689 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3690
3691
3692 if (hsotg->lx_state == DWC2_L2) {
3693 dwc2_exit_partial_power_down(hsotg, true);
3694 hsotg->lx_state = DWC2_L0;
3695 }
3696 }
3697
3698 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3699 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3700 u32 connected = hsotg->connected;
3701
3702 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3703 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3704 dwc2_readl(hsotg, GNPTXSTS));
3705
3706 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3707
3708
3709 dwc2_hsotg_disconnect(hsotg);
3710
3711
3712 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3713
3714 if (usb_status & GOTGCTL_BSESVLD && connected)
3715 dwc2_hsotg_core_init_disconnected(hsotg, true);
3716 }
3717
3718 if (gintsts & GINTSTS_ENUMDONE) {
3719 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3720
3721 dwc2_hsotg_irq_enumdone(hsotg);
3722 }
3723
3724 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3725 u32 daint = dwc2_readl(hsotg, DAINT);
3726 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3727 u32 daint_out, daint_in;
3728 int ep;
3729
3730 daint &= daintmsk;
3731 daint_out = daint >> DAINT_OUTEP_SHIFT;
3732 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3733
3734 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3735
3736 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3737 ep++, daint_out >>= 1) {
3738 if (daint_out & 1)
3739 dwc2_hsotg_epint(hsotg, ep, 0);
3740 }
3741
3742 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3743 ep++, daint_in >>= 1) {
3744 if (daint_in & 1)
3745 dwc2_hsotg_epint(hsotg, ep, 1);
3746 }
3747 }
3748
3749
3750
3751 if (gintsts & GINTSTS_NPTXFEMP) {
3752 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3753
3754
3755
3756
3757
3758
3759
3760 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3761 dwc2_hsotg_irq_fifoempty(hsotg, false);
3762 }
3763
3764 if (gintsts & GINTSTS_PTXFEMP) {
3765 dev_dbg(hsotg->dev, "PTxFEmp\n");
3766
3767
3768
3769 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3770 dwc2_hsotg_irq_fifoempty(hsotg, true);
3771 }
3772
3773 if (gintsts & GINTSTS_RXFLVL) {
3774
3775
3776
3777
3778
3779
3780 dwc2_hsotg_handle_rx(hsotg);
3781 }
3782
3783 if (gintsts & GINTSTS_ERLYSUSP) {
3784 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3785 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3786 }
3787
3788
3789
3790
3791
3792
3793
3794 if (gintsts & GINTSTS_GOUTNAKEFF) {
3795 u8 idx;
3796 u32 epctrl;
3797 u32 gintmsk;
3798 u32 daintmsk;
3799 struct dwc2_hsotg_ep *hs_ep;
3800
3801 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3802 daintmsk >>= DAINT_OUTEP_SHIFT;
3803
3804 gintmsk = dwc2_readl(hsotg, GINTMSK);
3805 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3806 dwc2_writel(hsotg, gintmsk, GINTMSK);
3807
3808 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3809 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3810 hs_ep = hsotg->eps_out[idx];
3811
3812 if (BIT(idx) & ~daintmsk)
3813 continue;
3814
3815 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3816
3817
3818 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3819 epctrl |= DXEPCTL_SNAK;
3820 epctrl |= DXEPCTL_EPDIS;
3821 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3822 continue;
3823 }
3824
3825
3826 if (hs_ep->halted) {
3827 if (!(epctrl & DXEPCTL_EPENA))
3828 epctrl |= DXEPCTL_EPENA;
3829 epctrl |= DXEPCTL_EPDIS;
3830 epctrl |= DXEPCTL_STALL;
3831 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3832 }
3833 }
3834
3835
3836 }
3837
3838 if (gintsts & GINTSTS_GINNAKEFF) {
3839 dev_info(hsotg->dev, "GINNakEff triggered\n");
3840
3841 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3842
3843 dwc2_hsotg_dump(hsotg);
3844 }
3845
3846 if (gintsts & GINTSTS_INCOMPL_SOIN)
3847 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3848
3849 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3850 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3851
3852
3853
3854
3855
3856
3857 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3858 goto irq_retry;
3859
3860
3861 if (hsotg->params.service_interval)
3862 dwc2_gadget_wkup_alert_handler(hsotg);
3863
3864 spin_unlock(&hsotg->lock);
3865
3866 return IRQ_HANDLED;
3867}
3868
3869static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3870 struct dwc2_hsotg_ep *hs_ep)
3871{
3872 u32 epctrl_reg;
3873 u32 epint_reg;
3874
3875 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3876 DOEPCTL(hs_ep->index);
3877 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3878 DOEPINT(hs_ep->index);
3879
3880 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3881 hs_ep->name);
3882
3883 if (hs_ep->dir_in) {
3884 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3885 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3886
3887 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3888 DXEPINT_INEPNAKEFF, 100))
3889 dev_warn(hsotg->dev,
3890 "%s: timeout DIEPINT.NAKEFF\n",
3891 __func__);
3892 } else {
3893 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3894
3895 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3896 GINTSTS_GINNAKEFF, 100))
3897 dev_warn(hsotg->dev,
3898 "%s: timeout GINTSTS.GINNAKEFF\n",
3899 __func__);
3900 }
3901 } else {
3902 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3903 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3904
3905
3906 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3907 GINTSTS_GOUTNAKEFF, 100))
3908 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3909 __func__);
3910 }
3911
3912
3913 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3914
3915
3916 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3917 dev_warn(hsotg->dev,
3918 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3919
3920
3921 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3922
3923 if (hs_ep->dir_in) {
3924 unsigned short fifo_index;
3925
3926 if (hsotg->dedicated_fifos || hs_ep->periodic)
3927 fifo_index = hs_ep->fifo_index;
3928 else
3929 fifo_index = 0;
3930
3931
3932 dwc2_flush_tx_fifo(hsotg, fifo_index);
3933
3934
3935 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3936 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3937
3938 } else {
3939
3940 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3941 }
3942}
3943
3944
3945
3946
3947
3948
3949
3950
3951static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3952 const struct usb_endpoint_descriptor *desc)
3953{
3954 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3955 struct dwc2_hsotg *hsotg = hs_ep->parent;
3956 unsigned long flags;
3957 unsigned int index = hs_ep->index;
3958 u32 epctrl_reg;
3959 u32 epctrl;
3960 u32 mps;
3961 u32 mc;
3962 u32 mask;
3963 unsigned int dir_in;
3964 unsigned int i, val, size;
3965 int ret = 0;
3966 unsigned char ep_type;
3967 int desc_num;
3968
3969 dev_dbg(hsotg->dev,
3970 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3971 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
3972 desc->wMaxPacketSize, desc->bInterval);
3973
3974
3975 if (index == 0) {
3976 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
3977 return -EINVAL;
3978 }
3979
3980 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
3981 if (dir_in != hs_ep->dir_in) {
3982 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
3983 return -EINVAL;
3984 }
3985
3986 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
3987 mps = usb_endpoint_maxp(desc);
3988 mc = usb_endpoint_maxp_mult(desc);
3989
3990
3991 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
3992 dir_in && desc->bInterval > 10) {
3993 dev_err(hsotg->dev,
3994 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
3995 return -EINVAL;
3996 }
3997
3998
3999 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4000 !dir_in && mc > 1) {
4001 dev_err(hsotg->dev,
4002 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
4003 return -EINVAL;
4004 }
4005
4006
4007
4008 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4009 epctrl = dwc2_readl(hsotg, epctrl_reg);
4010
4011 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
4012 __func__, epctrl, epctrl_reg);
4013
4014 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
4015 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
4016 else
4017 desc_num = MAX_DMA_DESC_NUM_GENERIC;
4018
4019
4020 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4021 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4022 desc_num * sizeof(struct dwc2_dma_desc),
4023 &hs_ep->desc_list_dma, GFP_ATOMIC);
4024 if (!hs_ep->desc_list) {
4025 ret = -ENOMEM;
4026 goto error2;
4027 }
4028 }
4029
4030 spin_lock_irqsave(&hsotg->lock, flags);
4031
4032 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
4033 epctrl |= DXEPCTL_MPS(mps);
4034
4035
4036
4037
4038
4039 epctrl |= DXEPCTL_USBACTEP;
4040
4041
4042 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4043
4044
4045 hs_ep->isochronous = 0;
4046 hs_ep->periodic = 0;
4047 hs_ep->halted = 0;
4048 hs_ep->interval = desc->bInterval;
4049
4050 switch (ep_type) {
4051 case USB_ENDPOINT_XFER_ISOC:
4052 epctrl |= DXEPCTL_EPTYPE_ISO;
4053 epctrl |= DXEPCTL_SETEVENFR;
4054 hs_ep->isochronous = 1;
4055 hs_ep->interval = 1 << (desc->bInterval - 1);
4056 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4057 hs_ep->next_desc = 0;
4058 hs_ep->compl_desc = 0;
4059 if (dir_in) {
4060 hs_ep->periodic = 1;
4061 mask = dwc2_readl(hsotg, DIEPMSK);
4062 mask |= DIEPMSK_NAKMSK;
4063 dwc2_writel(hsotg, mask, DIEPMSK);
4064 } else {
4065 mask = dwc2_readl(hsotg, DOEPMSK);
4066 mask |= DOEPMSK_OUTTKNEPDISMSK;
4067 dwc2_writel(hsotg, mask, DOEPMSK);
4068 }
4069 break;
4070
4071 case USB_ENDPOINT_XFER_BULK:
4072 epctrl |= DXEPCTL_EPTYPE_BULK;
4073 break;
4074
4075 case USB_ENDPOINT_XFER_INT:
4076 if (dir_in)
4077 hs_ep->periodic = 1;
4078
4079 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4080 hs_ep->interval = 1 << (desc->bInterval - 1);
4081
4082 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4083 break;
4084
4085 case USB_ENDPOINT_XFER_CONTROL:
4086 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4087 break;
4088 }
4089
4090
4091
4092
4093
4094 if (dir_in && hsotg->dedicated_fifos) {
4095 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4096 u32 fifo_index = 0;
4097 u32 fifo_size = UINT_MAX;
4098
4099 size = hs_ep->ep.maxpacket * hs_ep->mc;
4100 for (i = 1; i <= fifo_count; ++i) {
4101 if (hsotg->fifo_map & (1 << i))
4102 continue;
4103 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4104 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4105 if (val < size)
4106 continue;
4107
4108 if (val < fifo_size) {
4109 fifo_size = val;
4110 fifo_index = i;
4111 }
4112 }
4113 if (!fifo_index) {
4114 dev_err(hsotg->dev,
4115 "%s: No suitable fifo found\n", __func__);
4116 ret = -ENOMEM;
4117 goto error1;
4118 }
4119 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4120 hsotg->fifo_map |= 1 << fifo_index;
4121 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4122 hs_ep->fifo_index = fifo_index;
4123 hs_ep->fifo_size = fifo_size;
4124 }
4125
4126
4127 if (index && !hs_ep->isochronous)
4128 epctrl |= DXEPCTL_SETD0PID;
4129
4130
4131
4132
4133
4134
4135
4136 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4137 hs_ep->isochronous && dir_in) {
4138
4139
4140
4141
4142 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4143
4144 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4145 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4146 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4147 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4148 epctrl |= DXEPCTL_CNAK;
4149 }
4150
4151 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4152 __func__, epctrl);
4153
4154 dwc2_writel(hsotg, epctrl, epctrl_reg);
4155 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4156 __func__, dwc2_readl(hsotg, epctrl_reg));
4157
4158
4159 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4160
4161error1:
4162 spin_unlock_irqrestore(&hsotg->lock, flags);
4163
4164error2:
4165 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4166 dmam_free_coherent(hsotg->dev, desc_num *
4167 sizeof(struct dwc2_dma_desc),
4168 hs_ep->desc_list, hs_ep->desc_list_dma);
4169 hs_ep->desc_list = NULL;
4170 }
4171
4172 return ret;
4173}
4174
4175
4176
4177
4178
4179static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4180{
4181 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4182 struct dwc2_hsotg *hsotg = hs_ep->parent;
4183 int dir_in = hs_ep->dir_in;
4184 int index = hs_ep->index;
4185 u32 epctrl_reg;
4186 u32 ctrl;
4187
4188 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4189
4190 if (ep == &hsotg->eps_out[0]->ep) {
4191 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4192 return -EINVAL;
4193 }
4194
4195 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4196 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4197 return -EINVAL;
4198 }
4199
4200 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4201
4202 ctrl = dwc2_readl(hsotg, epctrl_reg);
4203
4204 if (ctrl & DXEPCTL_EPENA)
4205 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4206
4207 ctrl &= ~DXEPCTL_EPENA;
4208 ctrl &= ~DXEPCTL_USBACTEP;
4209 ctrl |= DXEPCTL_SNAK;
4210
4211 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4212 dwc2_writel(hsotg, ctrl, epctrl_reg);
4213
4214
4215 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4216
4217
4218 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4219
4220 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4221 hs_ep->fifo_index = 0;
4222 hs_ep->fifo_size = 0;
4223
4224 return 0;
4225}
4226
4227static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4228{
4229 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4230 struct dwc2_hsotg *hsotg = hs_ep->parent;
4231 unsigned long flags;
4232 int ret;
4233
4234 spin_lock_irqsave(&hsotg->lock, flags);
4235 ret = dwc2_hsotg_ep_disable(ep);
4236 spin_unlock_irqrestore(&hsotg->lock, flags);
4237 return ret;
4238}
4239
4240
4241
4242
4243
4244
4245static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4246{
4247 struct dwc2_hsotg_req *req, *treq;
4248
4249 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4250 if (req == test)
4251 return true;
4252 }
4253
4254 return false;
4255}
4256
4257
4258
4259
4260
4261
4262static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4263{
4264 struct dwc2_hsotg_req *hs_req = our_req(req);
4265 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4266 struct dwc2_hsotg *hs = hs_ep->parent;
4267 unsigned long flags;
4268
4269 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4270
4271 spin_lock_irqsave(&hs->lock, flags);
4272
4273 if (!on_list(hs_ep, hs_req)) {
4274 spin_unlock_irqrestore(&hs->lock, flags);
4275 return -EINVAL;
4276 }
4277
4278
4279 if (req == &hs_ep->req->req)
4280 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4281
4282 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4283 spin_unlock_irqrestore(&hs->lock, flags);
4284
4285 return 0;
4286}
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4299{
4300 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4301 struct dwc2_hsotg *hs = hs_ep->parent;
4302 int index = hs_ep->index;
4303 u32 epreg;
4304 u32 epctl;
4305 u32 xfertype;
4306
4307 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4308
4309 if (index == 0) {
4310 if (value)
4311 dwc2_hsotg_stall_ep0(hs);
4312 else
4313 dev_warn(hs->dev,
4314 "%s: can't clear halt on ep0\n", __func__);
4315 return 0;
4316 }
4317
4318 if (hs_ep->isochronous) {
4319 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4320 return -EINVAL;
4321 }
4322
4323 if (!now && value && !list_empty(&hs_ep->queue)) {
4324 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4325 ep->name);
4326 return -EAGAIN;
4327 }
4328
4329 if (hs_ep->dir_in) {
4330 epreg = DIEPCTL(index);
4331 epctl = dwc2_readl(hs, epreg);
4332
4333 if (value) {
4334 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4335 if (epctl & DXEPCTL_EPENA)
4336 epctl |= DXEPCTL_EPDIS;
4337 } else {
4338 epctl &= ~DXEPCTL_STALL;
4339 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4340 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4341 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4342 epctl |= DXEPCTL_SETD0PID;
4343 }
4344 dwc2_writel(hs, epctl, epreg);
4345 } else {
4346 epreg = DOEPCTL(index);
4347 epctl = dwc2_readl(hs, epreg);
4348
4349 if (value) {
4350 if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4351 dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4352
4353 } else {
4354 epctl &= ~DXEPCTL_STALL;
4355 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4356 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4357 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4358 epctl |= DXEPCTL_SETD0PID;
4359 dwc2_writel(hs, epctl, epreg);
4360 }
4361 }
4362
4363 hs_ep->halted = value;
4364 return 0;
4365}
4366
4367
4368
4369
4370
4371
4372static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4373{
4374 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4375 struct dwc2_hsotg *hs = hs_ep->parent;
4376 unsigned long flags = 0;
4377 int ret = 0;
4378
4379 spin_lock_irqsave(&hs->lock, flags);
4380 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4381 spin_unlock_irqrestore(&hs->lock, flags);
4382
4383 return ret;
4384}
4385
4386static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4387 .enable = dwc2_hsotg_ep_enable,
4388 .disable = dwc2_hsotg_ep_disable_lock,
4389 .alloc_request = dwc2_hsotg_ep_alloc_request,
4390 .free_request = dwc2_hsotg_ep_free_request,
4391 .queue = dwc2_hsotg_ep_queue_lock,
4392 .dequeue = dwc2_hsotg_ep_dequeue,
4393 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4394
4395};
4396
4397
4398
4399
4400
4401static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4402{
4403
4404
4405 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4406 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4407 DIEPMSK);
4408
4409 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4410 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4411 DOEPMSK);
4412
4413 dwc2_writel(hsotg, 0, DAINTMSK);
4414
4415
4416 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4417
4418
4419
4420 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4421 dwc2_readl(hsotg, GRXFSIZ),
4422 dwc2_readl(hsotg, GNPTXFSIZ));
4423
4424 dwc2_hsotg_init_fifo(hsotg);
4425
4426 if (using_dma(hsotg))
4427 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4428}
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4439 struct usb_gadget_driver *driver)
4440{
4441 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4442 unsigned long flags;
4443 int ret;
4444
4445 if (!hsotg) {
4446 pr_err("%s: called with no device\n", __func__);
4447 return -ENODEV;
4448 }
4449
4450 if (!driver) {
4451 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4452 return -EINVAL;
4453 }
4454
4455 if (driver->max_speed < USB_SPEED_FULL)
4456 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4457
4458 if (!driver->setup) {
4459 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4460 return -EINVAL;
4461 }
4462
4463 WARN_ON(hsotg->driver);
4464
4465 driver->driver.bus = NULL;
4466 hsotg->driver = driver;
4467 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4468 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4469
4470 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4471 ret = dwc2_lowlevel_hw_enable(hsotg);
4472 if (ret)
4473 goto err;
4474 }
4475
4476 if (!IS_ERR_OR_NULL(hsotg->uphy))
4477 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4478
4479 spin_lock_irqsave(&hsotg->lock, flags);
4480 if (dwc2_hw_is_device(hsotg)) {
4481 dwc2_hsotg_init(hsotg);
4482 dwc2_hsotg_core_init_disconnected(hsotg, false);
4483 }
4484
4485 hsotg->enabled = 0;
4486 spin_unlock_irqrestore(&hsotg->lock, flags);
4487
4488 gadget->sg_supported = using_desc_dma(hsotg);
4489 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4490
4491 return 0;
4492
4493err:
4494 hsotg->driver = NULL;
4495 return ret;
4496}
4497
4498
4499
4500
4501
4502
4503
4504static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4505{
4506 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4507 unsigned long flags = 0;
4508 int ep;
4509
4510 if (!hsotg)
4511 return -ENODEV;
4512
4513
4514 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4515 if (hsotg->eps_in[ep])
4516 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4517 if (hsotg->eps_out[ep])
4518 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4519 }
4520
4521 spin_lock_irqsave(&hsotg->lock, flags);
4522
4523 hsotg->driver = NULL;
4524 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4525 hsotg->enabled = 0;
4526
4527 spin_unlock_irqrestore(&hsotg->lock, flags);
4528
4529 if (!IS_ERR_OR_NULL(hsotg->uphy))
4530 otg_set_peripheral(hsotg->uphy->otg, NULL);
4531
4532 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4533 dwc2_lowlevel_hw_disable(hsotg);
4534
4535 return 0;
4536}
4537
4538
4539
4540
4541
4542
4543
4544static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4545{
4546 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4547}
4548
4549
4550
4551
4552
4553
4554
4555
4556static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4557 int is_selfpowered)
4558{
4559 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4560 unsigned long flags;
4561
4562 spin_lock_irqsave(&hsotg->lock, flags);
4563 gadget->is_selfpowered = !!is_selfpowered;
4564 spin_unlock_irqrestore(&hsotg->lock, flags);
4565
4566 return 0;
4567}
4568
4569
4570
4571
4572
4573
4574
4575
4576static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4577{
4578 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4579 unsigned long flags = 0;
4580
4581 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4582 hsotg->op_state);
4583
4584
4585 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4586 hsotg->enabled = is_on;
4587 return 0;
4588 }
4589
4590 spin_lock_irqsave(&hsotg->lock, flags);
4591 if (is_on) {
4592 hsotg->enabled = 1;
4593 dwc2_hsotg_core_init_disconnected(hsotg, false);
4594
4595 dwc2_enable_acg(hsotg);
4596 dwc2_hsotg_core_connect(hsotg);
4597 } else {
4598 dwc2_hsotg_core_disconnect(hsotg);
4599 dwc2_hsotg_disconnect(hsotg);
4600 hsotg->enabled = 0;
4601 }
4602
4603 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4604 spin_unlock_irqrestore(&hsotg->lock, flags);
4605
4606 return 0;
4607}
4608
4609static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4610{
4611 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4612 unsigned long flags;
4613
4614 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4615 spin_lock_irqsave(&hsotg->lock, flags);
4616
4617
4618
4619
4620
4621 if (hsotg->lx_state == DWC2_L2)
4622 dwc2_exit_partial_power_down(hsotg, false);
4623
4624 if (is_active) {
4625 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4626
4627 dwc2_hsotg_core_init_disconnected(hsotg, false);
4628 if (hsotg->enabled) {
4629
4630 dwc2_enable_acg(hsotg);
4631 dwc2_hsotg_core_connect(hsotg);
4632 }
4633 } else {
4634 dwc2_hsotg_core_disconnect(hsotg);
4635 dwc2_hsotg_disconnect(hsotg);
4636 }
4637
4638 spin_unlock_irqrestore(&hsotg->lock, flags);
4639 return 0;
4640}
4641
4642
4643
4644
4645
4646
4647
4648
4649static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4650{
4651 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4652
4653 if (IS_ERR_OR_NULL(hsotg->uphy))
4654 return -ENOTSUPP;
4655 return usb_phy_set_power(hsotg->uphy, mA);
4656}
4657
4658static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4659 .get_frame = dwc2_hsotg_gadget_getframe,
4660 .set_selfpowered = dwc2_hsotg_set_selfpowered,
4661 .udc_start = dwc2_hsotg_udc_start,
4662 .udc_stop = dwc2_hsotg_udc_stop,
4663 .pullup = dwc2_hsotg_pullup,
4664 .vbus_session = dwc2_hsotg_vbus_session,
4665 .vbus_draw = dwc2_hsotg_vbus_draw,
4666};
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4680 struct dwc2_hsotg_ep *hs_ep,
4681 int epnum,
4682 bool dir_in)
4683{
4684 char *dir;
4685
4686 if (epnum == 0)
4687 dir = "";
4688 else if (dir_in)
4689 dir = "in";
4690 else
4691 dir = "out";
4692
4693 hs_ep->dir_in = dir_in;
4694 hs_ep->index = epnum;
4695
4696 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4697
4698 INIT_LIST_HEAD(&hs_ep->queue);
4699 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4700
4701
4702 if (epnum)
4703 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4704
4705 hs_ep->parent = hsotg;
4706 hs_ep->ep.name = hs_ep->name;
4707
4708 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4709 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4710 else
4711 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4712 epnum ? 1024 : EP0_MPS_LIMIT);
4713 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4714
4715 if (epnum == 0) {
4716 hs_ep->ep.caps.type_control = true;
4717 } else {
4718 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4719 hs_ep->ep.caps.type_iso = true;
4720 hs_ep->ep.caps.type_bulk = true;
4721 }
4722 hs_ep->ep.caps.type_int = true;
4723 }
4724
4725 if (dir_in)
4726 hs_ep->ep.caps.dir_in = true;
4727 else
4728 hs_ep->ep.caps.dir_out = true;
4729
4730
4731
4732
4733
4734
4735 if (using_dma(hsotg)) {
4736 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4737
4738 if (dir_in)
4739 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4740 else
4741 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4742 }
4743}
4744
4745
4746
4747
4748
4749
4750
4751static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4752{
4753 u32 cfg;
4754 u32 ep_type;
4755 u32 i;
4756
4757
4758
4759 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4760
4761
4762 hsotg->num_of_eps++;
4763
4764 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4765 sizeof(struct dwc2_hsotg_ep),
4766 GFP_KERNEL);
4767 if (!hsotg->eps_in[0])
4768 return -ENOMEM;
4769
4770 hsotg->eps_out[0] = hsotg->eps_in[0];
4771
4772 cfg = hsotg->hw_params.dev_ep_dirs;
4773 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4774 ep_type = cfg & 3;
4775
4776 if (!(ep_type & 2)) {
4777 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4778 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4779 if (!hsotg->eps_in[i])
4780 return -ENOMEM;
4781 }
4782
4783 if (!(ep_type & 1)) {
4784 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4785 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4786 if (!hsotg->eps_out[i])
4787 return -ENOMEM;
4788 }
4789 }
4790
4791 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4792 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4793
4794 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4795 hsotg->num_of_eps,
4796 hsotg->dedicated_fifos ? "dedicated" : "shared",
4797 hsotg->fifo_mem);
4798 return 0;
4799}
4800
4801
4802
4803
4804
4805
4806static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4807{
4808#ifdef DEBUG
4809 struct device *dev = hsotg->dev;
4810 u32 val;
4811 int idx;
4812
4813 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4814 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4815 dwc2_readl(hsotg, DIEPMSK));
4816
4817 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4818 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4819
4820 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4821 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4822
4823
4824
4825 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4826 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4827 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4828 val >> FIFOSIZE_DEPTH_SHIFT,
4829 val & FIFOSIZE_STARTADDR_MASK);
4830 }
4831
4832 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4833 dev_info(dev,
4834 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4835 dwc2_readl(hsotg, DIEPCTL(idx)),
4836 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4837 dwc2_readl(hsotg, DIEPDMA(idx)));
4838
4839 val = dwc2_readl(hsotg, DOEPCTL(idx));
4840 dev_info(dev,
4841 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4842 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4843 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4844 dwc2_readl(hsotg, DOEPDMA(idx)));
4845 }
4846
4847 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4848 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4849#endif
4850}
4851
4852
4853
4854
4855
4856
4857int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4858{
4859 struct device *dev = hsotg->dev;
4860 int epnum;
4861 int ret;
4862
4863
4864 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4865 hsotg->params.g_np_tx_fifo_size);
4866 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4867
4868 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4869 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4870 hsotg->gadget.name = dev_name(dev);
4871 hsotg->remote_wakeup_allowed = 0;
4872
4873 if (hsotg->params.lpm)
4874 hsotg->gadget.lpm_capable = true;
4875
4876 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4877 hsotg->gadget.is_otg = 1;
4878 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4879 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4880
4881 ret = dwc2_hsotg_hw_cfg(hsotg);
4882 if (ret) {
4883 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4884 return ret;
4885 }
4886
4887 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4888 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4889 if (!hsotg->ctrl_buff)
4890 return -ENOMEM;
4891
4892 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4893 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4894 if (!hsotg->ep0_buff)
4895 return -ENOMEM;
4896
4897 if (using_desc_dma(hsotg)) {
4898 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4899 if (ret < 0)
4900 return ret;
4901 }
4902
4903 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
4904 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
4905 if (ret < 0) {
4906 dev_err(dev, "cannot claim IRQ for gadget\n");
4907 return ret;
4908 }
4909
4910
4911
4912 if (hsotg->num_of_eps == 0) {
4913 dev_err(dev, "wrong number of EPs (zero)\n");
4914 return -EINVAL;
4915 }
4916
4917
4918
4919 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4920 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4921
4922
4923
4924 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4925 GFP_KERNEL);
4926 if (!hsotg->ctrl_req) {
4927 dev_err(dev, "failed to allocate ctrl req\n");
4928 return -ENOMEM;
4929 }
4930
4931
4932 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4933 if (hsotg->eps_in[epnum])
4934 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4935 epnum, 1);
4936 if (hsotg->eps_out[epnum])
4937 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4938 epnum, 0);
4939 }
4940
4941 dwc2_hsotg_dump(hsotg);
4942
4943 return 0;
4944}
4945
4946
4947
4948
4949
4950
4951int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
4952{
4953 usb_del_gadget_udc(&hsotg->gadget);
4954 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
4955
4956 return 0;
4957}
4958
4959int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
4960{
4961 unsigned long flags;
4962
4963 if (hsotg->lx_state != DWC2_L0)
4964 return 0;
4965
4966 if (hsotg->driver) {
4967 int ep;
4968
4969 dev_info(hsotg->dev, "suspending usb gadget %s\n",
4970 hsotg->driver->driver.name);
4971
4972 spin_lock_irqsave(&hsotg->lock, flags);
4973 if (hsotg->enabled)
4974 dwc2_hsotg_core_disconnect(hsotg);
4975 dwc2_hsotg_disconnect(hsotg);
4976 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4977 spin_unlock_irqrestore(&hsotg->lock, flags);
4978
4979 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
4980 if (hsotg->eps_in[ep])
4981 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4982 if (hsotg->eps_out[ep])
4983 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4984 }
4985 }
4986
4987 return 0;
4988}
4989
4990int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
4991{
4992 unsigned long flags;
4993
4994 if (hsotg->lx_state == DWC2_L2)
4995 return 0;
4996
4997 if (hsotg->driver) {
4998 dev_info(hsotg->dev, "resuming usb gadget %s\n",
4999 hsotg->driver->driver.name);
5000
5001 spin_lock_irqsave(&hsotg->lock, flags);
5002 dwc2_hsotg_core_init_disconnected(hsotg, false);
5003 if (hsotg->enabled) {
5004
5005 dwc2_enable_acg(hsotg);
5006 dwc2_hsotg_core_connect(hsotg);
5007 }
5008 spin_unlock_irqrestore(&hsotg->lock, flags);
5009 }
5010
5011 return 0;
5012}
5013
5014
5015
5016
5017
5018
5019
5020
5021int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5022{
5023 struct dwc2_dregs_backup *dr;
5024 int i;
5025
5026 dev_dbg(hsotg->dev, "%s\n", __func__);
5027
5028
5029 dr = &hsotg->dr_backup;
5030
5031 dr->dcfg = dwc2_readl(hsotg, DCFG);
5032 dr->dctl = dwc2_readl(hsotg, DCTL);
5033 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5034 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5035 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5036
5037 for (i = 0; i < hsotg->num_of_eps; i++) {
5038
5039 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5040
5041
5042 if (dr->diepctl[i] & DXEPCTL_DPID)
5043 dr->diepctl[i] |= DXEPCTL_SETD1PID;
5044 else
5045 dr->diepctl[i] |= DXEPCTL_SETD0PID;
5046
5047 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5048 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5049
5050
5051 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5052
5053
5054 if (dr->doepctl[i] & DXEPCTL_DPID)
5055 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5056 else
5057 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5058
5059 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5060 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5061 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5062 }
5063 dr->valid = true;
5064 return 0;
5065}
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
5077int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5078{
5079 struct dwc2_dregs_backup *dr;
5080 int i;
5081
5082 dev_dbg(hsotg->dev, "%s\n", __func__);
5083
5084
5085 dr = &hsotg->dr_backup;
5086 if (!dr->valid) {
5087 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5088 __func__);
5089 return -EINVAL;
5090 }
5091 dr->valid = false;
5092
5093 if (!remote_wakeup)
5094 dwc2_writel(hsotg, dr->dctl, DCTL);
5095
5096 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5097 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5098 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5099
5100 for (i = 0; i < hsotg->num_of_eps; i++) {
5101
5102 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5103 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5104 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5105
5106
5107
5108
5109
5110 if (hsotg->params.g_dma_desc &&
5111 (dr->diepctl[i] & DXEPCTL_EPENA))
5112 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5113 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5114 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5115
5116 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5117
5118
5119
5120
5121
5122 if (hsotg->params.g_dma_desc &&
5123 (dr->doepctl[i] & DXEPCTL_EPENA))
5124 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5125 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5126 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5127 }
5128
5129 return 0;
5130}
5131
5132
5133
5134
5135
5136
5137
5138void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5139{
5140 u32 val;
5141
5142 if (!hsotg->params.lpm)
5143 return;
5144
5145 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5146 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5147 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5148 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5149 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5150 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5151 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5152 dwc2_writel(hsotg, val, GLPMCFG);
5153 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5154
5155
5156 if (hsotg->params.service_interval)
5157 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5158}
5159
5160
5161
5162
5163
5164
5165
5166void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5167{
5168 u32 val = 0;
5169
5170 val |= GREFCLK_REF_CLK_MODE;
5171 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5172 val |= hsotg->params.sof_cnt_wkup_alert <<
5173 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5174
5175 dwc2_writel(hsotg, val, GREFCLK);
5176 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5177}
5178
5179
5180
5181
5182
5183
5184
5185
5186int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5187{
5188 u32 gpwrdn;
5189 int ret = 0;
5190
5191
5192 hsotg->lx_state = DWC2_L2;
5193 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5194 ret = dwc2_backup_global_registers(hsotg);
5195 if (ret) {
5196 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5197 __func__);
5198 return ret;
5199 }
5200 ret = dwc2_backup_device_registers(hsotg);
5201 if (ret) {
5202 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5203 __func__);
5204 return ret;
5205 }
5206
5207 gpwrdn = GPWRDN_PWRDNRSTN;
5208 gpwrdn |= GPWRDN_PMUACTV;
5209 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5210 udelay(10);
5211
5212
5213 hsotg->hibernated = 1;
5214
5215
5216 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5217 gpwrdn |= GPWRDN_PMUINTSEL;
5218 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5219 udelay(10);
5220
5221
5222 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5223 gpwrdn |= GPWRDN_RST_DET_MSK;
5224 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5225 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5226 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5227 udelay(10);
5228
5229
5230 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5231 gpwrdn |= GPWRDN_PWRDNCLMP;
5232 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5233 udelay(10);
5234
5235
5236 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5237 gpwrdn |= GPWRDN_PWRDNSWTCH;
5238 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5239 udelay(10);
5240
5241
5242 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5243 dev_dbg(hsotg->dev, "Hibernation completed\n");
5244
5245 return ret;
5246}
5247
5248
5249
5250
5251
5252
5253
5254
5255
5256
5257
5258
5259int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5260 int rem_wakeup, int reset)
5261{
5262 u32 pcgcctl;
5263 u32 gpwrdn;
5264 u32 dctl;
5265 int ret = 0;
5266 struct dwc2_gregs_backup *gr;
5267 struct dwc2_dregs_backup *dr;
5268
5269 gr = &hsotg->gr_backup;
5270 dr = &hsotg->dr_backup;
5271
5272 if (!hsotg->hibernated) {
5273 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5274 return 1;
5275 }
5276 dev_dbg(hsotg->dev,
5277 "%s: called with rem_wakeup = %d reset = %d\n",
5278 __func__, rem_wakeup, reset);
5279
5280 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5281
5282 if (!reset) {
5283
5284 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5285 }
5286
5287
5288 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5289 gpwrdn &= ~GPWRDN_RESTORE;
5290 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5291 udelay(10);
5292
5293 if (!rem_wakeup) {
5294 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5295 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5296 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5297 }
5298
5299
5300 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5301 dwc2_writel(hsotg, dr->dcfg, DCFG);
5302 dwc2_writel(hsotg, dr->dctl, DCTL);
5303
5304
5305 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5306 gpwrdn &= ~GPWRDN_PMUACTV;
5307 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5308
5309 if (rem_wakeup) {
5310 udelay(10);
5311
5312 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5313 } else {
5314 udelay(50);
5315
5316 dctl = dwc2_readl(hsotg, DCTL);
5317 dctl |= DCTL_PWRONPRGDONE;
5318 dwc2_writel(hsotg, dctl, DCTL);
5319 }
5320
5321 mdelay(2);
5322
5323 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5324
5325
5326 ret = dwc2_restore_global_registers(hsotg);
5327 if (ret) {
5328 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5329 __func__);
5330 return ret;
5331 }
5332
5333
5334 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5335 if (ret) {
5336 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5337 __func__);
5338 return ret;
5339 }
5340
5341 if (rem_wakeup) {
5342 mdelay(10);
5343 dctl = dwc2_readl(hsotg, DCTL);
5344 dctl &= ~DCTL_RMTWKUPSIG;
5345 dwc2_writel(hsotg, dctl, DCTL);
5346 }
5347
5348 hsotg->hibernated = 0;
5349 hsotg->lx_state = DWC2_L0;
5350 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5351
5352 return ret;
5353}
5354